2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.25 2005/04/30 23:04:21 swildner Exp $
34 #include "opt_simos.h"
35 #include "opt_compat_oldpci.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/fcntl.h>
43 #include <sys/kernel.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
50 #include <vm/vm_extern.h>
53 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/md_var.h> /* For the Alpha */
58 #include <bus/pci/i386/pci_cfgreg.h>
61 #include <sys/pciio.h>
64 #include "pci_private.h"
69 #include <machine/smp.h>
72 devclass_t pci_devclass;
74 static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
77 u_int32_t devid; /* Vendor/device of the card */
79 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
84 struct pci_quirk pci_quirks[] = {
86 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
88 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
89 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
90 /* As does the Serverworks OSB4 (the SMBus mapping register) */
91 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
96 /* map register information */
97 #define PCI_MAPMEM 0x01 /* memory map */
98 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
99 #define PCI_MAPPORT 0x04 /* port map */
101 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
102 u_int32_t pci_numdevs = 0;
103 static u_int32_t pci_generation = 0;
106 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
108 struct pci_devinfo *dinfo;
110 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
111 if ((dinfo->cfg.bus == bus) &&
112 (dinfo->cfg.slot == slot) &&
113 (dinfo->cfg.func == func)) {
114 return (dinfo->cfg.dev);
122 pci_find_device (u_int16_t vendor, u_int16_t device)
124 struct pci_devinfo *dinfo;
126 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
127 if ((dinfo->cfg.vendor == vendor) &&
128 (dinfo->cfg.device == device)) {
129 return (dinfo->cfg.dev);
136 /* return base address of memory or port map */
139 pci_mapbase(unsigned mapreg)
142 if ((mapreg & 0x01) == 0)
144 return (mapreg & ~mask);
147 /* return map type of memory or port map */
150 pci_maptype(unsigned mapreg)
152 static u_int8_t maptype[0x10] = {
153 PCI_MAPMEM, PCI_MAPPORT,
155 PCI_MAPMEM, PCI_MAPPORT,
157 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
158 PCI_MAPMEM|PCI_MAPMEMP, 0,
159 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
163 return maptype[mapreg & 0x0f];
166 /* return log2 of map size decoded for memory or port map */
169 pci_mapsize(unsigned testval)
173 testval = pci_mapbase(testval);
176 while ((testval & 1) == 0)
185 /* return log2 of address range supported by map register */
188 pci_maprange(unsigned mapreg)
191 switch (mapreg & 0x07) {
207 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
210 pci_fixancient(pcicfgregs *cfg)
212 if (cfg->hdrtype != 0)
215 /* PCI to PCI bridges use header type 1 */
216 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
220 /* read config data specific to header type 1 device (PCI to PCI bridge) */
223 pci_readppb(device_t pcib, int b, int s, int f)
227 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
231 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
232 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
234 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
236 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
238 PCIB_READ_CONFIG(pcib, b, s, f,
240 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
242 PCIB_READ_CONFIG(pcib, b, s, f,
243 PCIR_IOLIMITL_1, 1));
245 p->membase = PCI_PPBMEMBASE (0,
246 PCIB_READ_CONFIG(pcib, b, s, f,
248 p->memlimit = PCI_PPBMEMLIMIT (0,
249 PCIB_READ_CONFIG(pcib, b, s, f,
250 PCIR_MEMLIMIT_1, 2));
252 p->pmembase = PCI_PPBMEMBASE (
253 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
254 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
256 p->pmemlimit = PCI_PPBMEMLIMIT (
257 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
259 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
264 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
267 pci_readpcb(device_t pcib, int b, int s, int f)
271 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
275 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
276 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
278 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
280 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
281 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
282 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
283 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
285 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
286 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
287 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
288 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
290 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
294 /* extract header type specific config data */
297 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
299 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
300 switch (cfg->hdrtype) {
302 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
303 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
304 cfg->nummaps = PCI_MAXMAPS_0;
307 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
308 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
309 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
310 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
311 cfg->nummaps = PCI_MAXMAPS_1;
312 cfg->hdrspec = pci_readppb(pcib, b, s, f);
315 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
316 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
317 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
318 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
319 cfg->nummaps = PCI_MAXMAPS_2;
320 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
326 /* read configuration header into pcicfgrect structure */
329 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
331 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
333 pcicfgregs *cfg = NULL;
334 struct pci_devinfo *devlist_entry;
335 struct devlist *devlist_head;
337 devlist_head = &pci_devq;
339 devlist_entry = NULL;
341 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
343 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
344 if (devlist_entry == NULL)
347 cfg = &devlist_entry->cfg;
352 cfg->vendor = REG(PCIR_VENDOR, 2);
353 cfg->device = REG(PCIR_DEVICE, 2);
354 cfg->cmdreg = REG(PCIR_COMMAND, 2);
355 cfg->statreg = REG(PCIR_STATUS, 2);
356 cfg->baseclass = REG(PCIR_CLASS, 1);
357 cfg->subclass = REG(PCIR_SUBCLASS, 1);
358 cfg->progif = REG(PCIR_PROGIF, 1);
359 cfg->revid = REG(PCIR_REVID, 1);
360 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
361 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
362 cfg->lattimer = REG(PCIR_LATTIMER, 1);
363 cfg->intpin = REG(PCIR_INTPIN, 1);
364 cfg->intline = REG(PCIR_INTLINE, 1);
367 if (cfg->intpin != 0) {
370 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
372 /* PCI specific entry found in MP table */
373 if (airq != cfg->intline) {
374 undirect_pci_irq(cfg->intline);
379 * PCI interrupts might be redirected to the
380 * ISA bus according to some MP tables. Use the
381 * same methods as used by the ISA devices
382 * devices to find the proper IOAPIC int pin.
384 airq = isa_apic_irq(cfg->intline);
385 if ((airq >= 0) && (airq != cfg->intline)) {
386 /* XXX: undirect_pci_irq() ? */
387 undirect_isa_irq(cfg->intline);
394 cfg->mingnt = REG(PCIR_MINGNT, 1);
395 cfg->maxlat = REG(PCIR_MAXLAT, 1);
397 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
398 cfg->hdrtype &= ~PCIM_MFDEV;
401 pci_hdrtypedata(pcib, b, s, f, cfg);
403 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
404 pci_read_extcap(pcib, cfg);
406 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
408 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
409 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
410 devlist_entry->conf.pc_sel.pc_func = cfg->func;
411 devlist_entry->conf.pc_hdr = cfg->hdrtype;
413 devlist_entry->conf.pc_subvendor = cfg->subvendor;
414 devlist_entry->conf.pc_subdevice = cfg->subdevice;
415 devlist_entry->conf.pc_vendor = cfg->vendor;
416 devlist_entry->conf.pc_device = cfg->device;
418 devlist_entry->conf.pc_class = cfg->baseclass;
419 devlist_entry->conf.pc_subclass = cfg->subclass;
420 devlist_entry->conf.pc_progif = cfg->progif;
421 devlist_entry->conf.pc_revid = cfg->revid;
426 return (devlist_entry);
431 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
433 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
434 int ptr, nextptr, ptrptr;
436 switch (cfg->hdrtype) {
444 return; /* no extended capabilities support */
446 nextptr = REG(ptrptr, 1); /* sanity check? */
449 * Read capability entries.
451 while (nextptr != 0) {
454 printf("illegal PCI extended capability offset %d\n",
458 /* Find the next entry */
460 nextptr = REG(ptr + 1, 1);
462 /* Process this entry */
463 switch (REG(ptr, 1)) {
464 case 0x01: /* PCI power management */
465 if (cfg->pp_cap == 0) {
466 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
467 cfg->pp_status = ptr + PCIR_POWER_STATUS;
468 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
469 if ((nextptr - ptr) > PCIR_POWER_DATA)
470 cfg->pp_data = ptr + PCIR_POWER_DATA;
480 /* free pcicfgregs structure and all depending data structures */
483 pci_freecfg(struct pci_devinfo *dinfo)
485 struct devlist *devlist_head;
487 devlist_head = &pci_devq;
489 if (dinfo->cfg.hdrspec != NULL)
490 free(dinfo->cfg.hdrspec, M_DEVBUF);
491 /* XXX this hasn't been tested */
492 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
493 free(dinfo, M_DEVBUF);
495 /* increment the generation count */
498 /* we're losing one device */
505 * PCI power manangement
508 pci_set_powerstate_method(device_t dev, device_t child, int state)
510 struct pci_devinfo *dinfo = device_get_ivars(child);
511 pcicfgregs *cfg = &dinfo->cfg;
515 if (cfg->pp_cap != 0) {
516 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
519 case PCI_POWERSTATE_D0:
520 status |= PCIM_PSTAT_D0;
522 case PCI_POWERSTATE_D1:
523 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
524 status |= PCIM_PSTAT_D1;
529 case PCI_POWERSTATE_D2:
530 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
531 status |= PCIM_PSTAT_D2;
536 case PCI_POWERSTATE_D3:
537 status |= PCIM_PSTAT_D3;
543 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
551 pci_get_powerstate_method(device_t dev, device_t child)
553 struct pci_devinfo *dinfo = device_get_ivars(child);
554 pcicfgregs *cfg = &dinfo->cfg;
558 if (cfg->pp_cap != 0) {
559 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
560 switch (status & PCIM_PSTAT_DMASK) {
562 result = PCI_POWERSTATE_D0;
565 result = PCI_POWERSTATE_D1;
568 result = PCI_POWERSTATE_D2;
571 result = PCI_POWERSTATE_D3;
574 result = PCI_POWERSTATE_UNKNOWN;
578 /* No support, device is always at D0 */
579 result = PCI_POWERSTATE_D0;
585 * Some convenience functions for PCI device drivers.
589 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
593 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
595 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
599 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
603 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
605 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
609 pci_enable_busmaster_method(device_t dev, device_t child)
611 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
616 pci_disable_busmaster_method(device_t dev, device_t child)
618 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
623 pci_enable_io_method(device_t dev, device_t child, int space)
634 bit = PCIM_CMD_PORTEN;
638 bit = PCIM_CMD_MEMEN;
644 pci_set_command_bit(dev, child, bit);
645 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
648 device_printf(child, "failed to enable %s mapping!\n", error);
653 pci_disable_io_method(device_t dev, device_t child, int space)
664 bit = PCIM_CMD_PORTEN;
668 bit = PCIM_CMD_MEMEN;
674 pci_clear_command_bit(dev, child, bit);
675 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
677 device_printf(child, "failed to disable %s mapping!\n", error);
684 * This is the user interface to PCI configuration space.
688 pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
690 if ((oflags & FWRITE) && securelevel > 0) {
697 pci_close(dev_t dev, int flag, int devtype, struct thread *td)
703 * Match a single pci_conf structure against an array of pci_match_conf
704 * structures. The first argument, 'matches', is an array of num_matches
705 * pci_match_conf structures. match_buf is a pointer to the pci_conf
706 * structure that will be compared to every entry in the matches array.
707 * This function returns 1 on failure, 0 on success.
710 pci_conf_match(struct pci_match_conf *matches, int num_matches,
711 struct pci_conf *match_buf)
715 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
718 for (i = 0; i < num_matches; i++) {
720 * I'm not sure why someone would do this...but...
722 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
726 * Look at each of the match flags. If it's set, do the
727 * comparison. If the comparison fails, we don't have a
728 * match, go on to the next item if there is one.
730 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
731 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
734 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
735 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
738 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
739 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
742 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
743 && (match_buf->pc_vendor != matches[i].pc_vendor))
746 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
747 && (match_buf->pc_device != matches[i].pc_device))
750 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
751 && (match_buf->pc_class != matches[i].pc_class))
754 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
755 && (match_buf->pd_unit != matches[i].pd_unit))
758 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
759 && (strncmp(matches[i].pd_name, match_buf->pd_name,
760 sizeof(match_buf->pd_name)) != 0))
770 * Locate the parent of a PCI device by scanning the PCI devlist
771 * and return the entry for the parent.
772 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
773 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
777 pci_devlist_get_parent(pcicfgregs *cfg)
779 struct devlist *devlist_head;
780 struct pci_devinfo *dinfo;
781 pcicfgregs *bridge_cfg;
784 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
786 /* If the device is on PCI bus 0, look for the host */
788 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
789 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
790 bridge_cfg = &dinfo->cfg;
791 if (bridge_cfg->baseclass == PCIC_BRIDGE
792 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
793 && bridge_cfg->bus == cfg->bus) {
799 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
801 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
802 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
803 bridge_cfg = &dinfo->cfg;
804 if (bridge_cfg->baseclass == PCIC_BRIDGE
805 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
806 && bridge_cfg->secondarybus == cfg->bus) {
816 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
823 if (!(flag & FWRITE))
830 struct pci_devinfo *dinfo;
831 struct pci_conf_io *cio;
832 struct devlist *devlist_head;
833 struct pci_match_conf *pattern_buf;
838 cio = (struct pci_conf_io *)data;
844 * Hopefully the user won't pass in a null pointer, but it
845 * can't hurt to check.
853 * If the user specified an offset into the device list,
854 * but the list has changed since they last called this
855 * ioctl, tell them that the list has changed. They will
856 * have to get the list from the beginning.
858 if ((cio->offset != 0)
859 && (cio->generation != pci_generation)){
860 cio->num_matches = 0;
861 cio->status = PCI_GETCONF_LIST_CHANGED;
867 * Check to see whether the user has asked for an offset
868 * past the end of our list.
870 if (cio->offset >= pci_numdevs) {
871 cio->num_matches = 0;
872 cio->status = PCI_GETCONF_LAST_DEVICE;
877 /* get the head of the device queue */
878 devlist_head = &pci_devq;
881 * Determine how much room we have for pci_conf structures.
882 * Round the user's buffer size down to the nearest
883 * multiple of sizeof(struct pci_conf) in case the user
884 * didn't specify a multiple of that size.
886 iolen = min(cio->match_buf_len -
887 (cio->match_buf_len % sizeof(struct pci_conf)),
888 pci_numdevs * sizeof(struct pci_conf));
891 * Since we know that iolen is a multiple of the size of
892 * the pciconf union, it's okay to do this.
894 ionum = iolen / sizeof(struct pci_conf);
897 * If this test is true, the user wants the pci_conf
898 * structures returned to match the supplied entries.
900 if ((cio->num_patterns > 0)
901 && (cio->pat_buf_len > 0)) {
903 * pat_buf_len needs to be:
904 * num_patterns * sizeof(struct pci_match_conf)
905 * While it is certainly possible the user just
906 * allocated a large buffer, but set the number of
907 * matches correctly, it is far more likely that
908 * their kernel doesn't match the userland utility
909 * they're using. It's also possible that the user
910 * forgot to initialize some variables. Yes, this
911 * may be overly picky, but I hazard to guess that
912 * it's far more likely to just catch folks that
913 * updated their kernel but not their userland.
915 if ((cio->num_patterns *
916 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
917 /* The user made a mistake, return an error*/
918 cio->status = PCI_GETCONF_ERROR;
919 printf("pci_ioctl: pat_buf_len %d != "
920 "num_patterns (%d) * sizeof(struct "
921 "pci_match_conf) (%d)\npci_ioctl: "
922 "pat_buf_len should be = %d\n",
923 cio->pat_buf_len, cio->num_patterns,
924 (int)sizeof(struct pci_match_conf),
925 (int)sizeof(struct pci_match_conf) *
927 printf("pci_ioctl: do your headers match your "
929 cio->num_matches = 0;
935 * Check the user's buffer to make sure it's readable.
937 if (!useracc((caddr_t)cio->patterns,
938 cio->pat_buf_len, VM_PROT_READ)) {
939 printf("pci_ioctl: pattern buffer %p, "
940 "length %u isn't user accessible for"
941 " READ\n", cio->patterns,
947 * Allocate a buffer to hold the patterns.
949 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
951 error = copyin(cio->patterns, pattern_buf,
955 num_patterns = cio->num_patterns;
957 } else if ((cio->num_patterns > 0)
958 || (cio->pat_buf_len > 0)) {
960 * The user made a mistake, spit out an error.
962 cio->status = PCI_GETCONF_ERROR;
963 cio->num_matches = 0;
964 printf("pci_ioctl: invalid GETCONF arguments\n");
971 * Make sure we can write to the match buffer.
973 if (!useracc((caddr_t)cio->matches,
974 cio->match_buf_len, VM_PROT_WRITE)) {
975 printf("pci_ioctl: match buffer %p, length %u "
976 "isn't user accessible for WRITE\n",
977 cio->matches, cio->match_buf_len);
983 * Go through the list of devices and copy out the devices
984 * that match the user's criteria.
986 for (cio->num_matches = 0, error = 0, i = 0,
987 dinfo = STAILQ_FIRST(devlist_head);
988 (dinfo != NULL) && (cio->num_matches < ionum)
989 && (error == 0) && (i < pci_numdevs);
990 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
995 /* Populate pd_name and pd_unit */
997 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
998 name = device_get_name(dinfo->cfg.dev);
1000 strncpy(dinfo->conf.pd_name, name,
1001 sizeof(dinfo->conf.pd_name));
1002 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1003 dinfo->conf.pd_unit =
1004 device_get_unit(dinfo->cfg.dev);
1007 if ((pattern_buf == NULL) ||
1008 (pci_conf_match(pattern_buf, num_patterns,
1009 &dinfo->conf) == 0)) {
1012 * If we've filled up the user's buffer,
1013 * break out at this point. Since we've
1014 * got a match here, we'll pick right back
1015 * up at the matching entry. We can also
1016 * tell the user that there are more matches
1019 if (cio->num_matches >= ionum)
1022 error = copyout(&dinfo->conf,
1023 &cio->matches[cio->num_matches],
1024 sizeof(struct pci_conf));
1030 * Set the pointer into the list, so if the user is getting
1031 * n records at a time, where n < pci_numdevs,
1036 * Set the generation, the user will need this if they make
1037 * another ioctl call with offset != 0.
1039 cio->generation = pci_generation;
1042 * If this is the last device, inform the user so he won't
1043 * bother asking for more devices. If dinfo isn't NULL, we
1044 * know that there are more matches in the list because of
1045 * the way the traversal is done.
1048 cio->status = PCI_GETCONF_LAST_DEVICE;
1050 cio->status = PCI_GETCONF_MORE_DEVS;
1052 if (pattern_buf != NULL)
1053 free(pattern_buf, M_TEMP);
1058 io = (struct pci_io *)data;
1059 switch(io->pi_width) {
1064 * Assume that the user-level bus number is
1065 * actually the pciN instance number. We map
1066 * from that to the real pcib+bus combination.
1068 pci = devclass_get_device(pci_devclass,
1071 int b = pcib_get_bus(pci);
1072 pcib = device_get_parent(pci);
1074 PCIB_READ_CONFIG(pcib,
1092 io = (struct pci_io *)data;
1093 switch(io->pi_width) {
1098 * Assume that the user-level bus number is
1099 * actually the pciN instance number. We map
1100 * from that to the real pcib+bus combination.
1102 pci = devclass_get_device(pci_devclass,
1105 int b = pcib_get_bus(pci);
1106 pcib = device_get_parent(pci);
1107 PCIB_WRITE_CONFIG(pcib,
1135 static struct cdevsw pcicdev = {
1142 /* open */ pci_open,
1143 /* close */ pci_close,
1145 /* write */ nowrite,
1146 /* ioctl */ pci_ioctl,
1149 /* strategy */ nostrategy,
1157 * New style pci driver. Parent device is either a pci-host-bridge or a
1158 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1161 pci_class_to_string(int baseclass)
1178 case PCIC_MULTIMEDIA:
1179 name = "MULTIMEDIA";
1187 case PCIC_SIMPLECOMM:
1188 name = "SIMPLECOMM";
1190 case PCIC_BASEPERIPH:
1191 name = "BASEPERIPH";
1199 case PCIC_PROCESSOR:
1202 case PCIC_SERIALBUS:
1211 case PCIC_SATELLITE:
1231 pci_print_verbose(struct pci_devinfo *dinfo)
1234 pcicfgregs *cfg = &dinfo->cfg;
1236 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1237 cfg->vendor, cfg->device, cfg->revid);
1238 printf("\tbus=%d, slot=%d, func=%d\n",
1239 cfg->bus, cfg->slot, cfg->func);
1240 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1241 pci_class_to_string(cfg->baseclass),
1242 cfg->baseclass, cfg->subclass, cfg->progif,
1243 cfg->hdrtype, cfg->mfdev);
1244 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1245 cfg->subordinatebus, cfg->secondarybus);
1247 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1248 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1249 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1250 cfg->lattimer, cfg->lattimer * 30,
1251 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1252 #endif /* PCI_DEBUG */
1253 if (cfg->intpin > 0)
1254 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1259 pci_porten(device_t pcib, int b, int s, int f)
1261 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1262 & PCIM_CMD_PORTEN) != 0;
1266 pci_memen(device_t pcib, int b, int s, int f)
1268 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1269 & PCIM_CMD_MEMEN) != 0;
1273 * Add a resource based on a pci map register. Return 1 if the map
1274 * register is a 32bit map register or 2 if it is a 64bit register.
1277 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1278 struct resource_list *rl)
1287 #ifdef PCI_ENABLE_IO_MODES
1292 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1294 if (map == 0 || map == 0xffffffff)
1295 return 1; /* skip invalid entry */
1297 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1298 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1299 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1301 base = pci_mapbase(map);
1302 if (pci_maptype(map) & PCI_MAPMEM)
1303 type = SYS_RES_MEMORY;
1305 type = SYS_RES_IOPORT;
1306 ln2size = pci_mapsize(testval);
1307 ln2range = pci_maprange(testval);
1308 if (ln2range == 64) {
1309 /* Read the other half of a 64bit map register */
1310 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1314 * This code theoretically does the right thing, but has
1315 * undesirable side effects in some cases where
1316 * peripherals respond oddly to having these bits
1317 * enabled. Leave them alone by default.
1319 #ifdef PCI_ENABLE_IO_MODES
1320 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1321 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1322 cmd |= PCIM_CMD_PORTEN;
1323 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1325 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1326 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1327 cmd |= PCIM_CMD_MEMEN;
1328 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1331 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1333 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1337 resource_list_add(rl, type, reg,
1338 base, base + (1 << ln2size) - 1,
1342 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1343 reg, pci_maptype(base), ln2range,
1344 (unsigned int) base, ln2size);
1347 return (ln2range == 64) ? 2 : 1;
1351 pci_add_resources(device_t pcib, device_t bus, device_t dev)
1353 struct pci_devinfo *dinfo = device_get_ivars(dev);
1354 pcicfgregs *cfg = &dinfo->cfg;
1355 struct resource_list *rl = &dinfo->resources;
1356 struct pci_quirk *q;
1358 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1365 for (i = 0; i < cfg->nummaps;) {
1366 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1369 for (q = &pci_quirks[0]; q->devid; q++) {
1370 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1371 && q->type == PCI_QUIRK_MAP_REG)
1372 pci_add_map(pcib, b, s, f, q->arg1, rl);
1375 if (cfg->intpin > 0 && cfg->intline != 255)
1376 resource_list_add(rl, SYS_RES_IRQ, 0,
1377 cfg->intline, cfg->intline, 1);
1381 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1383 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1384 device_t pcib = device_get_parent(dev);
1385 struct pci_devinfo *dinfo;
1387 int s, f, pcifunchigh;
1390 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
1392 maxslots = PCIB_MAXSLOTS(pcib);
1394 for (s = 0; s <= maxslots; s++) {
1397 hdrtype = REG(PCIR_HDRTYPE, 1);
1398 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1400 if (hdrtype & PCIM_MFDEV)
1401 pcifunchigh = PCI_FUNCMAX;
1402 for (f = 0; f <= pcifunchigh; f++) {
1403 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1404 if (dinfo != NULL) {
1405 pci_add_child(dev, dinfo);
1413 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1417 pcib = device_get_parent(bus);
1418 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1419 device_set_ivars(dinfo->cfg.dev, dinfo);
1420 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1421 pci_print_verbose(dinfo);
1425 * Probe the PCI bus. Note: probe code is not supposed to add children
1429 pci_probe(device_t dev)
1431 device_set_desc(dev, "PCI bus");
1433 /* Allow other subclasses to override this driver */
1438 pci_attach(device_t dev)
1441 int lunit = device_get_unit(dev);
1443 cdevsw_add(&pcicdev, -1, lunit);
1444 make_dev(&pcicdev, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
1447 * Since there can be multiple independantly numbered PCI
1448 * busses on some large alpha systems, we can't use the unit
1449 * number to decide what bus we are probing. We ask the parent
1450 * pcib what our bus number is.
1452 busno = pcib_get_bus(dev);
1454 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
1456 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1458 return (bus_generic_attach(dev));
1462 pci_print_resources(struct resource_list *rl, const char *name, int type,
1465 struct resource_list_entry *rle;
1466 int printed, retval;
1470 /* Yes, this is kinda cheating */
1471 SLIST_FOREACH(rle, rl, link) {
1472 if (rle->type == type) {
1474 retval += printf(" %s ", name);
1475 else if (printed > 0)
1476 retval += printf(",");
1478 retval += printf(format, rle->start);
1479 if (rle->count > 1) {
1480 retval += printf("-");
1481 retval += printf(format, rle->start +
1490 pci_print_child(device_t dev, device_t child)
1492 struct pci_devinfo *dinfo;
1493 struct resource_list *rl;
1497 dinfo = device_get_ivars(child);
1499 rl = &dinfo->resources;
1501 retval += bus_print_child_header(dev, child);
1503 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1504 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1505 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1506 if (device_get_flags(dev))
1507 retval += printf(" flags %#x", device_get_flags(dev));
1509 retval += printf(" at device %d.%d", pci_get_slot(child),
1510 pci_get_function(child));
1512 retval += bus_print_child_footer(dev, child);
1518 pci_probe_nomatch(device_t dev, device_t child)
1520 struct pci_devinfo *dinfo;
1526 dinfo = device_get_ivars(child);
1528 desc = pci_ata_match(child);
1529 if (!desc) desc = pci_usb_match(child);
1530 if (!desc) desc = pci_vga_match(child);
1531 if (!desc) desc = pci_chip_match(child);
1533 desc = "unknown card";
1536 device_printf(dev, "<%s>", desc);
1537 if (bootverbose || unknown) {
1538 printf(" (vendor=0x%04x, dev=0x%04x)",
1543 pci_get_slot(child),
1544 pci_get_function(child));
1545 if (cfg->intpin > 0 && cfg->intline != 255) {
1546 printf(" irq %d", cfg->intline);
1554 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1556 struct pci_devinfo *dinfo;
1559 dinfo = device_get_ivars(child);
1563 case PCI_IVAR_SUBVENDOR:
1564 *result = cfg->subvendor;
1566 case PCI_IVAR_SUBDEVICE:
1567 *result = cfg->subdevice;
1569 case PCI_IVAR_VENDOR:
1570 *result = cfg->vendor;
1572 case PCI_IVAR_DEVICE:
1573 *result = cfg->device;
1575 case PCI_IVAR_DEVID:
1576 *result = (cfg->device << 16) | cfg->vendor;
1578 case PCI_IVAR_CLASS:
1579 *result = cfg->baseclass;
1581 case PCI_IVAR_SUBCLASS:
1582 *result = cfg->subclass;
1584 case PCI_IVAR_PROGIF:
1585 *result = cfg->progif;
1587 case PCI_IVAR_REVID:
1588 *result = cfg->revid;
1590 case PCI_IVAR_INTPIN:
1591 *result = cfg->intpin;
1594 *result = cfg->intline;
1600 *result = cfg->slot;
1602 case PCI_IVAR_FUNCTION:
1603 *result = cfg->func;
1605 case PCI_IVAR_SECONDARYBUS:
1606 *result = cfg->secondarybus;
1608 case PCI_IVAR_SUBORDINATEBUS:
1609 *result = cfg->subordinatebus;
1611 case PCI_IVAR_ETHADDR:
1613 * The generic accessor doesn't deal with failure, so
1614 * we set the return value, then return an error.
1625 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1627 struct pci_devinfo *dinfo;
1630 dinfo = device_get_ivars(child);
1634 case PCI_IVAR_SUBVENDOR:
1635 case PCI_IVAR_SUBDEVICE:
1636 case PCI_IVAR_VENDOR:
1637 case PCI_IVAR_DEVICE:
1638 case PCI_IVAR_DEVID:
1639 case PCI_IVAR_CLASS:
1640 case PCI_IVAR_SUBCLASS:
1641 case PCI_IVAR_PROGIF:
1642 case PCI_IVAR_REVID:
1643 case PCI_IVAR_INTPIN:
1647 case PCI_IVAR_FUNCTION:
1648 case PCI_IVAR_ETHADDR:
1649 return EINVAL; /* disallow for now */
1651 case PCI_IVAR_SECONDARYBUS:
1652 cfg->secondarybus = value;
1654 case PCI_IVAR_SUBORDINATEBUS:
1655 cfg->subordinatebus = value;
1664 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1665 u_long start, u_long end, u_long count, u_int flags)
1667 struct pci_devinfo *dinfo = device_get_ivars(child);
1668 struct resource_list *rl = &dinfo->resources;
1671 pcicfgregs *cfg = &dinfo->cfg;
1673 * Perform lazy resource allocation
1675 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1677 if (device_get_parent(child) == dev) {
1679 * If device doesn't have an interrupt routed, and is
1680 * deserving of an interrupt, try to assign it one.
1682 if ((type == SYS_RES_IRQ) &&
1683 (cfg->intline == 255 || cfg->intline == 0) &&
1684 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1685 cfg->intline = PCIB_ROUTE_INTERRUPT(
1686 device_get_parent(dev), child,
1688 if (cfg->intline != 255) {
1689 pci_write_config(child, PCIR_INTLINE,
1691 resource_list_add(rl, SYS_RES_IRQ, 0,
1692 cfg->intline, cfg->intline, 1);
1697 return resource_list_alloc(rl, dev, child, type, rid,
1698 start, end, count, flags);
1702 pci_release_resource(device_t dev, device_t child, int type, int rid,
1705 struct pci_devinfo *dinfo = device_get_ivars(child);
1706 struct resource_list *rl = &dinfo->resources;
1708 return resource_list_release(rl, dev, child, type, rid, r);
1712 pci_set_resource(device_t dev, device_t child, int type, int rid,
1713 u_long start, u_long count)
1715 struct pci_devinfo *dinfo = device_get_ivars(child);
1716 struct resource_list *rl = &dinfo->resources;
1718 resource_list_add(rl, type, rid, start, start + count - 1, count);
1723 pci_get_resource(device_t dev, device_t child, int type, int rid,
1724 u_long *startp, u_long *countp)
1726 struct pci_devinfo *dinfo = device_get_ivars(child);
1727 struct resource_list *rl = &dinfo->resources;
1728 struct resource_list_entry *rle;
1730 rle = resource_list_find(rl, type, rid);
1735 *startp = rle->start;
1737 *countp = rle->count;
1743 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1745 printf("pci_delete_resource: PCI resources can not be deleted\n");
1748 struct resource_list *
1749 pci_get_resource_list (device_t dev, device_t child)
1751 struct pci_devinfo * dinfo = device_get_ivars(child);
1752 struct resource_list * rl = &dinfo->resources;
1761 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1763 struct pci_devinfo *dinfo = device_get_ivars(child);
1764 pcicfgregs *cfg = &dinfo->cfg;
1766 return PCIB_READ_CONFIG(device_get_parent(dev),
1767 cfg->bus, cfg->slot, cfg->func,
1772 pci_write_config_method(device_t dev, device_t child, int reg,
1773 u_int32_t val, int width)
1775 struct pci_devinfo *dinfo = device_get_ivars(child);
1776 pcicfgregs *cfg = &dinfo->cfg;
1778 PCIB_WRITE_CONFIG(device_get_parent(dev),
1779 cfg->bus, cfg->slot, cfg->func,
1784 pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
1787 struct pci_devinfo *dinfo;
1789 dinfo = device_get_ivars(child);
1790 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1791 pci_get_function(child));
1796 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
1799 struct pci_devinfo *dinfo;
1802 dinfo = device_get_ivars(child);
1804 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
1805 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
1806 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
1812 pci_assign_interrupt_method(device_t dev, device_t child)
1814 struct pci_devinfo *dinfo = device_get_ivars(child);
1815 pcicfgregs *cfg = &dinfo->cfg;
1817 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
1822 pci_modevent(module_t mod, int what, void *arg)
1826 STAILQ_INIT(&pci_devq);
1836 pci_resume(device_t dev)
1842 struct pci_devinfo *dinfo;
1845 device_get_children(dev, &children, &numdevs);
1847 for (i = 0; i < numdevs; i++) {
1848 child = children[i];
1850 dinfo = device_get_ivars(child);
1852 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1853 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
1854 if (PCI_INTERRUPT_VALID(cfg->intline)) {
1855 pci_write_config(child, PCIR_INTLINE,
1861 free(children, M_TEMP);
1863 return (bus_generic_resume(dev));
1866 static device_method_t pci_methods[] = {
1867 /* Device interface */
1868 DEVMETHOD(device_probe, pci_probe),
1869 DEVMETHOD(device_attach, pci_attach),
1870 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1871 DEVMETHOD(device_suspend, bus_generic_suspend),
1872 DEVMETHOD(device_resume, pci_resume),
1875 DEVMETHOD(bus_print_child, pci_print_child),
1876 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1877 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1878 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1879 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1880 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1881 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1883 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
1884 DEVMETHOD(bus_set_resource, pci_set_resource),
1885 DEVMETHOD(bus_get_resource, pci_get_resource),
1886 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1887 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1888 DEVMETHOD(bus_release_resource, pci_release_resource),
1889 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1890 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1891 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
1892 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
1895 DEVMETHOD(pci_read_config, pci_read_config_method),
1896 DEVMETHOD(pci_write_config, pci_write_config_method),
1897 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1898 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1899 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1900 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1901 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1902 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1903 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
1908 static driver_t pci_driver = {
1914 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
1915 MODULE_VERSION(pci, 1);