2 * Copyright (c) 1995 HD Associates, Inc.
7 * Pepperell, MA 01463-0276
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20 * This product includes software developed by HD Associates, Inc.
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41 * $FreeBSD: src/sys/i386/isa/labpc.c,v 1.35 1999/09/25 18:24:08 phk Exp $
42 * $DragonFly: src/sys/dev/misc/labpc/labpc.c,v 1.3 2003/07/21 05:50:40 dillon Exp $
47 #include "opt_debug_outb.h"
48 #include <sys/param.h>
50 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #define b_actf b_act.tqe_next
56 #include <sys/dataacq.h>
60 #include <machine/clock.h>
63 #include <i386/isa/isa_device.h>
70 #define LABPC_MIN_TMO (hz)
73 #ifndef LABPC_DEFAULT_HERZ
74 #define LABPC_DEFAULT_HERZ 500
80 * S: SCAN bit for scan enable.
81 * I: INTERVAL for interval support
82 * D: 1: Digital I/O, 0: Analog I/O
85 * input: channel must be 0 to 7.
86 * output: channel must be 0 to 2
89 * 2: Alternate channel 0 then 1
92 * input: Channel must be 0 to 2.
93 * output: Channel must be 0 to 2.
99 #define UNIT(dev) (((minor(dev) & 0xB0) >> 6) & 0x3)
101 #define SCAN(dev) ((minor(dev) & 0x20) >> 5)
102 #define INTERVAL(dev) ((minor(dev) & 0x10) >> 4)
103 #define DIGITAL(dev) ((minor(dev) & 0x08) >> 3)
108 #define CHAN(dev) (minor(dev) & 0x7)
110 /* History: Derived from "dt2811.c" March 1995
116 #define DROPPED_INPUT 0x100
120 #define BUSY 0x00000001
126 struct buf start_queue; /* Start queue */
127 struct buf *last; /* End of start queue */
130 long tmo; /* Timeout in Herz */
131 long min_tmo; /* Timeout in Herz */
136 dev_t dev; /* Copy of device */
138 void (*starter)(struct ctlr *ctlr, long count);
139 void (*stop)(struct ctlr *ctlr);
140 void (*intr)(struct ctlr *ctlr);
142 /* Digital I/O support. Copy of Data Control Register for 8255:
144 u_char dcr_val, dcr_is;
147 * Handle for canceling our timeout.
149 struct callout_handle ch;
151 /* Device configuration structure:
156 /* loutb is a slow outb for debugging. The overrun test may fail
157 * with this for some slower processors.
159 static __inline void loutb(int port, u_char val)
165 #define loutb(port, val) outb(port, val)
168 static struct ctlr **labpcs; /* XXX: Should be dynamic */
170 /* CR_EXPR: A macro that sets the shadow register in addition to
171 * sending out the data.
173 #define CR_EXPR(LABPC, CR, EXPR) do { \
174 (LABPC)->cr_image[CR - 1] EXPR ; \
175 loutb(((LABPC)->base + ( (CR == 4) ? (0x0F) : (CR - 1))), ((LABPC)->cr_image[(CR - 1)])); \
178 #define CR_CLR(LABPC, CR) CR_EXPR(LABPC, CR, &=0)
179 #define CR_REFRESH(LABPC, CR) CR_EXPR(LABPC, CR, &=0xff)
180 #define CR_SET(LABPC, CR, EXPR) CR_EXPR(LABPC, CR, = EXPR)
182 /* Configuration and Status Register Group.
184 #define CR1(LABPC) ((LABPC)->base + 0x00) /* Page 4-5 */
186 #define GAINMASK 0x70
187 #define GAIN(LABPC, SEL) do { \
188 (LABPC)->cr_image[1 - 1] &= ~GAINMASK; \
189 (LABPC)->cr_image[1 - 1] |= (SEL << 4); \
190 loutb((LABPC)->base + (1 - 1), (LABPC)->cr_image[(1 - 1)]); \
195 #define MA(LABPC, SEL) do { \
196 (LABPC)->cr_image[1 - 1] &= ~MAMASK; \
197 (LABPC)->cr_image[1 - 1] |= SEL; \
198 loutb((LABPC)->base + (1 - 1), (LABPC)->cr_image[(1 - 1)]); \
201 #define STATUS(LABPC) ((LABPC)->base + 0x00) /* Page 4-7 */
202 #define LABPCPLUS 0x80
203 #define EXTGATA0 0x40
207 #define OVERFLOW 0x04
211 #define CR2(LABPC) ((LABPC)->base + 0x01) /* Page 4-9 */
220 #define SWTRIGGERRED(LABPC) ((LABPC->cr_image[1]) & SWTRIG)
222 #define CR3(LABPC) ((LABPC)->base + 0x02) /* Page 4-11 */
223 #define FIFOINTEN 0x20
224 #define ERRINTEN 0x10
225 #define CNTINTEN 0x08
227 #define DIOINTEN 0x02
230 #define ALLINTEN 0x3E
231 #define FIFOINTENABLED(LABPC) ((LABPC->cr_image[2]) & FIFOINTEN)
233 #define CR4(LABPC) ((LABPC)->base + 0x0F) /* Page 4-13 */
240 /* Analog Input Register Group
242 #define ADFIFO(LABPC) ((LABPC)->base + 0x0A) /* Page 4-16 */
243 #define ADCLEAR(LABPC) ((LABPC)->base + 0x08) /* Page 4-18 */
244 #define ADSTART(LABPC) ((LABPC)->base + 0x03) /* Page 4-19 */
245 #define DMATCICLR(LABPC) ((LABPC)->base + 0x0A) /* Page 4-20 */
247 /* Analog Output Register Group
249 #define DAC0L(LABPC) ((LABPC)->base + 0x04) /* Page 4-22 */
250 #define DAC0H(LABPC) ((LABPC)->base + 0x05) /* Page 4-22 */
251 #define DAC1L(LABPC) ((LABPC)->base + 0x06) /* Page 4-22 */
252 #define DAC1H(LABPC) ((LABPC)->base + 0x07) /* Page 4-22 */
256 #define A0DATA(LABPC) ((LABPC)->base + 0x14)
257 #define A1DATA(LABPC) ((LABPC)->base + 0x15)
258 #define A2DATA(LABPC) ((LABPC)->base + 0x16)
259 #define AMODE(LABPC) ((LABPC)->base + 0x17)
261 #define TICR(LABPC) ((LABPC)->base + 0x0c)
263 #define B0DATA(LABPC) ((LABPC)->base + 0x18)
264 #define B1DATA(LABPC) ((LABPC)->base + 0x19)
265 #define B2DATA(LABPC) ((LABPC)->base + 0x1A)
266 #define BMODE(LABPC) ((LABPC)->base + 0x1B)
271 #define PORTX(LABPC, X) ((LABPC)->base + 0x10 + X)
273 #define PORTA(LABPC) PORTX(LABPC, 0)
274 #define PORTB(LABPC) PORTX(LABPC, 1)
275 #define PORTC(LABPC) PORTX(LABPC, 2)
277 #define DCR(LABPC) ((LABPC)->base + 0x13)
279 static int labpcattach(struct isa_device *dev);
280 static int labpcprobe(struct isa_device *dev);
281 struct isa_driver labpcdriver =
282 { labpcprobe, labpcattach, "labpc", 0 };
284 static d_open_t labpcopen;
285 static d_close_t labpcclose;
286 static d_ioctl_t labpcioctl;
287 static d_strategy_t labpcstrategy;
289 #define CDEV_MAJOR 66
290 static struct cdevsw labpc_cdevsw = {
292 /* maj */ CDEV_MAJOR,
297 /* open */ labpcopen,
298 /* close */ labpcclose,
300 /* write */ physwrite,
301 /* ioctl */ labpcioctl,
304 /* strategy */ labpcstrategy,
309 static ointhand2_t labpcintr;
310 static void start(struct ctlr *ctlr);
313 bp_done(struct buf *bp, int err)
317 if (err || bp->b_resid)
319 bp->b_flags |= B_ERROR;
325 static void tmo_stop(void *p);
328 done_and_start_next(struct ctlr *ctlr, struct buf *bp, int err)
330 bp->b_resid = ctlr->data_end - ctlr->data;
334 ctlr->start_queue.b_actf = bp->b_actf;
337 untimeout(tmo_stop, ctlr, ctlr->ch);
343 ad_clear(struct ctlr *ctlr)
346 loutb(ADCLEAR(ctlr), 0);
347 for (i = 0; i < 10000 && (inb(STATUS(ctlr)) & GATA0); i++)
349 (void)inb(ADFIFO(ctlr));
350 (void)inb(ADFIFO(ctlr));
353 /* reset: Reset the board following the sequence on page 5-1
356 reset(struct ctlr *ctlr)
360 CR_CLR(ctlr, 3); /* Turn off interrupts first */
367 loutb(AMODE(ctlr), 0x34);
368 loutb(A0DATA(ctlr),0x0A);
369 loutb(A0DATA(ctlr),0x00);
371 loutb(DMATCICLR(ctlr), 0x00);
372 loutb(TICR(ctlr), 0x00);
376 loutb(DAC0L(ctlr), 0);
377 loutb(DAC0H(ctlr), 0);
378 loutb(DAC1L(ctlr), 0);
379 loutb(DAC1H(ctlr), 0);
384 /* overrun: slam the start convert register and OVERRUN should get set:
387 overrun(struct ctlr *ctlr)
391 u_char status = inb(STATUS(ctlr));
392 for (i = 0; ((status & OVERRUN) == 0) && i < 100; i++)
394 loutb(ADSTART(ctlr), 1);
395 status = inb(STATUS(ctlr));
404 if (NLABPC > MAX_UNITS)
407 labpcs = malloc(NLABPC * sizeof(struct ctlr *), M_DEVBUF, M_NOWAIT);
410 bzero(labpcs, NLABPC * sizeof(struct ctlr *));
413 cdevsw_add(&labpc_cdevsw);
418 labpcprobe(struct isa_device *dev)
421 struct ctlr scratch, *ctlr;
426 if (labpcinit() == 0)
428 printf("labpcprobe: init failed\n");
435 printf("Too many LAB-PCs. Reconfigure O/S.\n");
438 ctlr = &scratch; /* Need somebody with the right base for the macros */
439 ctlr->base = dev->id_iobase;
441 /* XXX: There really isn't a perfect way to probe this board.
442 * Here is my best attempt:
446 /* After reset none of these bits should be set:
448 status = inb(STATUS(ctlr));
449 if (status & (GATA0 | OVERFLOW | DAVAIL | OVERRUN))
452 /* Now try to overrun the board FIFO and get the overrun bit set:
454 status = overrun(ctlr);
456 if ((status & OVERRUN) == 0) /* No overrun bit set? */
459 /* Assume we have a board.
463 if ( (labpcs[unit] = malloc(sizeof(struct ctlr), M_DEVBUF, M_NOWAIT)) )
465 struct ctlr *l = labpcs[unit];
467 bzero(l, sizeof(struct ctlr));
468 l->base = ctlr->base;
469 dev->id_unit = l->unit = unit;
476 printf("labpc%d: Can't malloc.\n", unit);
481 /* attach: Set things in a normal state.
484 labpcattach(struct isa_device *dev)
486 struct ctlr *ctlr = labpcs[dev->id_unit];
488 dev->id_ointr = labpcintr;
489 callout_handle_init(&ctlr->ch);
490 ctlr->sample_us = (1000000.0 / (double)LABPC_DEFAULT_HERZ) + .50;
493 ctlr->min_tmo = LABPC_MIN_TMO;
495 ctlr->dcr_val = 0x80;
497 loutb(DCR(ctlr), ctlr->dcr_val);
499 make_dev(&labpc_cdevsw, 0, 0, 0, 0600, "labpc%d", dev->id_unit);
505 static void null_intr (struct ctlr *ctlr) { }
506 static void null_start(struct ctlr *ctlr, long count) { }
507 static void null_stop (struct ctlr *ctlr) { }
510 trigger(struct ctlr *ctlr)
512 CR_EXPR(ctlr, 2, |= SWTRIG);
516 ad_start(struct ctlr *ctlr, long count)
518 if (!SWTRIGGERRED(ctlr)) {
519 int chan = CHAN(ctlr->dev);
520 CR_EXPR(ctlr, 1, &= ~SCANEN);
521 CR_EXPR(ctlr, 2, &= ~TBSEL);
524 GAIN(ctlr, ctlr->gains[chan]);
527 CR_EXPR(ctlr, 1, |= SCANEN);
529 loutb(AMODE(ctlr), 0x34);
530 loutb(A0DATA(ctlr), (u_char)((ctlr->sample_us & 0xff)));
531 loutb(A0DATA(ctlr), (u_char)((ctlr->sample_us >> 8)&0xff));
532 loutb(AMODE(ctlr), 0x70);
538 ctlr->tmo = ((count + 16) * (long)ctlr->sample_us * hz) / 1000000 +
543 ad_interval_start(struct ctlr *ctlr, long count)
545 int chan = CHAN(ctlr->dev);
546 int n_frames = count / (chan + 1);
548 if (!SWTRIGGERRED(ctlr)) {
549 CR_EXPR(ctlr, 1, &= ~SCANEN);
550 CR_EXPR(ctlr, 2, &= ~TBSEL);
553 GAIN(ctlr, ctlr->gains[chan]);
555 /* XXX: Is it really possible that you clear INTSCAN as
556 * the documentation says? That seems pretty unlikely.
558 CR_EXPR(ctlr, 4, &= ~INTSCAN); /* XXX: Is this possible? */
560 /* Program the sample interval counter to run as fast as
563 loutb(AMODE(ctlr), 0x34);
564 loutb(A0DATA(ctlr), (u_char)(0x02));
565 loutb(A0DATA(ctlr), (u_char)(0x00));
566 loutb(AMODE(ctlr), 0x70);
568 /* Program the interval scanning counter to run at the sample
571 loutb(BMODE(ctlr), 0x74);
572 loutb(B1DATA(ctlr), (u_char)((ctlr->sample_us & 0xff)));
573 loutb(B1DATA(ctlr), (u_char)((ctlr->sample_us >> 8)&0xff));
574 CR_EXPR(ctlr, 1, |= SCANEN);
580 /* Each frame time takes two microseconds per channel times
581 * the number of channels being sampled plus the sample period.
583 ctlr->tmo = ((n_frames + 16) *
584 ((long)ctlr->sample_us + (chan + 1 ) * 2 ) * hz) / 1000000 +
589 all_stop(struct ctlr *ctlr)
597 struct ctlr *ctlr = (struct ctlr *)p;
604 printf("labpc?: Null ctlr struct?\n");
609 printf("labpc%d: timeout", ctlr->unit);
613 bp = ctlr->start_queue.b_actf;
616 printf(", Null bp.\n");
623 done_and_start_next(ctlr, bp, ETIMEDOUT);
628 static void ad_intr(struct ctlr *ctlr)
632 if (ctlr->cr_image[2] == 0)
634 if (ctlr->cleared_intr)
636 ctlr->cleared_intr = 0;
640 printf("ad_intr (should not happen) interrupt with interrupts off\n");
641 printf("status %x, cr3 %x\n", inb(STATUS(ctlr)), ctlr->cr_image[2]);
645 while ( (status = (inb(STATUS(ctlr)) & (DAVAIL|OVERRUN|OVERFLOW)) ) )
647 if ((status & (OVERRUN|OVERFLOW)))
649 struct buf *bp = ctlr->start_queue.b_actf;
651 printf("ad_intr: error: bp %p, data %p, status %x",
652 (void *)bp, (void *)ctlr->data, status);
654 if (status & OVERRUN)
655 printf(" Conversion overrun (multiple A-D trigger)");
657 if (status & OVERFLOW)
658 printf(" FIFO overflow");
664 done_and_start_next(ctlr, bp, EIO);
669 printf("ad_intr: (should not happen) error between records\n");
670 ctlr->err = status; /* Set overrun condition */
674 else /* FIFO interrupt */
676 struct buf *bp = ctlr->start_queue.b_actf;
680 *ctlr->data++ = inb(ADFIFO(ctlr));
681 if (ctlr->data == ctlr->data_end) /* Normal completion */
683 done_and_start_next(ctlr, bp, 0);
687 else /* Interrupt with no where to put the data. */
689 printf("ad_intr: (should not happen) dropped input.\n");
690 (void)inb(ADFIFO(ctlr));
692 printf("bp %p, status %x, cr3 %x\n",
693 (void *)bp, status, ctlr->cr_image[2]);
695 ctlr->err = DROPPED_INPUT;
702 static void labpcintr(int unit)
704 struct ctlr *ctlr = labpcs[unit];
708 /* lockout_multiple_opens: Return whether or not we can open again, or
709 * if the new mode is inconsistent with an already opened mode.
710 * We only permit multiple opens for digital I/O now.
714 lockout_multiple_open(dev_t current, dev_t next)
716 return ! (DIGITAL(current) && DIGITAL(next));
720 labpcopen(dev_t dev, int flags, int fmt, struct proc *p)
722 u_short unit = UNIT(dev);
726 if (unit >= MAX_UNITS)
734 /* Don't allow another open if we have to change modes.
737 if ( (ctlr->flags & BUSY) == 0)
746 ctlr->intr = null_intr;
747 ctlr->starter = null_start;
748 ctlr->stop = null_stop;
750 else if (lockout_multiple_open(ctlr->dev, dev))
757 labpcclose(dev_t dev, int flags, int fmt, struct proc *p)
759 struct ctlr *ctlr = labpcs[UNIT(dev)];
763 ctlr->flags &= ~BUSY;
769 * Start: Start a frame going in or out.
772 start(struct ctlr *ctlr)
776 if ((bp = ctlr->start_queue.b_actf) == 0)
778 /* We must turn off FIFO interrupts when there is no
779 * place to put the data. We have to get back to
780 * reading before the FIFO overflows.
782 CR_EXPR(ctlr, 3, &= ~(FIFOINTEN|ERRINTEN));
783 ctlr->cleared_intr = 1;
784 ctlr->start_queue.b_bcount = 0;
788 ctlr->data = (u_char *)bp->b_data;
789 ctlr->data_end = ctlr->data + bp->b_bcount;
793 printf("labpc start: (should not happen) error between records.\n");
794 done_and_start_next(ctlr, bp, EIO);
800 printf("labpc start: (should not happen) NULL data pointer.\n");
801 done_and_start_next(ctlr, bp, EIO);
806 (*ctlr->starter)(ctlr, bp->b_bcount);
808 if (!FIFOINTENABLED(ctlr)) /* We can store the data again */
810 CR_EXPR(ctlr, 3, |= (FIFOINTEN|ERRINTEN));
812 /* Don't wait for the interrupts to fill things up.
817 ctlr->ch = timeout(tmo_stop, ctlr, ctlr->tmo);
821 ad_strategy(struct buf *bp, struct ctlr *ctlr)
828 if (ctlr->start_queue.b_bcount)
830 ctlr->last->b_actf = bp;
835 ctlr->start_queue.b_bcount = 1;
836 ctlr->start_queue.b_actf = bp;
843 /* da_strategy: Send data to the D-A. The CHAN field should be
846 * 2: Alternate port 0 then port 1
850 * 1. There is no state for CHAN field 2:
851 * the first sample in each buffer goes to channel 0.
853 * 2. No interrupt support yet.
856 da_strategy(struct buf *bp, struct ctlr *ctlr)
863 switch(CHAN(bp->b_dev))
873 case 2: /* Device 2 handles both ports interleaved. */
874 if (bp->b_bcount <= 2)
880 len = bp->b_bcount / 2;
881 data = (u_char *)bp->b_data;
883 for (i = 0; i < len; i++)
885 loutb(DAC0H(ctlr), *data++);
886 loutb(DAC0L(ctlr), *data++);
887 loutb(DAC1H(ctlr), *data++);
888 loutb(DAC1L(ctlr), *data++);
891 bp->b_resid = bp->b_bcount & 3;
900 /* Port 0 or 1 falls through to here.
902 if (bp->b_bcount & 1) /* Odd transfers are illegal */
906 data = (u_char *)bp->b_data;
908 for (i = 0; i < len; i++)
910 loutb(port + 1, *data++);
911 loutb(port, *data++);
919 /* Input masks for MODE 0 of the ports treating PC as a single
920 * 8 bit port. Set these bits to set the port to input.
922 /* A B lowc highc combined */
923 static u_char set_input[] = { 0x10, 0x02, 0x01, 0x08, 0x09 };
925 static void flush_dcr(struct ctlr *ctlr)
927 if (ctlr->dcr_is != ctlr->dcr_val)
929 loutb(DCR(ctlr), ctlr->dcr_val);
930 ctlr->dcr_is = ctlr->dcr_val;
934 /* do: Digital output
937 digital_out_strategy(struct buf *bp, struct ctlr *ctlr)
943 int chan = CHAN(bp->b_dev);
945 ctlr->dcr_val &= ~set_input[chan]; /* Digital out: Clear bit */
948 port = PORTX(ctlr, chan);
951 data = (u_char *)bp->b_data;
953 for (i = 0; i < len; i++)
955 loutb(port, *data++);
963 /* digital_in_strategy: Digital input
966 digital_in_strategy(struct buf *bp, struct ctlr *ctlr)
972 int chan = CHAN(bp->b_dev);
974 ctlr->dcr_val |= set_input[chan]; /* Digital in: Set bit */
976 port = PORTX(ctlr, chan);
979 data = (u_char *)bp->b_data;
981 for (i = 0; i < len; i++)
993 labpcstrategy(struct buf *bp)
995 struct ctlr *ctlr = labpcs[UNIT(bp->b_dev)];
997 if (DIGITAL(bp->b_dev)) {
998 if (bp->b_flags & B_READ) {
999 ctlr->starter = null_start;
1000 ctlr->stop = all_stop;
1001 ctlr->intr = null_intr;
1002 digital_in_strategy(bp, ctlr);
1006 ctlr->starter = null_start;
1007 ctlr->stop = all_stop;
1008 ctlr->intr = null_intr;
1009 digital_out_strategy(bp, ctlr);
1013 if (bp->b_flags & B_READ) {
1015 ctlr->starter = INTERVAL(ctlr->dev) ? ad_interval_start : ad_start;
1016 ctlr->stop = all_stop;
1017 ctlr->intr = ad_intr;
1018 ad_strategy(bp, ctlr);
1022 ctlr->starter = null_start;
1023 ctlr->stop = all_stop;
1024 ctlr->intr = null_intr;
1025 da_strategy(bp, ctlr);
1031 labpcioctl(dev_t dev, u_long cmd, caddr_t arg, int mode, struct proc *p)
1033 struct ctlr *ctlr = labpcs[UNIT(dev)];
1037 case AD_MICRO_PERIOD_SET:
1039 /* XXX I'm only supporting what I have to, which is
1040 * no slow periods. You can't get any slower than 15 Hz
1041 * with the current setup. To go slower you'll need to
1042 * support TCINTEN in CR3.
1045 long sample_us = *(long *)arg;
1047 if (sample_us > 65535)
1050 ctlr->sample_us = sample_us;
1054 case AD_MICRO_PERIOD_GET:
1055 *(long *)arg = ctlr->sample_us;
1066 case AD_SUPPORTED_GAINS:
1068 static double gains[] = {1., 1.25, 2., 5., 10., 20., 50., 100.};
1069 copyout(gains, *(caddr_t *)arg, sizeof(gains));
1076 copyin(*(caddr_t *)arg, ctlr->gains, sizeof(ctlr->gains));
1082 copyout(ctlr->gains, *(caddr_t *)arg, sizeof(ctlr->gains));