2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.40 2008/09/17 08:51:29 sephe Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/interrupt.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/queue.h>
46 #include <sys/thread2.h>
49 #include <net/ifq_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
71 #include <dev/netif/bfe/if_bfereg.h>
73 MODULE_DEPEND(bfe, pci, 1, 1, 1);
74 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
76 /* "controller miibus0" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
81 static struct bfe_type bfe_devs[] = {
82 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
83 "Broadcom BCM4401 Fast Ethernet" },
84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
85 "Broadcom BCM4401-B0 Fast Ethernet" },
86 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
87 "Broadcom BCM4402 Fast Ethernet" },
91 static int bfe_probe(device_t);
92 static int bfe_attach(device_t);
93 static int bfe_detach(device_t);
94 static void bfe_intr(void *);
95 static void bfe_start(struct ifnet *);
96 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
97 static void bfe_init(void *);
98 static void bfe_stop(struct bfe_softc *);
99 static void bfe_watchdog(struct ifnet *);
100 static void bfe_shutdown(device_t);
101 static void bfe_tick(void *);
102 static void bfe_txeof(struct bfe_softc *);
103 static void bfe_rxeof(struct bfe_softc *);
104 static void bfe_set_rx_mode(struct bfe_softc *);
105 static int bfe_list_rx_init(struct bfe_softc *);
106 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
107 static void bfe_rx_ring_free(struct bfe_softc *);
109 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
110 static int bfe_ifmedia_upd(struct ifnet *);
111 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
112 static int bfe_miibus_readreg(device_t, int, int);
113 static int bfe_miibus_writereg(device_t, int, int, int);
114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
116 static void bfe_get_config(struct bfe_softc *sc);
117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
118 static void bfe_stats_update(struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
122 static int bfe_resetphy(struct bfe_softc *);
123 static int bfe_setupphy(struct bfe_softc *);
124 static void bfe_chip_reset(struct bfe_softc *);
125 static void bfe_chip_halt(struct bfe_softc *);
126 static void bfe_core_reset(struct bfe_softc *);
127 static void bfe_core_disable(struct bfe_softc *);
128 static int bfe_dma_alloc(device_t);
129 static void bfe_dma_free(struct bfe_softc *);
130 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
131 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
132 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
134 static device_method_t bfe_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_probe, bfe_probe),
137 DEVMETHOD(device_attach, bfe_attach),
138 DEVMETHOD(device_detach, bfe_detach),
139 DEVMETHOD(device_shutdown, bfe_shutdown),
142 DEVMETHOD(bus_print_child, bus_generic_print_child),
143 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
152 static driver_t bfe_driver = {
155 sizeof(struct bfe_softc)
158 static devclass_t bfe_devclass;
160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
164 * Probe for a Broadcom 4401 chip.
167 bfe_probe(device_t dev)
170 uint16_t vendor, product;
172 vendor = pci_get_vendor(dev);
173 product = pci_get_device(dev);
175 for (t = bfe_devs; t->bfe_name != NULL; t++) {
176 if (vendor == t->bfe_vid && product == t->bfe_did) {
177 device_set_desc(dev, t->bfe_name);
186 bfe_dma_alloc(device_t dev)
188 struct bfe_softc *sc = device_get_softc(dev);
189 int error, i, tx_pos = 0, rx_pos = 0;
192 * Parent tag. Apparently the chip cannot handle any DMA address
193 * greater than BFE_BUS_SPACE_MAXADDR (1GB).
195 error = bus_dma_tag_create(NULL, /* parent */
196 1, 0, /* alignment, boundary */
197 BFE_BUS_SPACE_MAXADDR, /* lowaddr */
198 BUS_SPACE_MAXADDR, /* highaddr */
199 NULL, NULL, /* filter, filterarg */
200 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
201 0, /* num of segments */
202 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
204 &sc->bfe_parent_tag);
206 device_printf(dev, "could not allocate parent dma tag\n");
210 /* tag for TX ring */
211 error = bus_dma_tag_create(sc->bfe_parent_tag, PAGE_SIZE, 0,
212 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
214 BFE_TX_LIST_SIZE, 1, BFE_TX_LIST_SIZE,
217 device_printf(dev, "could not allocate dma tag for TX list\n");
221 /* tag for RX ring */
222 error = bus_dma_tag_create(sc->bfe_parent_tag, PAGE_SIZE, 0,
223 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
225 BFE_RX_LIST_SIZE, 1, BFE_RX_LIST_SIZE,
228 device_printf(dev, "could not allocate dma tag for RX list\n");
232 /* Tag for RX mbufs */
233 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
234 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
236 MCLBYTES, 1, MCLBYTES,
237 BUS_DMA_ALLOCNOW, &sc->bfe_rxbuf_tag);
239 device_printf(dev, "could not allocate dma tag for RX mbufs\n");
243 error = bus_dmamap_create(sc->bfe_rxbuf_tag, 0, &sc->bfe_rx_tmpmap);
245 device_printf(dev, "could not create RX mbuf tmp map\n");
246 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
247 sc->bfe_rxbuf_tag = NULL;
251 /* Allocate dma maps for RX list */
252 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
253 error = bus_dmamap_create(sc->bfe_rxbuf_tag, 0,
254 &sc->bfe_rx_ring[i].bfe_map);
257 device_printf(dev, "cannot create DMA map for RX\n");
261 rx_pos = BFE_RX_LIST_CNT;
263 /* Tag for TX mbufs */
264 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
265 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
267 MCLBYTES, 1, MCLBYTES,
268 BUS_DMA_ALLOCNOW, &sc->bfe_txbuf_tag);
270 device_printf(dev, "could not allocate dma tag for TX mbufs\n");
274 /* Allocate dmamaps for TX list */
275 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
276 error = bus_dmamap_create(sc->bfe_txbuf_tag, 0,
277 &sc->bfe_tx_ring[i].bfe_map);
280 device_printf(dev, "cannot create DMA map for TX\n");
285 /* Alloc dma for rx ring */
286 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
287 BUS_DMA_WAITOK | BUS_DMA_ZERO,
290 device_printf(dev, "cannot allocate DMA mem for RX\n");
294 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
295 sc->bfe_rx_list, sizeof(struct bfe_desc),
296 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK);
298 device_printf(dev, "cannot load DMA map for RX\n");
302 /* Alloc dma for tx ring */
303 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
304 BUS_DMA_WAITOK | BUS_DMA_ZERO,
307 device_printf(dev, "cannot allocate DMA mem for TX\n");
311 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
312 sc->bfe_tx_list, sizeof(struct bfe_desc),
313 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK);
315 device_printf(dev, "cannot load DMA map for TX\n");
322 if (sc->bfe_rxbuf_tag != NULL) {
323 for (i = 0; i < rx_pos; ++i) {
324 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
325 sc->bfe_rx_ring[i].bfe_map);
327 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
328 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
329 sc->bfe_rxbuf_tag = NULL;
332 if (sc->bfe_txbuf_tag != NULL) {
333 for (i = 0; i < tx_pos; ++i) {
334 bus_dmamap_destroy(sc->bfe_txbuf_tag,
335 sc->bfe_tx_ring[i].bfe_map);
337 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
338 sc->bfe_txbuf_tag = NULL;
344 bfe_attach(device_t dev)
347 struct bfe_softc *sc;
350 sc = device_get_softc(dev);
353 callout_init(&sc->bfe_stat_timer);
357 * Handle power management nonsense.
359 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
360 uint32_t membase, irq;
362 /* Save important PCI config data. */
363 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
364 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
366 /* Reset the power state. */
367 device_printf(dev, "chip is in D%d power mode"
368 " -- setting to D0\n", pci_get_powerstate(dev));
370 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
372 /* Restore PCI config data. */
373 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
374 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
376 #endif /* !BURN_BRIDGE */
379 * Map control/status registers.
381 pci_enable_busmaster(dev);
384 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
386 if (sc->bfe_res == NULL) {
387 device_printf(dev, "couldn't map memory\n");
391 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
392 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
394 /* Allocate interrupt */
397 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
398 RF_SHAREABLE | RF_ACTIVE);
399 if (sc->bfe_irq == NULL) {
400 device_printf(dev, "couldn't map interrupt\n");
405 error = bfe_dma_alloc(dev);
407 device_printf(dev, "failed to allocate DMA resources\n");
411 /* Set up ifnet structure */
412 ifp = &sc->arpcom.ac_if;
414 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
415 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
416 ifp->if_ioctl = bfe_ioctl;
417 ifp->if_start = bfe_start;
418 ifp->if_watchdog = bfe_watchdog;
419 ifp->if_init = bfe_init;
420 ifp->if_mtu = ETHERMTU;
421 ifp->if_baudrate = 100000000;
422 ifp->if_capabilities |= IFCAP_VLAN_MTU;
423 ifp->if_capenable |= IFCAP_VLAN_MTU;
424 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
425 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
426 ifq_set_ready(&ifp->if_snd);
430 /* Reset the chip and turn on the PHY */
433 if (mii_phy_probe(dev, &sc->bfe_miibus,
434 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
435 device_printf(dev, "MII without any PHY!\n");
440 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
443 * Hook interrupt last to avoid having to lock softc
445 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
446 bfe_intr, sc, &sc->bfe_intrhand,
447 sc->arpcom.ac_if.if_serializer);
451 device_printf(dev, "couldn't set up irq\n");
455 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq));
456 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
464 bfe_detach(device_t dev)
466 struct bfe_softc *sc = device_get_softc(dev);
467 struct ifnet *ifp = &sc->arpcom.ac_if;
469 if (device_is_attached(dev)) {
470 lwkt_serialize_enter(ifp->if_serializer);
473 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
474 lwkt_serialize_exit(ifp->if_serializer);
478 if (sc->bfe_miibus != NULL)
479 device_delete_child(dev, sc->bfe_miibus);
480 bus_generic_detach(dev);
482 if (sc->bfe_irq != NULL)
483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
485 if (sc->bfe_res != NULL) {
486 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
495 * Stop all chip I/O so that the kernel's probe routines don't
496 * get confused by errant DMAs when rebooting.
499 bfe_shutdown(device_t dev)
501 struct bfe_softc *sc = device_get_softc(dev);
502 struct ifnet *ifp = &sc->arpcom.ac_if;
504 lwkt_serialize_enter(ifp->if_serializer);
506 lwkt_serialize_exit(ifp->if_serializer);
510 bfe_miibus_readreg(device_t dev, int phy, int reg)
512 struct bfe_softc *sc;
515 sc = device_get_softc(dev);
516 if (phy != sc->bfe_phyaddr)
518 bfe_readphy(sc, reg, &ret);
524 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
526 struct bfe_softc *sc;
528 sc = device_get_softc(dev);
529 if (phy != sc->bfe_phyaddr)
531 bfe_writephy(sc, reg, val);
537 bfe_tx_ring_free(struct bfe_softc *sc)
541 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
542 bus_dmamap_unload(sc->bfe_txbuf_tag,
543 sc->bfe_tx_ring[i].bfe_map);
544 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
545 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
546 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
549 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
550 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
554 bfe_rx_ring_free(struct bfe_softc *sc)
558 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
559 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
560 bus_dmamap_unload(sc->bfe_rxbuf_tag,
561 sc->bfe_rx_ring[i].bfe_map);
562 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
563 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
566 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
567 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
571 bfe_list_rx_init(struct bfe_softc *sc)
575 for (i = 0; i < BFE_RX_LIST_CNT; i++)
576 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
579 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
580 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
588 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
590 struct bfe_rxheader *rx_header;
595 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
599 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
602 m->m_len = m->m_pkthdr.len = MCLBYTES;
605 m->m_data = m->m_ext.ext_buf;
607 rx_header = mtod(m, struct bfe_rxheader *);
609 rx_header->flags = 0;
611 /* Map the mbuf into DMA */
612 d = &sc->bfe_rx_list[c];
613 r = &sc->bfe_rx_ring[c];
615 bus_dmamap_load(sc->bfe_rxbuf_tag, r->bfe_map, mtod(m, void *),
616 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT);
617 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
619 ctrl = ETHER_MAX_LEN + 32;
621 if(c == BFE_RX_LIST_CNT - 1)
622 ctrl |= BFE_DESC_EOT;
626 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
631 bfe_get_config(struct bfe_softc *sc)
635 bfe_read_eeprom(sc, eeprom);
637 sc->arpcom.ac_enaddr[0] = eeprom[79];
638 sc->arpcom.ac_enaddr[1] = eeprom[78];
639 sc->arpcom.ac_enaddr[2] = eeprom[81];
640 sc->arpcom.ac_enaddr[3] = eeprom[80];
641 sc->arpcom.ac_enaddr[4] = eeprom[83];
642 sc->arpcom.ac_enaddr[5] = eeprom[82];
644 sc->bfe_phyaddr = eeprom[90] & 0x1f;
645 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
647 sc->bfe_core_unit = 0;
648 sc->bfe_dma_offset = BFE_PCI_DMA;
652 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
654 uint32_t bar_orig, pci_rev, val;
656 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
657 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
658 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
660 val = CSR_READ_4(sc, BFE_SBINTVEC);
662 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
664 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
665 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
666 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
668 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
672 bfe_clear_stats(struct bfe_softc *sc)
676 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
677 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
679 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
684 bfe_resetphy(struct bfe_softc *sc)
688 bfe_writephy(sc, 0, BMCR_RESET);
690 bfe_readphy(sc, 0, &val);
691 if (val & BMCR_RESET) {
692 if_printf(&sc->arpcom.ac_if,
693 "PHY Reset would not complete.\n");
700 bfe_chip_halt(struct bfe_softc *sc)
702 /* disable interrupts - not that it actually does..*/
703 CSR_WRITE_4(sc, BFE_IMASK, 0);
704 CSR_READ_4(sc, BFE_IMASK);
706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
709 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
715 bfe_chip_reset(struct bfe_softc *sc)
719 /* Set the interrupt vector for the enet core */
720 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
723 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
724 if (val == BFE_CLOCK) {
725 /* It is, so shut it down */
726 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
727 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
728 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
729 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
730 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
731 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
732 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
733 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
741 * We want the phy registers to be accessible even when
742 * the driver is "downed" so initialize MDC preamble, frequency,
743 * and whether internal or external phy here.
746 /* 4402 has 62.5Mhz SB clock and internal phy */
747 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
749 /* Internal or external PHY? */
750 val = CSR_READ_4(sc, BFE_DEVCTRL);
751 if (!(val & BFE_IPP))
752 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
753 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
754 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
758 /* Enable CRC32 generation and set proper LED modes */
759 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
761 /* Reset or clear powerdown control bit */
762 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
764 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
768 * We don't want lazy interrupts, so just send them at the end of a
771 BFE_OR(sc, BFE_RCV_LAZY, 0);
773 /* Set max lengths, accounting for VLAN tags */
774 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
775 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
777 /* Set watermark XXX - magic */
778 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
781 * Initialise DMA channels - not forgetting dma addresses need to be
782 * added to BFE_PCI_DMA
784 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
785 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
787 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
789 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
796 bfe_core_disable(struct bfe_softc *sc)
798 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
802 * Set reject, wait for it set, then wait for the core to stop being busy
803 * Then set reset and reject and enable the clocks
805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
806 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
807 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
808 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
810 CSR_READ_4(sc, BFE_SBTMSLOW);
812 /* Leave reset and reject set */
813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
818 bfe_core_reset(struct bfe_softc *sc)
822 /* Disable the core */
823 bfe_core_disable(sc);
825 /* and bring it back up */
826 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
827 CSR_READ_4(sc, BFE_SBTMSLOW);
830 /* Chip bug, clear SERR, IB and TO if they are set. */
831 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
832 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
833 val = CSR_READ_4(sc, BFE_SBIMSTATE);
834 if (val & (BFE_IBE | BFE_TO))
835 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
837 /* Clear reset and allow it to move through the core */
838 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
839 CSR_READ_4(sc, BFE_SBTMSLOW);
842 /* Leave the clock set */
843 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
844 CSR_READ_4(sc, BFE_SBTMSLOW);
849 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
853 val = ((uint32_t) data[2]) << 24;
854 val |= ((uint32_t) data[3]) << 16;
855 val |= ((uint32_t) data[4]) << 8;
856 val |= ((uint32_t) data[5]);
857 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
858 val = (BFE_CAM_HI_VALID |
859 (((uint32_t) data[0]) << 8) |
860 (((uint32_t) data[1])));
861 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
862 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
863 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
864 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
868 bfe_set_rx_mode(struct bfe_softc *sc)
870 struct ifnet *ifp = &sc->arpcom.ac_if;
871 struct ifmultiaddr *ifma;
875 val = CSR_READ_4(sc, BFE_RXCONF);
877 if (ifp->if_flags & IFF_PROMISC)
878 val |= BFE_RXCONF_PROMISC;
880 val &= ~BFE_RXCONF_PROMISC;
882 if (ifp->if_flags & IFF_BROADCAST)
883 val &= ~BFE_RXCONF_DBCAST;
885 val |= BFE_RXCONF_DBCAST;
888 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
889 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
891 if (ifp->if_flags & IFF_ALLMULTI) {
892 val |= BFE_RXCONF_ALLMULTI;
894 val &= ~BFE_RXCONF_ALLMULTI;
895 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
896 if (ifma->ifma_addr->sa_family != AF_LINK)
899 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
903 CSR_WRITE_4(sc, BFE_RXCONF, val);
904 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
908 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
913 *ptr = segs->ds_addr;
917 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
922 /* The chip needs all addresses to be added to BFE_PCI_DMA */
923 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
927 bfe_dma_free(struct bfe_softc *sc)
931 if (sc->bfe_tx_tag != NULL) {
932 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
933 if (sc->bfe_tx_list != NULL) {
934 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
936 sc->bfe_tx_list = NULL;
938 bus_dma_tag_destroy(sc->bfe_tx_tag);
939 sc->bfe_tx_tag = NULL;
942 if (sc->bfe_rx_tag != NULL) {
943 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
944 if (sc->bfe_rx_list != NULL) {
945 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
947 sc->bfe_rx_list = NULL;
949 bus_dma_tag_destroy(sc->bfe_rx_tag);
950 sc->bfe_rx_tag = NULL;
953 if (sc->bfe_txbuf_tag != NULL) {
954 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
955 bus_dmamap_destroy(sc->bfe_txbuf_tag,
956 sc->bfe_tx_ring[i].bfe_map);
958 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
959 sc->bfe_txbuf_tag = NULL;
962 if (sc->bfe_rxbuf_tag != NULL) {
963 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
964 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
965 sc->bfe_rx_ring[i].bfe_map);
967 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
968 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
969 sc->bfe_rxbuf_tag = NULL;
972 if (sc->bfe_parent_tag != NULL) {
973 bus_dma_tag_destroy(sc->bfe_parent_tag);
974 sc->bfe_parent_tag = NULL;
979 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
982 uint16_t *ptr = (uint16_t *)data;
984 for (i = 0; i < 128; i += 2)
985 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
989 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
990 u_long timeout, const int clear)
994 for (i = 0; i < timeout; i++) {
995 uint32_t val = CSR_READ_4(sc, reg);
997 if (clear && !(val & bit))
999 if (!clear && (val & bit))
1004 if_printf(&sc->arpcom.ac_if,
1005 "BUG! Timeout waiting for bit %08x of register "
1006 "%x to %s.\n", bit, reg,
1007 (clear ? "clear" : "set"));
1014 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
1019 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1020 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1021 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1022 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1023 (reg << BFE_MDIO_RA_SHIFT) |
1024 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1025 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1026 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1031 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1035 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1036 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1037 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1038 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1039 (reg << BFE_MDIO_RA_SHIFT) |
1040 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1041 (val & BFE_MDIO_DATA_DATA)));
1042 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1048 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1052 bfe_setupphy(struct bfe_softc *sc)
1056 /* Enable activity LED */
1057 bfe_readphy(sc, 26, &val);
1058 bfe_writephy(sc, 26, val & 0x7fff);
1059 bfe_readphy(sc, 26, &val);
1061 /* Enable traffic meter LED mode */
1062 bfe_readphy(sc, 27, &val);
1063 bfe_writephy(sc, 27, val | (1 << 6));
1069 bfe_stats_update(struct bfe_softc *sc)
1074 val = &sc->bfe_hwstats.tx_good_octets;
1075 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1076 *val++ += CSR_READ_4(sc, reg);
1077 val = &sc->bfe_hwstats.rx_good_octets;
1078 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1079 *val++ += CSR_READ_4(sc, reg);
1083 bfe_txeof(struct bfe_softc *sc)
1085 struct ifnet *ifp = &sc->arpcom.ac_if;
1086 uint32_t i, chipidx;
1088 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1089 chipidx /= sizeof(struct bfe_desc);
1091 i = sc->bfe_tx_cons;
1092 /* Go through the mbufs and free those that have been transmitted */
1093 while (i != chipidx) {
1094 struct bfe_data *r = &sc->bfe_tx_ring[i];
1096 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map);
1097 if (r->bfe_mbuf != NULL) {
1099 m_freem(r->bfe_mbuf);
1103 BFE_INC(i, BFE_TX_LIST_CNT);
1106 if (i != sc->bfe_tx_cons) {
1107 /* we freed up some mbufs */
1108 sc->bfe_tx_cons = i;
1109 ifp->if_flags &= ~IFF_OACTIVE;
1111 if (sc->bfe_tx_cnt == 0)
1117 /* Pass a received packet up the stack */
1119 bfe_rxeof(struct bfe_softc *sc)
1121 struct ifnet *ifp = &sc->arpcom.ac_if;
1123 struct bfe_rxheader *rxheader;
1125 uint32_t cons, status, current, len, flags;
1126 struct mbuf_chain chain[MAXCPU];
1128 cons = sc->bfe_rx_cons;
1129 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1130 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1132 ether_input_chain_init(chain);
1134 while (current != cons) {
1135 r = &sc->bfe_rx_ring[cons];
1137 rxheader = mtod(m, struct bfe_rxheader*);
1138 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_POSTREAD);
1139 len = rxheader->len;
1142 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map);
1143 flags = rxheader->flags;
1145 len -= ETHER_CRC_LEN;
1147 /* flag an error and try again */
1148 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1150 if (flags & BFE_RX_FLAG_SERR)
1151 ifp->if_collisions++;
1152 bfe_list_newbuf(sc, cons, m);
1153 BFE_INC(cons, BFE_RX_LIST_CNT);
1157 /* Go past the rx header */
1158 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1159 bfe_list_newbuf(sc, cons, m);
1160 BFE_INC(cons, BFE_RX_LIST_CNT);
1165 m_adj(m, BFE_RX_OFFSET);
1166 m->m_len = m->m_pkthdr.len = len;
1169 m->m_pkthdr.rcvif = ifp;
1171 ether_input_chain(ifp, m, chain);
1172 BFE_INC(cons, BFE_RX_LIST_CNT);
1175 ether_input_dispatch(chain);
1177 sc->bfe_rx_cons = cons;
1183 struct bfe_softc *sc = xsc;
1184 struct ifnet *ifp = &sc->arpcom.ac_if;
1185 uint32_t istat, imask, flag;
1187 istat = CSR_READ_4(sc, BFE_ISTAT);
1188 imask = CSR_READ_4(sc, BFE_IMASK);
1191 * Defer unsolicited interrupts - This is necessary because setting the
1192 * chips interrupt mask register to 0 doesn't actually stop the
1196 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1197 CSR_READ_4(sc, BFE_ISTAT);
1199 /* not expecting this interrupt, disregard it */
1204 if (istat & BFE_ISTAT_ERRORS) {
1205 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1206 if (flag & BFE_STAT_EMASK)
1209 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1210 if (flag & BFE_RX_FLAG_ERRORS)
1213 ifp->if_flags &= ~IFF_RUNNING;
1217 /* A packet was received */
1218 if (istat & BFE_ISTAT_RX)
1221 /* A packet was sent */
1222 if (istat & BFE_ISTAT_TX)
1225 /* We have packets pending, fire them out */
1226 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1231 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1233 struct bfe_desc *d = NULL;
1234 struct bfe_data *r = NULL;
1236 uint32_t frag, cur, cnt = 0;
1237 int error, chainlen = 0;
1239 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt));
1242 * Count the number of frags in this chain to see if
1243 * we need to m_defrag. Since the descriptor list is shared
1244 * by all packets, we'll m_defrag long chains so that they
1245 * do not use up the entire list, even if they would fit.
1247 for (m = *m_head; m != NULL; m = m->m_next)
1250 if (chainlen > (BFE_TX_LIST_CNT / 4) ||
1251 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) {
1252 m = m_defrag(*m_head, MB_DONTWAIT);
1261 * Start packing the mbufs in this chain into
1262 * the fragment pointers. Stop when we run out
1263 * of fragments or hit the end of the mbuf chain.
1265 cur = frag = *txidx;
1268 for (m = *m_head; m != NULL; m = m->m_next) {
1269 if (m->m_len != 0) {
1270 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt));
1272 d = &sc->bfe_tx_list[cur];
1273 r = &sc->bfe_tx_ring[cur];
1274 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1275 /* always intterupt on completion */
1276 d->bfe_ctrl |= BFE_DESC_IOC;
1278 /* Set start of frame */
1279 d->bfe_ctrl |= BFE_DESC_SOF;
1281 if (cur == BFE_TX_LIST_CNT - 1) {
1283 * Tell the chip to wrap to the start of the
1286 d->bfe_ctrl |= BFE_DESC_EOT;
1289 error = bus_dmamap_load(sc->bfe_txbuf_tag, r->bfe_map,
1290 mtod(m, void *), m->m_len,
1291 bfe_dma_map_desc, d,
1294 /* XXX This should be a fatal error. */
1295 if_printf(&sc->arpcom.ac_if,
1296 "%s bus_dmamap_load failed: %d",
1302 bus_dmamap_sync(sc->bfe_txbuf_tag, r->bfe_map,
1303 BUS_DMASYNC_PREWRITE);
1306 BFE_INC(cur, BFE_TX_LIST_CNT);
1311 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1312 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head;
1313 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
1316 sc->bfe_tx_cnt += cnt;
1321 * Set up to transmit a packet
1324 bfe_start(struct ifnet *ifp)
1326 struct bfe_softc *sc = ifp->if_softc;
1327 struct mbuf *m_head = NULL;
1328 int idx, need_trans;
1330 ASSERT_SERIALIZED(ifp->if_serializer);
1333 * Not much point trying to send if the link is down
1334 * or we have nothing to send.
1336 if (!sc->bfe_link) {
1337 ifq_purge(&ifp->if_snd);
1341 if (ifp->if_flags & IFF_OACTIVE)
1344 idx = sc->bfe_tx_prod;
1347 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1348 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) {
1349 ifp->if_flags |= IFF_OACTIVE;
1353 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1358 * Pack the data into the tx ring. If we don't have
1359 * enough room, let the chip drain the ring.
1361 if (bfe_encap(sc, &m_head, &idx)) {
1362 ifp->if_flags |= IFF_OACTIVE;
1368 * If there's a BPF listener, bounce a copy of this frame
1371 BPF_MTAP(ifp, m_head);
1377 sc->bfe_tx_prod = idx;
1378 /* Transmit - twice due to apparent hardware bug */
1379 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1380 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1383 * Set a timeout in case the chip goes out to lunch.
1391 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1392 struct ifnet *ifp = &sc->arpcom.ac_if;
1394 ASSERT_SERIALIZED(ifp->if_serializer);
1396 if (ifp->if_flags & IFF_RUNNING)
1402 if (bfe_list_rx_init(sc) == ENOBUFS) {
1403 if_printf(ifp, "bfe_init failed. "
1404 " Not enough memory for list buffers\n");
1409 bfe_set_rx_mode(sc);
1411 /* Enable the chip and core */
1412 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1413 /* Enable interrupts */
1414 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1416 bfe_ifmedia_upd(ifp);
1417 ifp->if_flags |= IFF_RUNNING;
1418 ifp->if_flags &= ~IFF_OACTIVE;
1420 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1424 * Set media options.
1427 bfe_ifmedia_upd(struct ifnet *ifp)
1429 struct bfe_softc *sc = ifp->if_softc;
1430 struct mii_data *mii;
1432 ASSERT_SERIALIZED(ifp->if_serializer);
1434 mii = device_get_softc(sc->bfe_miibus);
1436 if (mii->mii_instance) {
1437 struct mii_softc *miisc;
1438 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1439 miisc = LIST_NEXT(miisc, mii_list))
1440 mii_phy_reset(miisc);
1450 * Report current media status.
1453 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1455 struct bfe_softc *sc = ifp->if_softc;
1456 struct mii_data *mii;
1458 ASSERT_SERIALIZED(ifp->if_serializer);
1460 mii = device_get_softc(sc->bfe_miibus);
1462 ifmr->ifm_active = mii->mii_media_active;
1463 ifmr->ifm_status = mii->mii_media_status;
1467 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1469 struct bfe_softc *sc = ifp->if_softc;
1470 struct ifreq *ifr = (struct ifreq *) data;
1471 struct mii_data *mii;
1474 ASSERT_SERIALIZED(ifp->if_serializer);
1478 if (ifp->if_flags & IFF_UP)
1479 if (ifp->if_flags & IFF_RUNNING)
1480 bfe_set_rx_mode(sc);
1483 else if (ifp->if_flags & IFF_RUNNING)
1488 if (ifp->if_flags & IFF_RUNNING)
1489 bfe_set_rx_mode(sc);
1493 mii = device_get_softc(sc->bfe_miibus);
1494 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1498 error = ether_ioctl(ifp, command, data);
1505 bfe_watchdog(struct ifnet *ifp)
1507 struct bfe_softc *sc = ifp->if_softc;
1509 ASSERT_SERIALIZED(ifp->if_serializer);
1511 if_printf(ifp, "watchdog timeout -- resetting\n");
1513 ifp->if_flags &= ~IFF_RUNNING;
1522 struct bfe_softc *sc = xsc;
1523 struct mii_data *mii;
1524 struct ifnet *ifp = &sc->arpcom.ac_if;
1526 mii = device_get_softc(sc->bfe_miibus);
1528 lwkt_serialize_enter(ifp->if_serializer);
1530 bfe_stats_update(sc);
1531 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1533 if (sc->bfe_link == 0) {
1535 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1536 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1542 lwkt_serialize_exit(ifp->if_serializer);
1546 * Stop the adapter and free any mbufs allocated to the
1550 bfe_stop(struct bfe_softc *sc)
1552 struct ifnet *ifp = &sc->arpcom.ac_if;
1554 ASSERT_SERIALIZED(ifp->if_serializer);
1556 callout_stop(&sc->bfe_stat_timer);
1559 bfe_tx_ring_free(sc);
1560 bfe_rx_ring_free(sc);
1562 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);