sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c

   1 /*
   2  *   Copyright (c) 2001 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id$
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.6.2.2 2002/05/15 08:12:42 gj Exp $
  39  *
  40  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  41  *
  42  *---------------------------------------------------------------------------*/
  43
  44 #include "use_ifpi2.h"
  45 #include "use_pci.h"
  46 #include "opt_i4b.h"
  47
  48 #if (NIFPI2 > 0) && (NPCI > 0)
  49
  50 #include <sys/param.h>
  51 #include <sys/kernel.h>
  52 #include <sys/systm.h>
  53 #include <sys/mbuf.h>
  54 #include <sys/bus.h>
  55 #include <sys/rman.h>
  56 #include <sys/socket.h>
  57 #include <sys/thread2.h>
  58
  59 #include <bus/pci/pcireg.h>
  60 #include <bus/pci/pcivar.h>
  61
  62 #include <net/if.h>
  63 #include <net/i4b/include/machine/i4b_debug.h>
  64 #include <net/i4b/include/machine/i4b_ioctl.h>
  65 #include <net/i4b/include/machine/i4b_trace.h>
  66
  67 #include "../../include/i4b_global.h"
  68 #include "../../include/i4b_mbuf.h"
  69
  70 #include "../i4b_l1.h"
  71 #include "../isic/i4b_isic.h"
  72 /*#include "../isic/i4b_isac.h"*/
  73 #include "../isic/i4b_hscx.h"
  74
  75 #include "i4b_ifpi2_ext.h"
  76 #include "i4b_ifpi2_isacsx.h"
  77
  78 #define PCI_AVMA1_VID 0x1244
  79 #define PCI_AVMA1_V2_DID 0x0e00
  80
  81 /* prototypes */
  82 static void avma1pp2_disable(device_t);
  83
  84 static void avma1pp2_intr(void *);
  85 static void hscx_write_reg(int, u_int, struct l1_softc *);
  86 static u_char hscx_read_reg(int, struct l1_softc *);
  87 static u_int hscx_read_reg_int(int, struct l1_softc *);
  88 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  89 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  90 static void avma1pp2_hscx_int_handler(struct l1_softc *);
  91 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
  92 static void avma1pp2_init_linktab(struct l1_softc *);
  93 static void avma1pp2_bchannel_setup(int, int, int, int);
  94 static void avma1pp2_bchannel_start(int, int);
  95 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
  96 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
  97 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
  98 static isdn_link_t * avma1pp2_ret_linktab(int, int);
  99 static int avma1pp2_pci_probe(device_t);
 100 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 101 int avma1pp2_attach_avma1pp(device_t);
 102 static void ifpi2_isacsx_intr(struct l1_softc *sc);
 103
 104 static device_method_t avma1pp2_pci_methods[] = {
 105         /* Device interface */
 106         DEVMETHOD(device_probe,         avma1pp2_pci_probe),
 107         DEVMETHOD(device_attach,        avma1pp2_attach_avma1pp),
 108         DEVMETHOD(device_shutdown,      avma1pp2_disable),
 109
 110         /* bus interface */
 111         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 112         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 113
 114         { 0, 0 }
 115 };
 116
 117 static driver_t avma1pp2_pci_driver = {
 118         "ifpi2-",
 119         avma1pp2_pci_methods,
 120         sizeof(struct l1_softc)
 121 };
 122
 123 static devclass_t avma1pp2_pci_devclass;
 124
 125 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, NULL, NULL);
 126
 127 /* jump table for multiplex routines */
 128
 129 struct i4b_l1mux_func avma1pp2_l1mux_func = {
 130         avma1pp2_ret_linktab,
 131         avma1pp2_set_linktab,
 132         ifpi2_mph_command_req,
 133         ifpi2_ph_data_req,
 134         ifpi2_ph_activate_req,
 135 };
 136
 137 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
 138
 139 /*---------------------------------------------------------------------------*
 140  *      AVM PCI Fritz!Card V. 2 special registers
 141  *---------------------------------------------------------------------------*/
 142
 143 /*
 144  *      AVM PCI Status Latch 0 read only bits
 145  */
 146 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active high */
 147 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active high */
 148 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active high */
 149 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 150 /* actually active high */
 151 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 152
 153 /*
 154  *      AVM PCI Status Latch 0 read only bits
 155  */
 156 #define ASL_TIMERRESET          0x04
 157 #define ASL_ENABLE_INT          0x08
 158
 159 /*
 160  * "HSCX" status bits
 161  */
 162 #define  HSCX_STAT_RME          0x01
 163 #define  HSCX_STAT_RDO          0x10
 164 #define  HSCX_STAT_CRCVFRRAB    0x0E
 165 #define  HSCX_STAT_CRCVFR       0x06
 166 #define  HSCX_STAT_RML_MASK     0x3f00
 167
 168 /*
 169  * "HSCX" interrupt bits
 170  */
 171 #define  HSCX_INT_XPR           0x80
 172 #define  HSCX_INT_XDU           0x40
 173 #define  HSCX_INT_RPR           0x20
 174 #define  HSCX_INT_MASK          0xE0
 175
 176 /*
 177  * "HSCX" command bits
 178  */
 179 #define  HSCX_CMD_XRS           0x80
 180 #define  HSCX_CMD_XME           0x01
 181 #define  HSCX_CMD_RRS           0x20
 182 #define  HSCX_CMD_XML_MASK      0x3f00
 183
 184 /* "HSCX" mode bits */
 185 #define HSCX_MODE_ITF_FLG       0x01
 186 #define HSCX_MODE_TRANS         0x02
 187
 188 /* offsets to various registers in the ASIC, evidently */
 189 #define  STAT0_OFFSET           0x02
 190
 191 #define  HSCX_FIFO1             0x10
 192 #define  HSCX_FIFO2             0x18
 193
 194 #define  HSCX_STAT1             0x14
 195 #define  HSCX_STAT2             0x1c
 196
 197 #define  ISACSX_INDEX           0x04
 198 #define  ISACSX_DATA            0x08
 199
 200 /*
 201  * Commands and parameters are sent to the "HSCX" as a long, but the
 202  * fields are handled as bytes.
 203  *
 204  * The long contains:
 205  *      (prot << 16)|(txl << 8)|cmd
 206  *
 207  * where:
 208  *      prot = protocol to use
 209  *      txl = transmit length
 210  *      cmd = the command to be executed
 211  *
 212  * The fields are defined as u_char in struct l1_softc.
 213  *
 214  * Macro to coalesce the byte fields into a u_int
 215  */
 216 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 217                                         | (sc->avma1pp_prot << 16))
 218
 219 /*
 220  * to prevent deactivating the "HSCX" when both channels are active we
 221  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 222  * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
 223  * It is set high to allow room for new flags.
 224  */
 225 #define HSCX_AVMA1PP_ACTIVE     0x1000
 226
 227 /*---------------------------------------------------------------------------*
 228  *      AVM read fifo routines
 229  *---------------------------------------------------------------------------*/
 230
 231 static void
 232 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 233 {
 234         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 235         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 236         int i;
 237
 238         switch (what) {
 239                 case ISIC_WHAT_ISAC:
 240                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
 241                         /* evidently each byte must be read as a long */
 242                         for (i = 0; i < size; i++)
 243                                 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 244                         break;
 245                 case ISIC_WHAT_HSCXA:
 246                         hscx_read_fifo(0, buf, size, sc);
 247                         break;
 248                 case ISIC_WHAT_HSCXB:
 249                         hscx_read_fifo(1, buf, size, sc);
 250                         break;
 251         }
 252 }
 253
 254 static void
 255 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 256 {
 257         u_int32_t *ip;
 258         size_t cnt;
 259         int dataoff;
 260         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 261         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 262
 263         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 264
 265         ip = (u_int32_t *)buf;
 266         cnt = 0;
 267         /* what if len isn't a multiple of sizeof(int) and buf is */
 268         /* too small ???? */
 269         while (cnt < len)
 270         {
 271                 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
 272                 cnt += 4;
 273         }
 274 }
 275
 276 /*---------------------------------------------------------------------------*
 277  *      AVM write fifo routines
 278  *---------------------------------------------------------------------------*/
 279 static void
 280 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 281 {
 282         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 283         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 284         int i;
 285
 286         switch (what) {
 287                 case ISIC_WHAT_ISAC:
 288                         bus_space_write_4(btag, bhandle,  ISACSX_INDEX, 0);
 289                         /* evidently each byte must written as a long */
 290                         for (i = 0; i < size; i++)
 291                                 bus_space_write_4(btag, bhandle,  ISACSX_DATA, ((unsigned char *)buf)[i]);
 292                         break;
 293                 case ISIC_WHAT_HSCXA:
 294                         hscx_write_fifo(0, buf, size, sc);
 295                         break;
 296                 case ISIC_WHAT_HSCXB:
 297                         hscx_write_fifo(1, buf, size, sc);
 298                         break;
 299         }
 300 }
 301
 302 static void
 303 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 304 {
 305         u_int32_t *ip;
 306         size_t cnt;
 307         int dataoff;
 308         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 309         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 310         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 311
 312         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 313
 314         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 315         sc->avma1pp_txl = 0;
 316         if (Bchan->out_mbuf_cur == NULL)
 317         {
 318           if (Bchan->bprot != BPROT_NONE)
 319                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 320         }
 321         if (len != sc->sc_bfifolen)
 322                 sc->avma1pp_txl = len;
 323
 324         cnt = 0; /* borrow cnt */
 325         AVMA1PPSETCMDLONG(cnt);
 326         hscx_write_reg(chan, cnt, sc);
 327
 328         ip = (u_int32_t *)buf;
 329         cnt = 0;
 330         while (cnt < len)
 331         {
 332                 bus_space_write_4(btag, bhandle, dataoff, *ip);
 333                 ip++;
 334                 cnt += 4;
 335         }
 336 }
 337
 338 /*---------------------------------------------------------------------------*
 339  *      AVM write register routines
 340  *---------------------------------------------------------------------------*/
 341
 342 static void
 343 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 344 {
 345         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 346         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 347
 348         switch (what) {
 349                 case ISIC_WHAT_ISAC:
 350                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 351                         bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
 352                         break;
 353                 case ISIC_WHAT_HSCXA:
 354                         hscx_write_reg(0, data, sc);
 355                         break;
 356                 case ISIC_WHAT_HSCXB:
 357                         hscx_write_reg(1, data, sc);
 358                         break;
 359         }
 360 }
 361
 362 static void
 363 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
 364 {
 365         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 366         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 367         u_int off;
 368
 369         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 370
 371         bus_space_write_4(btag, bhandle, off, val);
 372 }
 373
 374 /*---------------------------------------------------------------------------*
 375  *      AVM read register routines
 376  *---------------------------------------------------------------------------*/
 377 static u_int8_t
 378 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 379 {
 380         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 381         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 382         u_int8_t val;
 383
 384         switch (what) {
 385                 case ISIC_WHAT_ISAC:
 386                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 387                         val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 388                         return(val);
 389                 case ISIC_WHAT_HSCXA:
 390                         return hscx_read_reg(0, sc);
 391                 case ISIC_WHAT_HSCXB:
 392                         return hscx_read_reg(1, sc);
 393         }
 394         return 0;
 395 }
 396
 397 static u_char
 398 hscx_read_reg(int chan, struct l1_softc *sc)
 399 {
 400         return(hscx_read_reg_int(chan, sc) & 0xff);
 401 }
 402
 403 /*
 404  * need to be able to return an int because the RBCH is in the 2nd
 405  * byte.
 406  */
 407 static u_int
 408 hscx_read_reg_int(int chan, struct l1_softc *sc)
 409 {
 410         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 411         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 412         u_int off;
 413
 414         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 415         return(bus_space_read_4(btag, bhandle, off));
 416 }
 417
 418 /*---------------------------------------------------------------------------*
 419  *      avma1pp2_probe - probe for a card
 420  *---------------------------------------------------------------------------*/
 421 static int
 422 avma1pp2_pci_probe(device_t dev)
 423 {
 424         u_int16_t               did, vid;
 425
 426         vid = pci_get_vendor(dev);
 427         did = pci_get_device(dev);
 428
 429         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
 430                 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
 431                 return(0);
 432         }
 433
 434         return(ENXIO);
 435 }
 436
 437 /*---------------------------------------------------------------------------*
 438  *      avma1pp2_attach_avma1pp - attach Fritz!Card PCI
 439  *---------------------------------------------------------------------------*/
 440 int
 441 avma1pp2_attach_avma1pp(device_t dev)
 442 {
 443         struct l1_softc *sc;
 444         u_int v;
 445         int unit, error = 0;
 446         u_int16_t did, vid;
 447         void *ih = NULL;
 448         bus_space_handle_t bhandle;
 449         bus_space_tag_t btag;
 450
 451         crit_enter();
 452
 453         vid = pci_get_vendor(dev);
 454         did = pci_get_device(dev);
 455         sc = device_get_softc(dev);
 456         unit = device_get_unit(dev);
 457         bzero(sc, sizeof(struct l1_softc));
 458
 459         /* probably not really required */
 460         if(unit > IFPI2_MAXUNIT) {
 461                 kprintf("ifpi2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 462                 crit_exit();
 463                 return(ENXIO);
 464         }
 465
 466         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
 467                 kprintf("ifpi2-%d: unknown device!?\n", unit);
 468                 goto fail;
 469         }
 470
 471         ifpi2_scp[unit] = sc;
 472
 473         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 474         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 475                 &sc->sc_resources.io_rid[0],
 476                 0, ~0, 1, RF_ACTIVE);
 477
 478         if (sc->sc_resources.io_base[0] == NULL) {
 479                 kprintf("ifpi2-%d: couldn't map IO port\n", unit);
 480                 error = ENXIO;
 481                 goto fail;
 482         }
 483
 484         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 485         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 486
 487         /* Allocate interrupt */
 488         sc->sc_resources.irq_rid = 0;
 489         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 490                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 491
 492         if (sc->sc_resources.irq == NULL) {
 493                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 494                 kprintf("ifpi2-%d: couldn't map interrupt\n", unit);
 495                 error = ENXIO;
 496                 goto fail;
 497         }
 498
 499         error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
 500                                avma1pp2_intr, sc, &ih, NULL);
 501
 502         if (error) {
 503                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 504                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 505                 kprintf("ifpi2-%d: couldn't set up irq\n", unit);
 506                 goto fail;
 507         }
 508
 509         sc->sc_unit = unit;
 510
 511         /* end of new-bus stuff */
 512
 513         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 514
 515         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 516         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 517
 518         /* setup access routines */
 519
 520         sc->clearirq = NULL;
 521         sc->readreg = avma1pp2_read_reg;
 522         sc->writereg = avma1pp2_write_reg;
 523
 524         sc->readfifo = avma1pp2_read_fifo;
 525         sc->writefifo = avma1pp2_write_fifo;
 526
 527         /* setup card type */
 528
 529         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
 530
 531         /* setup IOM bus type */
 532
 533         sc->sc_bustyp = BUS_TYPE_IOM2;
 534
 535         /* set up some other miscellaneous things */
 536         sc->sc_ipac = 0;
 537         sc->sc_bfifolen = HSCX_FIFO_LEN;
 538
 539         /* reset the card */
 540         /* the Linux driver does this to clear any pending ISAC interrupts */
 541         v = 0;
 542         v = ISAC_READ(I_RMODED);
 543 #ifdef AVMA1PCI_V2_DEBUG
 544         kprintf("avma1pp2_attach: I_MODED %x...", v);
 545 #endif
 546         v = ISAC_READ(I_ISTAD);
 547 #ifdef AVMA1PCI_V2_DEBUG
 548         kprintf("avma1pp2_attach: I_ISTAD %x...", v);
 549 #endif
 550         v = ISAC_READ(I_ISTA);
 551 #ifdef AVMA1PCI_V2_DEBUG
 552         kprintf("avma1pp2_attach: I_ISTA %x...", v);
 553 #endif
 554         ISAC_WRITE(I_MASKD, 0xff);
 555         ISAC_WRITE(I_MASK, 0xff);
 556         /* the Linux driver does this to clear any pending HSCX interrupts */
 557         v = hscx_read_reg_int(0, sc);
 558 #ifdef AVMA1PCI_V2_DEBUG
 559         kprintf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
 560 #endif
 561         v = hscx_read_reg_int(1, sc);
 562 #ifdef AVMA1PCI_V2_DEBUG
 563         kprintf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
 564 #endif
 565
 566         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
 567         DELAY(SEC_DELAY/100); /* 10 ms */
 568         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
 569         DELAY(SEC_DELAY/100); /* 10 ms */
 570
 571    /* from here to the end would normally be done in isic_pciattach */
 572
 573          kprintf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
 574
 575         /* init the ISAC */
 576         ifpi2_isacsx_init(sc);
 577
 578         /* init the "HSCX" */
 579         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 580
 581         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 582
 583         /* can't use the normal B-Channel stuff */
 584         avma1pp2_init_linktab(sc);
 585
 586         /* set trace level */
 587
 588         sc->sc_trace = TRACE_OFF;
 589
 590         sc->sc_state = ISAC_IDLE;
 591
 592         sc->sc_ibuf = NULL;
 593         sc->sc_ib = NULL;
 594         sc->sc_ilen = 0;
 595
 596         sc->sc_obuf = NULL;
 597         sc->sc_op = NULL;
 598         sc->sc_ol = 0;
 599         sc->sc_freeflag = 0;
 600
 601         sc->sc_obuf2 = NULL;
 602         sc->sc_freeflag2 = 0;
 603
 604         callout_init(&sc->sc_T3_timeout);
 605         callout_init(&sc->sc_T4_timeout);
 606
 607         /* init higher protocol layers */
 608
 609         i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
 610
 611   fail:
 612         crit_exit();
 613         return(error);
 614 }
 615
 616 /*
 617  * this is the real interrupt routine
 618  */
 619 static void
 620 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 621 {
 622         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 623         int activity = -1;
 624         u_int param = 0;
 625
 626         NDBGL1(L1_H_IRQ, "%#x", stat);
 627
 628         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 629         {
 630                 chan->stat_XDU++;
 631                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 632                 /* abort the transmission */
 633                 sc->avma1pp_txl = 0;
 634                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 635                 AVMA1PPSETCMDLONG(param);
 636                 hscx_write_reg(h_chan, param, sc);
 637                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 638                 AVMA1PPSETCMDLONG(param);
 639                 hscx_write_reg(h_chan, param, sc);
 640
 641                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 642                 {
 643                         i4b_Bfreembuf(chan->out_mbuf_head);
 644                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 645                 }
 646         }
 647
 648         /*
 649          * The following is based on examination of the Linux driver.
 650          *
 651          * The logic here is different than with a "real" HSCX; all kinds
 652          * of information (interrupt/status bits) are in stat.
 653          *              HSCX_INT_RPR indicates a receive interrupt
 654          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 655          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 656          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 657          *                      CRC/framing errors are only reported in this state.
 658          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 659          *                                      CRC/framing error
 660          */
 661
 662         if(stat & HSCX_INT_RPR)
 663         {
 664                 int fifo_data_len;
 665                 int error = 0;
 666                 /* always have to read the FIFO, so use a scratch buffer */
 667                 u_char scrbuf[HSCX_FIFO_LEN];
 668
 669                 if(stat & HSCX_STAT_RDO)
 670                 {
 671                         chan->stat_RDO++;
 672                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 673                         error++;
 674                 }
 675
 676                 /*
 677                  * check whether we're receiving data for an inactive B-channel
 678                  * and discard it. This appears to happen for telephony when
 679                  * both B-channels are active and one is deactivated. Since
 680                  * it is not really possible to deactivate the channel in that
 681                  * case (the ASIC seems to deactivate _both_ channels), the
 682                  * "deactivated" channel keeps receiving data which can lead
 683                  * to exhaustion of mbufs and a kernel panic.
 684                  *
 685                  * This is a hack, but it's the only solution I can think of
 686                  * without having the documentation for the ASIC.
 687                  * GJ - 28 Nov 1999
 688                  */
 689                  if (chan->state == HSCX_IDLE)
 690                  {
 691                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 692                         error++;
 693                  }
 694
 695                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 696
 697                 if(fifo_data_len == 0)
 698                         fifo_data_len = sc->sc_bfifolen;
 699
 700                 /* ALWAYS read data from HSCX fifo */
 701
 702                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 703                 chan->rxcount += fifo_data_len;
 704
 705                 /* all error conditions checked, now decide and take action */
 706
 707                 if(error == 0)
 708                 {
 709                         if(chan->in_mbuf == NULL)
 710                         {
 711                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 712                                         panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
 713                                 chan->in_cbptr = chan->in_mbuf->m_data;
 714                                 chan->in_len = 0;
 715                         }
 716
 717                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 718                         {
 719                                 /* OK to copy the data */
 720                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 721                                 chan->in_cbptr += fifo_data_len;
 722                                 chan->in_len += fifo_data_len;
 723
 724                                 /* setup mbuf data length */
 725
 726                                 chan->in_mbuf->m_len = chan->in_len;
 727                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 728
 729                                 if(sc->sc_trace & TRACE_B_RX)
 730                                 {
 731                                         i4b_trace_hdr_t hdr;
 732                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 733                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 734                                         hdr.dir = FROM_NT;
 735                                         hdr.count = ++sc->sc_trace_bcount;
 736                                         MICROTIME(hdr.time);
 737                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 738                                 }
 739
 740                                 if (stat & HSCX_STAT_RME)
 741                                 {
 742                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 743                                   {
 744                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 745                                          activity = ACT_RX;
 746
 747                                          /* mark buffer ptr as unused */
 748
 749                                          chan->in_mbuf = NULL;
 750                                          chan->in_cbptr = NULL;
 751                                          chan->in_len = 0;
 752                                   }
 753                                   else
 754                                   {
 755                                                 chan->stat_CRC++;
 756                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 757                                           if (chan->in_mbuf != NULL)
 758                                           {
 759                                                   i4b_Bfreembuf(chan->in_mbuf);
 760                                                   chan->in_mbuf = NULL;
 761                                                   chan->in_cbptr = NULL;
 762                                                   chan->in_len = 0;
 763                                           }
 764                                   }
 765                                 }
 766                         } /* END enough space in mbuf */
 767                         else
 768                         {
 769                                  if(chan->bprot == BPROT_NONE)
 770                                  {
 771                                           /* setup mbuf data length */
 772
 773                                           chan->in_mbuf->m_len = chan->in_len;
 774                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 775
 776                                           if(sc->sc_trace & TRACE_B_RX)
 777                                           {
 778                                                         i4b_trace_hdr_t hdr;
 779                                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 780                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 781                                                         hdr.dir = FROM_NT;
 782                                                         hdr.count = ++sc->sc_trace_bcount;
 783                                                         MICROTIME(hdr.time);
 784                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 785                                                 }
 786
 787                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 788                                                  activity = ACT_RX;
 789
 790                                           /* move rx'd data to rx queue */
 791
 792                                           if(!(IF_QFULL(&chan->rx_queue)))
 793                                           {
 794                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 795                                           }
 796                                           else
 797                                           {
 798                                                 i4b_Bfreembuf(chan->in_mbuf);
 799                                           }
 800                                           /* signal upper layer that data are available */
 801                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 802
 803                                           /* alloc new buffer */
 804
 805                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 806                                                  panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
 807
 808                                           /* setup new data ptr */
 809
 810                                           chan->in_cbptr = chan->in_mbuf->m_data;
 811
 812                                           /* OK to copy the data */
 813                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 814
 815                                           chan->in_cbptr += fifo_data_len;
 816                                           chan->in_len = fifo_data_len;
 817
 818                                           chan->rxcount += fifo_data_len;
 819                                         }
 820                                  else
 821                                         {
 822                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 823                                           chan->in_cbptr = chan->in_mbuf->m_data;
 824                                           chan->in_len = 0;
 825                                         }
 826                           }
 827                 } /* if(error == 0) */
 828                 else
 829                 {
 830                         /* land here for RDO */
 831                         if (chan->in_mbuf != NULL)
 832                         {
 833                                 i4b_Bfreembuf(chan->in_mbuf);
 834                                 chan->in_mbuf = NULL;
 835                                 chan->in_cbptr = NULL;
 836                                 chan->in_len = 0;
 837                         }
 838                         sc->avma1pp_txl = 0;
 839                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 840                         AVMA1PPSETCMDLONG(param);
 841                         hscx_write_reg(h_chan, param, sc);
 842                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 843                         AVMA1PPSETCMDLONG(param);
 844                         hscx_write_reg(h_chan, param, sc);
 845                 }
 846         }
 847
 848
 849         /* transmit fifo empty, new data can be written to fifo */
 850
 851         if(stat & HSCX_INT_XPR)
 852         {
 853                 /*
 854                  * for a description what is going on here, please have
 855                  * a look at isic_bchannel_start() in i4b_bchan.c !
 856                  */
 857
 858                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 859
 860                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 861                 {
 862                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 863
 864                         if(chan->out_mbuf_head == NULL)
 865                         {
 866                                 chan->state &= ~HSCX_TX_ACTIVE;
 867                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 868                         }
 869                         else
 870                         {
 871                                 chan->state |= HSCX_TX_ACTIVE;
 872                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 873                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 874                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 875
 876                                 if(sc->sc_trace & TRACE_B_TX)
 877                                 {
 878                                         i4b_trace_hdr_t hdr;
 879                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 880                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 881                                         hdr.dir = FROM_TE;
 882                                         hdr.count = ++sc->sc_trace_bcount;
 883                                         MICROTIME(hdr.time);
 884                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 885                                 }
 886
 887                                 if(chan->bprot == BPROT_NONE)
 888                                 {
 889                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 890                                                 activity = ACT_TX;
 891                                 }
 892                                 else
 893                                 {
 894                                         activity = ACT_TX;
 895                                 }
 896                         }
 897                 }
 898
 899                 avma1pp2_hscx_fifo(chan, sc);
 900         }
 901
 902         /* call timeout handling routine */
 903
 904         if(activity == ACT_RX || activity == ACT_TX)
 905                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 906 }
 907
 908 /*
 909  * this is the main routine which checks each channel and then calls
 910  * the real interrupt routine as appropriate
 911  */
 912 static void
 913 avma1pp2_hscx_int_handler(struct l1_softc *sc)
 914 {
 915         u_int stat;
 916
 917         /* has to be a u_int because the byte count is in the 2nd byte */
 918         stat = hscx_read_reg_int(0, sc);
 919         if (stat & HSCX_INT_MASK)
 920           avma1pp2_hscx_intr(0, stat, sc);
 921         stat = hscx_read_reg_int(1, sc);
 922         if (stat & HSCX_INT_MASK)
 923           avma1pp2_hscx_intr(1, stat, sc);
 924 }
 925
 926 static void
 927 avma1pp2_disable(device_t dev)
 928 {
 929         struct l1_softc *sc = device_get_softc(dev);
 930         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 931         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 932
 933         /* could still be wrong, but it seems to help */
 934         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
 935 }
 936
 937 static void
 938 avma1pp2_intr(void *xsc)
 939 {
 940         u_char stat;
 941         struct l1_softc *sc;
 942         bus_space_handle_t bhandle;
 943         bus_space_tag_t btag;
 944
 945         sc = xsc;
 946         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 947         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 948
 949         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 950         NDBGL1(L1_H_IRQ, "stat %x", stat);
 951         /* was there an interrupt from this card ? */
 952         if ((stat & ASL_IRQ_Pending) == 0)
 953                 return; /* no */
 954         /* For slow machines loop as long as an interrupt is active */
 955         for (; ((stat & ASL_IRQ_Pending) != 0) ;)
 956         {
 957                 /* interrupts are high active */
 958                 if (stat & ASL_IRQ_TIMER)
 959                         NDBGL1(L1_H_IRQ, "timer interrupt ???");
 960                 if (stat & ASL_IRQ_HSCX)
 961                 {
 962                         NDBGL1(L1_H_IRQ, "HSCX");
 963                         avma1pp2_hscx_int_handler(sc);
 964                 }
 965                 if (stat & ASL_IRQ_ISAC)
 966                 {
 967                        NDBGL1(L1_H_IRQ, "ISAC");
 968                        ifpi2_isacsx_intr(sc);
 969                 }
 970                 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 971                 NDBGL1(L1_H_IRQ, "stat %x", stat);
 972
 973         }
 974 }
 975
 976 static void
 977 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 978 {
 979         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 980         u_int param = 0;
 981
 982         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
 983                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
 984
 985         sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
 986
 987         if (activate == 0)
 988         {
 989                 /* only deactivate if both channels are idle */
 990                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 991                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 992                 {
 993                         return;
 994                 }
 995                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 996                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 997                 AVMA1PPSETCMDLONG(param);
 998                 hscx_write_reg(h_chan, param, sc);
 999                 return;
1000         }
1001         if(chan->bprot == BPROT_RHDLC)
1002         {
1003                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1004
1005                 /* HDLC Frames, transparent mode 0 */
1006                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1007                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1008                 AVMA1PPSETCMDLONG(param);
1009                 hscx_write_reg(h_chan, param, sc);
1010                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1011                 AVMA1PPSETCMDLONG(param);
1012                 hscx_write_reg(h_chan, param, sc);
1013                 sc->avma1pp_cmd = 0;
1014         }
1015         else
1016         {
1017                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1018
1019                 /* Raw Telephony, extended transparent mode 1 */
1020                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1021                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1022                 AVMA1PPSETCMDLONG(param);
1023                 hscx_write_reg(h_chan, param, sc);
1024                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1025                 AVMA1PPSETCMDLONG(param);
1026                 hscx_write_reg(h_chan, param, sc);
1027                 sc->avma1pp_cmd = 0;
1028         }
1029 }
1030
1031 static void
1032 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1033 {
1034         struct l1_softc *sc = ifpi2_scp[unit];
1035         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1036
1037         crit_enter();
1038
1039         if(activate == 0)
1040         {
1041                 /* deactivation */
1042                 chan->state = HSCX_IDLE;
1043                 avma1pp2_hscx_init(sc, h_chan, activate);
1044         }
1045
1046         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1047                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1048
1049         /* general part */
1050
1051         chan->unit = sc->sc_unit;       /* unit number */
1052         chan->channel = h_chan;         /* B channel */
1053         chan->bprot = bprot;            /* B channel protocol */
1054         chan->state = HSCX_IDLE;        /* B channel state */
1055
1056         /* receiver part */
1057
1058         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1059
1060         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1061
1062         chan->rxcount = 0;              /* reset rx counter */
1063
1064         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1065
1066         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1067         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1068         chan->in_len = 0;               /* reset mbuf data len */
1069
1070         /* transmitter part */
1071
1072         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1073
1074         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1075
1076         chan->txcount = 0;              /* reset tx counter */
1077
1078         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1079
1080         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1081         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1082         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1083         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1084
1085         if(activate != 0)
1086         {
1087                 /* activation */
1088                 avma1pp2_hscx_init(sc, h_chan, activate);
1089                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1090         }
1091
1092         crit_exit();
1093 }
1094
1095 static void
1096 avma1pp2_bchannel_start(int unit, int h_chan)
1097 {
1098         struct l1_softc *sc = ifpi2_scp[unit];
1099         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1100         int activity = -1;
1101
1102         crit_enter();
1103         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1104         {
1105                 crit_exit();
1106                 return;                         /* yes, leave */
1107         }
1108
1109         /* get next mbuf from queue */
1110
1111         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1112
1113         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1114         {
1115                 crit_exit();
1116                 return;                         /* yes, exit */
1117         }
1118
1119         /* init current mbuf values */
1120
1121         chan->out_mbuf_cur = chan->out_mbuf_head;
1122         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1123         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1124
1125         /* activity indicator for timeout handling */
1126
1127         if(chan->bprot == BPROT_NONE)
1128         {
1129                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1130                         activity = ACT_TX;
1131         }
1132         else
1133         {
1134                 activity = ACT_TX;
1135         }
1136
1137         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1138
1139         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1140         {
1141                 i4b_trace_hdr_t hdr;
1142                 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1143                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1144                 hdr.dir = FROM_TE;
1145                 hdr.count = ++sc->sc_trace_bcount;
1146                 MICROTIME(hdr.time);
1147                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1148         }
1149
1150         avma1pp2_hscx_fifo(chan, sc);
1151
1152         /* call timeout handling routine */
1153
1154         if(activity == ACT_RX || activity == ACT_TX)
1155                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1156
1157         crit_exit();
1158 }
1159
1160 /*---------------------------------------------------------------------------*
1161  *      return the address of isic drivers linktab
1162  *---------------------------------------------------------------------------*/
1163 static isdn_link_t *
1164 avma1pp2_ret_linktab(int unit, int channel)
1165 {
1166         struct l1_softc *sc = ifpi2_scp[unit];
1167         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1168
1169         return(&chan->isic_isdn_linktab);
1170 }
1171
1172 /*---------------------------------------------------------------------------*
1173  *      set the driver linktab in the b channel softc
1174  *---------------------------------------------------------------------------*/
1175 static void
1176 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1177 {
1178         struct l1_softc *sc = ifpi2_scp[unit];
1179         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1180
1181         chan->isic_drvr_linktab = dlt;
1182 }
1183
1184
1185 /*---------------------------------------------------------------------------*
1186  *      initialize our local linktab
1187  *---------------------------------------------------------------------------*/
1188 static void
1189 avma1pp2_init_linktab(struct l1_softc *sc)
1190 {
1191         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1192         isdn_link_t *lt = &chan->isic_isdn_linktab;
1193
1194         /* make sure the hardware driver is known to layer 4 */
1195         /* avoid overwriting if already set */
1196         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1197         {
1198                 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1199                 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1200         }
1201
1202         /* local setup */
1203         lt->unit = sc->sc_unit;
1204         lt->channel = HSCX_CH_A;
1205         lt->bch_config = avma1pp2_bchannel_setup;
1206         lt->bch_tx_start = avma1pp2_bchannel_start;
1207         lt->bch_stat = avma1pp2_bchannel_stat;
1208         lt->tx_queue = &chan->tx_queue;
1209
1210         /* used by non-HDLC data transfers, i.e. telephony drivers */
1211         lt->rx_queue = &chan->rx_queue;
1212
1213         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1214         lt->rx_mbuf = &chan->in_mbuf;
1215
1216         chan = &sc->sc_chan[HSCX_CH_B];
1217         lt = &chan->isic_isdn_linktab;
1218
1219         lt->unit = sc->sc_unit;
1220         lt->channel = HSCX_CH_B;
1221         lt->bch_config = avma1pp2_bchannel_setup;
1222         lt->bch_tx_start = avma1pp2_bchannel_start;
1223         lt->bch_stat = avma1pp2_bchannel_stat;
1224         lt->tx_queue = &chan->tx_queue;
1225
1226         /* used by non-HDLC data transfers, i.e. telephony drivers */
1227         lt->rx_queue = &chan->rx_queue;
1228
1229         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1230         lt->rx_mbuf = &chan->in_mbuf;
1231 }
1232
1233 /*
1234  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1235  */
1236 static void
1237 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1238 {
1239         struct l1_softc *sc = ifpi2_scp[unit];
1240         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1241
1242         crit_enter();
1243
1244         bsp->outbytes = chan->txcount;
1245         bsp->inbytes = chan->rxcount;
1246
1247         chan->txcount = 0;
1248         chan->rxcount = 0;
1249
1250         crit_exit();
1251 }
1252
1253 /*---------------------------------------------------------------------------*
1254  *      fill HSCX fifo with data from the current mbuf
1255  *      Put this here until it can go into i4b_hscx.c
1256  *---------------------------------------------------------------------------*/
1257 static int
1258 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1259 {
1260         int len;
1261         int nextlen;
1262         int i;
1263         int cmd = 0;
1264         /* using a scratch buffer simplifies writing to the FIFO */
1265         u_char scrbuf[HSCX_FIFO_LEN];
1266
1267         len = 0;
1268
1269         /*
1270          * fill the HSCX tx fifo with data from the current mbuf. if
1271          * current mbuf holds less data than HSCX fifo length, try to
1272          * get the next mbuf from (a possible) mbuf chain. if there is
1273          * not enough data in a single mbuf or in a chain, then this
1274          * is the last mbuf and we tell the HSCX that it has to send
1275          * CRC and closing flag
1276          */
1277
1278         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1279         {
1280                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1281
1282 #ifdef NOTDEF
1283                 kprintf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1284                         chan->out_mbuf_head,
1285                         chan->out_mbuf_cur,
1286                         chan->out_mbuf_cur_ptr,
1287                         chan->out_mbuf_cur_len,
1288                         len,
1289                         nextlen);
1290 #endif
1291
1292                 cmd |= HSCX_CMDR_XTF;
1293                 /* collect the data in the scratch buffer */
1294                 for (i = 0; i < nextlen; i++)
1295                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1296
1297                 len += nextlen;
1298                 chan->txcount += nextlen;
1299
1300                 chan->out_mbuf_cur_ptr += nextlen;
1301                 chan->out_mbuf_cur_len -= nextlen;
1302
1303                 if(chan->out_mbuf_cur_len == 0)
1304                 {
1305                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1306                         {
1307                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1308                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1309
1310                                 if(sc->sc_trace & TRACE_B_TX)
1311                                 {
1312                                         i4b_trace_hdr_t hdr;
1313                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1314                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1315                                         hdr.dir = FROM_TE;
1316                                         hdr.count = ++sc->sc_trace_bcount;
1317                                         MICROTIME(hdr.time);
1318                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1319                                 }
1320                         }
1321                         else
1322                         {
1323                                 if (chan->bprot != BPROT_NONE)
1324                                         cmd |= HSCX_CMDR_XME;
1325                                 i4b_Bfreembuf(chan->out_mbuf_head);
1326                                 chan->out_mbuf_head = NULL;
1327                         }
1328                 }
1329         }
1330         /* write what we have from the scratch buf to the HSCX fifo */
1331         if (len != 0)
1332                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1333         return(cmd);
1334 }
1335
1336 /*---------------------------------------------------------------------------*
1337  *      ifpi2 - ISAC interrupt routine
1338  *---------------------------------------------------------------------------*/
1339 static void
1340 ifpi2_isacsx_intr(struct l1_softc *sc)
1341 {
1342         u_char isacsx_irq_stat;
1343
1344         for(;;)
1345         {
1346                 /* get isac irq status */
1347                 /* ISTA tells us whether it was a C/I or HDLC int. */
1348                 isacsx_irq_stat = ISAC_READ(I_ISTA);
1349
1350                 if(isacsx_irq_stat)
1351                         ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1352                 else
1353                         break;
1354         }
1355
1356         ISAC_WRITE(I_MASKD, 0xff);
1357         ISAC_WRITE(I_MASK, 0xff);
1358
1359         DELAY(100);
1360
1361         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1362         ISAC_WRITE(I_MASK, isacsx_imask);
1363 }
1364
1365 /*---------------------------------------------------------------------------*
1366  *      ifpi2_recover - try to recover from irq lockup
1367  *---------------------------------------------------------------------------*/
1368 void
1369 ifpi2_recover(struct l1_softc *sc)
1370 {
1371         kprintf("ifpi2_recover %d\n", sc->sc_unit);
1372 #if 0 /* fix me later */
1373         u_char byte;
1374
1375         /* get isac irq status */
1376
1377         byte = ISAC_READ(I_ISTA);
1378
1379         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1380
1381         if(byte & ISACSX_ISTA_EXI)
1382                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1383
1384         if(byte & ISACSX_ISTA_CISQ)
1385         {
1386                 byte = ISAC_READ(I_CIRR);
1387
1388                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1389
1390                 if(byte & ISACSX_CIRR_SQC)
1391                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1392         }
1393
1394         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISACSX_IMASK);
1395
1396         ISAC_WRITE(I_MASKD, 0xff);
1397         ISAC_WRITE(I_MASK, 0xff);
1398         DELAY(100);
1399         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1400         ISAC_WRITE(I_MASK, isacsx_imask);
1401 #endif
1402 }
1403
1404
1405 #endif /* NIFPI2 > 0 */