sys/net/i4b/layer1/isic/i4b_isac.c

   1 /*
   2  * Copyright (c) 1997, 2001 Hellmuth Michaelis. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  *---------------------------------------------------------------------------
  26  *
  27  *      i4b_isac.c - i4b siemens isdn chipset driver ISAC handler
  28  *      ---------------------------------------------------------
  29  *
  30  * $FreeBSD: src/sys/i4b/layer1/isic/i4b_isac.c,v 1.5.2.1 2001/08/10 14:08:38 obrien Exp $
  31  * $DragonFly: src/sys/net/i4b/layer1/isic/i4b_isac.c,v 1.6 2006/12/22 23:44:56 swildner Exp $
  32  *
  33  *      last edit-date: [Wed Jan 24 09:10:36 2001]
  34  *
  35  *---------------------------------------------------------------------------*/
  36
  37 #include "use_isic.h"
  38
  39 #if NISIC > 0
  40
  41 #include "opt_i4b.h"
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/mbuf.h>
  46 #include <sys/socket.h>
  47
  48 #include <net/if.h>
  49
  50 #include <net/i4b/include/machine/i4b_debug.h>
  51 #include <net/i4b/include/machine/i4b_ioctl.h>
  52 #include <net/i4b/include/machine/i4b_trace.h>
  53
  54 #include "../i4b_l1.h"
  55
  56 #include "i4b_isic.h"
  57 #include "i4b_isac.h"
  58 #include "i4b_hscx.h"
  59
  60 #include "../../include/i4b_global.h"
  61 #include "../../include/i4b_mbuf.h"
  62
  63 static u_char isic_isac_exir_hdlr(struct l1_softc *sc, u_char exir);
  64 static void isic_isac_ind_hdlr(struct l1_softc *sc, int ind);
  65
  66 /*---------------------------------------------------------------------------*
  67  *      ISAC interrupt service routine
  68  *---------------------------------------------------------------------------*/
  69 void
  70 isic_isac_irq(struct l1_softc *sc, int ista)
  71 {
  72         u_char c = 0;
  73         NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
  74
  75         if(ista & ISAC_ISTA_EXI)        /* extended interrupt */
  76         {
  77                 c |= isic_isac_exir_hdlr(sc, ISAC_READ(I_EXIR));
  78         }
  79
  80         if(ista & ISAC_ISTA_RME)        /* receive message end */
  81         {
  82                 int rest;
  83                 u_char rsta;
  84
  85                 /* get rx status register */
  86
  87                 rsta = ISAC_READ(I_RSTA);
  88
  89                 if((rsta & ISAC_RSTA_MASK) != 0x20)
  90                 {
  91                         int error = 0;
  92
  93                         if(!(rsta & ISAC_RSTA_CRC))     /* CRC error */
  94                         {
  95                                 error++;
  96                                 NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
  97                         }
  98
  99                         if(rsta & ISAC_RSTA_RDO)        /* ReceiveDataOverflow */
 100                         {
 101                                 error++;
 102                                 NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
 103                         }
 104
 105                         if(rsta & ISAC_RSTA_RAB)        /* ReceiveABorted */
 106                         {
 107                                 error++;
 108                                 NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
 109                         }
 110
 111                         if(error == 0)
 112                                 NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTA = 0x%02x!", sc->sc_unit, rsta);
 113
 114                         i4b_Dfreembuf(sc->sc_ibuf);
 115
 116                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 117
 118                         sc->sc_ibuf = NULL;
 119                         sc->sc_ib = NULL;
 120                         sc->sc_ilen = 0;
 121
 122                         ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
 123                         ISACCMDRWRDELAY();
 124
 125                         return;
 126                 }
 127
 128                 rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
 129
 130                 if(rest == 0)
 131                         rest = ISAC_FIFO_LEN;
 132
 133                 if(sc->sc_ibuf == NULL)
 134                 {
 135                         if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
 136                                 sc->sc_ib = sc->sc_ibuf->m_data;
 137                         else
 138                                 panic("isic_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n");
 139                         sc->sc_ilen = 0;
 140                 }
 141
 142                 if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
 143                 {
 144                         ISAC_RDFIFO(sc->sc_ib, rest);
 145                         sc->sc_ilen += rest;
 146
 147                         sc->sc_ibuf->m_pkthdr.len =
 148                                 sc->sc_ibuf->m_len = sc->sc_ilen;
 149
 150                         if(sc->sc_trace & TRACE_D_RX)
 151                         {
 152                                 i4b_trace_hdr_t hdr;
 153                                 hdr.unit = L0ISICUNIT(sc->sc_unit);
 154                                 hdr.type = TRC_CH_D;
 155                                 hdr.dir = FROM_NT;
 156                                 hdr.count = ++sc->sc_trace_dcount;
 157                                 MICROTIME(hdr.time);
 158                                 i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
 159                         }
 160
 161                         c |= ISAC_CMDR_RMC;
 162
 163                         if(sc->sc_enabled &&
 164                            (ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
 165                         {
 166                                 i4b_l1_ph_data_ind(L0ISICUNIT(sc->sc_unit), sc->sc_ibuf);
 167                         }
 168                         else
 169                         {
 170                                 i4b_Dfreembuf(sc->sc_ibuf);
 171                         }
 172                 }
 173                 else
 174                 {
 175                         NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
 176                         i4b_Dfreembuf(sc->sc_ibuf);
 177                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 178                 }
 179
 180                 sc->sc_ibuf = NULL;
 181                 sc->sc_ib = NULL;
 182                 sc->sc_ilen = 0;
 183         }
 184
 185         if(ista & ISAC_ISTA_RPF)        /* receive fifo full */
 186         {
 187                 if(sc->sc_ibuf == NULL)
 188                 {
 189                         if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
 190                                 sc->sc_ib= sc->sc_ibuf->m_data;
 191                         else
 192                                 panic("isic_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
 193                         sc->sc_ilen = 0;
 194                 }
 195
 196                 if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
 197                 {
 198                         ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
 199                         sc->sc_ilen += ISAC_FIFO_LEN;
 200                         sc->sc_ib += ISAC_FIFO_LEN;
 201                         c |= ISAC_CMDR_RMC;
 202                 }
 203                 else
 204                 {
 205                         NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
 206                         i4b_Dfreembuf(sc->sc_ibuf);
 207                         sc->sc_ibuf = NULL;
 208                         sc->sc_ib = NULL;
 209                         sc->sc_ilen = 0;
 210                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 211                 }
 212         }
 213
 214         if(ista & ISAC_ISTA_XPR)        /* transmit fifo empty (XPR bit set) */
 215         {
 216                 if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
 217                 {
 218                         sc->sc_freeflag = sc->sc_freeflag2;
 219                         sc->sc_obuf = sc->sc_obuf2;
 220                         sc->sc_op = sc->sc_obuf->m_data;
 221                         sc->sc_ol = sc->sc_obuf->m_len;
 222                         sc->sc_obuf2 = NULL;
 223 #ifdef NOTDEF
 224                         kprintf("ob2=%x, op=%x, ol=%d, f=%d #",
 225                                 sc->sc_obuf,
 226                                 sc->sc_op,
 227                                 sc->sc_ol,
 228                                 sc->sc_state);
 229 #endif
 230                 }
 231                 else
 232                 {
 233 #ifdef NOTDEF
 234                         kprintf("ob=%x, op=%x, ol=%d, f=%d #",
 235                                 sc->sc_obuf,
 236                                 sc->sc_op,
 237                                 sc->sc_ol,
 238                                 sc->sc_state);
 239 #endif
 240                 }
 241
 242                 if(sc->sc_obuf)
 243                 {
 244                         ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
 245
 246                         if(sc->sc_ol > ISAC_FIFO_LEN)   /* length > 32 ? */
 247                         {
 248                                 sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
 249                                 sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
 250                                 c |= ISAC_CMDR_XTF;         /* set XTF bit */
 251                         }
 252                         else
 253                         {
 254                                 if(sc->sc_freeflag)
 255                                 {
 256                                         i4b_Dfreembuf(sc->sc_obuf);
 257                                         sc->sc_freeflag = 0;
 258                                 }
 259                                 sc->sc_obuf = NULL;
 260                                 sc->sc_op = NULL;
 261                                 sc->sc_ol = 0;
 262
 263                                 c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
 264                         }
 265                 }
 266                 else
 267                 {
 268                         sc->sc_state &= ~ISAC_TX_ACTIVE;
 269                 }
 270         }
 271
 272         if(ista & ISAC_ISTA_CISQ)       /* channel status change CISQ */
 273         {
 274                 u_char ci;
 275
 276                 /* get command/indication rx register*/
 277
 278                 ci = ISAC_READ(I_CIRR);
 279
 280                 /* if S/Q IRQ, read SQC reg to clr SQC IRQ */
 281
 282                 if(ci & ISAC_CIRR_SQC)
 283                         ISAC_READ(I_SQRR);
 284
 285                 /* C/I code change IRQ (flag already cleared by CIRR read) */
 286
 287                 if(ci & ISAC_CIRR_CIC0)
 288                         isic_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
 289         }
 290
 291         if(c)
 292         {
 293                 ISAC_WRITE(I_CMDR, c);
 294                 ISACCMDRWRDELAY();
 295         }
 296 }
 297
 298 /*---------------------------------------------------------------------------*
 299  *      ISAC L1 Extended IRQ handler
 300  *---------------------------------------------------------------------------*/
 301 static u_char
 302 isic_isac_exir_hdlr(struct l1_softc *sc, u_char exir)
 303 {
 304         u_char c = 0;
 305
 306         if(exir & ISAC_EXIR_XMR)
 307         {
 308                 NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
 309
 310                 c |= ISAC_CMDR_XRES;
 311         }
 312
 313         if(exir & ISAC_EXIR_XDU)
 314         {
 315                 NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
 316
 317                 c |= ISAC_CMDR_XRES;
 318         }
 319
 320         if(exir & ISAC_EXIR_PCE)
 321         {
 322                 NDBGL1(L1_I_ERR, "EXIRQ Protocol Error");
 323         }
 324
 325         if(exir & ISAC_EXIR_RFO)
 326         {
 327                 NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
 328
 329                 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 330         }
 331
 332         if(exir & ISAC_EXIR_SOV)
 333         {
 334                 NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
 335         }
 336
 337         if(exir & ISAC_EXIR_MOS)
 338         {
 339                 NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
 340         }
 341
 342         if(exir & ISAC_EXIR_SAW)
 343         {
 344                 /* cannot happen, STCR:TSF is set to 0 */
 345
 346                 NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
 347         }
 348
 349         if(exir & ISAC_EXIR_WOV)
 350         {
 351                 /* cannot happen, STCR:TSF is set to 0 */
 352
 353                 NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
 354         }
 355
 356         return(c);
 357 }
 358
 359 /*---------------------------------------------------------------------------*
 360  *      ISAC L1 Indication handler
 361  *---------------------------------------------------------------------------*/
 362 static void
 363 isic_isac_ind_hdlr(struct l1_softc *sc, int ind)
 364 {
 365         int event;
 366
 367         switch(ind)
 368         {
 369                 case ISAC_CIRR_IAI8:
 370                         NDBGL1(L1_I_CICO, "rx AI8 in state %s", isic_printstate(sc));
 371                         if(sc->sc_bustyp == BUS_TYPE_IOM2)
 372                                 isic_isac_l1_cmd(sc, CMD_AR8);
 373                         event = EV_INFO48;
 374                         i4b_l1_mph_status_ind(L0ISICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 375                         break;
 376
 377                 case ISAC_CIRR_IAI10:
 378                         NDBGL1(L1_I_CICO, "rx AI10 in state %s", isic_printstate(sc));
 379                         if(sc->sc_bustyp == BUS_TYPE_IOM2)
 380                                 isic_isac_l1_cmd(sc, CMD_AR10);
 381                         event = EV_INFO410;
 382                         i4b_l1_mph_status_ind(L0ISICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 383                         break;
 384
 385                 case ISAC_CIRR_IRSY:
 386                         NDBGL1(L1_I_CICO, "rx RSY in state %s", isic_printstate(sc));
 387                         event = EV_RSY;
 388                         break;
 389
 390                 case ISAC_CIRR_IPU:
 391                         NDBGL1(L1_I_CICO, "rx PU in state %s", isic_printstate(sc));
 392                         event = EV_PU;
 393                         break;
 394
 395                 case ISAC_CIRR_IDR:
 396                         NDBGL1(L1_I_CICO, "rx DR in state %s", isic_printstate(sc));
 397                         isic_isac_l1_cmd(sc, CMD_DIU);
 398                         event = EV_DR;
 399                         break;
 400
 401                 case ISAC_CIRR_IDID:
 402                         NDBGL1(L1_I_CICO, "rx DID in state %s", isic_printstate(sc));
 403                         event = EV_INFO0;
 404                         i4b_l1_mph_status_ind(L0ISICUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
 405                         break;
 406
 407                 case ISAC_CIRR_IDIS:
 408                         NDBGL1(L1_I_CICO, "rx DIS in state %s", isic_printstate(sc));
 409                         event = EV_DIS;
 410                         break;
 411
 412                 case ISAC_CIRR_IEI:
 413                         NDBGL1(L1_I_CICO, "rx EI in state %s", isic_printstate(sc));
 414                         isic_isac_l1_cmd(sc, CMD_DIU);
 415                         event = EV_EI;
 416                         break;
 417
 418                 case ISAC_CIRR_IARD:
 419                         NDBGL1(L1_I_CICO, "rx ARD in state %s", isic_printstate(sc));
 420                         event = EV_INFO2;
 421                         break;
 422
 423                 case ISAC_CIRR_ITI:
 424                         NDBGL1(L1_I_CICO, "rx TI in state %s", isic_printstate(sc));
 425                         event = EV_INFO0;
 426                         break;
 427
 428                 case ISAC_CIRR_IATI:
 429                         NDBGL1(L1_I_CICO, "rx ATI in state %s", isic_printstate(sc));
 430                         event = EV_INFO0;
 431                         break;
 432
 433                 case ISAC_CIRR_ISD:
 434                         NDBGL1(L1_I_CICO, "rx SD in state %s", isic_printstate(sc));
 435                         event = EV_INFO0;
 436                         break;
 437
 438                 default:
 439                         NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, isic_printstate(sc));
 440                         event = EV_INFO0;
 441                         break;
 442         }
 443         isic_next_state(sc, event);
 444 }
 445
 446 /*---------------------------------------------------------------------------*
 447  *      execute a layer 1 command
 448  *---------------------------------------------------------------------------*/
 449 void
 450 isic_isac_l1_cmd(struct l1_softc *sc, int command)
 451 {
 452         u_char cmd;
 453
 454 #ifdef I4B_SMP_WORKAROUND
 455
 456         /* XXXXXXXXXXXXXXXXXXX */
 457
 458         /*
 459          * patch from Wolfgang Helbig:
 460          *
 461          * Here is a patch that makes i4b work on an SMP:
 462          * The card (TELES 16.3) didn't interrupt on an SMP machine.
 463          * This is a gross workaround, but anyway it works *and* provides
 464          * some information as how to finally fix this problem.
 465          */
 466
 467         HSCX_WRITE(0, H_MASK, 0xff);
 468         HSCX_WRITE(1, H_MASK, 0xff);
 469         ISAC_WRITE(I_MASK, 0xff);
 470         DELAY(100);
 471         HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
 472         HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
 473         ISAC_WRITE(I_MASK, ISAC_IMASK);
 474
 475         /* XXXXXXXXXXXXXXXXXXX */
 476
 477 #endif /* I4B_SMP_WORKAROUND */
 478
 479         if(command < 0 || command > CMD_ILL)
 480         {
 481                 NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, isic_printstate(sc));
 482                 return;
 483         }
 484
 485         if(sc->sc_bustyp == BUS_TYPE_IOM2)
 486                 cmd = ISAC_CIX0_LOW;
 487         else
 488                 cmd = 0;
 489
 490         switch(command)
 491         {
 492                 case CMD_TIM:
 493                         NDBGL1(L1_I_CICO, "tx TIM in state %s", isic_printstate(sc));
 494                         cmd |= (ISAC_CIXR_CTIM << 2);
 495                         break;
 496
 497                 case CMD_RS:
 498                         NDBGL1(L1_I_CICO, "tx RS in state %s", isic_printstate(sc));
 499                         cmd |= (ISAC_CIXR_CRS << 2);
 500                         break;
 501
 502                 case CMD_AR8:
 503                         NDBGL1(L1_I_CICO, "tx AR8 in state %s", isic_printstate(sc));
 504                         cmd |= (ISAC_CIXR_CAR8 << 2);
 505                         break;
 506
 507                 case CMD_AR10:
 508                         NDBGL1(L1_I_CICO, "tx AR10 in state %s", isic_printstate(sc));
 509                         cmd |= (ISAC_CIXR_CAR10 << 2);
 510                         break;
 511
 512                 case CMD_DIU:
 513                         NDBGL1(L1_I_CICO, "tx DIU in state %s", isic_printstate(sc));
 514                         cmd |= (ISAC_CIXR_CDIU << 2);
 515                         break;
 516         }
 517         ISAC_WRITE(I_CIXR, cmd);
 518 }
 519
 520 /*---------------------------------------------------------------------------*
 521  *      L1 ISAC initialization
 522  *---------------------------------------------------------------------------*/
 523 int
 524 isic_isac_init(struct l1_softc *sc)
 525 {
 526         ISAC_IMASK = 0xff;              /* disable all irqs */
 527
 528         ISAC_WRITE(I_MASK, ISAC_IMASK);
 529
 530         if(sc->sc_bustyp != BUS_TYPE_IOM2)
 531         {
 532                 NDBGL1(L1_I_SETUP, "configuring for IOM-1 mode");
 533
 534                 /* ADF2: Select mode IOM-1 */
 535                 ISAC_WRITE(I_ADF2, 0x00);
 536
 537                 /* SPCR: serial port control register:
 538                  *      SPU - software power up = 0
 539                  *      SAC - SIP port high Z
 540                  *      SPM - timing mode 0
 541                  *      TLP - test loop = 0
 542                  *      C1C, C2C - B1 and B2 switched to/from SPa
 543                  */
 544                 ISAC_WRITE(I_SPCR, ISAC_SPCR_C1C1|ISAC_SPCR_C2C1);
 545
 546                 /* SQXR: S/Q channel xmit register:
 547                  *      SQIE - S/Q IRQ enable = 0
 548                  *      SQX1-4 - Fa bits = 1
 549                  */
 550                 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
 551
 552                 /* ADF1: additional feature reg 1:
 553                  *      WTC - watchdog = 0
 554                  *      TEM - test mode = 0
 555                  *      PFS - pre-filter = 0
 556                  *      CFS - IOM clock/frame always active
 557                  *      FSC1/2 - polarity of 8kHz strobe
 558                  *      ITF - interframe fill = idle
 559                  */
 560                 ISAC_WRITE(I_ADF1, ISAC_ADF1_FC2);      /* ADF1 */
 561
 562                 /* STCR: sync transfer control reg:
 563                  *      TSF - terminal secific functions = 0
 564                  *      TBA - TIC bus address = 7
 565                  *      STx/SCx = 0
 566                  */
 567                 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
 568
 569                 /* MODE: Mode Register:
 570                  *      MDSx - transparent mode 2
 571                  *      TMD  - timer mode = external
 572                  *      RAC  - Receiver enabled
 573                  *      DIMx - digital i/f mode
 574                  */
 575                 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
 576         }
 577         else
 578         {
 579                 NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
 580
 581                 /* ADF2: Select mode IOM-2 */
 582                 ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
 583
 584                 /* SPCR: serial port control register:
 585                  *      SPU - software power up = 0
 586                  *      SPM - timing mode 0
 587                  *      TLP - test loop = 0
 588                  *      C1C, C2C - B1 + C1 and B2 + IC2 monitoring
 589                  */
 590                 ISAC_WRITE(I_SPCR, 0x00);
 591
 592                 /* SQXR: S/Q channel xmit register:
 593                  *      IDC  - IOM direction = 0 (master)
 594                  *      CFS  - Config Select = 0 (clock always active)
 595                  *      CI1E - C/I channel 1 IRQ enable = 0
 596                  *      SQIE - S/Q IRQ enable = 0
 597                  *      SQX1-4 - Fa bits = 1
 598                  */
 599                 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
 600
 601                 /* ADF1: additional feature reg 1:
 602                  *      WTC - watchdog = 0
 603                  *      TEM - test mode = 0
 604                  *      PFS - pre-filter = 0
 605                  *      IOF - IOM i/f off = 0
 606                  *      ITF - interframe fill = idle
 607                  */
 608                 ISAC_WRITE(I_ADF1, 0x00);
 609
 610                 /* STCR: sync transfer control reg:
 611                  *      TSF - terminal secific functions = 0
 612                  *      TBA - TIC bus address = 7
 613                  *      STx/SCx = 0
 614                  */
 615                 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
 616
 617                 /* MODE: Mode Register:
 618                  *      MDSx - transparent mode 2
 619                  *      TMD  - timer mode = external
 620                  *      RAC  - Receiver enabled
 621                  *      DIMx - digital i/f mode
 622                  */
 623                 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
 624         }
 625
 626 #ifdef NOTDEF
 627         /*
 628          * XXX a transmitter reset causes an ISAC tx IRQ which will not
 629          * be serviced at attach time under some circumstances leaving
 630          * the associated IRQ line on the ISA bus active. This prevents
 631          * any further interrupts to be serviced because no low -> high
 632          * transition can take place anymore. (-hm)
 633          */
 634
 635         /* command register:
 636          *      RRES - HDLC receiver reset
 637          *      XRES - transmitter reset
 638          */
 639         ISAC_WRITE(I_CMDR, ISAC_CMDR_RRES|ISAC_CMDR_XRES);
 640         ISACCMDRWRDELAY();
 641 #endif
 642
 643         /* enabled interrupts:
 644          * ===================
 645          * RME  - receive message end
 646          * RPF  - receive pool full
 647          * XPR  - transmit pool ready
 648          * CISQ - CI or S/Q channel change
 649          * EXI  - extended interrupt
 650          */
 651
 652         ISAC_IMASK = ISAC_MASK_RSC |    /* auto mode only       */
 653                      ISAC_MASK_TIN |    /* timer irq            */
 654                      ISAC_MASK_SIN;     /* sync xfer irq        */
 655
 656         ISAC_WRITE(I_MASK, ISAC_IMASK);
 657
 658         return(0);
 659 }
 660
 661 #endif /* NISIC > 0 */