2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/cputypes.h>
36 #include <machine/md_var.h>
37 #include <machine/pmap.h>
38 #include <machine_base/apic/lapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
40 #include <machine/segments.h>
41 #include <sys/thread2.h>
43 #include <machine/intr_machdep.h>
45 volatile lapic_t *lapic;
47 static void lapic_timer_calibrate(void);
48 static void lapic_timer_set_divisor(int);
49 static void lapic_timer_fixup_handler(void *);
50 static void lapic_timer_restart_handler(void *);
52 void lapic_timer_process(void);
53 void lapic_timer_process_frame(struct intrframe *);
55 static int lapic_timer_enable = 1;
56 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
58 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
59 static void lapic_timer_intr_enable(struct cputimer_intr *);
60 static void lapic_timer_intr_restart(struct cputimer_intr *);
61 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
63 static struct cputimer_intr lapic_cputimer_intr = {
65 .reload = lapic_timer_intr_reload,
66 .enable = lapic_timer_intr_enable,
67 .config = cputimer_intr_default_config,
68 .restart = lapic_timer_intr_restart,
69 .pmfixup = lapic_timer_intr_pmfixup,
70 .initclock = cputimer_intr_default_initclock,
71 .next = SLIST_ENTRY_INITIALIZER,
73 .type = CPUTIMER_INTR_LAPIC,
74 .prio = CPUTIMER_INTR_PRIO_LAPIC,
75 .caps = CPUTIMER_INTR_CAP_NONE
78 static int lapic_timer_divisor_idx = -1;
79 static const uint32_t lapic_timer_divisors[] = {
80 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
81 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
83 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
86 * APIC ID logical/physical mapping structures.
87 * We oversize these to simplify boot-time config.
89 int cpu_num_to_apic_id[NAPICID];
90 int apic_id_to_logical[NAPICID];
93 * Enable LAPIC, configure interrupts.
96 lapic_init(boolean_t bsp)
104 * Since IDT is shared between BSP and APs, these vectors
105 * only need to be installed once; we do it on BSP.
108 /* Install a 'Spurious INTerrupt' vector */
109 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
110 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
112 /* Install an inter-CPU IPI for TLB invalidation */
113 setidt(XINVLTLB_OFFSET, Xinvltlb,
114 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
116 /* Install an inter-CPU IPI for IPIQ messaging */
117 setidt(XIPIQ_OFFSET, Xipiq,
118 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
120 /* Install a timer vector */
121 setidt(XTIMER_OFFSET, Xtimer,
122 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
124 /* Install an inter-CPU IPI for CPU stop/restart */
125 setidt(XCPUSTOP_OFFSET, Xcpustop,
126 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
130 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
131 * aggregate interrupt input from the 8259. The INTA cycle
132 * will be routed to the external controller (the 8259) which
133 * is expected to supply the vector.
135 * Must be setup edge triggered, active high.
137 * Disable LINT0 on BSP, if I/O APIC is enabled.
139 * Disable LINT0 on the APs. It doesn't matter what delivery
140 * mode we use because we leave it masked.
142 temp = lapic->lvt_lint0;
143 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
144 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
146 temp |= APIC_LVT_DM_EXTINT;
148 temp |= APIC_LVT_MASKED;
150 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
152 lapic->lvt_lint0 = temp;
155 * Setup LINT1 as NMI.
157 * Must be setup edge trigger, active high.
159 * Enable LINT1 on BSP, if I/O APIC is enabled.
161 * Disable LINT1 on the APs.
163 temp = lapic->lvt_lint1;
164 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
165 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
166 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
167 if (bsp && apic_io_enable)
168 temp &= ~APIC_LVT_MASKED;
169 lapic->lvt_lint1 = temp;
172 * Mask the LAPIC error interrupt, LAPIC performance counter
175 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
176 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
179 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
181 timer = lapic->lvt_timer;
182 timer &= ~APIC_LVTT_VECTOR;
183 timer |= XTIMER_OFFSET;
184 timer |= APIC_LVTT_MASKED;
185 lapic->lvt_timer = timer;
188 * Set the Task Priority Register as needed. At the moment allow
189 * interrupts on all cpus (the APs will remain CLId until they are
190 * ready to deal). We could disable all but IPIs by setting
191 * temp |= TPR_IPI for cpu != 0.
194 temp &= ~APIC_TPR_PRIO; /* clear priority field */
195 #ifdef SMP /* APIC-IO */
196 if (!apic_io_enable) {
199 * If we are NOT running the IO APICs, the LAPIC will only be used
200 * for IPIs. Set the TPR to prevent any unintentional interrupts.
203 #ifdef SMP /* APIC-IO */
213 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
214 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
217 * Set the spurious interrupt vector. The low 4 bits of the vector
220 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
221 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
222 temp &= ~APIC_SVR_VECTOR;
223 temp |= XSPURIOUSINT_OFFSET;
228 * Pump out a few EOIs to clean out interrupts that got through
229 * before we were able to set the TPR.
236 lapic_timer_calibrate();
237 if (lapic_timer_enable) {
238 cputimer_intr_register(&lapic_cputimer_intr);
239 cputimer_intr_select(&lapic_cputimer_intr, 0);
242 lapic_timer_set_divisor(lapic_timer_divisor_idx);
246 apic_dump("apic_initialize()");
250 lapic_timer_set_divisor(int divisor_idx)
252 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
253 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
257 lapic_timer_oneshot(u_int count)
261 value = lapic->lvt_timer;
262 value &= ~APIC_LVTT_PERIODIC;
263 lapic->lvt_timer = value;
264 lapic->icr_timer = count;
268 lapic_timer_oneshot_quick(u_int count)
270 lapic->icr_timer = count;
274 lapic_timer_calibrate(void)
278 /* Try to calibrate the local APIC timer. */
279 for (lapic_timer_divisor_idx = 0;
280 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
281 lapic_timer_divisor_idx++) {
282 lapic_timer_set_divisor(lapic_timer_divisor_idx);
283 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
285 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
286 if (value != APIC_TIMER_MAX_COUNT)
289 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
290 panic("lapic: no proper timer divisor?!\n");
291 lapic_cputimer_intr.freq = value / 2;
293 kprintf("lapic: divisor index %d, frequency %u Hz\n",
294 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
298 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
302 gd->gd_timer_running = 0;
304 count = sys_cputimer->count();
305 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
306 systimer_intr(&count, 0, frame);
310 lapic_timer_process(void)
312 lapic_timer_process_oncpu(mycpu, NULL);
316 lapic_timer_process_frame(struct intrframe *frame)
318 lapic_timer_process_oncpu(mycpu, frame);
322 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
324 struct globaldata *gd = mycpu;
326 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
330 if (gd->gd_timer_running) {
331 if (reload < lapic->ccr_timer)
332 lapic_timer_oneshot_quick(reload);
334 gd->gd_timer_running = 1;
335 lapic_timer_oneshot_quick(reload);
340 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
344 timer = lapic->lvt_timer;
345 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
346 lapic->lvt_timer = timer;
348 lapic_timer_fixup_handler(NULL);
352 lapic_timer_fixup_handler(void *arg)
359 if (cpu_vendor_id == CPU_VENDOR_AMD) {
361 * Detect the presence of C1E capability mostly on latest
362 * dual-cores (or future) k8 family. This feature renders
363 * the local APIC timer dead, so we disable it by reading
364 * the Interrupt Pending Message register and clearing both
365 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
368 * "BIOS and Kernel Developer's Guide for AMD NPT
369 * Family 0Fh Processors"
370 * #32559 revision 3.00
372 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
373 (cpu_id & 0x0fff0000) >= 0x00040000) {
376 msr = rdmsr(0xc0010055);
377 if (msr & 0x18000000) {
378 struct globaldata *gd = mycpu;
380 kprintf("cpu%d: AMD C1E detected\n",
382 wrmsr(0xc0010055, msr & ~0x18000000ULL);
385 * We are kinda stalled;
388 gd->gd_timer_running = 1;
389 lapic_timer_oneshot_quick(2);
399 lapic_timer_restart_handler(void *dummy __unused)
403 lapic_timer_fixup_handler(&started);
405 struct globaldata *gd = mycpu;
407 gd->gd_timer_running = 1;
408 lapic_timer_oneshot_quick(2);
413 * This function is called only by ACPI-CA code currently:
414 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
415 * module controls PM. So once ACPI-CA is attached, we try
416 * to apply the fixup to prevent LAPIC timer from hanging.
419 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
421 lwkt_send_ipiq_mask(smp_active_mask,
422 lapic_timer_fixup_handler, NULL);
426 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
428 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
433 * dump contents of local APIC registers
438 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
439 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
440 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
444 * Inter Processor Interrupt functions.
448 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
450 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
451 * vector is any valid SYSTEM INT vector
452 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
454 * A backlog of requests can create a deadlock between cpus. To avoid this
455 * we have to be able to accept IPIs at the same time we are trying to send
456 * them. The critical section prevents us from attempting to send additional
457 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
458 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
459 * to occur but fortunately it does not happen too often.
462 apic_ipi(int dest_type, int vector, int delivery_mode)
467 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
468 unsigned int eflags = read_eflags();
470 DEBUG_PUSH_INFO("apic_ipi");
471 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
475 write_eflags(eflags);
478 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
479 delivery_mode | vector;
480 lapic->icr_lo = icr_lo;
486 single_apic_ipi(int cpu, int vector, int delivery_mode)
492 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
493 unsigned int eflags = read_eflags();
495 DEBUG_PUSH_INFO("single_apic_ipi");
496 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
500 write_eflags(eflags);
502 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
503 icr_hi |= (CPU_TO_ID(cpu) << 24);
504 lapic->icr_hi = icr_hi;
507 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
508 | APIC_DEST_DESTFLD | delivery_mode | vector;
511 lapic->icr_lo = icr_lo;
518 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
520 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
521 * to the target, and the scheduler does not 'poll' for IPI messages.
524 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
530 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
534 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
535 icr_hi |= (CPU_TO_ID(cpu) << 24);
536 lapic->icr_hi = icr_hi;
539 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
540 | APIC_DEST_DESTFLD | delivery_mode | vector;
543 lapic->icr_lo = icr_lo;
551 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
553 * target is a bitmask of destination cpus. Vector is any
554 * valid system INT vector. Delivery mode may be either
555 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
558 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
562 int n = BSFCPUMASK(target);
563 target &= ~CPUMASK(n);
564 single_apic_ipi(n, vector, delivery_mode);
570 * Timer code, in development...
571 * - suggested by rgrimes@gndrsh.aac.dev.com
574 get_apic_timer_frequency(void)
576 return(lapic_cputimer_intr.freq);
580 * Load a 'downcount time' in uSeconds.
583 set_apic_timer(int us)
588 * When we reach here, lapic timer's frequency
589 * must have been calculated as well as the
590 * divisor (lapic.dcr_timer is setup during the
591 * divisor calculation).
593 KKASSERT(lapic_cputimer_intr.freq != 0 &&
594 lapic_timer_divisor_idx >= 0);
596 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
597 lapic_timer_oneshot(count);
602 * Read remaining time in timer.
605 read_apic_timer(void)
608 /** XXX FIXME: we need to return the actual remaining time,
609 * for now we just return the remaining count.
612 return lapic->ccr_timer;
618 * Spin-style delay, set delay time in uS, spin till it drains.
623 set_apic_timer(count);
624 while (read_apic_timer())
629 lapic_unused_apic_id(int start)
633 for (i = start; i < NAPICID; ++i) {
634 if (ID_TO_CPU(i) == -1)
641 lapic_map(vm_offset_t lapic_addr)
643 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
645 kprintf("lapic: at %p\n", (void *)lapic_addr);
648 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
649 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
654 struct lapic_enumerator *e;
657 for (i = 0; i < NAPICID; ++i)
660 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
661 error = e->lapic_probe(e);
666 panic("can't config lapic\n");
668 e->lapic_enumerate(e);
672 lapic_enumerator_register(struct lapic_enumerator *ne)
674 struct lapic_enumerator *e;
676 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
677 if (e->lapic_prio < ne->lapic_prio) {
678 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
682 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
686 lapic_set_cpuid(int cpu_id, int apic_id)
688 CPU_TO_ID(cpu_id) = apic_id;
689 ID_TO_CPU(apic_id) = cpu_id;