sys/dev/drm/mga/mga_drv.h

   1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $FreeBSD: src/sys/dev/drm/mga_drv.h,v 1.5.2.1 2003/04/26 07:05:29 anholt Exp $
  31  * $DragonFly: src/sys/dev/drm/mga/Attic/mga_drv.h,v 1.2 2003/06/17 04:28:24 dillon Exp $
  32  */
  33
  34 #ifndef __MGA_DRV_H__
  35 #define __MGA_DRV_H__
  36
  37 typedef struct drm_mga_primary_buffer {
  38         u8 *start;
  39         u8 *end;
  40         int size;
  41
  42         u32 tail;
  43         int space;
  44         volatile long wrapped;
  45
  46         volatile u32 *status;
  47
  48         u32 last_flush;
  49         u32 last_wrap;
  50
  51         u32 high_mark;
  52 } drm_mga_primary_buffer_t;
  53
  54 typedef struct drm_mga_freelist {
  55         struct drm_mga_freelist *next;
  56         struct drm_mga_freelist *prev;
  57         drm_mga_age_t age;
  58         drm_buf_t *buf;
  59 } drm_mga_freelist_t;
  60
  61 typedef struct {
  62         drm_mga_freelist_t *list_entry;
  63         int discard;
  64         int dispatched;
  65 } drm_mga_buf_priv_t;
  66
  67 typedef struct drm_mga_private {
  68         drm_mga_primary_buffer_t prim;
  69         drm_mga_sarea_t *sarea_priv;
  70
  71         drm_mga_freelist_t *head;
  72         drm_mga_freelist_t *tail;
  73
  74         unsigned int warp_pipe;
  75         unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
  76
  77         int chipset;
  78         int usec_timeout;
  79
  80         u32 clear_cmd;
  81         u32 maccess;
  82
  83         unsigned int fb_cpp;
  84         unsigned int front_offset;
  85         unsigned int front_pitch;
  86         unsigned int back_offset;
  87         unsigned int back_pitch;
  88
  89         unsigned int depth_cpp;
  90         unsigned int depth_offset;
  91         unsigned int depth_pitch;
  92
  93         unsigned int texture_offset;
  94         unsigned int texture_size;
  95
  96         drm_local_map_t *sarea;
  97         drm_local_map_t *fb;
  98         drm_local_map_t *mmio;
  99         drm_local_map_t *status;
 100         drm_local_map_t *warp;
 101         drm_local_map_t *primary;
 102         drm_local_map_t *buffers;
 103         drm_local_map_t *agp_textures;
 104 } drm_mga_private_t;
 105
 106                                 /* mga_dma.c */
 107 extern int mga_dma_init( DRM_IOCTL_ARGS );
 108 extern int mga_dma_flush( DRM_IOCTL_ARGS );
 109 extern int mga_dma_reset( DRM_IOCTL_ARGS );
 110 extern int mga_dma_buffers( DRM_IOCTL_ARGS );
 111
 112 extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
 113 extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
 114 extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
 115 extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
 116 extern int mga_do_cleanup_dma( drm_device_t *dev );
 117
 118 extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
 119 extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
 120 extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
 121
 122 extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
 123
 124                                 /* mga_state.c */
 125 extern int  mga_dma_clear( DRM_IOCTL_ARGS );
 126 extern int  mga_dma_swap( DRM_IOCTL_ARGS );
 127 extern int  mga_dma_vertex( DRM_IOCTL_ARGS );
 128 extern int  mga_dma_indices( DRM_IOCTL_ARGS );
 129 extern int  mga_dma_iload( DRM_IOCTL_ARGS );
 130 extern int  mga_dma_blit( DRM_IOCTL_ARGS );
 131 extern int  mga_getparam( DRM_IOCTL_ARGS );
 132
 133                                 /* mga_warp.c */
 134 extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
 135 extern int mga_warp_init( drm_mga_private_t *dev_priv );
 136
 137 #define mga_flush_write_combine()       DRM_WRITEMEMORYBARRIER(dev_priv->primary)
 138
 139 #if defined(__linux__) && defined(__alpha__)
 140 #define MGA_BASE( reg )         ((unsigned long)(dev_priv->mmio->handle))
 141 #define MGA_ADDR( reg )         (MGA_BASE(reg) + reg)
 142
 143 #define MGA_DEREF( reg )        *(volatile u32 *)MGA_ADDR( reg )
 144 #define MGA_DEREF8( reg )       *(volatile u8 *)MGA_ADDR( reg )
 145
 146 #define MGA_READ( reg )         (_MGA_READ((u32 *)MGA_ADDR(reg)))
 147 #define MGA_READ8( reg )        (_MGA_READ((u8 *)MGA_ADDR(reg)))
 148 #define MGA_WRITE( reg, val )   do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF( reg ) = val; } while (0)
 149 #define MGA_WRITE8( reg, val )  do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF8( reg ) = val; } while (0)
 150
 151 static inline u32 _MGA_READ(u32 *addr)
 152 {
 153         DRM_READMEMORYBARRIER(dev_priv->mmio);
 154         return *(volatile u32 *)addr;
 155 }
 156 #else
 157 #define MGA_READ8( reg )        DRM_READ8(dev_priv->mmio, (reg))
 158 #define MGA_READ( reg )         DRM_READ32(dev_priv->mmio, (reg))
 159 #define MGA_WRITE8( reg, val )  DRM_WRITE8(dev_priv->mmio, (reg), (val))
 160 #define MGA_WRITE( reg, val )   DRM_WRITE32(dev_priv->mmio, (reg), (val))
 161 #endif
 162
 163 #define DWGREG0         0x1c00
 164 #define DWGREG0_END     0x1dff
 165 #define DWGREG1         0x2c00
 166 #define DWGREG1_END     0x2dff
 167
 168 #define ISREG0(r)       (r >= DWGREG0 && r <= DWGREG0_END)
 169 #define DMAREG0(r)      (u8)((r - DWGREG0) >> 2)
 170 #define DMAREG1(r)      (u8)(((r - DWGREG1) >> 2) | 0x80)
 171 #define DMAREG(r)       (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
 172
 173
 174
 175 /* ================================================================
 176  * Helper macross...
 177  */
 178
 179 #define MGA_EMIT_STATE( dev_priv, dirty )                               \
 180 do {                                                                    \
 181         if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) {                        \
 182                 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {        \
 183                         mga_g400_emit_state( dev_priv );                \
 184                 } else {                                                \
 185                         mga_g200_emit_state( dev_priv );                \
 186                 }                                                       \
 187         }                                                               \
 188 } while (0)
 189
 190 #define WRAP_TEST_WITH_RETURN( dev_priv )                               \
 191 do {                                                                    \
 192         if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {                 \
 193                 if ( mga_is_idle( dev_priv ) ) {                        \
 194                         mga_do_dma_wrap_end( dev_priv );                \
 195                 } else if ( dev_priv->prim.space <                      \
 196                             dev_priv->prim.high_mark ) {                \
 197                         if ( MGA_DMA_DEBUG )                            \
 198                                 DRM_INFO( "%s: wrap...\n", __FUNCTION__ );      \
 199                         return DRM_ERR(EBUSY);                  \
 200                 }                                                       \
 201         }                                                               \
 202 } while (0)
 203
 204 #define WRAP_WAIT_WITH_RETURN( dev_priv )                               \
 205 do {                                                                    \
 206         if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {                 \
 207                 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {           \
 208                         if ( MGA_DMA_DEBUG )                            \
 209                                 DRM_INFO( "%s: wrap...\n", __FUNCTION__ );      \
 210                         return DRM_ERR(EBUSY);                  \
 211                 }                                                       \
 212                 mga_do_dma_wrap_end( dev_priv );                        \
 213         }                                                               \
 214 } while (0)
 215
 216
 217 /* ================================================================
 218  * Primary DMA command stream
 219  */
 220
 221 #define MGA_VERBOSE     0
 222
 223 #define DMA_LOCALS      unsigned int write; volatile u8 *prim;
 224
 225 #define DMA_BLOCK_SIZE  (5 * sizeof(u32))
 226
 227 #define BEGIN_DMA( n )                                                  \
 228 do {                                                                    \
 229         if ( MGA_VERBOSE ) {                                            \
 230                 DRM_INFO( "BEGIN_DMA( %d ) in %s\n",                    \
 231                           (n), __FUNCTION__ );                          \
 232                 DRM_INFO( "   space=0x%x req=0x%x\n",                   \
 233                           dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
 234         }                                                               \
 235         prim = dev_priv->prim.start;                                    \
 236         write = dev_priv->prim.tail;                                    \
 237 } while (0)
 238
 239 #define BEGIN_DMA_WRAP()                                                \
 240 do {                                                                    \
 241         if ( MGA_VERBOSE ) {                                            \
 242                 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ );                \
 243                 DRM_INFO( "   space=0x%x\n", dev_priv->prim.space );    \
 244         }                                                               \
 245         prim = dev_priv->prim.start;                                    \
 246         write = dev_priv->prim.tail;                                    \
 247 } while (0)
 248
 249 #define ADVANCE_DMA()                                                   \
 250 do {                                                                    \
 251         dev_priv->prim.tail = write;                                    \
 252         if ( MGA_VERBOSE ) {                                            \
 253                 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n",        \
 254                           write, dev_priv->prim.space );                \
 255         }                                                               \
 256 } while (0)
 257
 258 #define FLUSH_DMA()                                                     \
 259 do {                                                                    \
 260         if ( 0 ) {                                                      \
 261                 DRM_INFO( "%s:\n", __FUNCTION__ );                              \
 262                 DRM_INFO( "   tail=0x%06x head=0x%06lx\n",              \
 263                           dev_priv->prim.tail,                          \
 264                           MGA_READ( MGA_PRIMADDRESS ) -                 \
 265                           dev_priv->primary->offset );                  \
 266         }                                                               \
 267         if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) {                \
 268                 if ( dev_priv->prim.space <                             \
 269                      dev_priv->prim.high_mark ) {                       \
 270                         mga_do_dma_wrap_start( dev_priv );              \
 271                 } else {                                                \
 272                         mga_do_dma_flush( dev_priv );                   \
 273                 }                                                       \
 274         }                                                               \
 275 } while (0)
 276
 277 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
 278  */
 279 #define DMA_WRITE( offset, val )                                        \
 280 do {                                                                    \
 281         if ( MGA_VERBOSE ) {                                            \
 282                 DRM_INFO( "   DMA_WRITE( 0x%08x ) at 0x%04x\n",         \
 283                           (u32)(val), write + (offset) * sizeof(u32) ); \
 284         }                                                               \
 285         *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
 286 } while (0)
 287
 288 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 )     \
 289 do {                                                                    \
 290         DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) |                          \
 291                        (DMAREG( reg1 ) << 8) |                          \
 292                        (DMAREG( reg2 ) << 16) |                         \
 293                        (DMAREG( reg3 ) << 24)) );                       \
 294         DMA_WRITE( 1, val0 );                                           \
 295         DMA_WRITE( 2, val1 );                                           \
 296         DMA_WRITE( 3, val2 );                                           \
 297         DMA_WRITE( 4, val3 );                                           \
 298         write += DMA_BLOCK_SIZE;                                        \
 299 } while (0)
 300
 301
 302 /* Buffer aging via primary DMA stream head pointer.
 303  */
 304
 305 #define SET_AGE( age, h, w )                                            \
 306 do {                                                                    \
 307         (age)->head = h;                                                \
 308         (age)->wrap = w;                                                \
 309 } while (0)
 310
 311 #define TEST_AGE( age, h, w )           ( (age)->wrap < w ||            \
 312                                           ( (age)->wrap == w &&         \
 313                                             (age)->head < h ) )
 314
 315 #define AGE_BUFFER( buf_priv )                                          \
 316 do {                                                                    \
 317         drm_mga_freelist_t *entry = (buf_priv)->list_entry;             \
 318         if ( (buf_priv)->dispatched ) {                                 \
 319                 entry->age.head = (dev_priv->prim.tail +                \
 320                                    dev_priv->primary->offset);          \
 321                 entry->age.wrap = dev_priv->sarea_priv->last_wrap;      \
 322         } else {                                                        \
 323                 entry->age.head = 0;                                    \
 324                 entry->age.wrap = 0;                                    \
 325         }                                                               \
 326 } while (0)
 327
 328
 329 #define MGA_ENGINE_IDLE_MASK            (MGA_SOFTRAPEN |                \
 330                                          MGA_DWGENGSTS |                \
 331                                          MGA_ENDPRDMASTS)
 332 #define MGA_DMA_IDLE_MASK               (MGA_SOFTRAPEN |                \
 333                                          MGA_ENDPRDMASTS)
 334
 335 #define MGA_DMA_DEBUG                   0
 336
 337
 338
 339 /* A reduced set of the mga registers.
 340  */
 341 #define MGA_CRTC_INDEX                  0x1fd4
 342 #define MGA_CRTC_DATA                   0x1fd5
 343
 344 /* CRTC11 */
 345 #define MGA_VINTCLR                     (1 << 4)
 346 #define MGA_VINTEN                      (1 << 5)
 347
 348 #define MGA_ALPHACTRL                   0x2c7c
 349 #define MGA_AR0                         0x1c60
 350 #define MGA_AR1                         0x1c64
 351 #define MGA_AR2                         0x1c68
 352 #define MGA_AR3                         0x1c6c
 353 #define MGA_AR4                         0x1c70
 354 #define MGA_AR5                         0x1c74
 355 #define MGA_AR6                         0x1c78
 356
 357 #define MGA_CXBNDRY                     0x1c80
 358 #define MGA_CXLEFT                      0x1ca0
 359 #define MGA_CXRIGHT                     0x1ca4
 360
 361 #define MGA_DMAPAD                      0x1c54
 362 #define MGA_DSTORG                      0x2cb8
 363 #define MGA_DWGCTL                      0x1c00
 364 #       define MGA_OPCOD_MASK                   (15 << 0)
 365 #       define MGA_OPCOD_TRAP                   (4 << 0)
 366 #       define MGA_OPCOD_TEXTURE_TRAP           (6 << 0)
 367 #       define MGA_OPCOD_BITBLT                 (8 << 0)
 368 #       define MGA_OPCOD_ILOAD                  (9 << 0)
 369 #       define MGA_ATYPE_MASK                   (7 << 4)
 370 #       define MGA_ATYPE_RPL                    (0 << 4)
 371 #       define MGA_ATYPE_RSTR                   (1 << 4)
 372 #       define MGA_ATYPE_ZI                     (3 << 4)
 373 #       define MGA_ATYPE_BLK                    (4 << 4)
 374 #       define MGA_ATYPE_I                      (7 << 4)
 375 #       define MGA_LINEAR                       (1 << 7)
 376 #       define MGA_ZMODE_MASK                   (7 << 8)
 377 #       define MGA_ZMODE_NOZCMP                 (0 << 8)
 378 #       define MGA_ZMODE_ZE                     (2 << 8)
 379 #       define MGA_ZMODE_ZNE                    (3 << 8)
 380 #       define MGA_ZMODE_ZLT                    (4 << 8)
 381 #       define MGA_ZMODE_ZLTE                   (5 << 8)
 382 #       define MGA_ZMODE_ZGT                    (6 << 8)
 383 #       define MGA_ZMODE_ZGTE                   (7 << 8)
 384 #       define MGA_SOLID                        (1 << 11)
 385 #       define MGA_ARZERO                       (1 << 12)
 386 #       define MGA_SGNZERO                      (1 << 13)
 387 #       define MGA_SHIFTZERO                    (1 << 14)
 388 #       define MGA_BOP_MASK                     (15 << 16)
 389 #       define MGA_BOP_ZERO                     (0 << 16)
 390 #       define MGA_BOP_DST                      (10 << 16)
 391 #       define MGA_BOP_SRC                      (12 << 16)
 392 #       define MGA_BOP_ONE                      (15 << 16)
 393 #       define MGA_TRANS_SHIFT                  20
 394 #       define MGA_TRANS_MASK                   (15 << 20)
 395 #       define MGA_BLTMOD_MASK                  (15 << 25)
 396 #       define MGA_BLTMOD_BMONOLEF              (0 << 25)
 397 #       define MGA_BLTMOD_BMONOWF               (4 << 25)
 398 #       define MGA_BLTMOD_PLAN                  (1 << 25)
 399 #       define MGA_BLTMOD_BFCOL                 (2 << 25)
 400 #       define MGA_BLTMOD_BU32BGR               (3 << 25)
 401 #       define MGA_BLTMOD_BU32RGB               (7 << 25)
 402 #       define MGA_BLTMOD_BU24BGR               (11 << 25)
 403 #       define MGA_BLTMOD_BU24RGB               (15 << 25)
 404 #       define MGA_PATTERN                      (1 << 29)
 405 #       define MGA_TRANSC                       (1 << 30)
 406 #       define MGA_CLIPDIS                      (1 << 31)
 407 #define MGA_DWGSYNC                     0x2c4c
 408
 409 #define MGA_FCOL                        0x1c24
 410 #define MGA_FIFOSTATUS                  0x1e10
 411 #define MGA_FOGCOL                      0x1cf4
 412 #define MGA_FXBNDRY                     0x1c84
 413 #define MGA_FXLEFT                      0x1ca8
 414 #define MGA_FXRIGHT                     0x1cac
 415
 416 #define MGA_ICLEAR                      0x1e18
 417 #       define MGA_SOFTRAPICLR                  (1 << 0)
 418 #       define MGA_VLINEICLR                    (1 << 5)
 419 #define MGA_IEN                         0x1e1c
 420 #       define MGA_SOFTRAPIEN                   (1 << 0)
 421 #       define MGA_VLINEIEN                     (1 << 5)
 422
 423 #define MGA_LEN                         0x1c5c
 424
 425 #define MGA_MACCESS                     0x1c04
 426
 427 #define MGA_PITCH                       0x1c8c
 428 #define MGA_PLNWT                       0x1c1c
 429 #define MGA_PRIMADDRESS                 0x1e58
 430 #       define MGA_DMA_GENERAL                  (0 << 0)
 431 #       define MGA_DMA_BLIT                     (1 << 0)
 432 #       define MGA_DMA_VECTOR                   (2 << 0)
 433 #       define MGA_DMA_VERTEX                   (3 << 0)
 434 #define MGA_PRIMEND                     0x1e5c
 435 #       define MGA_PRIMNOSTART                  (1 << 0)
 436 #       define MGA_PAGPXFER                     (1 << 1)
 437 #define MGA_PRIMPTR                     0x1e50
 438 #       define MGA_PRIMPTREN0                   (1 << 0)
 439 #       define MGA_PRIMPTREN1                   (1 << 1)
 440
 441 #define MGA_RST                         0x1e40
 442 #       define MGA_SOFTRESET                    (1 << 0)
 443 #       define MGA_SOFTEXTRST                   (1 << 1)
 444
 445 #define MGA_SECADDRESS                  0x2c40
 446 #define MGA_SECEND                      0x2c44
 447 #define MGA_SETUPADDRESS                0x2cd0
 448 #define MGA_SETUPEND                    0x2cd4
 449 #define MGA_SGN                         0x1c58
 450 #define MGA_SOFTRAP                     0x2c48
 451 #define MGA_SRCORG                      0x2cb4
 452 #       define MGA_SRMMAP_MASK                  (1 << 0)
 453 #       define MGA_SRCMAP_FB                    (0 << 0)
 454 #       define MGA_SRCMAP_SYSMEM                (1 << 0)
 455 #       define MGA_SRCACC_MASK                  (1 << 1)
 456 #       define MGA_SRCACC_PCI                   (0 << 1)
 457 #       define MGA_SRCACC_AGP                   (1 << 1)
 458 #define MGA_STATUS                      0x1e14
 459 #       define MGA_SOFTRAPEN                    (1 << 0)
 460 #       define MGA_VSYNCPEN                     (1 << 4)
 461 #       define MGA_VLINEPEN                     (1 << 5)
 462 #       define MGA_DWGENGSTS                    (1 << 16)
 463 #       define MGA_ENDPRDMASTS                  (1 << 17)
 464 #define MGA_STENCIL                     0x2cc8
 465 #define MGA_STENCILCTL                  0x2ccc
 466
 467 #define MGA_TDUALSTAGE0                 0x2cf8
 468 #define MGA_TDUALSTAGE1                 0x2cfc
 469 #define MGA_TEXBORDERCOL                0x2c5c
 470 #define MGA_TEXCTL                      0x2c30
 471 #define MGA_TEXCTL2                     0x2c3c
 472 #       define MGA_DUALTEX                      (1 << 7)
 473 #       define MGA_G400_TC2_MAGIC               (1 << 15)
 474 #       define MGA_MAP1_ENABLE                  (1 << 31)
 475 #define MGA_TEXFILTER                   0x2c58
 476 #define MGA_TEXHEIGHT                   0x2c2c
 477 #define MGA_TEXORG                      0x2c24
 478 #       define MGA_TEXORGMAP_MASK               (1 << 0)
 479 #       define MGA_TEXORGMAP_FB                 (0 << 0)
 480 #       define MGA_TEXORGMAP_SYSMEM             (1 << 0)
 481 #       define MGA_TEXORGACC_MASK               (1 << 1)
 482 #       define MGA_TEXORGACC_PCI                (0 << 1)
 483 #       define MGA_TEXORGACC_AGP                (1 << 1)
 484 #define MGA_TEXORG1                     0x2ca4
 485 #define MGA_TEXORG2                     0x2ca8
 486 #define MGA_TEXORG3                     0x2cac
 487 #define MGA_TEXORG4                     0x2cb0
 488 #define MGA_TEXTRANS                    0x2c34
 489 #define MGA_TEXTRANSHIGH                0x2c38
 490 #define MGA_TEXWIDTH                    0x2c28
 491
 492 #define MGA_WACCEPTSEQ                  0x1dd4
 493 #define MGA_WCODEADDR                   0x1e6c
 494 #define MGA_WFLAG                       0x1dc4
 495 #define MGA_WFLAG1                      0x1de0
 496 #define MGA_WFLAGNB                     0x1e64
 497 #define MGA_WFLAGNB1                    0x1e08
 498 #define MGA_WGETMSB                     0x1dc8
 499 #define MGA_WIADDR                      0x1dc0
 500 #define MGA_WIADDR2                     0x1dd8
 501 #       define MGA_WMODE_SUSPEND                (0 << 0)
 502 #       define MGA_WMODE_RESUME                 (1 << 0)
 503 #       define MGA_WMODE_JUMP                   (2 << 0)
 504 #       define MGA_WMODE_START                  (3 << 0)
 505 #       define MGA_WAGP_ENABLE                  (1 << 2)
 506 #define MGA_WMISC                       0x1e70
 507 #       define MGA_WUCODECACHE_ENABLE           (1 << 0)
 508 #       define MGA_WMASTER_ENABLE               (1 << 1)
 509 #       define MGA_WCACHEFLUSH_ENABLE           (1 << 3)
 510 #define MGA_WVRTXSZ                     0x1dcc
 511
 512 #define MGA_YBOT                        0x1c9c
 513 #define MGA_YDST                        0x1c90
 514 #define MGA_YDSTLEN                     0x1c88
 515 #define MGA_YDSTORG                     0x1c94
 516 #define MGA_YTOP                        0x1c98
 517
 518 #define MGA_ZORG                        0x1c0c
 519
 520 /* This finishes the current batch of commands
 521  */
 522 #define MGA_EXEC                        0x0100
 523
 524 /* Warp registers
 525  */
 526 #define MGA_WR0                         0x2d00
 527 #define MGA_WR1                         0x2d04
 528 #define MGA_WR2                         0x2d08
 529 #define MGA_WR3                         0x2d0c
 530 #define MGA_WR4                         0x2d10
 531 #define MGA_WR5                         0x2d14
 532 #define MGA_WR6                         0x2d18
 533 #define MGA_WR7                         0x2d1c
 534 #define MGA_WR8                         0x2d20
 535 #define MGA_WR9                         0x2d24
 536 #define MGA_WR10                        0x2d28
 537 #define MGA_WR11                        0x2d2c
 538 #define MGA_WR12                        0x2d30
 539 #define MGA_WR13                        0x2d34
 540 #define MGA_WR14                        0x2d38
 541 #define MGA_WR15                        0x2d3c
 542 #define MGA_WR16                        0x2d40
 543 #define MGA_WR17                        0x2d44
 544 #define MGA_WR18                        0x2d48
 545 #define MGA_WR19                        0x2d4c
 546 #define MGA_WR20                        0x2d50
 547 #define MGA_WR21                        0x2d54
 548 #define MGA_WR22                        0x2d58
 549 #define MGA_WR23                        0x2d5c
 550 #define MGA_WR24                        0x2d60
 551 #define MGA_WR25                        0x2d64
 552 #define MGA_WR26                        0x2d68
 553 #define MGA_WR27                        0x2d6c
 554 #define MGA_WR28                        0x2d70
 555 #define MGA_WR29                        0x2d74
 556 #define MGA_WR30                        0x2d78
 557 #define MGA_WR31                        0x2d7c
 558 #define MGA_WR32                        0x2d80
 559 #define MGA_WR33                        0x2d84
 560 #define MGA_WR34                        0x2d88
 561 #define MGA_WR35                        0x2d8c
 562 #define MGA_WR36                        0x2d90
 563 #define MGA_WR37                        0x2d94
 564 #define MGA_WR38                        0x2d98
 565 #define MGA_WR39                        0x2d9c
 566 #define MGA_WR40                        0x2da0
 567 #define MGA_WR41                        0x2da4
 568 #define MGA_WR42                        0x2da8
 569 #define MGA_WR43                        0x2dac
 570 #define MGA_WR44                        0x2db0
 571 #define MGA_WR45                        0x2db4
 572 #define MGA_WR46                        0x2db8
 573 #define MGA_WR47                        0x2dbc
 574 #define MGA_WR48                        0x2dc0
 575 #define MGA_WR49                        0x2dc4
 576 #define MGA_WR50                        0x2dc8
 577 #define MGA_WR51                        0x2dcc
 578 #define MGA_WR52                        0x2dd0
 579 #define MGA_WR53                        0x2dd4
 580 #define MGA_WR54                        0x2dd8
 581 #define MGA_WR55                        0x2ddc
 582 #define MGA_WR56                        0x2de0
 583 #define MGA_WR57                        0x2de4
 584 #define MGA_WR58                        0x2de8
 585 #define MGA_WR59                        0x2dec
 586 #define MGA_WR60                        0x2df0
 587 #define MGA_WR61                        0x2df4
 588 #define MGA_WR62                        0x2df8
 589 #define MGA_WR63                        0x2dfc
 590 #       define MGA_G400_WR_MAGIC                (1 << 6)
 591 #       define MGA_G400_WR56_MAGIC              0x46480000      /* 12800.0f */
 592
 593
 594 #define MGA_ILOAD_ALIGN         64
 595 #define MGA_ILOAD_MASK          (MGA_ILOAD_ALIGN - 1)
 596
 597 #define MGA_DWGCTL_FLUSH        (MGA_OPCOD_TEXTURE_TRAP |               \
 598                                  MGA_ATYPE_I |                          \
 599                                  MGA_ZMODE_NOZCMP |                     \
 600                                  MGA_ARZERO |                           \
 601                                  MGA_SGNZERO |                          \
 602                                  MGA_BOP_SRC |                          \
 603                                  (15 << MGA_TRANS_SHIFT))
 604
 605 #define MGA_DWGCTL_CLEAR        (MGA_OPCOD_TRAP |                       \
 606                                  MGA_ZMODE_NOZCMP |                     \
 607                                  MGA_SOLID |                            \
 608                                  MGA_ARZERO |                           \
 609                                  MGA_SGNZERO |                          \
 610                                  MGA_SHIFTZERO |                        \
 611                                  MGA_BOP_SRC |                          \
 612                                  (0 << MGA_TRANS_SHIFT) |               \
 613                                  MGA_BLTMOD_BMONOLEF |                  \
 614                                  MGA_TRANSC |                           \
 615                                  MGA_CLIPDIS)
 616
 617 #define MGA_DWGCTL_COPY         (MGA_OPCOD_BITBLT |                     \
 618                                  MGA_ATYPE_RPL |                        \
 619                                  MGA_SGNZERO |                          \
 620                                  MGA_SHIFTZERO |                        \
 621                                  MGA_BOP_SRC |                          \
 622                                  (0 << MGA_TRANS_SHIFT) |               \
 623                                  MGA_BLTMOD_BFCOL |                     \
 624                                  MGA_CLIPDIS)
 625
 626 /* Simple idle test.
 627  */
 628 static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
 629 {
 630         u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
 631         return ( status == MGA_ENDPRDMASTS );
 632 }
 633
 634 #endif