sys/dev/netif/mii_layer/brgphy.c

   1 /*      $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $        */
   2
   3 /*
   4  * Copyright (c) 2000
   5  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
  35  * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.18 2007/05/26 08:50:49 sephe Exp $
  36  */
  37
  38 /*
  39  * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
  40  * 1000mbps; all we need to negotiate here is full or half duplex.
  41  */
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/socket.h>
  47 #include <sys/bus.h>
  48
  49 #include <net/ethernet.h>
  50 #include <net/if.h>
  51 #include <net/if_media.h>
  52 #include <net/if_arp.h>
  53
  54 #include "mii.h"
  55 #include "miivar.h"
  56 #include "miidevs.h"
  57
  58 #include "brgphyreg.h"
  59 #include <dev/netif/bge/if_bgereg.h>
  60
  61 #include "miibus_if.h"
  62
  63 static int brgphy_probe(device_t);
  64 static int brgphy_attach(device_t);
  65
  66 static const struct mii_phydesc brgphys[] = {
  67         MII_PHYDESC(xxBROADCOM, BCM5400),
  68         MII_PHYDESC(xxBROADCOM, BCM5401),
  69         MII_PHYDESC(xxBROADCOM, BCM5411),
  70         MII_PHYDESC(xxBROADCOM, BCM5421),
  71         MII_PHYDESC(xxBROADCOM, BCM54K2),
  72         MII_PHYDESC(xxBROADCOM, BCM5462),
  73
  74         MII_PHYDESC(xxBROADCOM, BCM5701),
  75         MII_PHYDESC(xxBROADCOM, BCM5703),
  76         MII_PHYDESC(xxBROADCOM, BCM5704),
  77         MII_PHYDESC(xxBROADCOM, BCM5705),
  78
  79         MII_PHYDESC(xxBROADCOM, BCM5714),
  80         MII_PHYDESC(xxBROADCOM, BCM5750),
  81         MII_PHYDESC(xxBROADCOM, BCM5752),
  82         MII_PHYDESC(xxBROADCOM2,BCM5755),
  83         MII_PHYDESC(xxBROADCOM, BCM5780),
  84         MII_PHYDESC(xxBROADCOM2,BCM5787),
  85
  86         MII_PHYDESC(xxBROADCOM, BCM5706C),
  87         MII_PHYDESC(xxBROADCOM, BCM5708C),
  88
  89         MII_PHYDESC_NULL
  90 };
  91
  92 static device_method_t brgphy_methods[] = {
  93         /* device interface */
  94         DEVMETHOD(device_probe,         brgphy_probe),
  95         DEVMETHOD(device_attach,        brgphy_attach),
  96         DEVMETHOD(device_detach,        ukphy_detach),
  97         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  98         { 0, 0 }
  99 };
 100
 101 static devclass_t brgphy_devclass;
 102
 103 static driver_t brgphy_driver = {
 104         "brgphy",
 105         brgphy_methods,
 106         sizeof(struct mii_softc)
 107 };
 108
 109 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
 110
 111 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 112 static void     brgphy_status(struct mii_softc *);
 113 static void     brgphy_mii_phy_auto(struct mii_softc *);
 114 static void     brgphy_reset(struct mii_softc *);
 115 static void     brgphy_loop(struct mii_softc *);
 116
 117 static void     brgphy_bcm5401_dspcode(struct mii_softc *);
 118 static void     brgphy_bcm5411_dspcode(struct mii_softc *);
 119 static void     brgphy_bcm5421_dspcode(struct mii_softc *);
 120 static void     brgphy_bcm54k2_dspcode(struct mii_softc *);
 121
 122 static void     brgphy_adc_bug(struct mii_softc *);
 123 static void     brgphy_5704_a0_bug(struct mii_softc *);
 124 static void     brgphy_ber_bug(struct mii_softc *);
 125 static void     brgphy_crc_bug(struct mii_softc *);
 126
 127 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 128 static void     brgphy_eth_wirespeed(struct mii_softc *);
 129
 130 static int
 131 brgphy_probe(device_t dev)
 132 {
 133         struct mii_attach_args *ma = device_get_ivars(dev);
 134         const struct mii_phydesc *mpd;
 135
 136         mpd = mii_phy_match(ma, brgphys);
 137         if (mpd != NULL) {
 138                 device_set_desc(dev, mpd->mpd_name);
 139                 return (0);
 140         }
 141         return(ENXIO);
 142 }
 143
 144 static int
 145 brgphy_attach(device_t dev)
 146 {
 147         struct mii_softc *sc;
 148         struct mii_attach_args *ma;
 149         struct mii_data *mii;
 150
 151         sc = device_get_softc(dev);
 152         ma = device_get_ivars(dev);
 153         mii_softc_init(sc, ma);
 154         sc->mii_dev = device_get_parent(dev);
 155         mii = device_get_softc(sc->mii_dev);
 156         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 157
 158         sc->mii_inst = mii->mii_instance;
 159         sc->mii_service = brgphy_service;
 160         sc->mii_reset = brgphy_reset;
 161         sc->mii_pdata = mii;
 162
 163         sc->mii_flags |= MIIF_NOISOLATE;
 164         mii->mii_instance++;
 165
 166         brgphy_reset(sc);
 167
 168 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 169
 170         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
 171             MII_MEDIA_NONE);
 172 #if 0
 173         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
 174             MII_MEDIA_100_TX);
 175 #endif
 176
 177 #undef ADD
 178
 179         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 180         if (sc->mii_capabilities & BMSR_EXTSTAT)
 181                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 182
 183         device_printf(dev, " ");
 184         if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
 185             (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
 186                 mii_phy_add_media(sc);
 187         else
 188                 kprintf("no media present");
 189         kprintf("\n");
 190
 191         MIIBUS_MEDIAINIT(sc->mii_dev);
 192         return(0);
 193 }
 194
 195 static int
 196 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 197 {
 198         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 199         int reg, speed, gig;
 200
 201         switch (cmd) {
 202         case MII_POLLSTAT:
 203                 /*
 204                  * If we're not polling our PHY instance, just return.
 205                  */
 206                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 207                         return (0);
 208                 break;
 209
 210         case MII_MEDIACHG:
 211                 /*
 212                  * If the media indicates a different PHY instance,
 213                  * isolate ourselves.
 214                  */
 215                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 216                         reg = PHY_READ(sc, MII_BMCR);
 217                         PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
 218                         return (0);
 219                 }
 220
 221                 /*
 222                  * If the interface is not up, don't do anything.
 223                  */
 224                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 225                         break;
 226
 227                 brgphy_reset(sc);       /* XXX hardware bug work-around */
 228
 229                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 230                 case IFM_AUTO:
 231 #ifdef foo
 232                         /*
 233                          * If we're already in auto mode, just return.
 234                          */
 235                         if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
 236                                 return (0);
 237 #endif
 238                         brgphy_mii_phy_auto(sc);
 239                         break;
 240                 case IFM_1000_T:
 241                         speed = BRGPHY_S1000;
 242                         goto setit;
 243                 case IFM_100_TX:
 244                         speed = BRGPHY_S100;
 245                         goto setit;
 246                 case IFM_10_T:
 247                         speed = BRGPHY_S10;
 248 setit:
 249                         brgphy_loop(sc);
 250                         if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
 251                                 speed |= BRGPHY_BMCR_FDX;
 252                                 gig = BRGPHY_1000CTL_AFD;
 253                         } else {
 254                                 gig = BRGPHY_1000CTL_AHD;
 255                         }
 256
 257                         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 258                         PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
 259                         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 260
 261                         if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
 262                                 break;
 263
 264                         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 265                         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 266                             speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
 267
 268                         if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
 269                                 break;
 270
 271                         /*
 272                          * When settning the link manually, one side must
 273                          * be the master and the other the slave. However
 274                          * ifmedia doesn't give us a good way to specify
 275                          * this, so we fake it by using one of the LINK
 276                          * flags. If LINK0 is set, we program the PHY to
 277                          * be a master, otherwise it's a slave.
 278                          */
 279                         if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
 280                                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 281                                     gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
 282                         } else {
 283                                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 284                                     gig|BRGPHY_1000CTL_MSE);
 285                         }
 286                         break;
 287 #ifdef foo
 288                 case IFM_NONE:
 289                         PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
 290                         break;
 291 #endif
 292                 case IFM_100_T4:
 293                 default:
 294                         return (EINVAL);
 295                 }
 296                 break;
 297
 298         case MII_TICK:
 299                 /*
 300                  * If we're not currently selected, just return.
 301                  */
 302                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 303                         return (0);
 304
 305                 /*
 306                  * Is the interface even up?
 307                  */
 308                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 309                         return (0);
 310
 311                 /*
 312                  * Only used for autonegotiation.
 313                  */
 314                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
 315                         break;
 316
 317                 /*
 318                  * Check to see if we have link.  If we do, we don't
 319                  * need to restart the autonegotiation process.  Read
 320                  * the BMSR twice in case it's latched.
 321                  */
 322                 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 323                 if (reg & BRGPHY_AUXSTS_LINK)
 324                         break;
 325
 326                 /*
 327                  * Only retry autonegotiation every 5 seconds.
 328                  */
 329                 if (++sc->mii_ticks <= sc->mii_anegticks)
 330                         break;
 331
 332                 sc->mii_ticks = 0;
 333                 brgphy_mii_phy_auto(sc);
 334                 break;
 335         }
 336
 337         /* Update the media status. */
 338         brgphy_status(sc);
 339
 340         /*
 341          * Callback if something changed. Note that we need to poke
 342          * the DSP on the Broadcom PHYs if the media changes.
 343          */
 344         if (sc->mii_media_active != mii->mii_media_active ||
 345             sc->mii_media_status != mii->mii_media_status ||
 346             cmd == MII_MEDIACHG) {
 347                 switch (sc->mii_model) {
 348                 case MII_MODEL_xxBROADCOM_BCM5400:
 349                         brgphy_bcm5401_dspcode(sc);
 350                         break;
 351                 case MII_MODEL_xxBROADCOM_BCM5401:
 352                         if (sc->mii_rev == 1 || sc->mii_rev == 3)
 353                                 brgphy_bcm5401_dspcode(sc);
 354                         break;
 355                 case MII_MODEL_xxBROADCOM_BCM5411:
 356                         brgphy_bcm5411_dspcode(sc);
 357                         break;
 358                 }
 359         }
 360         mii_phy_update(sc, cmd);
 361         return (0);
 362 }
 363
 364 static void
 365 brgphy_status(struct mii_softc *sc)
 366 {
 367         struct mii_data *mii = sc->mii_pdata;
 368         int bmcr, aux;
 369
 370         mii->mii_media_status = IFM_AVALID;
 371         mii->mii_media_active = IFM_ETHER;
 372
 373         aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 374         if (aux & BRGPHY_AUXSTS_LINK)
 375                 mii->mii_media_status |= IFM_ACTIVE;
 376
 377         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 378         if (bmcr & BRGPHY_BMCR_LOOP)
 379                 mii->mii_media_active |= IFM_LOOP;
 380
 381         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 382                 if ((PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_ACOMP) == 0) {
 383                         /* Erg, still trying, I guess... */
 384                         mii->mii_media_active |= IFM_NONE;
 385                         return;
 386                 }
 387
 388                 switch (aux & BRGPHY_AUXSTS_AN_RES) {
 389                 case BRGPHY_RES_1000FD:
 390                         mii->mii_media_active |= IFM_1000_T | IFM_FDX;
 391                         break;
 392                 case BRGPHY_RES_1000HD:
 393                         mii->mii_media_active |= IFM_1000_T | IFM_HDX;
 394                         break;
 395                 case BRGPHY_RES_100FD:
 396                         mii->mii_media_active |= IFM_100_TX | IFM_FDX;
 397                         break;
 398                 case BRGPHY_RES_100T4:
 399                         mii->mii_media_active |= IFM_100_T4;
 400                         break;
 401                 case BRGPHY_RES_100HD:
 402                         mii->mii_media_active |= IFM_100_TX | IFM_HDX;
 403                         break;
 404                 case BRGPHY_RES_10FD:
 405                         mii->mii_media_active |= IFM_10_T | IFM_FDX;
 406                         break;
 407                 case BRGPHY_RES_10HD:
 408                         mii->mii_media_active |= IFM_10_T | IFM_HDX;
 409                         break;
 410                 default:
 411                         mii->mii_media_active |= IFM_NONE;
 412                         break;
 413                 }
 414         } else {
 415                 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media;
 416         }
 417 }
 418
 419
 420 static void
 421 brgphy_mii_phy_auto(struct mii_softc *sc)
 422 {
 423         int ktcr = 0;
 424
 425         brgphy_loop(sc);
 426         brgphy_reset(sc);
 427         ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
 428         if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
 429                 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
 430         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 431         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 432         DELAY(1000);
 433         PHY_WRITE(sc, BRGPHY_MII_ANAR,
 434             BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
 435         DELAY(1000);
 436         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 437             BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 438         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 439 }
 440
 441 static void
 442 brgphy_loop(struct mii_softc *sc)
 443 {
 444         uint32_t bmsr;
 445         int i;
 446
 447         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 448         for (i = 0; i < 15000; i++) {
 449                 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
 450                 if (!(bmsr & BRGPHY_BMSR_LINK))
 451                         break;
 452                 DELAY(10);
 453         }
 454 }
 455
 456 static void
 457 brgphy_reset(struct mii_softc *sc)
 458 {
 459         struct ifnet *ifp;
 460
 461         mii_phy_reset(sc);
 462
 463         switch (sc->mii_model) {
 464         case MII_MODEL_xxBROADCOM_BCM5400:
 465                 brgphy_bcm5401_dspcode(sc);
 466                         break;
 467         case MII_MODEL_xxBROADCOM_BCM5401:
 468                 if (sc->mii_rev == 1 || sc->mii_rev == 3)
 469                         brgphy_bcm5401_dspcode(sc);
 470                 break;
 471         case MII_MODEL_xxBROADCOM_BCM5411:
 472                 brgphy_bcm5411_dspcode(sc);
 473                 break;
 474         case MII_MODEL_xxBROADCOM_BCM5421:
 475                 brgphy_bcm5421_dspcode(sc);
 476                 break;
 477         case MII_MODEL_xxBROADCOM_BCM54K2:
 478                 brgphy_bcm54k2_dspcode(sc);
 479                 break;
 480         }
 481
 482         ifp = sc->mii_pdata->mii_ifp;
 483         if (strncmp(ifp->if_xname, "bge", 3) == 0) {
 484                 struct bge_softc *bge_sc = ifp->if_softc;
 485
 486                 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
 487                         brgphy_adc_bug(sc);
 488                 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
 489                         brgphy_5704_a0_bug(sc);
 490                 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) {
 491                         brgphy_ber_bug(sc);
 492                 } else if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) {
 493                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
 494                         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
 495
 496                         if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) {
 497                                 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
 498                                 PHY_WRITE(sc, BRGPHY_TEST1,
 499                                     BRGPHY_TEST1_TRIM_EN | 0x4);
 500                         } else {
 501                                 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
 502                         }
 503
 504                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
 505                 }
 506                 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
 507                         brgphy_crc_bug(sc);
 508
 509                 /* Set Jumbo frame settings in the PHY. */
 510                 brgphy_jumbo_settings(sc, ifp->if_mtu);
 511
 512                 /* Enable Ethernet@Wirespeed */
 513                 if (bge_sc->bge_flags & BGE_FLAG_ETH_WIRESPEED)
 514                         brgphy_eth_wirespeed(sc);
 515
 516                 /* Enable Link LED on Dell boxes */
 517                 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
 518                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 519                         PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
 520                                 & ~BRGPHY_PHY_EXTCTL_3_LED);
 521                 }
 522         } else if (strncmp(ifp->if_xname, "bce", 3) == 0) {
 523                 brgphy_ber_bug(sc);
 524                 brgphy_jumbo_settings(sc, ifp->if_mtu);
 525                 brgphy_eth_wirespeed(sc);
 526         }
 527 }
 528
 529 /* Turn off tap power management on 5401. */
 530 static void
 531 brgphy_bcm5401_dspcode(struct mii_softc *sc)
 532 {
 533         static const struct {
 534                 int             reg;
 535                 uint16_t        val;
 536         } dspcode[] = {
 537                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 538                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 539                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 540                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 541                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 542                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 543                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 544                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 545                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 546                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 547                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 548                 { 0,                            0 },
 549         };
 550         int i;
 551
 552         for (i = 0; dspcode[i].reg != 0; i++)
 553                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 554         DELAY(40);
 555 }
 556
 557 /* Setting some undocumented voltage */
 558 static void
 559 brgphy_bcm5411_dspcode(struct mii_softc *sc)
 560 {
 561         static const struct {
 562                 int             reg;
 563                 uint16_t        val;
 564         } dspcode[] = {
 565                 { 0x1c,                         0x8c23 },
 566                 { 0x1c,                         0x8ca3 },
 567                 { 0x1c,                         0x8c23 },
 568                 { 0,                            0 },
 569         };
 570         int i;
 571
 572         for (i = 0; dspcode[i].reg != 0; i++)
 573                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 574 }
 575
 576 static void
 577 brgphy_bcm5421_dspcode(struct mii_softc *sc)
 578 {
 579         uint16_t data;
 580
 581         /* Set Class A mode */
 582         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
 583         data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 584         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
 585
 586         /* Set FFE gamma override to -0.125 */
 587         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
 588         data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 589         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
 590         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
 591         data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 592         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
 593 }
 594
 595 static void
 596 brgphy_bcm54k2_dspcode(struct mii_softc *sc)
 597 {
 598         static const struct {
 599                 int             reg;
 600                 uint16_t        val;
 601         } dspcode[] = {
 602                 { 4,                            0x01e1 },
 603                 { 9,                            0x0300 },
 604                 { 0,                            0 },
 605         };
 606         int i;
 607
 608         for (i = 0; dspcode[i].reg != 0; i++)
 609                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 610 }
 611
 612 static void
 613 brgphy_adc_bug(struct mii_softc *sc)
 614 {
 615         static const struct {
 616                 int             reg;
 617                 uint16_t        val;
 618         } dspcode[] = {
 619                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 620                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 621                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 622                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 623                 { BRGPHY_MII_DSP_RW_PORT,       0x0323 },
 624                 { BRGPHY_MII_AUXCTL,            0x0400 },
 625                 { 0,                            0 },
 626         };
 627         int i;
 628
 629         for (i = 0; dspcode[i].reg != 0; i++)
 630                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 631 }
 632
 633 static void
 634 brgphy_5704_a0_bug(struct mii_softc *sc)
 635 {
 636         static const struct {
 637                 int             reg;
 638                 u_int16_t       val;
 639         } dspcode[] = {
 640                 { 0x1c,                         0x8d68 },
 641                 { 0x1c,                         0x8d68 },
 642                 { 0,                            0 },
 643         };
 644         int i;
 645
 646         for (i = 0; dspcode[i].reg != 0; i++)
 647                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 648 }
 649
 650 static void
 651 brgphy_ber_bug(struct mii_softc *sc)
 652 {
 653         static const struct {
 654                 int             reg;
 655                 uint16_t        val;
 656         } dspcode[] = {
 657                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 658                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 659                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 660                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 661                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 662                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 663                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 664                 { BRGPHY_MII_AUXCTL,            0x0400 },
 665                 { 0,                            0 },
 666         };
 667         int i;
 668
 669         for (i = 0; dspcode[i].reg != 0; i++)
 670                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 671 }
 672
 673 static void
 674 brgphy_crc_bug(struct mii_softc *sc)
 675 {
 676         static const struct {
 677                 int             reg;
 678                 uint16_t        val;
 679         } dspcode[] = {
 680                 { BRGPHY_MII_DSP_ADDR_REG,      0x0a75 },
 681                 { 0x1c,                         0x8c68 },
 682                 { 0x1c,                         0x8d68 },
 683                 { 0x1c,                         0x8c68 },
 684                 { 0,                            0 },
 685         };
 686         int i;
 687
 688         for (i = 0; dspcode[i].reg != 0; i++)
 689                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 690 }
 691
 692 static void
 693 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 694 {
 695         uint32_t val;
 696
 697         /* Set or clear jumbo frame settings in the PHY. */
 698         if (mtu > ETHER_MAX_LEN) {
 699                 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
 700                         /* BCM5401 PHY cannot read-modify-write. */
 701                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 702                 } else {
 703                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 704                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 705                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 706                             val | BRGPHY_AUXCTL_LONG_PKT);
 707                 }
 708
 709                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 710                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 711                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 712         } else {
 713                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 714                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 715                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 716                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 717
 718                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 719                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 720                     val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 721         }
 722 }
 723
 724 static void
 725 brgphy_eth_wirespeed(struct mii_softc *sc)
 726 {
 727         u_int32_t val;
 728
 729         /* Enable Ethernet@Wirespeed */
 730         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 731         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 732         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4)));
 733 }