2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/export.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
47 static const struct dp_link_dpll gen4_dpll[] = {
49 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
54 static const struct dp_link_dpll pch_dpll[] = {
56 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
61 static const struct dp_link_dpll vlv_dpll[] = {
63 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
69 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
70 * @intel_dp: DP struct
72 * If a CPU or PCH DP output is attached to an eDP panel, this function
73 * will return true, and false otherwise.
75 static bool is_edp(struct intel_dp *intel_dp)
77 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
79 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
82 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
84 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
86 return intel_dig_port->base.base.dev;
89 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
91 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
94 static void intel_dp_link_down(struct intel_dp *intel_dp);
97 intel_dp_max_link_bw(struct intel_dp *intel_dp)
99 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
101 switch (max_link_bw) {
102 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
106 max_link_bw = DP_LINK_BW_2_7;
109 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
111 max_link_bw = DP_LINK_BW_1_62;
118 * The units on the numbers in the next two are... bizarre. Examples will
119 * make it clearer; this one parallels an example in the eDP spec.
121 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
123 * 270000 * 1 * 8 / 10 == 216000
125 * The actual data capacity of that configuration is 2.16Gbit/s, so the
126 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
127 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
128 * 119000. At 18bpp that's 2142000 kilobits per second.
130 * Thus the strange-looking division by 10 in intel_dp_link_required, to
131 * get the result in decakilobits instead of kilobits.
135 intel_dp_link_required(int pixel_clock, int bpp)
137 return (pixel_clock * bpp + 9) / 10;
141 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
143 return (max_link_clock * max_lanes * 8) / 10;
146 static enum drm_mode_status
147 intel_dp_mode_valid(struct drm_connector *connector,
148 struct drm_display_mode *mode)
150 struct intel_dp *intel_dp = intel_attached_dp(connector);
151 struct intel_connector *intel_connector = to_intel_connector(connector);
152 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
153 int target_clock = mode->clock;
154 int max_rate, mode_rate, max_lanes, max_link_clock;
156 if (is_edp(intel_dp) && fixed_mode) {
157 if (mode->hdisplay > fixed_mode->hdisplay)
160 if (mode->vdisplay > fixed_mode->vdisplay)
163 target_clock = fixed_mode->clock;
166 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
167 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
169 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
170 mode_rate = intel_dp_link_required(target_clock, 18);
172 if (mode_rate > max_rate)
173 return MODE_CLOCK_HIGH;
175 if (mode->clock < 10000)
176 return MODE_CLOCK_LOW;
178 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
179 return MODE_H_ILLEGAL;
185 pack_aux(uint8_t *src, int src_bytes)
192 for (i = 0; i < src_bytes; i++)
193 v |= ((uint32_t) src[i]) << ((3-i) * 8);
198 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
203 for (i = 0; i < dst_bytes; i++)
204 dst[i] = src >> ((3-i) * 8);
207 /* hrawclock is 1/4 the FSB frequency */
209 intel_hrawclk(struct drm_device *dev)
211 struct drm_i915_private *dev_priv = dev->dev_private;
214 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
215 if (IS_VALLEYVIEW(dev))
218 clkcfg = I915_READ(CLKCFG);
219 switch (clkcfg & CLKCFG_FSB_MASK) {
228 case CLKCFG_FSB_1067:
230 case CLKCFG_FSB_1333:
232 /* these two are just a guess; one of them might be right */
233 case CLKCFG_FSB_1600:
234 case CLKCFG_FSB_1600_ALT:
242 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
243 struct intel_dp *intel_dp,
244 struct edp_power_seq *out);
246 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
247 struct intel_dp *intel_dp,
248 struct edp_power_seq *out);
250 static enum i915_pipe
251 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
254 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
255 struct drm_device *dev = intel_dig_port->base.base.dev;
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 enum port port = intel_dig_port->port;
260 /* modeset should have pipe */
262 return to_intel_crtc(crtc)->pipe;
264 /* init time, try to find a pipe with this port selected */
265 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
266 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
267 PANEL_PORT_SELECT_MASK;
268 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
270 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
278 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
280 struct drm_device *dev = intel_dp_to_dev(intel_dp);
282 if (HAS_PCH_SPLIT(dev))
283 return PCH_PP_CONTROL;
285 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
288 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
290 struct drm_device *dev = intel_dp_to_dev(intel_dp);
292 if (HAS_PCH_SPLIT(dev))
293 return PCH_PP_STATUS;
295 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
298 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
300 struct drm_device *dev = intel_dp_to_dev(intel_dp);
301 struct drm_i915_private *dev_priv = dev->dev_private;
303 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
306 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
308 struct drm_device *dev = intel_dp_to_dev(intel_dp);
309 struct drm_i915_private *dev_priv = dev->dev_private;
311 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
315 intel_dp_check_edp(struct intel_dp *intel_dp)
317 struct drm_device *dev = intel_dp_to_dev(intel_dp);
318 struct drm_i915_private *dev_priv = dev->dev_private;
320 if (!is_edp(intel_dp))
323 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
324 WARN(1, "eDP powered off while attempting aux channel communication.\n");
325 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
326 I915_READ(_pp_stat_reg(intel_dp)),
327 I915_READ(_pp_ctrl_reg(intel_dp)));
332 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct drm_device *dev = intel_dig_port->base.base.dev;
336 struct drm_i915_private *dev_priv = dev->dev_private;
337 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
341 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
343 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
344 msecs_to_jiffies_timeout(10));
346 done = wait_for_atomic(C, 10) == 0;
348 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
355 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
358 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
359 struct drm_device *dev = intel_dig_port->base.base.dev;
360 struct drm_i915_private *dev_priv = dev->dev_private;
362 /* The clock divider is based off the hrawclk,
363 * and would like to run at 2MHz. So, take the
364 * hrawclk value and divide by 2 and use that
366 * Note that PCH attached eDP panels should use a 125MHz input
369 if (IS_VALLEYVIEW(dev)) {
370 return index ? 0 : 100;
371 } else if (intel_dig_port->port == PORT_A) {
375 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
376 else if (IS_GEN6(dev) || IS_GEN7(dev))
377 return 200; /* SNB & IVB eDP input clock at 400Mhz */
379 return 225; /* eDP input clock at 450Mhz */
380 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
381 /* Workaround for non-ULT HSW */
387 } else if (HAS_PCH_SPLIT(dev)) {
388 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
390 return index ? 0 :intel_hrawclk(dev) / 2;
395 intel_dp_aux_ch(struct intel_dp *intel_dp,
396 uint8_t *send, int send_bytes,
397 uint8_t *recv, int recv_size)
399 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
400 struct drm_device *dev = intel_dig_port->base.base.dev;
401 struct drm_i915_private *dev_priv = dev->dev_private;
402 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
403 uint32_t ch_data = ch_ctl + 4;
404 uint32_t aux_clock_divider;
405 int i, ret, recv_bytes;
407 int try, precharge, clock = 0;
408 bool has_aux_irq = HAS_AUX_IRQ(dev);
411 /* dp aux is extremely sensitive to irq latency, hence request the
412 * lowest possible wakeup latency and so prevent the cpu from going into
415 pm_qos_update_request(&dev_priv->pm_qos, 0);
417 intel_dp_check_edp(intel_dp);
424 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
425 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
427 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
429 intel_aux_display_runtime_get(dev_priv);
431 /* Try to wait for any previous AUX channel activity */
432 for (try = 0; try < 3; try++) {
433 status = I915_READ_NOTRACE(ch_ctl);
434 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
440 WARN(1, "dp_aux_ch not started status 0x%08x\n",
446 /* Only 5 data registers! */
447 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
452 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
453 /* Must try at least 3 times according to DP spec */
454 for (try = 0; try < 5; try++) {
455 /* Load the send data into the aux channel data registers */
456 for (i = 0; i < send_bytes; i += 4)
457 I915_WRITE(ch_data + i,
458 pack_aux(send + i, send_bytes - i));
460 /* Send the command and wait for it to complete */
462 DP_AUX_CH_CTL_SEND_BUSY |
463 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
465 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
466 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
467 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
469 DP_AUX_CH_CTL_TIME_OUT_ERROR |
470 DP_AUX_CH_CTL_RECEIVE_ERROR);
472 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
474 /* Clear done status and any errors */
478 DP_AUX_CH_CTL_TIME_OUT_ERROR |
479 DP_AUX_CH_CTL_RECEIVE_ERROR);
481 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
482 DP_AUX_CH_CTL_RECEIVE_ERROR))
484 if (status & DP_AUX_CH_CTL_DONE)
487 if (status & DP_AUX_CH_CTL_DONE)
491 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
492 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
497 /* Check for timeout or receive error.
498 * Timeouts occur when the sink is not connected
500 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
501 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
506 /* Timeouts occur when the device isn't connected, so they're
507 * "normal" -- don't fill the kernel log with these */
508 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
509 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
514 /* Unload any bytes sent back from the other side */
515 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
516 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
517 if (recv_bytes > recv_size)
518 recv_bytes = recv_size;
520 for (i = 0; i < recv_bytes; i += 4)
521 unpack_aux(I915_READ(ch_data + i),
522 recv + i, recv_bytes - i);
526 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
527 intel_aux_display_runtime_put(dev_priv);
532 /* Write data to the aux channel in native mode */
534 intel_dp_aux_native_write(struct intel_dp *intel_dp,
535 uint16_t address, uint8_t *send, int send_bytes)
543 if (WARN_ON(send_bytes > 16))
546 intel_dp_check_edp(intel_dp);
547 msg[0] = DP_AUX_NATIVE_WRITE << 4;
548 msg[1] = address >> 8;
549 msg[2] = address & 0xff;
550 msg[3] = send_bytes - 1;
551 memcpy(&msg[4], send, send_bytes);
552 msg_bytes = send_bytes + 4;
553 for (retry = 0; retry < 7; retry++) {
554 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
558 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
560 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
561 usleep_range(400, 500);
566 DRM_ERROR("too many retries, giving up\n");
570 /* Write a single byte to the aux channel in native mode */
572 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
573 uint16_t address, uint8_t byte)
575 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
578 /* read bytes from a native aux channel */
580 intel_dp_aux_native_read(struct intel_dp *intel_dp,
581 uint16_t address, uint8_t *recv, int recv_bytes)
591 if (WARN_ON(recv_bytes > 19))
594 intel_dp_check_edp(intel_dp);
595 msg[0] = DP_AUX_NATIVE_READ << 4;
596 msg[1] = address >> 8;
597 msg[2] = address & 0xff;
598 msg[3] = recv_bytes - 1;
601 reply_bytes = recv_bytes + 1;
603 for (retry = 0; retry < 7; retry++) {
604 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
611 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
612 memcpy(recv, reply + 1, ret - 1);
615 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
616 usleep_range(400, 500);
621 DRM_ERROR("too many retries, giving up\n");
626 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
627 uint8_t write_byte, uint8_t *read_byte)
629 struct i2c_algo_dp_aux_data *data = device_get_softc(adapter);
630 struct intel_dp *intel_dp = data->priv;
631 uint16_t address = data->address;
639 ironlake_edp_panel_vdd_on(intel_dp);
640 intel_dp_check_edp(intel_dp);
641 /* Set up the command byte */
642 if (mode & MODE_I2C_READ)
643 msg[0] = DP_AUX_I2C_READ << 4;
645 msg[0] = DP_AUX_I2C_WRITE << 4;
647 if (!(mode & MODE_I2C_STOP))
648 msg[0] |= DP_AUX_I2C_MOT << 4;
650 msg[1] = address >> 8;
672 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
673 * required to retry at least seven times upon receiving AUX_DEFER
674 * before giving up the AUX transaction.
676 for (retry = 0; retry < 7; retry++) {
677 ret = intel_dp_aux_ch(intel_dp,
681 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
685 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
686 case DP_AUX_NATIVE_REPLY_ACK:
687 /* I2C-over-AUX Reply field is only valid
688 * when paired with AUX ACK.
691 case DP_AUX_NATIVE_REPLY_NACK:
692 DRM_DEBUG_KMS("aux_ch native nack\n");
695 case DP_AUX_NATIVE_REPLY_DEFER:
697 * For now, just give more slack to branch devices. We
698 * could check the DPCD for I2C bit rate capabilities,
699 * and if available, adjust the interval. We could also
700 * be more careful with DP-to-Legacy adapters where a
701 * long legacy cable may force very low I2C bit rates.
703 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
704 DP_DWN_STRM_PORT_PRESENT)
705 usleep_range(500, 600);
707 usleep_range(300, 400);
710 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
716 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
717 case DP_AUX_I2C_REPLY_ACK:
718 if (mode == MODE_I2C_READ) {
719 *read_byte = reply[1];
721 ret = 0; /* reply_bytes - 1 */
723 case DP_AUX_I2C_REPLY_NACK:
724 DRM_DEBUG_KMS("aux_i2c nack\n");
727 case DP_AUX_I2C_REPLY_DEFER:
728 DRM_DEBUG_KMS("aux_i2c defer\n");
732 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
738 DRM_ERROR("too many retries, giving up\n");
742 ironlake_edp_panel_vdd_off(intel_dp, false);
747 intel_dp_i2c_init(struct intel_dp *intel_dp,
748 struct intel_connector *intel_connector, const char *name)
752 DRM_DEBUG_KMS("i2c_init %s\n", name);
754 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
755 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
761 intel_dp_set_clock(struct intel_encoder *encoder,
762 struct intel_crtc_config *pipe_config, int link_bw)
764 struct drm_device *dev = encoder->base.dev;
765 const struct dp_link_dpll *divisor = NULL;
770 count = ARRAY_SIZE(gen4_dpll);
771 } else if (IS_HASWELL(dev)) {
772 /* Haswell has special-purpose DP DDI clocks. */
773 } else if (HAS_PCH_SPLIT(dev)) {
775 count = ARRAY_SIZE(pch_dpll);
776 } else if (IS_VALLEYVIEW(dev)) {
778 count = ARRAY_SIZE(vlv_dpll);
781 if (divisor && count) {
782 for (i = 0; i < count; i++) {
783 if (link_bw == divisor[i].link_bw) {
784 pipe_config->dpll = divisor[i].dpll;
785 pipe_config->clock_set = true;
793 intel_dp_compute_config(struct intel_encoder *encoder,
794 struct intel_crtc_config *pipe_config)
796 struct drm_device *dev = encoder->base.dev;
797 struct drm_i915_private *dev_priv = dev->dev_private;
798 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
799 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
800 enum port port = dp_to_dig_port(intel_dp)->port;
801 struct intel_crtc *intel_crtc = encoder->new_crtc;
802 struct intel_connector *intel_connector = intel_dp->attached_connector;
803 int lane_count, clock;
804 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
805 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
807 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
808 int link_avail, link_clock;
810 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
811 pipe_config->has_pch_encoder = true;
813 pipe_config->has_dp_encoder = true;
815 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
816 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
818 if (!HAS_PCH_SPLIT(dev))
819 intel_gmch_panel_fitting(intel_crtc, pipe_config,
820 intel_connector->panel.fitting_mode);
822 intel_pch_panel_fitting(intel_crtc, pipe_config,
823 intel_connector->panel.fitting_mode);
826 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
829 DRM_DEBUG_KMS("DP link computation with max lane count %i "
830 "max bw %02x pixel clock %iKHz\n",
831 max_lane_count, bws[max_clock],
832 adjusted_mode->crtc_clock);
834 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
836 bpp = pipe_config->pipe_bpp;
837 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
838 dev_priv->vbt.edp_bpp < bpp) {
839 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
840 dev_priv->vbt.edp_bpp);
841 bpp = dev_priv->vbt.edp_bpp;
844 for (; bpp >= 6*3; bpp -= 2*3) {
845 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
848 for (clock = 0; clock <= max_clock; clock++) {
849 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
850 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
851 link_avail = intel_dp_max_data_rate(link_clock,
854 if (mode_rate <= link_avail) {
864 if (intel_dp->color_range_auto) {
867 * CEA-861-E - 5.1 Default Encoding Parameters
868 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
870 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
871 intel_dp->color_range = DP_COLOR_RANGE_16_235;
873 intel_dp->color_range = 0;
876 if (intel_dp->color_range)
877 pipe_config->limited_color_range = true;
879 intel_dp->link_bw = bws[clock];
880 intel_dp->lane_count = lane_count;
881 pipe_config->pipe_bpp = bpp;
882 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
884 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
885 intel_dp->link_bw, intel_dp->lane_count,
886 pipe_config->port_clock, bpp);
887 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
888 mode_rate, link_avail);
890 intel_link_compute_m_n(bpp, lane_count,
891 adjusted_mode->crtc_clock,
892 pipe_config->port_clock,
893 &pipe_config->dp_m_n);
895 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
900 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
902 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
903 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
904 struct drm_device *dev = crtc->base.dev;
905 struct drm_i915_private *dev_priv = dev->dev_private;
908 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
909 dpa_ctl = I915_READ(DP_A);
910 dpa_ctl &= ~DP_PLL_FREQ_MASK;
912 if (crtc->config.port_clock == 162000) {
913 /* For a long time we've carried around a ILK-DevA w/a for the
914 * 160MHz clock. If we're really unlucky, it's still required.
916 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
917 dpa_ctl |= DP_PLL_FREQ_160MHZ;
918 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
920 dpa_ctl |= DP_PLL_FREQ_270MHZ;
921 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
924 I915_WRITE(DP_A, dpa_ctl);
930 static void intel_dp_mode_set(struct intel_encoder *encoder)
932 struct drm_device *dev = encoder->base.dev;
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
935 enum port port = dp_to_dig_port(intel_dp)->port;
936 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
937 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
940 * There are four kinds of DP registers:
947 * IBX PCH and CPU are the same for almost everything,
948 * except that the CPU DP PLL is configured in this
951 * CPT PCH is quite different, having many bits moved
952 * to the TRANS_DP_CTL register instead. That
953 * configuration happens (oddly) in ironlake_pch_enable
956 /* Preserve the BIOS-computed detected bit. This is
957 * supposed to be read-only.
959 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
961 /* Handle DP bits in common between all three register formats */
962 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
963 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
965 if (intel_dp->has_audio) {
966 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
967 pipe_name(crtc->pipe));
968 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
969 intel_write_eld(&encoder->base, adjusted_mode);
972 /* Split out the IBX/CPU vs CPT settings */
974 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
975 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
976 intel_dp->DP |= DP_SYNC_HS_HIGH;
977 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
978 intel_dp->DP |= DP_SYNC_VS_HIGH;
979 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
981 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
982 intel_dp->DP |= DP_ENHANCED_FRAMING;
984 intel_dp->DP |= crtc->pipe << 29;
985 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
986 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
987 intel_dp->DP |= intel_dp->color_range;
989 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
990 intel_dp->DP |= DP_SYNC_HS_HIGH;
991 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
992 intel_dp->DP |= DP_SYNC_VS_HIGH;
993 intel_dp->DP |= DP_LINK_TRAIN_OFF;
995 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
996 intel_dp->DP |= DP_ENHANCED_FRAMING;
999 intel_dp->DP |= DP_PIPEB_SELECT;
1001 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1004 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1005 ironlake_set_pll_cpu_edp(intel_dp);
1008 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1009 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1011 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1012 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1014 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1015 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1017 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1021 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 pp_stat_reg, pp_ctrl_reg;
1025 pp_stat_reg = _pp_stat_reg(intel_dp);
1026 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1028 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1030 I915_READ(pp_stat_reg),
1031 I915_READ(pp_ctrl_reg));
1033 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1034 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1035 I915_READ(pp_stat_reg),
1036 I915_READ(pp_ctrl_reg));
1039 DRM_DEBUG_KMS("Wait complete\n");
1042 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1044 DRM_DEBUG_KMS("Wait for panel power on\n");
1045 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1048 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1050 DRM_DEBUG_KMS("Wait for panel power off time\n");
1051 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1054 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1056 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1057 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1061 /* Read the current pp_control value, unlocking the register if it
1065 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1067 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1071 control = I915_READ(_pp_ctrl_reg(intel_dp));
1072 control &= ~PANEL_UNLOCK_MASK;
1073 control |= PANEL_UNLOCK_REGS;
1077 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1082 u32 pp_stat_reg, pp_ctrl_reg;
1084 if (!is_edp(intel_dp))
1087 WARN(intel_dp->want_panel_vdd,
1088 "eDP VDD already requested on\n");
1090 intel_dp->want_panel_vdd = true;
1092 if (ironlake_edp_have_panel_vdd(intel_dp))
1095 intel_runtime_pm_get(dev_priv);
1097 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1099 if (!ironlake_edp_have_panel_power(intel_dp))
1100 ironlake_wait_panel_power_cycle(intel_dp);
1102 pp = ironlake_get_pp_control(intel_dp);
1103 pp |= EDP_FORCE_VDD;
1105 pp_stat_reg = _pp_stat_reg(intel_dp);
1106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1108 I915_WRITE(pp_ctrl_reg, pp);
1109 POSTING_READ(pp_ctrl_reg);
1110 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1111 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1113 * If the panel wasn't on, delay before accessing aux channel
1115 if (!ironlake_edp_have_panel_power(intel_dp)) {
1116 DRM_DEBUG_KMS("eDP was not running\n");
1117 msleep(intel_dp->panel_power_up_delay);
1121 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1124 struct drm_i915_private *dev_priv = dev->dev_private;
1126 u32 pp_stat_reg, pp_ctrl_reg;
1128 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1130 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1131 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1133 pp = ironlake_get_pp_control(intel_dp);
1134 pp &= ~EDP_FORCE_VDD;
1136 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1137 pp_stat_reg = _pp_stat_reg(intel_dp);
1139 I915_WRITE(pp_ctrl_reg, pp);
1140 POSTING_READ(pp_ctrl_reg);
1142 /* Make sure sequencer is idle before allowing subsequent activity */
1143 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1144 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1146 if ((pp & POWER_TARGET_ON) == 0)
1147 msleep(intel_dp->panel_power_cycle_delay);
1149 intel_runtime_pm_put(dev_priv);
1153 static void ironlake_panel_vdd_work(struct work_struct *__work)
1155 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1156 struct intel_dp, panel_vdd_work);
1157 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1159 mutex_lock(&dev->mode_config.mutex);
1160 ironlake_panel_vdd_off_sync(intel_dp);
1161 mutex_unlock(&dev->mode_config.mutex);
1164 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1166 if (!is_edp(intel_dp))
1169 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1171 intel_dp->want_panel_vdd = false;
1174 ironlake_panel_vdd_off_sync(intel_dp);
1177 * Queue the timer to fire a long
1178 * time from now (relative to the power down delay)
1179 * to keep the panel power up across a sequence of operations
1181 schedule_delayed_work(&intel_dp->panel_vdd_work,
1182 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1186 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1188 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1193 if (!is_edp(intel_dp))
1196 DRM_DEBUG_KMS("Turn eDP power on\n");
1198 if (ironlake_edp_have_panel_power(intel_dp)) {
1199 DRM_DEBUG_KMS("eDP power already on\n");
1203 ironlake_wait_panel_power_cycle(intel_dp);
1205 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1206 pp = ironlake_get_pp_control(intel_dp);
1208 /* ILK workaround: disable reset around power sequence */
1209 pp &= ~PANEL_POWER_RESET;
1210 I915_WRITE(pp_ctrl_reg, pp);
1211 POSTING_READ(pp_ctrl_reg);
1214 pp |= POWER_TARGET_ON;
1216 pp |= PANEL_POWER_RESET;
1218 I915_WRITE(pp_ctrl_reg, pp);
1219 POSTING_READ(pp_ctrl_reg);
1221 ironlake_wait_panel_on(intel_dp);
1224 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1225 I915_WRITE(pp_ctrl_reg, pp);
1226 POSTING_READ(pp_ctrl_reg);
1230 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1233 struct drm_i915_private *dev_priv = dev->dev_private;
1237 if (!is_edp(intel_dp))
1240 DRM_DEBUG_KMS("Turn eDP power off\n");
1242 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1244 pp = ironlake_get_pp_control(intel_dp);
1245 /* We need to switch off panel power _and_ force vdd, for otherwise some
1246 * panels get very unhappy and cease to work. */
1247 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1249 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1251 I915_WRITE(pp_ctrl_reg, pp);
1252 POSTING_READ(pp_ctrl_reg);
1254 intel_dp->want_panel_vdd = false;
1256 ironlake_wait_panel_off(intel_dp);
1258 /* We got a reference when we enabled the VDD. */
1259 intel_runtime_pm_put(dev_priv);
1262 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1264 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1265 struct drm_device *dev = intel_dig_port->base.base.dev;
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1270 if (!is_edp(intel_dp))
1273 DRM_DEBUG_KMS("\n");
1275 * If we enable the backlight right away following a panel power
1276 * on, we may see slight flicker as the panel syncs with the eDP
1277 * link. So delay a bit to make sure the image is solid before
1278 * allowing it to appear.
1280 msleep(intel_dp->backlight_on_delay);
1281 pp = ironlake_get_pp_control(intel_dp);
1282 pp |= EDP_BLC_ENABLE;
1284 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1286 I915_WRITE(pp_ctrl_reg, pp);
1287 POSTING_READ(pp_ctrl_reg);
1289 intel_panel_enable_backlight(intel_dp->attached_connector);
1292 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1294 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1299 if (!is_edp(intel_dp))
1302 intel_panel_disable_backlight(intel_dp->attached_connector);
1304 DRM_DEBUG_KMS("\n");
1305 pp = ironlake_get_pp_control(intel_dp);
1306 pp &= ~EDP_BLC_ENABLE;
1308 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1310 I915_WRITE(pp_ctrl_reg, pp);
1311 POSTING_READ(pp_ctrl_reg);
1312 msleep(intel_dp->backlight_off_delay);
1315 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1317 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1318 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1319 struct drm_device *dev = crtc->dev;
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1323 assert_pipe_disabled(dev_priv,
1324 to_intel_crtc(crtc)->pipe);
1326 DRM_DEBUG_KMS("\n");
1327 dpa_ctl = I915_READ(DP_A);
1328 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1329 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1331 /* We don't adjust intel_dp->DP while tearing down the link, to
1332 * facilitate link retraining (e.g. after hotplug). Hence clear all
1333 * enable bits here to ensure that we don't enable too much. */
1334 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1335 intel_dp->DP |= DP_PLL_ENABLE;
1336 I915_WRITE(DP_A, intel_dp->DP);
1341 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1344 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1345 struct drm_device *dev = crtc->dev;
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1349 assert_pipe_disabled(dev_priv,
1350 to_intel_crtc(crtc)->pipe);
1352 dpa_ctl = I915_READ(DP_A);
1353 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1354 "dp pll off, should be on\n");
1355 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1357 /* We can't rely on the value tracked for the DP register in
1358 * intel_dp->DP because link_down must not change that (otherwise link
1359 * re-training will fail. */
1360 dpa_ctl &= ~DP_PLL_ENABLE;
1361 I915_WRITE(DP_A, dpa_ctl);
1366 /* If the sink supports it, try to set the power state appropriately */
1367 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1371 /* Should have a valid DPCD by this point */
1372 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1375 if (mode != DRM_MODE_DPMS_ON) {
1376 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1379 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1382 * When turning on, we need to retry for 1ms to give the sink
1385 for (i = 0; i < 3; i++) {
1386 ret = intel_dp_aux_native_write_1(intel_dp,
1396 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1397 enum i915_pipe *pipe)
1399 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1400 enum port port = dp_to_dig_port(intel_dp)->port;
1401 struct drm_device *dev = encoder->base.dev;
1402 struct drm_i915_private *dev_priv = dev->dev_private;
1403 u32 tmp = I915_READ(intel_dp->output_reg);
1405 if (!(tmp & DP_PORT_EN))
1408 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1409 *pipe = PORT_TO_PIPE_CPT(tmp);
1410 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1411 *pipe = PORT_TO_PIPE(tmp);
1417 switch (intel_dp->output_reg) {
1419 trans_sel = TRANS_DP_PORT_SEL_B;
1422 trans_sel = TRANS_DP_PORT_SEL_C;
1425 trans_sel = TRANS_DP_PORT_SEL_D;
1432 trans_dp = I915_READ(TRANS_DP_CTL(i));
1433 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1439 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1440 intel_dp->output_reg);
1446 static void intel_dp_get_config(struct intel_encoder *encoder,
1447 struct intel_crtc_config *pipe_config)
1449 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1451 struct drm_device *dev = encoder->base.dev;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 enum port port = dp_to_dig_port(intel_dp)->port;
1454 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1457 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1458 tmp = I915_READ(intel_dp->output_reg);
1459 if (tmp & DP_SYNC_HS_HIGH)
1460 flags |= DRM_MODE_FLAG_PHSYNC;
1462 flags |= DRM_MODE_FLAG_NHSYNC;
1464 if (tmp & DP_SYNC_VS_HIGH)
1465 flags |= DRM_MODE_FLAG_PVSYNC;
1467 flags |= DRM_MODE_FLAG_NVSYNC;
1469 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1470 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1471 flags |= DRM_MODE_FLAG_PHSYNC;
1473 flags |= DRM_MODE_FLAG_NHSYNC;
1475 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1476 flags |= DRM_MODE_FLAG_PVSYNC;
1478 flags |= DRM_MODE_FLAG_NVSYNC;
1481 pipe_config->adjusted_mode.flags |= flags;
1483 pipe_config->has_dp_encoder = true;
1485 intel_dp_get_m_n(crtc, pipe_config);
1487 if (port == PORT_A) {
1488 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1489 pipe_config->port_clock = 162000;
1491 pipe_config->port_clock = 270000;
1494 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1495 &pipe_config->dp_m_n);
1497 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1498 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1500 pipe_config->adjusted_mode.crtc_clock = dotclock;
1502 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1503 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1505 * This is a big fat ugly hack.
1507 * Some machines in UEFI boot mode provide us a VBT that has 18
1508 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1509 * unknown we fail to light up. Yet the same BIOS boots up with
1510 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1511 * max, not what it tells us to use.
1513 * Note: This will still be broken if the eDP panel is not lit
1514 * up by the BIOS, and thus we can't get the mode at module
1517 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1518 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1519 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1523 static bool is_edp_psr(struct drm_device *dev)
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1527 return dev_priv->psr.sink_support;
1530 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1537 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1540 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1541 struct edp_vsc_psr *vsc_psr)
1543 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1544 struct drm_device *dev = dig_port->base.base.dev;
1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1547 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1548 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1549 uint32_t *data = (uint32_t *) vsc_psr;
1552 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1553 the video DIP being updated before program video DIP data buffer
1554 registers for DIP being updated. */
1555 I915_WRITE(ctl_reg, 0);
1556 POSTING_READ(ctl_reg);
1558 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1559 if (i < sizeof(struct edp_vsc_psr))
1560 I915_WRITE(data_reg + i, *data++);
1562 I915_WRITE(data_reg + i, 0);
1565 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1566 POSTING_READ(ctl_reg);
1569 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1571 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 struct edp_vsc_psr psr_vsc;
1575 if (intel_dp->psr_setup_done)
1578 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1579 memset(&psr_vsc, 0, sizeof(psr_vsc));
1580 psr_vsc.sdp_header.HB0 = 0;
1581 psr_vsc.sdp_header.HB1 = 0x7;
1582 psr_vsc.sdp_header.HB2 = 0x2;
1583 psr_vsc.sdp_header.HB3 = 0x8;
1584 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1586 /* Avoid continuous PSR exit by masking memup and hpd */
1587 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1588 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1590 intel_dp->psr_setup_done = true;
1593 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1595 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1598 int precharge = 0x3;
1599 int msg_size = 5; /* Header(4) + Message(1) */
1601 /* Enable PSR in sink */
1602 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1603 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1605 ~DP_PSR_MAIN_LINK_ACTIVE);
1607 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1609 DP_PSR_MAIN_LINK_ACTIVE);
1611 /* Setup AUX registers */
1612 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1613 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1614 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1615 DP_AUX_CH_CTL_TIME_OUT_400us |
1616 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1617 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1618 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1621 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1623 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 uint32_t max_sleep_time = 0x1f;
1626 uint32_t idle_frames = 1;
1628 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1630 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1631 val |= EDP_PSR_LINK_STANDBY;
1632 val |= EDP_PSR_TP2_TP3_TIME_0us;
1633 val |= EDP_PSR_TP1_TIME_0us;
1634 val |= EDP_PSR_SKIP_AUX_EXIT;
1636 val |= EDP_PSR_LINK_DISABLE;
1638 I915_WRITE(EDP_PSR_CTL(dev), val |
1639 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1640 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1641 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1645 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1647 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1648 struct drm_device *dev = dig_port->base.base.dev;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 struct drm_crtc *crtc = dig_port->base.base.crtc;
1651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1652 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1653 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1655 dev_priv->psr.source_ok = false;
1657 if (!HAS_PSR(dev)) {
1658 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1662 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1663 (dig_port->port != PORT_A)) {
1664 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1668 if (!i915_enable_psr) {
1669 DRM_DEBUG_KMS("PSR disable by flag\n");
1673 crtc = dig_port->base.base.crtc;
1675 DRM_DEBUG_KMS("crtc not active for PSR\n");
1679 intel_crtc = to_intel_crtc(crtc);
1680 if (!intel_crtc_active(crtc)) {
1681 DRM_DEBUG_KMS("crtc not active for PSR\n");
1685 obj = to_intel_framebuffer(crtc->fb)->obj;
1686 if (obj->tiling_mode != I915_TILING_X ||
1687 obj->fence_reg == I915_FENCE_REG_NONE) {
1688 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1692 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1693 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1697 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1699 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1703 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1704 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1708 dev_priv->psr.source_ok = true;
1712 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1714 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1716 if (!intel_edp_psr_match_conditions(intel_dp) ||
1717 intel_edp_is_psr_enabled(dev))
1720 /* Setup PSR once */
1721 intel_edp_psr_setup(intel_dp);
1723 /* Enable PSR on the panel */
1724 intel_edp_psr_enable_sink(intel_dp);
1726 /* Enable PSR on the host */
1727 intel_edp_psr_enable_source(intel_dp);
1730 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1732 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1734 if (intel_edp_psr_match_conditions(intel_dp) &&
1735 !intel_edp_is_psr_enabled(dev))
1736 intel_edp_psr_do_enable(intel_dp);
1739 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1741 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1744 if (!intel_edp_is_psr_enabled(dev))
1747 I915_WRITE(EDP_PSR_CTL(dev),
1748 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1750 /* Wait till PSR is idle */
1751 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1752 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1753 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1756 void intel_edp_psr_update(struct drm_device *dev)
1758 struct intel_encoder *encoder;
1759 struct intel_dp *intel_dp = NULL;
1761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1762 if (encoder->type == INTEL_OUTPUT_EDP) {
1763 intel_dp = enc_to_intel_dp(&encoder->base);
1765 if (!is_edp_psr(dev))
1768 if (!intel_edp_psr_match_conditions(intel_dp))
1769 intel_edp_psr_disable(intel_dp);
1771 if (!intel_edp_is_psr_enabled(dev))
1772 intel_edp_psr_do_enable(intel_dp);
1776 static void intel_disable_dp(struct intel_encoder *encoder)
1778 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1779 enum port port = dp_to_dig_port(intel_dp)->port;
1780 struct drm_device *dev = encoder->base.dev;
1782 /* Make sure the panel is off before trying to change the mode. But also
1783 * ensure that we have vdd while we switch off the panel. */
1784 ironlake_edp_panel_vdd_on(intel_dp);
1785 ironlake_edp_backlight_off(intel_dp);
1786 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1787 ironlake_edp_panel_off(intel_dp);
1789 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1790 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1791 intel_dp_link_down(intel_dp);
1794 static void intel_post_disable_dp(struct intel_encoder *encoder)
1796 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1797 enum port port = dp_to_dig_port(intel_dp)->port;
1798 struct drm_device *dev = encoder->base.dev;
1800 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1801 intel_dp_link_down(intel_dp);
1802 if (!IS_VALLEYVIEW(dev))
1803 ironlake_edp_pll_off(intel_dp);
1807 static void intel_enable_dp(struct intel_encoder *encoder)
1809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1810 struct drm_device *dev = encoder->base.dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1814 if (WARN_ON(dp_reg & DP_PORT_EN))
1817 ironlake_edp_panel_vdd_on(intel_dp);
1818 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1819 intel_dp_start_link_train(intel_dp);
1820 ironlake_edp_panel_on(intel_dp);
1821 ironlake_edp_panel_vdd_off(intel_dp, true);
1822 intel_dp_complete_link_train(intel_dp);
1823 intel_dp_stop_link_train(intel_dp);
1826 static void g4x_enable_dp(struct intel_encoder *encoder)
1828 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1830 intel_enable_dp(encoder);
1831 ironlake_edp_backlight_on(intel_dp);
1834 static void vlv_enable_dp(struct intel_encoder *encoder)
1836 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1838 ironlake_edp_backlight_on(intel_dp);
1841 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1844 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1846 if (dport->port == PORT_A)
1847 ironlake_edp_pll_on(intel_dp);
1850 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1852 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1853 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1854 struct drm_device *dev = encoder->base.dev;
1855 struct drm_i915_private *dev_priv = dev->dev_private;
1856 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1857 enum dpio_channel port = vlv_dport_to_channel(dport);
1858 int pipe = intel_crtc->pipe;
1859 struct edp_power_seq power_seq;
1862 mutex_lock(&dev_priv->dpio_lock);
1864 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1871 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1872 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1873 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1875 mutex_unlock(&dev_priv->dpio_lock);
1877 if (is_edp(intel_dp)) {
1878 /* init power sequencer on this pipe and port */
1879 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1880 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1884 intel_enable_dp(encoder);
1886 vlv_wait_port_ready(dev_priv, dport);
1889 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1891 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1892 struct drm_device *dev = encoder->base.dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 struct intel_crtc *intel_crtc =
1895 to_intel_crtc(encoder->base.crtc);
1896 enum dpio_channel port = vlv_dport_to_channel(dport);
1897 int pipe = intel_crtc->pipe;
1899 /* Program Tx lane resets to default */
1900 mutex_lock(&dev_priv->dpio_lock);
1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1902 DPIO_PCS_TX_LANE2_RESET |
1903 DPIO_PCS_TX_LANE1_RESET);
1904 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1905 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1906 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1907 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1908 DPIO_PCS_CLK_SOFT_RESET);
1910 /* Fix up inter-pair skew failure */
1911 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1912 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1913 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1914 mutex_unlock(&dev_priv->dpio_lock);
1918 * Native read with retry for link status and receiver capability reads for
1919 * cases where the sink may still be asleep.
1922 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1923 uint8_t *recv, int recv_bytes)
1928 * Sinks are *supposed* to come up within 1ms from an off state,
1929 * but we're also supposed to retry 3 times per the spec.
1931 for (i = 0; i < 3; i++) {
1932 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1934 if (ret == recv_bytes)
1943 * Fetch AUX CH registers 0x202 - 0x207 which contain
1944 * link status information
1947 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1949 return intel_dp_aux_native_read_retry(intel_dp,
1952 DP_LINK_STATUS_SIZE);
1956 * These are source-specific values; current Intel hardware supports
1957 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1961 intel_dp_voltage_max(struct intel_dp *intel_dp)
1963 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1964 enum port port = dp_to_dig_port(intel_dp)->port;
1966 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1967 return DP_TRAIN_VOLTAGE_SWING_1200;
1968 else if (IS_GEN7(dev) && port == PORT_A)
1969 return DP_TRAIN_VOLTAGE_SWING_800;
1970 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1971 return DP_TRAIN_VOLTAGE_SWING_1200;
1973 return DP_TRAIN_VOLTAGE_SWING_800;
1977 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1979 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1980 enum port port = dp_to_dig_port(intel_dp)->port;
1982 if (IS_BROADWELL(dev)) {
1983 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1984 case DP_TRAIN_VOLTAGE_SWING_400:
1985 case DP_TRAIN_VOLTAGE_SWING_600:
1986 return DP_TRAIN_PRE_EMPHASIS_6;
1987 case DP_TRAIN_VOLTAGE_SWING_800:
1988 return DP_TRAIN_PRE_EMPHASIS_3_5;
1989 case DP_TRAIN_VOLTAGE_SWING_1200:
1991 return DP_TRAIN_PRE_EMPHASIS_0;
1993 } else if (IS_HASWELL(dev)) {
1994 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1995 case DP_TRAIN_VOLTAGE_SWING_400:
1996 return DP_TRAIN_PRE_EMPHASIS_9_5;
1997 case DP_TRAIN_VOLTAGE_SWING_600:
1998 return DP_TRAIN_PRE_EMPHASIS_6;
1999 case DP_TRAIN_VOLTAGE_SWING_800:
2000 return DP_TRAIN_PRE_EMPHASIS_3_5;
2001 case DP_TRAIN_VOLTAGE_SWING_1200:
2003 return DP_TRAIN_PRE_EMPHASIS_0;
2005 } else if (IS_VALLEYVIEW(dev)) {
2006 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2007 case DP_TRAIN_VOLTAGE_SWING_400:
2008 return DP_TRAIN_PRE_EMPHASIS_9_5;
2009 case DP_TRAIN_VOLTAGE_SWING_600:
2010 return DP_TRAIN_PRE_EMPHASIS_6;
2011 case DP_TRAIN_VOLTAGE_SWING_800:
2012 return DP_TRAIN_PRE_EMPHASIS_3_5;
2013 case DP_TRAIN_VOLTAGE_SWING_1200:
2015 return DP_TRAIN_PRE_EMPHASIS_0;
2017 } else if (IS_GEN7(dev) && port == PORT_A) {
2018 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2019 case DP_TRAIN_VOLTAGE_SWING_400:
2020 return DP_TRAIN_PRE_EMPHASIS_6;
2021 case DP_TRAIN_VOLTAGE_SWING_600:
2022 case DP_TRAIN_VOLTAGE_SWING_800:
2023 return DP_TRAIN_PRE_EMPHASIS_3_5;
2025 return DP_TRAIN_PRE_EMPHASIS_0;
2028 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2029 case DP_TRAIN_VOLTAGE_SWING_400:
2030 return DP_TRAIN_PRE_EMPHASIS_6;
2031 case DP_TRAIN_VOLTAGE_SWING_600:
2032 return DP_TRAIN_PRE_EMPHASIS_6;
2033 case DP_TRAIN_VOLTAGE_SWING_800:
2034 return DP_TRAIN_PRE_EMPHASIS_3_5;
2035 case DP_TRAIN_VOLTAGE_SWING_1200:
2037 return DP_TRAIN_PRE_EMPHASIS_0;
2042 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2044 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2046 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2047 struct intel_crtc *intel_crtc =
2048 to_intel_crtc(dport->base.base.crtc);
2049 unsigned long demph_reg_value, preemph_reg_value,
2050 uniqtranscale_reg_value;
2051 uint8_t train_set = intel_dp->train_set[0];
2052 enum dpio_channel port = vlv_dport_to_channel(dport);
2053 int pipe = intel_crtc->pipe;
2055 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2056 case DP_TRAIN_PRE_EMPHASIS_0:
2057 preemph_reg_value = 0x0004000;
2058 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2059 case DP_TRAIN_VOLTAGE_SWING_400:
2060 demph_reg_value = 0x2B405555;
2061 uniqtranscale_reg_value = 0x552AB83A;
2063 case DP_TRAIN_VOLTAGE_SWING_600:
2064 demph_reg_value = 0x2B404040;
2065 uniqtranscale_reg_value = 0x5548B83A;
2067 case DP_TRAIN_VOLTAGE_SWING_800:
2068 demph_reg_value = 0x2B245555;
2069 uniqtranscale_reg_value = 0x5560B83A;
2071 case DP_TRAIN_VOLTAGE_SWING_1200:
2072 demph_reg_value = 0x2B405555;
2073 uniqtranscale_reg_value = 0x5598DA3A;
2079 case DP_TRAIN_PRE_EMPHASIS_3_5:
2080 preemph_reg_value = 0x0002000;
2081 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2082 case DP_TRAIN_VOLTAGE_SWING_400:
2083 demph_reg_value = 0x2B404040;
2084 uniqtranscale_reg_value = 0x5552B83A;
2086 case DP_TRAIN_VOLTAGE_SWING_600:
2087 demph_reg_value = 0x2B404848;
2088 uniqtranscale_reg_value = 0x5580B83A;
2090 case DP_TRAIN_VOLTAGE_SWING_800:
2091 demph_reg_value = 0x2B404040;
2092 uniqtranscale_reg_value = 0x55ADDA3A;
2098 case DP_TRAIN_PRE_EMPHASIS_6:
2099 preemph_reg_value = 0x0000000;
2100 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2101 case DP_TRAIN_VOLTAGE_SWING_400:
2102 demph_reg_value = 0x2B305555;
2103 uniqtranscale_reg_value = 0x5570B83A;
2105 case DP_TRAIN_VOLTAGE_SWING_600:
2106 demph_reg_value = 0x2B2B4040;
2107 uniqtranscale_reg_value = 0x55ADDA3A;
2113 case DP_TRAIN_PRE_EMPHASIS_9_5:
2114 preemph_reg_value = 0x0006000;
2115 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2116 case DP_TRAIN_VOLTAGE_SWING_400:
2117 demph_reg_value = 0x1B405555;
2118 uniqtranscale_reg_value = 0x55ADDA3A;
2128 mutex_lock(&dev_priv->dpio_lock);
2129 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2130 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2131 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2132 uniqtranscale_reg_value);
2133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2134 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2135 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2136 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2137 mutex_unlock(&dev_priv->dpio_lock);
2143 intel_get_adjust_train(struct intel_dp *intel_dp,
2144 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2149 uint8_t voltage_max;
2150 uint8_t preemph_max;
2152 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2153 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2154 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2162 voltage_max = intel_dp_voltage_max(intel_dp);
2163 if (v >= voltage_max)
2164 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2166 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2167 if (p >= preemph_max)
2168 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2170 for (lane = 0; lane < 4; lane++)
2171 intel_dp->train_set[lane] = v | p;
2175 intel_gen4_signal_levels(uint8_t train_set)
2177 uint32_t signal_levels = 0;
2179 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2180 case DP_TRAIN_VOLTAGE_SWING_400:
2182 signal_levels |= DP_VOLTAGE_0_4;
2184 case DP_TRAIN_VOLTAGE_SWING_600:
2185 signal_levels |= DP_VOLTAGE_0_6;
2187 case DP_TRAIN_VOLTAGE_SWING_800:
2188 signal_levels |= DP_VOLTAGE_0_8;
2190 case DP_TRAIN_VOLTAGE_SWING_1200:
2191 signal_levels |= DP_VOLTAGE_1_2;
2194 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2195 case DP_TRAIN_PRE_EMPHASIS_0:
2197 signal_levels |= DP_PRE_EMPHASIS_0;
2199 case DP_TRAIN_PRE_EMPHASIS_3_5:
2200 signal_levels |= DP_PRE_EMPHASIS_3_5;
2202 case DP_TRAIN_PRE_EMPHASIS_6:
2203 signal_levels |= DP_PRE_EMPHASIS_6;
2205 case DP_TRAIN_PRE_EMPHASIS_9_5:
2206 signal_levels |= DP_PRE_EMPHASIS_9_5;
2209 return signal_levels;
2212 /* Gen6's DP voltage swing and pre-emphasis control */
2214 intel_gen6_edp_signal_levels(uint8_t train_set)
2216 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2217 DP_TRAIN_PRE_EMPHASIS_MASK);
2218 switch (signal_levels) {
2219 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2220 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2221 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2222 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2223 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2224 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2225 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2226 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2227 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2228 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2229 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2230 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2231 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2232 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2234 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2235 "0x%x\n", signal_levels);
2236 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2240 /* Gen7's DP voltage swing and pre-emphasis control */
2242 intel_gen7_edp_signal_levels(uint8_t train_set)
2244 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2245 DP_TRAIN_PRE_EMPHASIS_MASK);
2246 switch (signal_levels) {
2247 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2248 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2249 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2250 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2251 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2252 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2254 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2255 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2256 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2257 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2259 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2260 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2261 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2262 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2265 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2266 "0x%x\n", signal_levels);
2267 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2271 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2273 intel_hsw_signal_levels(uint8_t train_set)
2275 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2276 DP_TRAIN_PRE_EMPHASIS_MASK);
2277 switch (signal_levels) {
2278 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2279 return DDI_BUF_EMP_400MV_0DB_HSW;
2280 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2281 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2282 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2283 return DDI_BUF_EMP_400MV_6DB_HSW;
2284 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2285 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2287 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2288 return DDI_BUF_EMP_600MV_0DB_HSW;
2289 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2290 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2291 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2292 return DDI_BUF_EMP_600MV_6DB_HSW;
2294 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2295 return DDI_BUF_EMP_800MV_0DB_HSW;
2296 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2297 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2299 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2300 "0x%x\n", signal_levels);
2301 return DDI_BUF_EMP_400MV_0DB_HSW;
2306 intel_bdw_signal_levels(uint8_t train_set)
2308 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2309 DP_TRAIN_PRE_EMPHASIS_MASK);
2310 switch (signal_levels) {
2311 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2312 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2313 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2315 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2316 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2318 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2319 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2320 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2321 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2322 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2323 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2325 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2326 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2327 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2328 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2330 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2331 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2334 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2335 "0x%x\n", signal_levels);
2336 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2340 /* Properly updates "DP" with the correct signal levels. */
2342 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2344 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2345 enum port port = intel_dig_port->port;
2346 struct drm_device *dev = intel_dig_port->base.base.dev;
2347 uint32_t signal_levels, mask;
2348 uint8_t train_set = intel_dp->train_set[0];
2350 if (IS_BROADWELL(dev)) {
2351 signal_levels = intel_bdw_signal_levels(train_set);
2352 mask = DDI_BUF_EMP_MASK;
2353 } else if (IS_HASWELL(dev)) {
2354 signal_levels = intel_hsw_signal_levels(train_set);
2355 mask = DDI_BUF_EMP_MASK;
2356 } else if (IS_VALLEYVIEW(dev)) {
2357 signal_levels = intel_vlv_signal_levels(intel_dp);
2359 } else if (IS_GEN7(dev) && port == PORT_A) {
2360 signal_levels = intel_gen7_edp_signal_levels(train_set);
2361 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2362 } else if (IS_GEN6(dev) && port == PORT_A) {
2363 signal_levels = intel_gen6_edp_signal_levels(train_set);
2364 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2366 signal_levels = intel_gen4_signal_levels(train_set);
2367 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2370 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2372 *DP = (*DP & ~mask) | signal_levels;
2376 intel_dp_set_link_train(struct intel_dp *intel_dp,
2378 uint8_t dp_train_pat)
2380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2381 struct drm_device *dev = intel_dig_port->base.base.dev;
2382 struct drm_i915_private *dev_priv = dev->dev_private;
2383 enum port port = intel_dig_port->port;
2384 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2388 uint32_t temp = I915_READ(DP_TP_CTL(port));
2390 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2391 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2393 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2395 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2396 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2397 case DP_TRAINING_PATTERN_DISABLE:
2398 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2401 case DP_TRAINING_PATTERN_1:
2402 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2404 case DP_TRAINING_PATTERN_2:
2405 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2407 case DP_TRAINING_PATTERN_3:
2408 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2411 I915_WRITE(DP_TP_CTL(port), temp);
2413 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2414 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2416 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2417 case DP_TRAINING_PATTERN_DISABLE:
2418 *DP |= DP_LINK_TRAIN_OFF_CPT;
2420 case DP_TRAINING_PATTERN_1:
2421 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2423 case DP_TRAINING_PATTERN_2:
2424 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2426 case DP_TRAINING_PATTERN_3:
2427 DRM_ERROR("DP training pattern 3 not supported\n");
2428 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2433 *DP &= ~DP_LINK_TRAIN_MASK;
2435 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2436 case DP_TRAINING_PATTERN_DISABLE:
2437 *DP |= DP_LINK_TRAIN_OFF;
2439 case DP_TRAINING_PATTERN_1:
2440 *DP |= DP_LINK_TRAIN_PAT_1;
2442 case DP_TRAINING_PATTERN_2:
2443 *DP |= DP_LINK_TRAIN_PAT_2;
2445 case DP_TRAINING_PATTERN_3:
2446 DRM_ERROR("DP training pattern 3 not supported\n");
2447 *DP |= DP_LINK_TRAIN_PAT_2;
2452 I915_WRITE(intel_dp->output_reg, *DP);
2453 POSTING_READ(intel_dp->output_reg);
2455 buf[0] = dp_train_pat;
2456 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2457 DP_TRAINING_PATTERN_DISABLE) {
2458 /* don't write DP_TRAINING_LANEx_SET on disable */
2461 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2462 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2463 len = intel_dp->lane_count + 1;
2466 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2473 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2474 uint8_t dp_train_pat)
2476 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2477 intel_dp_set_signal_levels(intel_dp, DP);
2478 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2482 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2483 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2485 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2486 struct drm_device *dev = intel_dig_port->base.base.dev;
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2490 intel_get_adjust_train(intel_dp, link_status);
2491 intel_dp_set_signal_levels(intel_dp, DP);
2493 I915_WRITE(intel_dp->output_reg, *DP);
2494 POSTING_READ(intel_dp->output_reg);
2496 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2497 intel_dp->train_set,
2498 intel_dp->lane_count);
2500 return ret == intel_dp->lane_count;
2503 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2505 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2506 struct drm_device *dev = intel_dig_port->base.base.dev;
2507 struct drm_i915_private *dev_priv = dev->dev_private;
2508 enum port port = intel_dig_port->port;
2514 val = I915_READ(DP_TP_CTL(port));
2515 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2516 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2517 I915_WRITE(DP_TP_CTL(port), val);
2520 * On PORT_A we can have only eDP in SST mode. There the only reason
2521 * we need to set idle transmission mode is to work around a HW issue
2522 * where we enable the pipe while not in idle link-training mode.
2523 * In this case there is requirement to wait for a minimum number of
2524 * idle patterns to be sent.
2529 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2531 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2534 /* Enable corresponding port and start training pattern 1 */
2536 intel_dp_start_link_train(struct intel_dp *intel_dp)
2538 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2539 struct drm_device *dev = encoder->dev;
2542 int voltage_tries, loop_tries;
2543 uint32_t DP = intel_dp->DP;
2544 uint8_t link_config[2];
2547 intel_ddi_prepare_link_retrain(encoder);
2549 /* Write the link configuration data */
2550 link_config[0] = intel_dp->link_bw;
2551 link_config[1] = intel_dp->lane_count;
2552 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2553 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2554 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2557 link_config[1] = DP_SET_ANSI_8B10B;
2558 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2562 /* clock recovery */
2563 if (!intel_dp_reset_link_train(intel_dp, &DP,
2564 DP_TRAINING_PATTERN_1 |
2565 DP_LINK_SCRAMBLING_DISABLE)) {
2566 DRM_ERROR("failed to enable link training\n");
2574 uint8_t link_status[DP_LINK_STATUS_SIZE];
2576 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2577 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2578 DRM_ERROR("failed to get link status\n");
2582 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2583 DRM_DEBUG_KMS("clock recovery OK\n");
2587 /* Check to see if we've tried the max voltage */
2588 for (i = 0; i < intel_dp->lane_count; i++)
2589 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2591 if (i == intel_dp->lane_count) {
2593 if (loop_tries == 5) {
2594 DRM_ERROR("too many full retries, give up\n");
2597 intel_dp_reset_link_train(intel_dp, &DP,
2598 DP_TRAINING_PATTERN_1 |
2599 DP_LINK_SCRAMBLING_DISABLE);
2604 /* Check to see if we've tried the same voltage 5 times */
2605 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2607 if (voltage_tries == 5) {
2608 DRM_ERROR("too many voltage retries, give up\n");
2613 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2615 /* Update training set as requested by target */
2616 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2617 DRM_ERROR("failed to update link training\n");
2626 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2628 bool channel_eq = false;
2629 int tries, cr_tries;
2630 uint32_t DP = intel_dp->DP;
2632 /* channel equalization */
2633 if (!intel_dp_set_link_train(intel_dp, &DP,
2634 DP_TRAINING_PATTERN_2 |
2635 DP_LINK_SCRAMBLING_DISABLE)) {
2636 DRM_ERROR("failed to start channel equalization\n");
2644 uint8_t link_status[DP_LINK_STATUS_SIZE];
2647 DRM_ERROR("failed to train DP, aborting\n");
2651 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2652 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2653 DRM_ERROR("failed to get link status\n");
2657 /* Make sure clock is still ok */
2658 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2659 intel_dp_start_link_train(intel_dp);
2660 intel_dp_set_link_train(intel_dp, &DP,
2661 DP_TRAINING_PATTERN_2 |
2662 DP_LINK_SCRAMBLING_DISABLE);
2667 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2672 /* Try 5 times, then try clock recovery if that fails */
2674 intel_dp_link_down(intel_dp);
2675 intel_dp_start_link_train(intel_dp);
2676 intel_dp_set_link_train(intel_dp, &DP,
2677 DP_TRAINING_PATTERN_2 |
2678 DP_LINK_SCRAMBLING_DISABLE);
2684 /* Update training set as requested by target */
2685 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2686 DRM_ERROR("failed to update link training\n");
2692 intel_dp_set_idle_link_train(intel_dp);
2697 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2701 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2703 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2704 DP_TRAINING_PATTERN_DISABLE);
2708 intel_dp_link_down(struct intel_dp *intel_dp)
2710 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2711 enum port port = intel_dig_port->port;
2712 struct drm_device *dev = intel_dig_port->base.base.dev;
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 struct intel_crtc *intel_crtc =
2715 to_intel_crtc(intel_dig_port->base.base.crtc);
2716 uint32_t DP = intel_dp->DP;
2719 * DDI code has a strict mode set sequence and we should try to respect
2720 * it, otherwise we might hang the machine in many different ways. So we
2721 * really should be disabling the port only on a complete crtc_disable
2722 * sequence. This function is just called under two conditions on DDI
2724 * - Link train failed while doing crtc_enable, and on this case we
2725 * really should respect the mode set sequence and wait for a
2727 * - Someone turned the monitor off and intel_dp_check_link_status
2728 * called us. We don't need to disable the whole port on this case, so
2729 * when someone turns the monitor on again,
2730 * intel_ddi_prepare_link_retrain will take care of redoing the link
2736 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2739 DRM_DEBUG_KMS("\n");
2741 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2742 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2743 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2745 DP &= ~DP_LINK_TRAIN_MASK;
2746 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2748 POSTING_READ(intel_dp->output_reg);
2750 /* We don't really know why we're doing this */
2751 intel_wait_for_vblank(dev, intel_crtc->pipe);
2753 if (HAS_PCH_IBX(dev) &&
2754 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2755 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2757 /* Hardware workaround: leaving our transcoder select
2758 * set to transcoder B while it's off will prevent the
2759 * corresponding HDMI output on transcoder A.
2761 * Combine this with another hardware workaround:
2762 * transcoder select bit can only be cleared while the
2765 DP &= ~DP_PIPEB_SELECT;
2766 I915_WRITE(intel_dp->output_reg, DP);
2768 /* Changes to enable or select take place the vblank
2769 * after being written.
2771 if (WARN_ON(crtc == NULL)) {
2772 /* We should never try to disable a port without a crtc
2773 * attached. For paranoia keep the code around for a
2775 POSTING_READ(intel_dp->output_reg);
2778 intel_wait_for_vblank(dev, intel_crtc->pipe);
2781 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2782 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2783 POSTING_READ(intel_dp->output_reg);
2784 msleep(intel_dp->panel_power_down_delay);
2788 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2790 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2791 struct drm_device *dev = dig_port->base.base.dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2794 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2796 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2797 sizeof(intel_dp->dpcd)) == 0)
2798 return false; /* aux transfer failed */
2800 ksnprintf(dpcd_hex_dump,
2801 sizeof(dpcd_hex_dump),
2802 "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2803 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2804 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2805 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2807 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2809 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2810 return false; /* DPCD not present */
2812 /* Check if the panel supports PSR */
2813 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2814 if (is_edp(intel_dp)) {
2815 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2817 sizeof(intel_dp->psr_dpcd));
2818 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2819 dev_priv->psr.sink_support = true;
2820 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2824 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2825 DP_DWN_STRM_PORT_PRESENT))
2826 return true; /* native DP sink */
2828 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2829 return true; /* no per-port downstream info */
2831 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2832 intel_dp->downstream_ports,
2833 DP_MAX_DOWNSTREAM_PORTS) == 0)
2834 return false; /* downstream port status fetch failed */
2840 intel_dp_probe_oui(struct intel_dp *intel_dp)
2844 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2847 ironlake_edp_panel_vdd_on(intel_dp);
2849 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2850 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2851 buf[0], buf[1], buf[2]);
2853 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2854 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2855 buf[0], buf[1], buf[2]);
2857 ironlake_edp_panel_vdd_off(intel_dp, false);
2861 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2865 ret = intel_dp_aux_native_read_retry(intel_dp,
2866 DP_DEVICE_SERVICE_IRQ_VECTOR,
2867 sink_irq_vector, 1);
2875 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2877 /* NAK by default */
2878 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2882 * According to DP spec
2885 * 2. Configure link according to Receiver Capabilities
2886 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2887 * 4. Check link status on receipt of hot-plug interrupt
2891 intel_dp_check_link_status(struct intel_dp *intel_dp)
2893 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2895 u8 link_status[DP_LINK_STATUS_SIZE];
2897 if (!intel_encoder->connectors_active)
2900 if (WARN_ON(!intel_encoder->base.crtc))
2903 /* Try to read receiver status if the link appears to be up */
2904 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2908 /* Now read the DPCD to see if it's actually running */
2909 if (!intel_dp_get_dpcd(intel_dp)) {
2913 /* Try to read the source of the interrupt */
2914 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2915 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2916 /* Clear interrupt source */
2917 intel_dp_aux_native_write_1(intel_dp,
2918 DP_DEVICE_SERVICE_IRQ_VECTOR,
2921 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2922 intel_dp_handle_test_request(intel_dp);
2923 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2924 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2927 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2928 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2929 drm_get_encoder_name(&intel_encoder->base));
2930 intel_dp_start_link_train(intel_dp);
2931 intel_dp_complete_link_train(intel_dp);
2932 intel_dp_stop_link_train(intel_dp);
2936 /* XXX this is probably wrong for multiple downstream ports */
2937 static enum drm_connector_status
2938 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2940 uint8_t *dpcd = intel_dp->dpcd;
2943 if (!intel_dp_get_dpcd(intel_dp))
2944 return connector_status_disconnected;
2946 /* if there's no downstream port, we're done */
2947 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2948 return connector_status_connected;
2950 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2951 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2952 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2954 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2956 return connector_status_unknown;
2957 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2958 : connector_status_disconnected;
2961 /* If no HPD, poke DDC gently */
2962 if (drm_probe_ddc(intel_dp->adapter))
2963 return connector_status_connected;
2965 /* Well we tried, say unknown for unreliable port types */
2966 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2967 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2968 if (type == DP_DS_PORT_TYPE_VGA ||
2969 type == DP_DS_PORT_TYPE_NON_EDID)
2970 return connector_status_unknown;
2972 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2973 DP_DWN_STRM_PORT_TYPE_MASK;
2974 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2975 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2976 return connector_status_unknown;
2979 /* Anything else is out of spec, warn and ignore */
2980 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2981 return connector_status_disconnected;
2984 static enum drm_connector_status
2985 ironlake_dp_detect(struct intel_dp *intel_dp)
2987 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2988 struct drm_i915_private *dev_priv = dev->dev_private;
2989 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2990 enum drm_connector_status status;
2992 /* Can't disconnect eDP, but you can close the lid... */
2993 if (is_edp(intel_dp)) {
2994 status = intel_panel_detect(dev);
2995 if (status == connector_status_unknown)
2996 status = connector_status_connected;
3000 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3001 return connector_status_disconnected;
3003 return intel_dp_detect_dpcd(intel_dp);
3006 static enum drm_connector_status
3007 g4x_dp_detect(struct intel_dp *intel_dp)
3009 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3014 /* Can't disconnect eDP, but you can close the lid... */
3015 if (is_edp(intel_dp)) {
3016 enum drm_connector_status status;
3018 status = intel_panel_detect(dev);
3019 if (status == connector_status_unknown)
3020 status = connector_status_connected;
3024 if (IS_VALLEYVIEW(dev)) {
3025 switch (intel_dig_port->port) {
3027 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3030 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3033 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3036 return connector_status_unknown;
3039 switch (intel_dig_port->port) {
3041 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3044 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3047 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3050 return connector_status_unknown;
3054 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3055 return connector_status_disconnected;
3057 return intel_dp_detect_dpcd(intel_dp);
3060 static struct edid *
3061 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
3063 struct intel_connector *intel_connector = to_intel_connector(connector);
3065 /* use cached edid if we have one */
3066 if (intel_connector->edid) {
3068 if (IS_ERR(intel_connector->edid))
3071 return drm_edid_duplicate(intel_connector->edid);
3074 return drm_get_edid(connector, adapter);
3078 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
3080 struct intel_connector *intel_connector = to_intel_connector(connector);
3082 /* use cached edid if we have one */
3083 if (intel_connector->edid) {
3085 if (IS_ERR(intel_connector->edid))
3088 return intel_connector_update_modes(connector,
3089 intel_connector->edid);
3092 return intel_ddc_get_modes(connector, adapter);
3095 static enum drm_connector_status
3096 intel_dp_detect(struct drm_connector *connector, bool force)
3098 struct intel_dp *intel_dp = intel_attached_dp(connector);
3099 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3100 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3101 struct drm_device *dev = connector->dev;
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 enum drm_connector_status status;
3104 struct edid *edid = NULL;
3106 intel_runtime_pm_get(dev_priv);
3108 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3109 connector->base.id, drm_get_connector_name(connector));
3111 intel_dp->has_audio = false;
3113 if (HAS_PCH_SPLIT(dev))
3114 status = ironlake_dp_detect(intel_dp);
3116 status = g4x_dp_detect(intel_dp);
3118 if (status != connector_status_connected)
3121 intel_dp_probe_oui(intel_dp);
3123 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3124 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3126 edid = intel_dp_get_edid(connector, intel_dp->adapter);
3128 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3133 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3134 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3135 status = connector_status_connected;
3138 intel_runtime_pm_put(dev_priv);
3142 static int intel_dp_get_modes(struct drm_connector *connector)
3144 struct intel_dp *intel_dp = intel_attached_dp(connector);
3145 struct intel_connector *intel_connector = to_intel_connector(connector);
3146 struct drm_device *dev = connector->dev;
3149 /* We should parse the EDID data and find out if it has an audio sink
3152 ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
3156 /* if eDP has no EDID, fall back to fixed mode */
3157 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3158 struct drm_display_mode *mode;
3159 mode = drm_mode_duplicate(dev,
3160 intel_connector->panel.fixed_mode);
3162 drm_mode_probed_add(connector, mode);
3170 intel_dp_detect_audio(struct drm_connector *connector)
3172 struct intel_dp *intel_dp = intel_attached_dp(connector);
3174 bool has_audio = false;
3176 edid = intel_dp_get_edid(connector, intel_dp->adapter);
3178 has_audio = drm_detect_monitor_audio(edid);
3186 intel_dp_set_property(struct drm_connector *connector,
3187 struct drm_property *property,
3190 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3191 struct intel_connector *intel_connector = to_intel_connector(connector);
3192 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3193 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3196 ret = drm_object_property_set_value(&connector->base, property, val);
3200 if (property == dev_priv->force_audio_property) {
3204 if (i == intel_dp->force_audio)
3207 intel_dp->force_audio = i;
3209 if (i == HDMI_AUDIO_AUTO)
3210 has_audio = intel_dp_detect_audio(connector);
3212 has_audio = (i == HDMI_AUDIO_ON);
3214 if (has_audio == intel_dp->has_audio)
3217 intel_dp->has_audio = has_audio;
3221 if (property == dev_priv->broadcast_rgb_property) {
3222 bool old_auto = intel_dp->color_range_auto;
3223 uint32_t old_range = intel_dp->color_range;
3226 case INTEL_BROADCAST_RGB_AUTO:
3227 intel_dp->color_range_auto = true;
3229 case INTEL_BROADCAST_RGB_FULL:
3230 intel_dp->color_range_auto = false;
3231 intel_dp->color_range = 0;
3233 case INTEL_BROADCAST_RGB_LIMITED:
3234 intel_dp->color_range_auto = false;
3235 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3241 if (old_auto == intel_dp->color_range_auto &&
3242 old_range == intel_dp->color_range)
3248 if (is_edp(intel_dp) &&
3249 property == connector->dev->mode_config.scaling_mode_property) {
3250 if (val == DRM_MODE_SCALE_NONE) {
3251 DRM_DEBUG_KMS("no scaling not supported\n");
3255 if (intel_connector->panel.fitting_mode == val) {
3256 /* the eDP scaling property is not changed */
3259 intel_connector->panel.fitting_mode = val;
3267 if (intel_encoder->base.crtc)
3268 intel_crtc_restore_mode(intel_encoder->base.crtc);
3274 intel_dp_connector_destroy(struct drm_connector *connector)
3276 struct intel_connector *intel_connector = to_intel_connector(connector);
3278 if (!IS_ERR_OR_NULL(intel_connector->edid))
3279 kfree(intel_connector->edid);
3281 /* Can't call is_edp() since the encoder may have been destroyed
3283 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3284 intel_panel_fini(&intel_connector->panel);
3286 drm_connector_cleanup(connector);
3290 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3292 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3293 struct intel_dp *intel_dp = &intel_dig_port->dp;
3294 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3296 if (intel_dp->dp_iic_bus != NULL) {
3297 if (intel_dp->adapter != NULL) {
3298 device_delete_child(intel_dp->dp_iic_bus,
3301 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
3303 drm_encoder_cleanup(encoder);
3304 if (is_edp(intel_dp)) {
3305 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3306 mutex_lock(&dev->mode_config.mutex);
3307 ironlake_panel_vdd_off_sync(intel_dp);
3308 mutex_unlock(&dev->mode_config.mutex);
3310 kfree(intel_dig_port);
3313 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3314 .dpms = intel_connector_dpms,
3315 .detect = intel_dp_detect,
3316 .fill_modes = drm_helper_probe_single_connector_modes,
3317 .set_property = intel_dp_set_property,
3318 .destroy = intel_dp_connector_destroy,
3321 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3322 .get_modes = intel_dp_get_modes,
3323 .mode_valid = intel_dp_mode_valid,
3324 .best_encoder = intel_best_encoder,
3327 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3328 .destroy = intel_dp_encoder_destroy,
3332 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3334 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3336 intel_dp_check_link_status(intel_dp);
3339 /* Return which DP Port should be selected for Transcoder DP control */
3341 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3343 struct drm_device *dev = crtc->dev;
3344 struct intel_encoder *intel_encoder;
3345 struct intel_dp *intel_dp;
3347 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3348 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3350 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3351 intel_encoder->type == INTEL_OUTPUT_EDP)
3352 return intel_dp->output_reg;
3358 /* check the VBT to see whether the eDP is on DP-D port */
3359 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 union child_device_config *p_child;
3364 static const short port_mapping[] = {
3365 [PORT_B] = PORT_IDPB,
3366 [PORT_C] = PORT_IDPC,
3367 [PORT_D] = PORT_IDPD,
3373 if (!dev_priv->vbt.child_dev_num)
3376 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3377 p_child = dev_priv->vbt.child_dev + i;
3379 if (p_child->common.dvo_port == port_mapping[port] &&
3380 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3381 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3388 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3390 struct intel_connector *intel_connector = to_intel_connector(connector);
3392 intel_attach_force_audio_property(connector);
3393 intel_attach_broadcast_rgb_property(connector);
3394 intel_dp->color_range_auto = true;
3396 if (is_edp(intel_dp)) {
3397 drm_mode_create_scaling_mode_property(connector->dev);
3398 drm_object_attach_property(
3400 connector->dev->mode_config.scaling_mode_property,
3401 DRM_MODE_SCALE_ASPECT);
3402 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3407 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3408 struct intel_dp *intel_dp,
3409 struct edp_power_seq *out)
3411 struct drm_i915_private *dev_priv = dev->dev_private;
3412 struct edp_power_seq cur, vbt, spec, final;
3413 u32 pp_on, pp_off, pp_div, pp;
3414 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3416 if (HAS_PCH_SPLIT(dev)) {
3417 pp_ctrl_reg = PCH_PP_CONTROL;
3418 pp_on_reg = PCH_PP_ON_DELAYS;
3419 pp_off_reg = PCH_PP_OFF_DELAYS;
3420 pp_div_reg = PCH_PP_DIVISOR;
3422 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3424 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3425 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3426 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3427 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3430 /* Workaround: Need to write PP_CONTROL with the unlock key as
3431 * the very first thing. */
3432 pp = ironlake_get_pp_control(intel_dp);
3433 I915_WRITE(pp_ctrl_reg, pp);
3435 pp_on = I915_READ(pp_on_reg);
3436 pp_off = I915_READ(pp_off_reg);
3437 pp_div = I915_READ(pp_div_reg);
3439 /* Pull timing values out of registers */
3440 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3441 PANEL_POWER_UP_DELAY_SHIFT;
3443 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3444 PANEL_LIGHT_ON_DELAY_SHIFT;
3446 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3447 PANEL_LIGHT_OFF_DELAY_SHIFT;
3449 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3450 PANEL_POWER_DOWN_DELAY_SHIFT;
3452 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3453 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3455 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3456 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3458 vbt = dev_priv->vbt.edp_pps;
3460 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3461 * our hw here, which are all in 100usec. */
3462 spec.t1_t3 = 210 * 10;
3463 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3464 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3465 spec.t10 = 500 * 10;
3466 /* This one is special and actually in units of 100ms, but zero
3467 * based in the hw (so we need to add 100 ms). But the sw vbt
3468 * table multiplies it with 1000 to make it in units of 100usec,
3470 spec.t11_t12 = (510 + 100) * 10;
3472 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3473 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3475 /* Use the max of the register settings and vbt. If both are
3476 * unset, fall back to the spec limits. */
3477 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3479 max(cur.field, vbt.field))
3480 assign_final(t1_t3);
3484 assign_final(t11_t12);
3487 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3488 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3489 intel_dp->backlight_on_delay = get_delay(t8);
3490 intel_dp->backlight_off_delay = get_delay(t9);
3491 intel_dp->panel_power_down_delay = get_delay(t10);
3492 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3495 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3496 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3497 intel_dp->panel_power_cycle_delay);
3499 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3500 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3507 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3508 struct intel_dp *intel_dp,
3509 struct edp_power_seq *seq)
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 u32 pp_on, pp_off, pp_div, port_sel = 0;
3513 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3514 int pp_on_reg, pp_off_reg, pp_div_reg;
3516 if (HAS_PCH_SPLIT(dev)) {
3517 pp_on_reg = PCH_PP_ON_DELAYS;
3518 pp_off_reg = PCH_PP_OFF_DELAYS;
3519 pp_div_reg = PCH_PP_DIVISOR;
3521 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3523 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3524 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3525 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3528 /* And finally store the new values in the power sequencer. */
3529 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3530 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3531 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3532 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3533 /* Compute the divisor for the pp clock, simply match the Bspec
3535 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3536 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3537 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3539 /* Haswell doesn't have any port selection bits for the panel
3540 * power sequencer any more. */
3541 if (IS_VALLEYVIEW(dev)) {
3542 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3543 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3545 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3546 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3547 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3548 port_sel = PANEL_PORT_SELECT_DPA;
3550 port_sel = PANEL_PORT_SELECT_DPD;
3555 I915_WRITE(pp_on_reg, pp_on);
3556 I915_WRITE(pp_off_reg, pp_off);
3557 I915_WRITE(pp_div_reg, pp_div);
3559 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3560 I915_READ(pp_on_reg),
3561 I915_READ(pp_off_reg),
3562 I915_READ(pp_div_reg));
3565 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3566 struct intel_connector *intel_connector)
3568 struct drm_connector *connector = &intel_connector->base;
3569 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3570 struct drm_device *dev = intel_dig_port->base.base.dev;
3571 struct drm_i915_private *dev_priv = dev->dev_private;
3572 struct drm_display_mode *fixed_mode = NULL;
3573 struct edp_power_seq power_seq = { 0 };
3575 struct drm_display_mode *scan;
3578 if (!is_edp(intel_dp))
3581 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3583 /* Cache DPCD and EDID for edp. */
3584 ironlake_edp_panel_vdd_on(intel_dp);
3585 has_dpcd = intel_dp_get_dpcd(intel_dp);
3586 ironlake_edp_panel_vdd_off(intel_dp, false);
3589 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3590 dev_priv->no_aux_handshake =
3591 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3592 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3594 /* if this fails, presume the device is a ghost */
3595 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3599 /* We now know it's not a ghost, init power sequence regs. */
3600 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3603 edid = drm_get_edid(connector, intel_dp->adapter);
3605 if (drm_add_edid_modes(connector, edid)) {
3606 drm_mode_connector_update_edid_property(connector,
3608 drm_edid_to_eld(connector, edid);
3611 edid = ERR_PTR(-EINVAL);
3614 edid = ERR_PTR(-ENOENT);
3616 intel_connector->edid = edid;
3618 /* prefer fixed mode from EDID if available */
3619 list_for_each_entry(scan, &connector->probed_modes, head) {
3620 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3621 fixed_mode = drm_mode_duplicate(dev, scan);
3626 /* fallback to VBT if available for eDP */
3627 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3628 fixed_mode = drm_mode_duplicate(dev,
3629 dev_priv->vbt.lfp_lvds_vbt_mode);
3631 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3634 intel_panel_init(&intel_connector->panel, fixed_mode);
3635 intel_panel_setup_backlight(connector);
3641 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3642 struct intel_connector *intel_connector)
3644 struct drm_connector *connector = &intel_connector->base;
3645 struct intel_dp *intel_dp = &intel_dig_port->dp;
3646 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3647 struct drm_device *dev = intel_encoder->base.dev;
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 enum port port = intel_dig_port->port;
3650 const char *name = NULL;
3653 /* Preserve the current hw state. */
3654 intel_dp->DP = I915_READ(intel_dp->output_reg);
3655 intel_dp->attached_connector = intel_connector;
3657 if (intel_dp_is_edp(dev, port))
3658 type = DRM_MODE_CONNECTOR_eDP;
3660 type = DRM_MODE_CONNECTOR_DisplayPort;
3663 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3664 * for DP the encoder type can be set by the caller to
3665 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3667 if (type == DRM_MODE_CONNECTOR_eDP)
3668 intel_encoder->type = INTEL_OUTPUT_EDP;
3670 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3671 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3674 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3675 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3677 connector->interlace_allowed = true;
3678 connector->doublescan_allowed = 0;
3680 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3681 ironlake_panel_vdd_work);
3683 intel_connector_attach_encoder(intel_connector, intel_encoder);
3684 drm_sysfs_connector_add(connector);
3687 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3689 intel_connector->get_hw_state = intel_connector_get_hw_state;
3691 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3693 switch (intel_dig_port->port) {
3695 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3698 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3704 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3711 /* Set up the DDC bus. */
3714 intel_encoder->hpd_pin = HPD_PORT_A;
3718 intel_encoder->hpd_pin = HPD_PORT_B;
3722 intel_encoder->hpd_pin = HPD_PORT_C;
3726 intel_encoder->hpd_pin = HPD_PORT_D;
3733 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3734 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3735 error, port_name(port));
3737 intel_dp->psr_setup_done = false;
3739 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3741 i2c_del_adapter(&intel_dp->adapter);
3743 if (is_edp(intel_dp)) {
3744 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3745 mutex_lock(&dev->mode_config.mutex);
3746 ironlake_panel_vdd_off_sync(intel_dp);
3747 mutex_unlock(&dev->mode_config.mutex);
3749 drm_sysfs_connector_remove(connector);
3750 drm_connector_cleanup(connector);
3754 intel_dp_add_properties(intel_dp, connector);
3756 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3757 * 0xd. Failure to do so will result in spurious interrupts being
3758 * generated on the port when a cable is not attached.
3760 if (IS_G4X(dev) && !IS_GM45(dev)) {
3761 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3762 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3769 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3771 struct intel_digital_port *intel_dig_port;
3772 struct intel_encoder *intel_encoder;
3773 struct drm_encoder *encoder;
3774 struct intel_connector *intel_connector;
3776 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3777 if (!intel_dig_port)
3780 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3781 if (!intel_connector) {
3782 kfree(intel_dig_port);
3786 intel_encoder = &intel_dig_port->base;
3787 encoder = &intel_encoder->base;
3789 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3790 DRM_MODE_ENCODER_TMDS);
3792 intel_encoder->compute_config = intel_dp_compute_config;
3793 intel_encoder->mode_set = intel_dp_mode_set;
3794 intel_encoder->disable = intel_disable_dp;
3795 intel_encoder->post_disable = intel_post_disable_dp;
3796 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3797 intel_encoder->get_config = intel_dp_get_config;
3798 if (IS_VALLEYVIEW(dev)) {
3799 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3800 intel_encoder->pre_enable = vlv_pre_enable_dp;
3801 intel_encoder->enable = vlv_enable_dp;
3803 intel_encoder->pre_enable = g4x_pre_enable_dp;
3804 intel_encoder->enable = g4x_enable_dp;
3807 intel_dig_port->port = port;
3808 intel_dig_port->dp.output_reg = output_reg;
3810 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3811 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3812 intel_encoder->cloneable = false;
3813 intel_encoder->hot_plug = intel_dp_hot_plug;
3815 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3816 drm_encoder_cleanup(encoder);
3817 kfree(intel_dig_port);
3818 kfree(intel_connector);