sys/dev/netif/et/if_et.c

   1 /*
   2  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.17 2008/09/17 08:51:29 sephe Exp $
  35  */
  36
  37 #include <sys/param.h>
  38 #include <sys/bitops.h>
  39 #include <sys/endian.h>
  40 #include <sys/kernel.h>
  41 #include <sys/bus.h>
  42 #include <sys/interrupt.h>
  43 #include <sys/malloc.h>
  44 #include <sys/proc.h>
  45 #include <sys/rman.h>
  46 #include <sys/serialize.h>
  47 #include <sys/socket.h>
  48 #include <sys/sockio.h>
  49 #include <sys/sysctl.h>
  50
  51 #include <net/ethernet.h>
  52 #include <net/if.h>
  53 #include <net/bpf.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/vlan/if_vlan_var.h>
  59
  60 #include <dev/netif/mii_layer/miivar.h>
  61
  62 #include <bus/pci/pcireg.h>
  63 #include <bus/pci/pcivar.h>
  64 #include <bus/pci/pcidevs.h>
  65
  66 #include <dev/netif/et/if_etreg.h>
  67 #include <dev/netif/et/if_etvar.h>
  68
  69 #include "miibus_if.h"
  70
  71 static int      et_probe(device_t);
  72 static int      et_attach(device_t);
  73 static int      et_detach(device_t);
  74 static int      et_shutdown(device_t);
  75
  76 static int      et_miibus_readreg(device_t, int, int);
  77 static int      et_miibus_writereg(device_t, int, int, int);
  78 static void     et_miibus_statchg(device_t);
  79
  80 static void     et_init(void *);
  81 static int      et_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
  82 static void     et_start(struct ifnet *);
  83 static void     et_watchdog(struct ifnet *);
  84 static int      et_ifmedia_upd(struct ifnet *);
  85 static void     et_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  86
  87 static int      et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS);
  88 static int      et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS);
  89
  90 static void     et_intr(void *);
  91 static void     et_enable_intrs(struct et_softc *, uint32_t);
  92 static void     et_disable_intrs(struct et_softc *);
  93 static void     et_rxeof(struct et_softc *);
  94 static void     et_txeof(struct et_softc *, int);
  95
  96 static int      et_dma_alloc(device_t);
  97 static void     et_dma_free(device_t);
  98 static void     et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t);
  99 static int      et_dma_mbuf_create(device_t);
 100 static void     et_dma_mbuf_destroy(device_t, int, const int[]);
 101 static int      et_jumbo_mem_alloc(device_t);
 102 static void     et_jumbo_mem_free(device_t);
 103 static int      et_init_tx_ring(struct et_softc *);
 104 static int      et_init_rx_ring(struct et_softc *);
 105 static void     et_free_tx_ring(struct et_softc *);
 106 static void     et_free_rx_ring(struct et_softc *);
 107 static int      et_encap(struct et_softc *, struct mbuf **);
 108 static struct et_jslot *
 109                 et_jalloc(struct et_jumbo_data *);
 110 static void     et_jfree(void *);
 111 static void     et_jref(void *);
 112 static int      et_newbuf(struct et_rxbuf_data *, int, int, int);
 113 static int      et_newbuf_cluster(struct et_rxbuf_data *, int, int);
 114 static int      et_newbuf_hdr(struct et_rxbuf_data *, int, int);
 115 static int      et_newbuf_jumbo(struct et_rxbuf_data *, int, int);
 116
 117 static void     et_stop(struct et_softc *);
 118 static int      et_chip_init(struct et_softc *);
 119 static void     et_chip_attach(struct et_softc *);
 120 static void     et_init_mac(struct et_softc *);
 121 static void     et_init_rxmac(struct et_softc *);
 122 static void     et_init_txmac(struct et_softc *);
 123 static int      et_init_rxdma(struct et_softc *);
 124 static int      et_init_txdma(struct et_softc *);
 125 static int      et_start_rxdma(struct et_softc *);
 126 static int      et_start_txdma(struct et_softc *);
 127 static int      et_stop_rxdma(struct et_softc *);
 128 static int      et_stop_txdma(struct et_softc *);
 129 static int      et_enable_txrx(struct et_softc *, int);
 130 static void     et_reset(struct et_softc *);
 131 static int      et_bus_config(device_t);
 132 static void     et_get_eaddr(device_t, uint8_t[]);
 133 static void     et_setmulti(struct et_softc *);
 134 static void     et_tick(void *);
 135 static void     et_setmedia(struct et_softc *);
 136 static void     et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t);
 137
 138 static const struct et_dev {
 139         uint16_t        vid;
 140         uint16_t        did;
 141         const char      *desc;
 142 } et_devices[] = {
 143         { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310,
 144           "Agere ET1310 Gigabit Ethernet" },
 145         { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST,
 146           "Agere ET1310 Fast Ethernet" },
 147         { 0, 0, NULL }
 148 };
 149
 150 static device_method_t et_methods[] = {
 151         DEVMETHOD(device_probe,         et_probe),
 152         DEVMETHOD(device_attach,        et_attach),
 153         DEVMETHOD(device_detach,        et_detach),
 154         DEVMETHOD(device_shutdown,      et_shutdown),
 155 #if 0
 156         DEVMETHOD(device_suspend,       et_suspend),
 157         DEVMETHOD(device_resume,        et_resume),
 158 #endif
 159
 160         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 161         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 162
 163         DEVMETHOD(miibus_readreg,       et_miibus_readreg),
 164         DEVMETHOD(miibus_writereg,      et_miibus_writereg),
 165         DEVMETHOD(miibus_statchg,       et_miibus_statchg),
 166
 167         { 0, 0 }
 168 };
 169
 170 static driver_t et_driver = {
 171         "et",
 172         et_methods,
 173         sizeof(struct et_softc)
 174 };
 175
 176 static devclass_t et_devclass;
 177
 178 DECLARE_DUMMY_MODULE(if_et);
 179 MODULE_DEPEND(if_et, miibus, 1, 1, 1);
 180 DRIVER_MODULE(if_et, pci, et_driver, et_devclass, 0, 0);
 181 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0);
 182
 183 static int      et_rx_intr_npkts = 129;
 184 static int      et_rx_intr_delay = 25;          /* x4 usec */
 185 static int      et_tx_intr_nsegs = 256;
 186 static uint32_t et_timer = 1000 * 1000 * 1000;  /* nanosec */
 187
 188 TUNABLE_INT("hw.et.timer", &et_timer);
 189 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts);
 190 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay);
 191 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs);
 192
 193 struct et_bsize {
 194         int             bufsize;
 195         int             jumbo;
 196         et_newbuf_t     newbuf;
 197 };
 198
 199 static const struct et_bsize    et_bufsize_std[ET_RX_NRING] = {
 200         { .bufsize = ET_RXDMA_CTRL_RING0_128,   .jumbo = 0,
 201           .newbuf = et_newbuf_hdr },
 202         { .bufsize = ET_RXDMA_CTRL_RING1_2048,  .jumbo = 0,
 203           .newbuf = et_newbuf_cluster },
 204 };
 205
 206 static const struct et_bsize    et_bufsize_jumbo[ET_RX_NRING] = {
 207         { .bufsize = ET_RXDMA_CTRL_RING0_128,   .jumbo = 0,
 208           .newbuf = et_newbuf_hdr },
 209         { .bufsize = ET_RXDMA_CTRL_RING1_16384, .jumbo = 1,
 210           .newbuf = et_newbuf_jumbo },
 211 };
 212
 213 static int
 214 et_probe(device_t dev)
 215 {
 216         const struct et_dev *d;
 217         uint16_t did, vid;
 218
 219         vid = pci_get_vendor(dev);
 220         did = pci_get_device(dev);
 221
 222         for (d = et_devices; d->desc != NULL; ++d) {
 223                 if (vid == d->vid && did == d->did) {
 224                         device_set_desc(dev, d->desc);
 225                         return 0;
 226                 }
 227         }
 228         return ENXIO;
 229 }
 230
 231 static int
 232 et_attach(device_t dev)
 233 {
 234         struct et_softc *sc = device_get_softc(dev);
 235         struct ifnet *ifp = &sc->arpcom.ac_if;
 236         uint8_t eaddr[ETHER_ADDR_LEN];
 237         int error;
 238
 239         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 240         callout_init(&sc->sc_tick);
 241
 242         /*
 243          * Initialize tunables
 244          */
 245         sc->sc_rx_intr_npkts = et_rx_intr_npkts;
 246         sc->sc_rx_intr_delay = et_rx_intr_delay;
 247         sc->sc_tx_intr_nsegs = et_tx_intr_nsegs;
 248         sc->sc_timer = et_timer;
 249
 250 #ifndef BURN_BRIDGES
 251         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 252                 uint32_t irq, mem;
 253
 254                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 255                 mem = pci_read_config(dev, ET_PCIR_BAR, 4);
 256
 257                 device_printf(dev, "chip is in D%d power mode "
 258                     "-- setting to D0\n", pci_get_powerstate(dev));
 259
 260                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 261
 262                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 263                 pci_write_config(dev, ET_PCIR_BAR, mem, 4);
 264         }
 265 #endif  /* !BURN_BRIDGE */
 266
 267         /* Enable bus mastering */
 268         pci_enable_busmaster(dev);
 269
 270         /*
 271          * Allocate IO memory
 272          */
 273         sc->sc_mem_rid = ET_PCIR_BAR;
 274         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 275                                                 &sc->sc_mem_rid, RF_ACTIVE);
 276         if (sc->sc_mem_res == NULL) {
 277                 device_printf(dev, "can't allocate IO memory\n");
 278                 return ENXIO;
 279         }
 280         sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
 281         sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
 282
 283         /*
 284          * Allocate IRQ
 285          */
 286         sc->sc_irq_rid = 0;
 287         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 288                                                 &sc->sc_irq_rid,
 289                                                 RF_SHAREABLE | RF_ACTIVE);
 290         if (sc->sc_irq_res == NULL) {
 291                 device_printf(dev, "can't allocate irq\n");
 292                 error = ENXIO;
 293                 goto fail;
 294         }
 295
 296         /*
 297          * Create sysctl tree
 298          */
 299         sysctl_ctx_init(&sc->sc_sysctl_ctx);
 300         sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
 301                                              SYSCTL_STATIC_CHILDREN(_hw),
 302                                              OID_AUTO,
 303                                              device_get_nameunit(dev),
 304                                              CTLFLAG_RD, 0, "");
 305         if (sc->sc_sysctl_tree == NULL) {
 306                 device_printf(dev, "can't add sysctl node\n");
 307                 error = ENXIO;
 308                 goto fail;
 309         }
 310
 311         SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
 312                         SYSCTL_CHILDREN(sc->sc_sysctl_tree),
 313                         OID_AUTO, "rx_intr_npkts", CTLTYPE_INT | CTLFLAG_RW,
 314                         sc, 0, et_sysctl_rx_intr_npkts, "I",
 315                         "RX IM, # packets per RX interrupt");
 316         SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
 317                         SYSCTL_CHILDREN(sc->sc_sysctl_tree),
 318                         OID_AUTO, "rx_intr_delay", CTLTYPE_INT | CTLFLAG_RW,
 319                         sc, 0, et_sysctl_rx_intr_delay, "I",
 320                         "RX IM, RX interrupt delay (x10 usec)");
 321         SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
 322                        SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
 323                        "tx_intr_nsegs", CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0,
 324                        "TX IM, # segments per TX interrupt");
 325         SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
 326                         SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
 327                         "timer", CTLFLAG_RW, &sc->sc_timer, 0,
 328                         "TX timer");
 329
 330         error = et_bus_config(dev);
 331         if (error)
 332                 goto fail;
 333
 334         et_get_eaddr(dev, eaddr);
 335
 336         CSR_WRITE_4(sc, ET_PM,
 337                     ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE);
 338
 339         et_reset(sc);
 340
 341         et_disable_intrs(sc);
 342
 343         error = et_dma_alloc(dev);
 344         if (error)
 345                 goto fail;
 346
 347         ifp->if_softc = sc;
 348         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 349         ifp->if_init = et_init;
 350         ifp->if_ioctl = et_ioctl;
 351         ifp->if_start = et_start;
 352         ifp->if_watchdog = et_watchdog;
 353         ifp->if_mtu = ETHERMTU;
 354         ifp->if_capabilities = IFCAP_VLAN_MTU;
 355         ifp->if_capenable = ifp->if_capabilities;
 356         ifq_set_maxlen(&ifp->if_snd, ET_TX_NDESC);
 357         ifq_set_ready(&ifp->if_snd);
 358
 359         et_chip_attach(sc);
 360
 361         error = mii_phy_probe(dev, &sc->sc_miibus,
 362                               et_ifmedia_upd, et_ifmedia_sts);
 363         if (error) {
 364                 device_printf(dev, "can't probe any PHY\n");
 365                 goto fail;
 366         }
 367
 368         ether_ifattach(ifp, eaddr, NULL);
 369
 370         error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, et_intr, sc,
 371                                &sc->sc_irq_handle, ifp->if_serializer);
 372         if (error) {
 373                 ether_ifdetach(ifp);
 374                 device_printf(dev, "can't setup intr\n");
 375                 goto fail;
 376         }
 377
 378         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
 379         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 380
 381         return 0;
 382 fail:
 383         et_detach(dev);
 384         return error;
 385 }
 386
 387 static int
 388 et_detach(device_t dev)
 389 {
 390         struct et_softc *sc = device_get_softc(dev);
 391
 392         if (device_is_attached(dev)) {
 393                 struct ifnet *ifp = &sc->arpcom.ac_if;
 394
 395                 lwkt_serialize_enter(ifp->if_serializer);
 396                 et_stop(sc);
 397                 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
 398                 lwkt_serialize_exit(ifp->if_serializer);
 399
 400                 ether_ifdetach(ifp);
 401         }
 402
 403         if (sc->sc_sysctl_tree != NULL)
 404                 sysctl_ctx_free(&sc->sc_sysctl_ctx);
 405
 406         if (sc->sc_miibus != NULL)
 407                 device_delete_child(dev, sc->sc_miibus);
 408         bus_generic_detach(dev);
 409
 410         if (sc->sc_irq_res != NULL) {
 411                 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
 412                                      sc->sc_irq_res);
 413         }
 414
 415         if (sc->sc_mem_res != NULL) {
 416                 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
 417                                      sc->sc_mem_res);
 418         }
 419
 420         et_dma_free(dev);
 421
 422         return 0;
 423 }
 424
 425 static int
 426 et_shutdown(device_t dev)
 427 {
 428         struct et_softc *sc = device_get_softc(dev);
 429         struct ifnet *ifp = &sc->arpcom.ac_if;
 430
 431         lwkt_serialize_enter(ifp->if_serializer);
 432         et_stop(sc);
 433         lwkt_serialize_exit(ifp->if_serializer);
 434         return 0;
 435 }
 436
 437 static int
 438 et_miibus_readreg(device_t dev, int phy, int reg)
 439 {
 440         struct et_softc *sc = device_get_softc(dev);
 441         uint32_t val;
 442         int i, ret;
 443
 444         /* Stop any pending operations */
 445         CSR_WRITE_4(sc, ET_MII_CMD, 0);
 446
 447         val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
 448               __SHIFTIN(reg, ET_MII_ADDR_REG);
 449         CSR_WRITE_4(sc, ET_MII_ADDR, val);
 450
 451         /* Start reading */
 452         CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ);
 453
 454 #define NRETRY  50
 455
 456         for (i = 0; i < NRETRY; ++i) {
 457                 val = CSR_READ_4(sc, ET_MII_IND);
 458                 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0)
 459                         break;
 460                 DELAY(50);
 461         }
 462         if (i == NRETRY) {
 463                 if_printf(&sc->arpcom.ac_if,
 464                           "read phy %d, reg %d timed out\n", phy, reg);
 465                 ret = 0;
 466                 goto back;
 467         }
 468
 469 #undef NRETRY
 470
 471         val = CSR_READ_4(sc, ET_MII_STAT);
 472         ret = __SHIFTOUT(val, ET_MII_STAT_VALUE);
 473
 474 back:
 475         /* Make sure that the current operation is stopped */
 476         CSR_WRITE_4(sc, ET_MII_CMD, 0);
 477         return ret;
 478 }
 479
 480 static int
 481 et_miibus_writereg(device_t dev, int phy, int reg, int val0)
 482 {
 483         struct et_softc *sc = device_get_softc(dev);
 484         uint32_t val;
 485         int i;
 486
 487         /* Stop any pending operations */
 488         CSR_WRITE_4(sc, ET_MII_CMD, 0);
 489
 490         val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
 491               __SHIFTIN(reg, ET_MII_ADDR_REG);
 492         CSR_WRITE_4(sc, ET_MII_ADDR, val);
 493
 494         /* Start writing */
 495         CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE));
 496
 497 #define NRETRY 100
 498
 499         for (i = 0; i < NRETRY; ++i) {
 500                 val = CSR_READ_4(sc, ET_MII_IND);
 501                 if ((val & ET_MII_IND_BUSY) == 0)
 502                         break;
 503                 DELAY(50);
 504         }
 505         if (i == NRETRY) {
 506                 if_printf(&sc->arpcom.ac_if,
 507                           "write phy %d, reg %d timed out\n", phy, reg);
 508                 et_miibus_readreg(dev, phy, reg);
 509         }
 510
 511 #undef NRETRY
 512
 513         /* Make sure that the current operation is stopped */
 514         CSR_WRITE_4(sc, ET_MII_CMD, 0);
 515         return 0;
 516 }
 517
 518 static void
 519 et_miibus_statchg(device_t dev)
 520 {
 521         et_setmedia(device_get_softc(dev));
 522 }
 523
 524 static int
 525 et_ifmedia_upd(struct ifnet *ifp)
 526 {
 527         struct et_softc *sc = ifp->if_softc;
 528         struct mii_data *mii = device_get_softc(sc->sc_miibus);
 529
 530         if (mii->mii_instance != 0) {
 531                 struct mii_softc *miisc;
 532
 533                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 534                         mii_phy_reset(miisc);
 535         }
 536         mii_mediachg(mii);
 537
 538         return 0;
 539 }
 540
 541 static void
 542 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 543 {
 544         struct et_softc *sc = ifp->if_softc;
 545         struct mii_data *mii = device_get_softc(sc->sc_miibus);
 546
 547         mii_pollstat(mii);
 548         ifmr->ifm_active = mii->mii_media_active;
 549         ifmr->ifm_status = mii->mii_media_status;
 550 }
 551
 552 static void
 553 et_stop(struct et_softc *sc)
 554 {
 555         struct ifnet *ifp = &sc->arpcom.ac_if;
 556
 557         ASSERT_SERIALIZED(ifp->if_serializer);
 558
 559         callout_stop(&sc->sc_tick);
 560
 561         et_stop_rxdma(sc);
 562         et_stop_txdma(sc);
 563
 564         et_disable_intrs(sc);
 565
 566         et_free_tx_ring(sc);
 567         et_free_rx_ring(sc);
 568
 569         et_reset(sc);
 570
 571         sc->sc_tx = 0;
 572         sc->sc_tx_intr = 0;
 573         sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED;
 574
 575         ifp->if_timer = 0;
 576         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 577 }
 578
 579 static int
 580 et_bus_config(device_t dev)
 581 {
 582         uint32_t val, max_plsz;
 583         uint16_t ack_latency, replay_timer;
 584
 585         /*
 586          * Test whether EEPROM is valid
 587          * NOTE: Read twice to get the correct value
 588          */
 589         pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1);
 590         val = pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1);
 591         if (val & ET_PCIM_EEPROM_STATUS_ERROR) {
 592                 device_printf(dev, "EEPROM status error 0x%02x\n", val);
 593                 return ENXIO;
 594         }
 595
 596         /* TODO: LED */
 597
 598         /*
 599          * Configure ACK latency and replay timer according to
 600          * max playload size
 601          */
 602         val = pci_read_config(dev, ET_PCIR_DEVICE_CAPS, 4);
 603         max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ;
 604
 605         switch (max_plsz) {
 606         case ET_PCIV_DEVICE_CAPS_PLSZ_128:
 607                 ack_latency = ET_PCIV_ACK_LATENCY_128;
 608                 replay_timer = ET_PCIV_REPLAY_TIMER_128;
 609                 break;
 610
 611         case ET_PCIV_DEVICE_CAPS_PLSZ_256:
 612                 ack_latency = ET_PCIV_ACK_LATENCY_256;
 613                 replay_timer = ET_PCIV_REPLAY_TIMER_256;
 614                 break;
 615
 616         default:
 617                 ack_latency = pci_read_config(dev, ET_PCIR_ACK_LATENCY, 2);
 618                 replay_timer = pci_read_config(dev, ET_PCIR_REPLAY_TIMER, 2);
 619                 device_printf(dev, "ack latency %u, replay timer %u\n",
 620                               ack_latency, replay_timer);
 621                 break;
 622         }
 623         if (ack_latency != 0) {
 624                 pci_write_config(dev, ET_PCIR_ACK_LATENCY, ack_latency, 2);
 625                 pci_write_config(dev, ET_PCIR_REPLAY_TIMER, replay_timer, 2);
 626         }
 627
 628         /*
 629          * Set L0s and L1 latency timer to 2us
 630          */
 631         val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2);
 632         pci_write_config(dev, ET_PCIR_L0S_L1_LATENCY, val, 1);
 633
 634         /*
 635          * Set max read request size to 2048 bytes
 636          */
 637         val = pci_read_config(dev, ET_PCIR_DEVICE_CTRL, 2);
 638         val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ;
 639         val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K;
 640         pci_write_config(dev, ET_PCIR_DEVICE_CTRL, val, 2);
 641
 642         return 0;
 643 }
 644
 645 static void
 646 et_get_eaddr(device_t dev, uint8_t eaddr[])
 647 {
 648         uint32_t val;
 649         int i;
 650
 651         val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4);
 652         for (i = 0; i < 4; ++i)
 653                 eaddr[i] = (val >> (8 * i)) & 0xff;
 654
 655         val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2);
 656         for (; i < ETHER_ADDR_LEN; ++i)
 657                 eaddr[i] = (val >> (8 * (i - 4))) & 0xff;
 658 }
 659
 660 static void
 661 et_reset(struct et_softc *sc)
 662 {
 663         CSR_WRITE_4(sc, ET_MAC_CFG1,
 664                     ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
 665                     ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
 666                     ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
 667
 668         CSR_WRITE_4(sc, ET_SWRST,
 669                     ET_SWRST_TXDMA | ET_SWRST_RXDMA |
 670                     ET_SWRST_TXMAC | ET_SWRST_RXMAC |
 671                     ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC);
 672
 673         CSR_WRITE_4(sc, ET_MAC_CFG1,
 674                     ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
 675                     ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC);
 676         CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
 677 }
 678
 679 static void
 680 et_disable_intrs(struct et_softc *sc)
 681 {
 682         CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
 683 }
 684
 685 static void
 686 et_enable_intrs(struct et_softc *sc, uint32_t intrs)
 687 {
 688         CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs);
 689 }
 690
 691 static int
 692 et_dma_alloc(device_t dev)
 693 {
 694         struct et_softc *sc = device_get_softc(dev);
 695         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
 696         struct et_txstatus_data *txsd = &sc->sc_tx_status;
 697         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
 698         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
 699         int i, error;
 700
 701         /*
 702          * Create top level DMA tag
 703          */
 704         error = bus_dma_tag_create(NULL, 1, 0,
 705                                    BUS_SPACE_MAXADDR,
 706                                    BUS_SPACE_MAXADDR,
 707                                    NULL, NULL,
 708                                    BUS_SPACE_MAXSIZE_32BIT,
 709                                    0,
 710                                    BUS_SPACE_MAXSIZE_32BIT,
 711                                    0, &sc->sc_dtag);
 712         if (error) {
 713                 device_printf(dev, "can't create DMA tag\n");
 714                 return error;
 715         }
 716
 717         /*
 718          * Create TX ring DMA stuffs
 719          */
 720         tx_ring->tr_desc = bus_dmamem_coherent_any(sc->sc_dtag,
 721                                 ET_ALIGN, ET_TX_RING_SIZE,
 722                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
 723                                 &tx_ring->tr_dtag, &tx_ring->tr_dmap,
 724                                 &tx_ring->tr_paddr);
 725         if (tx_ring->tr_desc == NULL) {
 726                 device_printf(dev, "can't create TX ring DMA stuffs\n");
 727                 return ENOMEM;
 728         }
 729
 730         /*
 731          * Create TX status DMA stuffs
 732          */
 733         txsd->txsd_status = bus_dmamem_coherent_any(sc->sc_dtag,
 734                                 ET_ALIGN, sizeof(uint32_t),
 735                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
 736                                 &txsd->txsd_dtag, &txsd->txsd_dmap,
 737                                 &txsd->txsd_paddr);
 738         if (txsd->txsd_status == NULL) {
 739                 device_printf(dev, "can't create TX status DMA stuffs\n");
 740                 return ENOMEM;
 741         }
 742
 743         /*
 744          * Create DMA stuffs for RX rings
 745          */
 746         for (i = 0; i < ET_RX_NRING; ++i) {
 747                 static const uint32_t rx_ring_posreg[ET_RX_NRING] =
 748                 { ET_RX_RING0_POS, ET_RX_RING1_POS };
 749
 750                 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
 751
 752                 rx_ring->rr_desc = bus_dmamem_coherent_any(sc->sc_dtag,
 753                                         ET_ALIGN, ET_RX_RING_SIZE,
 754                                         BUS_DMA_WAITOK | BUS_DMA_ZERO,
 755                                         &rx_ring->rr_dtag, &rx_ring->rr_dmap,
 756                                         &rx_ring->rr_paddr);
 757                 if (rx_ring->rr_desc == NULL) {
 758                         device_printf(dev, "can't create DMA stuffs for "
 759                                       "the %d RX ring\n", i);
 760                         return ENOMEM;
 761                 }
 762                 rx_ring->rr_posreg = rx_ring_posreg[i];
 763         }
 764
 765         /*
 766          * Create RX stat ring DMA stuffs
 767          */
 768         rxst_ring->rsr_stat = bus_dmamem_coherent_any(sc->sc_dtag,
 769                                 ET_ALIGN, ET_RXSTAT_RING_SIZE,
 770                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
 771                                 &rxst_ring->rsr_dtag, &rxst_ring->rsr_dmap,
 772                                 &rxst_ring->rsr_paddr);
 773         if (rxst_ring->rsr_stat == NULL) {
 774                 device_printf(dev, "can't create RX stat ring DMA stuffs\n");
 775                 return ENOMEM;
 776         }
 777
 778         /*
 779          * Create RX status DMA stuffs
 780          */
 781         rxsd->rxsd_status = bus_dmamem_coherent_any(sc->sc_dtag,
 782                                 ET_ALIGN, sizeof(struct et_rxstatus),
 783                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
 784                                 &rxsd->rxsd_dtag, &rxsd->rxsd_dmap,
 785                                 &rxsd->rxsd_paddr);
 786         if (rxsd->rxsd_status == NULL) {
 787                 device_printf(dev, "can't create RX status DMA stuffs\n");
 788                 return ENOMEM;
 789         }
 790
 791         /*
 792          * Create mbuf DMA stuffs
 793          */
 794         error = et_dma_mbuf_create(dev);
 795         if (error)
 796                 return error;
 797
 798         /*
 799          * Create jumbo buffer DMA stuffs
 800          * NOTE: Allow it to fail
 801          */
 802         if (et_jumbo_mem_alloc(dev) == 0)
 803                 sc->sc_flags |= ET_FLAG_JUMBO;
 804
 805         return 0;
 806 }
 807
 808 static void
 809 et_dma_free(device_t dev)
 810 {
 811         struct et_softc *sc = device_get_softc(dev);
 812         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
 813         struct et_txstatus_data *txsd = &sc->sc_tx_status;
 814         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
 815         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
 816         int i, rx_done[ET_RX_NRING];
 817
 818         /*
 819          * Destroy TX ring DMA stuffs
 820          */
 821         et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc,
 822                            tx_ring->tr_dmap);
 823
 824         /*
 825          * Destroy TX status DMA stuffs
 826          */
 827         et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status,
 828                            txsd->txsd_dmap);
 829
 830         /*
 831          * Destroy DMA stuffs for RX rings
 832          */
 833         for (i = 0; i < ET_RX_NRING; ++i) {
 834                 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
 835
 836                 et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc,
 837                                    rx_ring->rr_dmap);
 838         }
 839
 840         /*
 841          * Destroy RX stat ring DMA stuffs
 842          */
 843         et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat,
 844                            rxst_ring->rsr_dmap);
 845
 846         /*
 847          * Destroy RX status DMA stuffs
 848          */
 849         et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status,
 850                            rxsd->rxsd_dmap);
 851
 852         /*
 853          * Destroy mbuf DMA stuffs
 854          */
 855         for (i = 0; i < ET_RX_NRING; ++i)
 856                 rx_done[i] = ET_RX_NDESC;
 857         et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done);
 858
 859         /*
 860          * Destroy jumbo buffer DMA stuffs
 861          */
 862         if (sc->sc_flags & ET_FLAG_JUMBO)
 863                 et_jumbo_mem_free(dev);
 864
 865         /*
 866          * Destroy top level DMA tag
 867          */
 868         if (sc->sc_dtag != NULL)
 869                 bus_dma_tag_destroy(sc->sc_dtag);
 870 }
 871
 872 static int
 873 et_dma_mbuf_create(device_t dev)
 874 {
 875         struct et_softc *sc = device_get_softc(dev);
 876         struct et_txbuf_data *tbd = &sc->sc_tx_data;
 877         int i, error, rx_done[ET_RX_NRING];
 878
 879         /*
 880          * Create RX mbuf DMA tag
 881          */
 882         error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
 883                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
 884                                    NULL, NULL,
 885                                    MCLBYTES, 1, MCLBYTES,
 886                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
 887                                    &sc->sc_rxbuf_dtag);
 888         if (error) {
 889                 device_printf(dev, "can't create RX mbuf DMA tag\n");
 890                 return error;
 891         }
 892
 893         /*
 894          * Create spare DMA map for RX mbufs
 895          */
 896         error = bus_dmamap_create(sc->sc_rxbuf_dtag, BUS_DMA_WAITOK,
 897                                   &sc->sc_rxbuf_tmp_dmap);
 898         if (error) {
 899                 device_printf(dev, "can't create spare mbuf DMA map\n");
 900                 bus_dma_tag_destroy(sc->sc_rxbuf_dtag);
 901                 sc->sc_rxbuf_dtag = NULL;
 902                 return error;
 903         }
 904
 905         /*
 906          * Create DMA maps for RX mbufs
 907          */
 908         bzero(rx_done, sizeof(rx_done));
 909         for (i = 0; i < ET_RX_NRING; ++i) {
 910                 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
 911                 int j;
 912
 913                 for (j = 0; j < ET_RX_NDESC; ++j) {
 914                         error = bus_dmamap_create(sc->sc_rxbuf_dtag,
 915                                                   BUS_DMA_WAITOK,
 916                                                   &rbd->rbd_buf[j].rb_dmap);
 917                         if (error) {
 918                                 device_printf(dev, "can't create %d RX mbuf "
 919                                               "for %d RX ring\n", j, i);
 920                                 rx_done[i] = j;
 921                                 et_dma_mbuf_destroy(dev, 0, rx_done);
 922                                 return error;
 923                         }
 924                 }
 925                 rx_done[i] = ET_RX_NDESC;
 926
 927                 rbd->rbd_softc = sc;
 928                 rbd->rbd_ring = &sc->sc_rx_ring[i];
 929         }
 930
 931         /*
 932          * Create TX mbuf DMA tag
 933          */
 934         error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
 935                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
 936                                    NULL, NULL,
 937                                    ET_JUMBO_FRAMELEN, ET_NSEG_MAX, MCLBYTES,
 938                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
 939                                    BUS_DMA_ONEBPAGE,
 940                                    &sc->sc_txbuf_dtag);
 941         if (error) {
 942                 device_printf(dev, "can't create TX mbuf DMA tag\n");
 943                 return error;
 944         }
 945
 946         /*
 947          * Create DMA maps for TX mbufs
 948          */
 949         for (i = 0; i < ET_TX_NDESC; ++i) {
 950                 error = bus_dmamap_create(sc->sc_txbuf_dtag,
 951                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
 952                                           &tbd->tbd_buf[i].tb_dmap);
 953                 if (error) {
 954                         device_printf(dev, "can't create %d TX mbuf "
 955                                       "DMA map\n", i);
 956                         et_dma_mbuf_destroy(dev, i, rx_done);
 957                         return error;
 958                 }
 959         }
 960
 961         return 0;
 962 }
 963
 964 static void
 965 et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[])
 966 {
 967         struct et_softc *sc = device_get_softc(dev);
 968         struct et_txbuf_data *tbd = &sc->sc_tx_data;
 969         int i;
 970
 971         /*
 972          * Destroy DMA tag and maps for RX mbufs
 973          */
 974         if (sc->sc_rxbuf_dtag) {
 975                 for (i = 0; i < ET_RX_NRING; ++i) {
 976                         struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
 977                         int j;
 978
 979                         for (j = 0; j < rx_done[i]; ++j) {
 980                                 struct et_rxbuf *rb = &rbd->rbd_buf[j];
 981
 982                                 KASSERT(rb->rb_mbuf == NULL,
 983                                         ("RX mbuf in %d RX ring is "
 984                                          "not freed yet\n", i));
 985                                 bus_dmamap_destroy(sc->sc_rxbuf_dtag,
 986                                                    rb->rb_dmap);
 987                         }
 988                 }
 989                 bus_dmamap_destroy(sc->sc_rxbuf_dtag, sc->sc_rxbuf_tmp_dmap);
 990                 bus_dma_tag_destroy(sc->sc_rxbuf_dtag);
 991                 sc->sc_rxbuf_dtag = NULL;
 992         }
 993
 994         /*
 995          * Destroy DMA tag and maps for TX mbufs
 996          */
 997         if (sc->sc_txbuf_dtag) {
 998                 for (i = 0; i < tx_done; ++i) {
 999                         struct et_txbuf *tb = &tbd->tbd_buf[i];
1000
1001                         KASSERT(tb->tb_mbuf == NULL,
1002                                 ("TX mbuf is not freed yet\n"));
1003                         bus_dmamap_destroy(sc->sc_txbuf_dtag, tb->tb_dmap);
1004                 }
1005                 bus_dma_tag_destroy(sc->sc_txbuf_dtag);
1006                 sc->sc_txbuf_dtag = NULL;
1007         }
1008 }
1009
1010 static void
1011 et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap)
1012 {
1013         if (dtag != NULL) {
1014                 bus_dmamap_unload(dtag, dmap);
1015                 bus_dmamem_free(dtag, addr, dmap);
1016                 bus_dma_tag_destroy(dtag);
1017         }
1018 }
1019
1020 static void
1021 et_chip_attach(struct et_softc *sc)
1022 {
1023         uint32_t val;
1024
1025         /*
1026          * Perform minimal initialization
1027          */
1028
1029         /* Disable loopback */
1030         CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1031
1032         /* Reset MAC */
1033         CSR_WRITE_4(sc, ET_MAC_CFG1,
1034                     ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1035                     ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1036                     ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1037
1038         /*
1039          * Setup half duplex mode
1040          */
1041         val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
1042               __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
1043               __SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
1044               ET_MAC_HDX_EXC_DEFER;
1045         CSR_WRITE_4(sc, ET_MAC_HDX, val);
1046
1047         /* Clear MAC control */
1048         CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1049
1050         /* Reset MII */
1051         CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1052
1053         /* Bring MAC out of reset state */
1054         CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1055
1056         /* Enable memory controllers */
1057         CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1058 }
1059
1060 static void
1061 et_intr(void *xsc)
1062 {
1063         struct et_softc *sc = xsc;
1064         struct ifnet *ifp = &sc->arpcom.ac_if;
1065         uint32_t intrs;
1066
1067         ASSERT_SERIALIZED(ifp->if_serializer);
1068
1069         if ((ifp->if_flags & IFF_RUNNING) == 0)
1070                 return;
1071
1072         et_disable_intrs(sc);
1073
1074         intrs = CSR_READ_4(sc, ET_INTR_STATUS);
1075         intrs &= ET_INTRS;
1076         if (intrs == 0) /* Not interested */
1077                 goto back;
1078
1079         if (intrs & ET_INTR_RXEOF)
1080                 et_rxeof(sc);
1081         if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER))
1082                 et_txeof(sc, 1);
1083         if (intrs & ET_INTR_TIMER)
1084                 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1085 back:
1086         et_enable_intrs(sc, ET_INTRS);
1087 }
1088
1089 static void
1090 et_init(void *xsc)
1091 {
1092         struct et_softc *sc = xsc;
1093         struct ifnet *ifp = &sc->arpcom.ac_if;
1094         const struct et_bsize *arr;
1095         int error, i;
1096
1097         ASSERT_SERIALIZED(ifp->if_serializer);
1098
1099         et_stop(sc);
1100
1101         arr = ET_FRAMELEN(ifp->if_mtu) < MCLBYTES ?
1102               et_bufsize_std : et_bufsize_jumbo;
1103         for (i = 0; i < ET_RX_NRING; ++i) {
1104                 sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize;
1105                 sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf;
1106                 sc->sc_rx_data[i].rbd_jumbo = arr[i].jumbo;
1107         }
1108
1109         error = et_init_tx_ring(sc);
1110         if (error)
1111                 goto back;
1112
1113         error = et_init_rx_ring(sc);
1114         if (error)
1115                 goto back;
1116
1117         error = et_chip_init(sc);
1118         if (error)
1119                 goto back;
1120
1121         error = et_enable_txrx(sc, 1);
1122         if (error)
1123                 goto back;
1124
1125         et_enable_intrs(sc, ET_INTRS);
1126
1127         callout_reset(&sc->sc_tick, hz, et_tick, sc);
1128
1129         CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1130
1131         ifp->if_flags |= IFF_RUNNING;
1132         ifp->if_flags &= ~IFF_OACTIVE;
1133 back:
1134         if (error)
1135                 et_stop(sc);
1136 }
1137
1138 static int
1139 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1140 {
1141         struct et_softc *sc = ifp->if_softc;
1142         struct mii_data *mii = device_get_softc(sc->sc_miibus);
1143         struct ifreq *ifr = (struct ifreq *)data;
1144         int error = 0, max_framelen;
1145
1146         ASSERT_SERIALIZED(ifp->if_serializer);
1147
1148         switch (cmd) {
1149         case SIOCSIFFLAGS:
1150                 if (ifp->if_flags & IFF_UP) {
1151                         if (ifp->if_flags & IFF_RUNNING) {
1152                                 if ((ifp->if_flags ^ sc->sc_if_flags) &
1153                                     (IFF_ALLMULTI | IFF_PROMISC))
1154                                         et_setmulti(sc);
1155                         } else {
1156                                 et_init(sc);
1157                         }
1158                 } else {
1159                         if (ifp->if_flags & IFF_RUNNING)
1160                                 et_stop(sc);
1161                 }
1162                 sc->sc_if_flags = ifp->if_flags;
1163                 break;
1164
1165         case SIOCSIFMEDIA:
1166         case SIOCGIFMEDIA:
1167                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1168                 break;
1169
1170         case SIOCADDMULTI:
1171         case SIOCDELMULTI:
1172                 if (ifp->if_flags & IFF_RUNNING)
1173                         et_setmulti(sc);
1174                 break;
1175
1176         case SIOCSIFMTU:
1177                 if (sc->sc_flags & ET_FLAG_JUMBO)
1178                         max_framelen = ET_JUMBO_FRAMELEN;
1179                 else
1180                         max_framelen = MCLBYTES - 1;
1181
1182                 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) {
1183                         error = EOPNOTSUPP;
1184                         break;
1185                 }
1186
1187                 ifp->if_mtu = ifr->ifr_mtu;
1188                 if (ifp->if_flags & IFF_RUNNING)
1189                         et_init(sc);
1190                 break;
1191
1192         default:
1193                 error = ether_ioctl(ifp, cmd, data);
1194                 break;
1195         }
1196         return error;
1197 }
1198
1199 static void
1200 et_start(struct ifnet *ifp)
1201 {
1202         struct et_softc *sc = ifp->if_softc;
1203         struct et_txbuf_data *tbd = &sc->sc_tx_data;
1204         int trans, oactive;
1205
1206         ASSERT_SERIALIZED(ifp->if_serializer);
1207
1208         if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) {
1209                 ifq_purge(&ifp->if_snd);
1210                 return;
1211         }
1212
1213         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1214                 return;
1215
1216         oactive = 0;
1217         trans = 0;
1218         for (;;) {
1219                 struct mbuf *m;
1220                 int error;
1221
1222                 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) {
1223                         if (oactive) {
1224                                 ifp->if_flags |= IFF_OACTIVE;
1225                                 break;
1226                         }
1227
1228                         et_txeof(sc, 0);
1229                         oactive = 1;
1230                         continue;
1231                 }
1232
1233                 m = ifq_dequeue(&ifp->if_snd, NULL);
1234                 if (m == NULL)
1235                         break;
1236
1237                 error = et_encap(sc, &m);
1238                 if (error) {
1239                         ifp->if_oerrors++;
1240                         KKASSERT(m == NULL);
1241
1242                         if (error == EFBIG) {
1243                                 /*
1244                                  * Excessive fragmented packets
1245                                  */
1246                                 if (oactive) {
1247                                         ifp->if_flags |= IFF_OACTIVE;
1248                                         break;
1249                                 }
1250                                 et_txeof(sc, 0);
1251                                 oactive = 1;
1252                         }
1253                         continue;
1254                 } else {
1255                         oactive = 0;
1256                 }
1257                 trans = 1;
1258
1259                 BPF_MTAP(ifp, m);
1260         }
1261
1262         if (trans)
1263                 ifp->if_timer = 5;
1264 }
1265
1266 static void
1267 et_watchdog(struct ifnet *ifp)
1268 {
1269         ASSERT_SERIALIZED(ifp->if_serializer);
1270
1271         if_printf(ifp, "watchdog timed out\n");
1272
1273         ifp->if_init(ifp->if_softc);
1274         if_devstart(ifp);
1275 }
1276
1277 static int
1278 et_stop_rxdma(struct et_softc *sc)
1279 {
1280         CSR_WRITE_4(sc, ET_RXDMA_CTRL,
1281                     ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE);
1282
1283         DELAY(5);
1284         if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {
1285                 if_printf(&sc->arpcom.ac_if, "can't stop RX DMA engine\n");
1286                 return ETIMEDOUT;
1287         }
1288         return 0;
1289 }
1290
1291 static int
1292 et_stop_txdma(struct et_softc *sc)
1293 {
1294         CSR_WRITE_4(sc, ET_TXDMA_CTRL,
1295                     ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT);
1296         return 0;
1297 }
1298
1299 static void
1300 et_free_tx_ring(struct et_softc *sc)
1301 {
1302         struct et_txbuf_data *tbd = &sc->sc_tx_data;
1303         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1304         int i;
1305
1306         for (i = 0; i < ET_TX_NDESC; ++i) {
1307                 struct et_txbuf *tb = &tbd->tbd_buf[i];
1308
1309                 if (tb->tb_mbuf != NULL) {
1310                         bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap);
1311                         m_freem(tb->tb_mbuf);
1312                         tb->tb_mbuf = NULL;
1313                 }
1314         }
1315         bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1316 }
1317
1318 static void
1319 et_free_rx_ring(struct et_softc *sc)
1320 {
1321         int n;
1322
1323         for (n = 0; n < ET_RX_NRING; ++n) {
1324                 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1325                 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n];
1326                 int i;
1327
1328                 for (i = 0; i < ET_RX_NDESC; ++i) {
1329                         struct et_rxbuf *rb = &rbd->rbd_buf[i];
1330
1331                         if (rb->rb_mbuf != NULL) {
1332                                 if (!rbd->rbd_jumbo) {
1333                                         bus_dmamap_unload(sc->sc_rxbuf_dtag,
1334                                                           rb->rb_dmap);
1335                                 }
1336                                 m_freem(rb->rb_mbuf);
1337                                 rb->rb_mbuf = NULL;
1338                         }
1339                 }
1340                 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE);
1341         }
1342 }
1343
1344 static void
1345 et_setmulti(struct et_softc *sc)
1346 {
1347         struct ifnet *ifp = &sc->arpcom.ac_if;
1348         uint32_t hash[4] = { 0, 0, 0, 0 };
1349         uint32_t rxmac_ctrl, pktfilt;
1350         struct ifmultiaddr *ifma;
1351         int i, count;
1352
1353         pktfilt = CSR_READ_4(sc, ET_PKTFILT);
1354         rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);
1355
1356         pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST);
1357         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1358                 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT;
1359                 goto back;
1360         }
1361
1362         count = 0;
1363         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1364                 uint32_t *hp, h;
1365
1366                 if (ifma->ifma_addr->sa_family != AF_LINK)
1367                         continue;
1368
1369                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1370                                    ifma->ifma_addr), ETHER_ADDR_LEN);
1371                 h = (h & 0x3f800000) >> 23;
1372
1373                 hp = &hash[0];
1374                 if (h >= 32 && h < 64) {
1375                         h -= 32;
1376                         hp = &hash[1];
1377                 } else if (h >= 64 && h < 96) {
1378                         h -= 64;
1379                         hp = &hash[2];
1380                 } else if (h >= 96) {
1381                         h -= 96;
1382                         hp = &hash[3];
1383                 }
1384                 *hp |= (1 << h);
1385
1386                 ++count;
1387         }
1388
1389         for (i = 0; i < 4; ++i)
1390                 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]);
1391
1392         if (count > 0)
1393                 pktfilt |= ET_PKTFILT_MCAST;
1394         rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT;
1395 back:
1396         CSR_WRITE_4(sc, ET_PKTFILT, pktfilt);
1397         CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl);
1398 }
1399
1400 static int
1401 et_chip_init(struct et_softc *sc)
1402 {
1403         struct ifnet *ifp = &sc->arpcom.ac_if;
1404         uint32_t rxq_end;
1405         int error, frame_len, rxmem_size;
1406
1407         /*
1408          * Split 16Kbytes internal memory between TX and RX
1409          * according to frame length.
1410          */
1411         frame_len = ET_FRAMELEN(ifp->if_mtu);
1412         if (frame_len < 2048) {
1413                 rxmem_size = ET_MEM_RXSIZE_DEFAULT;
1414         } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) {
1415                 rxmem_size = ET_MEM_SIZE / 2;
1416         } else {
1417                 rxmem_size = ET_MEM_SIZE -
1418                 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT);
1419         }
1420         rxq_end = ET_QUEUE_ADDR(rxmem_size);
1421
1422         CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START);
1423         CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end);
1424         CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1);
1425         CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END);
1426
1427         /* No loopback */
1428         CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1429
1430         /* Clear MSI configure */
1431         CSR_WRITE_4(sc, ET_MSI_CFG, 0);
1432
1433         /* Disable timer */
1434         CSR_WRITE_4(sc, ET_TIMER, 0);
1435
1436         /* Initialize MAC */
1437         et_init_mac(sc);
1438
1439         /* Enable memory controllers */
1440         CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1441
1442         /* Initialize RX MAC */
1443         et_init_rxmac(sc);
1444
1445         /* Initialize TX MAC */
1446         et_init_txmac(sc);
1447
1448         /* Initialize RX DMA engine */
1449         error = et_init_rxdma(sc);
1450         if (error)
1451                 return error;
1452
1453         /* Initialize TX DMA engine */
1454         error = et_init_txdma(sc);
1455         if (error)
1456                 return error;
1457
1458         return 0;
1459 }
1460
1461 static int
1462 et_init_tx_ring(struct et_softc *sc)
1463 {
1464         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1465         struct et_txstatus_data *txsd = &sc->sc_tx_status;
1466         struct et_txbuf_data *tbd = &sc->sc_tx_data;
1467
1468         bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1469
1470         tbd->tbd_start_index = 0;
1471         tbd->tbd_start_wrap = 0;
1472         tbd->tbd_used = 0;
1473
1474         bzero(txsd->txsd_status, sizeof(uint32_t));
1475
1476         return 0;
1477 }
1478
1479 static int
1480 et_init_rx_ring(struct et_softc *sc)
1481 {
1482         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1483         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1484         int n;
1485
1486         for (n = 0; n < ET_RX_NRING; ++n) {
1487                 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1488                 int i, error;
1489
1490                 for (i = 0; i < ET_RX_NDESC; ++i) {
1491                         error = rbd->rbd_newbuf(rbd, i, 1);
1492                         if (error) {
1493                                 if_printf(&sc->arpcom.ac_if, "%d ring %d buf, "
1494                                           "newbuf failed: %d\n", n, i, error);
1495                                 return error;
1496                         }
1497                 }
1498         }
1499
1500         bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus));
1501         bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE);
1502
1503         return 0;
1504 }
1505
1506 static int
1507 et_init_rxdma(struct et_softc *sc)
1508 {
1509         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1510         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1511         struct et_rxdesc_ring *rx_ring;
1512         int error;
1513
1514         error = et_stop_rxdma(sc);
1515         if (error) {
1516                 if_printf(&sc->arpcom.ac_if, "can't init RX DMA engine\n");
1517                 return error;
1518         }
1519
1520         /*
1521          * Install RX status
1522          */
1523         CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr));
1524         CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr));
1525
1526         /*
1527          * Install RX stat ring
1528          */
1529         CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr));
1530         CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr));
1531         CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1);
1532         CSR_WRITE_4(sc, ET_RXSTAT_POS, 0);
1533         CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1);
1534
1535         /* Match ET_RXSTAT_POS */
1536         rxst_ring->rsr_index = 0;
1537         rxst_ring->rsr_wrap = 0;
1538
1539         /*
1540          * Install the 2nd RX descriptor ring
1541          */
1542         rx_ring = &sc->sc_rx_ring[1];
1543         CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1544         CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1545         CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1);
1546         CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP);
1547         CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1548
1549         /* Match ET_RX_RING1_POS */
1550         rx_ring->rr_index = 0;
1551         rx_ring->rr_wrap = 1;
1552
1553         /*
1554          * Install the 1st RX descriptor ring
1555          */
1556         rx_ring = &sc->sc_rx_ring[0];
1557         CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1558         CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1559         CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1);
1560         CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP);
1561         CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1562
1563         /* Match ET_RX_RING0_POS */
1564         rx_ring->rr_index = 0;
1565         rx_ring->rr_wrap = 1;
1566
1567         /*
1568          * RX intr moderation
1569          */
1570         CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts);
1571         CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay);
1572
1573         return 0;
1574 }
1575
1576 static int
1577 et_init_txdma(struct et_softc *sc)
1578 {
1579         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1580         struct et_txstatus_data *txsd = &sc->sc_tx_status;
1581         int error;
1582
1583         error = et_stop_txdma(sc);
1584         if (error) {
1585                 if_printf(&sc->arpcom.ac_if, "can't init TX DMA engine\n");
1586                 return error;
1587         }
1588
1589         /*
1590          * Install TX descriptor ring
1591          */
1592         CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr));
1593         CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr));
1594         CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1);
1595
1596         /*
1597          * Install TX status
1598          */
1599         CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr));
1600         CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr));
1601
1602         CSR_WRITE_4(sc, ET_TX_READY_POS, 0);
1603
1604         /* Match ET_TX_READY_POS */
1605         tx_ring->tr_ready_index = 0;
1606         tx_ring->tr_ready_wrap = 0;
1607
1608         return 0;
1609 }
1610
1611 static void
1612 et_init_mac(struct et_softc *sc)
1613 {
1614         struct ifnet *ifp = &sc->arpcom.ac_if;
1615         const uint8_t *eaddr = IF_LLADDR(ifp);
1616         uint32_t val;
1617
1618         /* Reset MAC */
1619         CSR_WRITE_4(sc, ET_MAC_CFG1,
1620                     ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1621                     ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1622                     ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1623
1624         /*
1625          * Setup inter packet gap
1626          */
1627         val = __SHIFTIN(56, ET_IPG_NONB2B_1) |
1628               __SHIFTIN(88, ET_IPG_NONB2B_2) |
1629               __SHIFTIN(80, ET_IPG_MINIFG) |
1630               __SHIFTIN(96, ET_IPG_B2B);
1631         CSR_WRITE_4(sc, ET_IPG, val);
1632
1633         /*
1634          * Setup half duplex mode
1635          */
1636         val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
1637               __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
1638               __SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
1639               ET_MAC_HDX_EXC_DEFER;
1640         CSR_WRITE_4(sc, ET_MAC_HDX, val);
1641
1642         /* Clear MAC control */
1643         CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1644
1645         /* Reset MII */
1646         CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1647
1648         /*
1649          * Set MAC address
1650          */
1651         val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24);
1652         CSR_WRITE_4(sc, ET_MAC_ADDR1, val);
1653         val = (eaddr[0] << 16) | (eaddr[1] << 24);
1654         CSR_WRITE_4(sc, ET_MAC_ADDR2, val);
1655
1656         /* Set max frame length */
1657         CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu));
1658
1659         /* Bring MAC out of reset state */
1660         CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1661 }
1662
1663 static void
1664 et_init_rxmac(struct et_softc *sc)
1665 {
1666         struct ifnet *ifp = &sc->arpcom.ac_if;
1667         const uint8_t *eaddr = IF_LLADDR(ifp);
1668         uint32_t val;
1669         int i;
1670
1671         /* Disable RX MAC and WOL */
1672         CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE);
1673
1674         /*
1675          * Clear all WOL related registers
1676          */
1677         for (i = 0; i < 3; ++i)
1678                 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0);
1679         for (i = 0; i < 20; ++i)
1680                 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0);
1681
1682         /*
1683          * Set WOL source address.  XXX is this necessary?
1684          */
1685         val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5];
1686         CSR_WRITE_4(sc, ET_WOL_SA_LO, val);
1687         val = (eaddr[0] << 8) | eaddr[1];
1688         CSR_WRITE_4(sc, ET_WOL_SA_HI, val);
1689
1690         /* Clear packet filters */
1691         CSR_WRITE_4(sc, ET_PKTFILT, 0);
1692
1693         /* No ucast filtering */
1694         CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0);
1695         CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0);
1696         CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0);
1697
1698         if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) {
1699                 /*
1700                  * In order to transmit jumbo packets greater than
1701                  * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between
1702                  * RX MAC and RX DMA needs to be reduced in size to
1703                  * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen).  In
1704                  * order to implement this, we must use "cut through"
1705                  * mode in the RX MAC, which chops packets down into
1706                  * segments.  In this case we selected 256 bytes,
1707                  * since this is the size of the PCI-Express TLP's
1708                  * that the ET1310 uses.
1709                  */
1710                 val = __SHIFTIN(ET_RXMAC_SEGSZ(256), ET_RXMAC_MC_SEGSZ_MAX) |
1711                       ET_RXMAC_MC_SEGSZ_ENABLE;
1712         } else {
1713                 val = 0;
1714         }
1715         CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val);
1716
1717         CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0);
1718
1719         /* Initialize RX MAC management register */
1720         CSR_WRITE_4(sc, ET_RXMAC_MGT, 0);
1721
1722         CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0);
1723
1724         CSR_WRITE_4(sc, ET_RXMAC_MGT,
1725                     ET_RXMAC_MGT_PASS_ECRC |
1726                     ET_RXMAC_MGT_PASS_ELEN |
1727                     ET_RXMAC_MGT_PASS_ETRUNC |
1728                     ET_RXMAC_MGT_CHECK_PKT);
1729
1730         /*
1731          * Configure runt filtering (may not work on certain chip generation)
1732          */
1733         val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG;
1734         CSR_WRITE_4(sc, ET_PKTFILT, val);
1735
1736         /* Enable RX MAC but leave WOL disabled */
1737         CSR_WRITE_4(sc, ET_RXMAC_CTRL,
1738                     ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE);
1739
1740         /*
1741          * Setup multicast hash and allmulti/promisc mode
1742          */
1743         et_setmulti(sc);
1744 }
1745
1746 static void
1747 et_init_txmac(struct et_softc *sc)
1748 {
1749         /* Disable TX MAC and FC(?) */
1750         CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE);
1751
1752         /* No flow control yet */
1753         CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0);
1754
1755         /* Enable TX MAC but leave FC(?) diabled */
1756         CSR_WRITE_4(sc, ET_TXMAC_CTRL,
1757                     ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE);
1758 }
1759
1760 static int
1761 et_start_rxdma(struct et_softc *sc)
1762 {
1763         uint32_t val = 0;
1764
1765         val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize,
1766                          ET_RXDMA_CTRL_RING0_SIZE) |
1767                ET_RXDMA_CTRL_RING0_ENABLE;
1768         val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize,
1769                          ET_RXDMA_CTRL_RING1_SIZE) |
1770                ET_RXDMA_CTRL_RING1_ENABLE;
1771
1772         CSR_WRITE_4(sc, ET_RXDMA_CTRL, val);
1773
1774         DELAY(5);
1775
1776         if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {
1777                 if_printf(&sc->arpcom.ac_if, "can't start RX DMA engine\n");
1778                 return ETIMEDOUT;
1779         }
1780         return 0;
1781 }
1782
1783 static int
1784 et_start_txdma(struct et_softc *sc)
1785 {
1786         CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT);
1787         return 0;
1788 }
1789
1790 static int
1791 et_enable_txrx(struct et_softc *sc, int media_upd)
1792 {
1793         struct ifnet *ifp = &sc->arpcom.ac_if;
1794         uint32_t val;
1795         int i, error;
1796
1797         val = CSR_READ_4(sc, ET_MAC_CFG1);
1798         val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
1799         val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
1800                  ET_MAC_CFG1_LOOPBACK);
1801         CSR_WRITE_4(sc, ET_MAC_CFG1, val);
1802
1803         if (media_upd)
1804                 et_ifmedia_upd(ifp);
1805         else
1806                 et_setmedia(sc);
1807
1808 #define NRETRY  100
1809
1810         for (i = 0; i < NRETRY; ++i) {
1811                 val = CSR_READ_4(sc, ET_MAC_CFG1);
1812                 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
1813                     (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
1814                         break;
1815
1816                 DELAY(10);
1817         }
1818         if (i == NRETRY) {
1819                 if_printf(ifp, "can't enable RX/TX\n");
1820                 return 0;
1821         }
1822         sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
1823
1824 #undef NRETRY
1825
1826         /*
1827          * Start TX/RX DMA engine
1828          */
1829         error = et_start_rxdma(sc);
1830         if (error)
1831                 return error;
1832
1833         error = et_start_txdma(sc);
1834         if (error)
1835                 return error;
1836
1837         return 0;
1838 }
1839
1840 static void
1841 et_rxeof(struct et_softc *sc)
1842 {
1843         struct ifnet *ifp = &sc->arpcom.ac_if;
1844         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1845         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1846         uint32_t rxs_stat_ring;
1847         int rxst_wrap, rxst_index;
1848         struct mbuf_chain chain[MAXCPU];
1849
1850         if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
1851                 return;
1852
1853         rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring;
1854         rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0;
1855         rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX);
1856
1857         ether_input_chain_init(chain);
1858
1859         while (rxst_index != rxst_ring->rsr_index ||
1860                rxst_wrap != rxst_ring->rsr_wrap) {
1861                 struct et_rxbuf_data *rbd;
1862                 struct et_rxdesc_ring *rx_ring;
1863                 struct et_rxstat *st;
1864                 struct mbuf *m;
1865                 int buflen, buf_idx, ring_idx;
1866                 uint32_t rxstat_pos, rxring_pos;
1867
1868                 KKASSERT(rxst_ring->rsr_index < ET_RX_NSTAT);
1869                 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index];
1870
1871                 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN);
1872                 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX);
1873                 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX);
1874
1875                 if (++rxst_ring->rsr_index == ET_RX_NSTAT) {
1876                         rxst_ring->rsr_index = 0;
1877                         rxst_ring->rsr_wrap ^= 1;
1878                 }
1879                 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index,
1880                                        ET_RXSTAT_POS_INDEX);
1881                 if (rxst_ring->rsr_wrap)
1882                         rxstat_pos |= ET_RXSTAT_POS_WRAP;
1883                 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos);
1884
1885                 if (ring_idx >= ET_RX_NRING) {
1886                         ifp->if_ierrors++;
1887                         if_printf(ifp, "invalid ring index %d\n", ring_idx);
1888                         continue;
1889                 }
1890                 if (buf_idx >= ET_RX_NDESC) {
1891                         ifp->if_ierrors++;
1892                         if_printf(ifp, "invalid buf index %d\n", buf_idx);
1893                         continue;
1894                 }
1895
1896                 rbd = &sc->sc_rx_data[ring_idx];
1897                 m = rbd->rbd_buf[buf_idx].rb_mbuf;
1898
1899                 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) {
1900                         if (buflen < ETHER_CRC_LEN) {
1901                                 m_freem(m);
1902                                 ifp->if_ierrors++;
1903                         } else {
1904                                 m->m_pkthdr.len = m->m_len = buflen;
1905                                 m->m_pkthdr.rcvif = ifp;
1906
1907                                 m_adj(m, -ETHER_CRC_LEN);
1908
1909                                 ifp->if_ipackets++;
1910                                 ether_input_chain(ifp, m, NULL, chain);
1911                         }
1912                 } else {
1913                         ifp->if_ierrors++;
1914                 }
1915                 m = NULL;       /* Catch invalid reference */
1916
1917                 rx_ring = &sc->sc_rx_ring[ring_idx];
1918
1919                 if (buf_idx != rx_ring->rr_index) {
1920                         if_printf(ifp, "WARNING!! ring %d, "
1921                                   "buf_idx %d, rr_idx %d\n",
1922                                   ring_idx, buf_idx, rx_ring->rr_index);
1923                 }
1924
1925                 KKASSERT(rx_ring->rr_index < ET_RX_NDESC);
1926                 if (++rx_ring->rr_index == ET_RX_NDESC) {
1927                         rx_ring->rr_index = 0;
1928                         rx_ring->rr_wrap ^= 1;
1929                 }
1930                 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX);
1931                 if (rx_ring->rr_wrap)
1932                         rxring_pos |= ET_RX_RING_POS_WRAP;
1933                 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos);
1934         }
1935
1936         ether_input_dispatch(chain);
1937 }
1938
1939 static int
1940 et_encap(struct et_softc *sc, struct mbuf **m0)
1941 {
1942         bus_dma_segment_t segs[ET_NSEG_MAX];
1943         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1944         struct et_txbuf_data *tbd = &sc->sc_tx_data;
1945         struct et_txdesc *td;
1946         bus_dmamap_t map;
1947         int error, maxsegs, nsegs, first_idx, last_idx, i;
1948         uint32_t tx_ready_pos, last_td_ctrl2;
1949
1950         maxsegs = ET_TX_NDESC - tbd->tbd_used;
1951         if (maxsegs > ET_NSEG_MAX)
1952                 maxsegs = ET_NSEG_MAX;
1953         KASSERT(maxsegs >= ET_NSEG_SPARE,
1954                 ("not enough spare TX desc (%d)\n", maxsegs));
1955
1956         KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC);
1957         first_idx = tx_ring->tr_ready_index;
1958         map = tbd->tbd_buf[first_idx].tb_dmap;
1959
1960         error = bus_dmamap_load_mbuf_defrag(sc->sc_txbuf_dtag, map, m0,
1961                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1962         if (error)
1963                 goto back;
1964         bus_dmamap_sync(sc->sc_txbuf_dtag, map, BUS_DMASYNC_PREWRITE);
1965
1966         last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG;
1967         sc->sc_tx += nsegs;
1968         if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) {
1969                 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs;
1970                 last_td_ctrl2 |= ET_TDCTRL2_INTR;
1971         }
1972
1973         last_idx = -1;
1974         for (i = 0; i < nsegs; ++i) {
1975                 int idx;
1976
1977                 idx = (first_idx + i) % ET_TX_NDESC;
1978                 td = &tx_ring->tr_desc[idx];
1979                 td->td_addr_hi = ET_ADDR_HI(segs[i].ds_addr);
1980                 td->td_addr_lo = ET_ADDR_LO(segs[i].ds_addr);
1981                 td->td_ctrl1 = __SHIFTIN(segs[i].ds_len, ET_TDCTRL1_LEN);
1982
1983                 if (i == nsegs - 1) {   /* Last frag */
1984                         td->td_ctrl2 = last_td_ctrl2;
1985                         last_idx = idx;
1986                 }
1987
1988                 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC);
1989                 if (++tx_ring->tr_ready_index == ET_TX_NDESC) {
1990                         tx_ring->tr_ready_index = 0;
1991                         tx_ring->tr_ready_wrap ^= 1;
1992                 }
1993         }
1994         td = &tx_ring->tr_desc[first_idx];
1995         td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG;  /* First frag */
1996
1997         KKASSERT(last_idx >= 0);
1998         tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap;
1999         tbd->tbd_buf[last_idx].tb_dmap = map;
2000         tbd->tbd_buf[last_idx].tb_mbuf = *m0;
2001
2002         tbd->tbd_used += nsegs;
2003         KKASSERT(tbd->tbd_used <= ET_TX_NDESC);
2004
2005         tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index,
2006                        ET_TX_READY_POS_INDEX);
2007         if (tx_ring->tr_ready_wrap)
2008                 tx_ready_pos |= ET_TX_READY_POS_WRAP;
2009         CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos);
2010
2011         error = 0;
2012 back:
2013         if (error) {
2014                 m_freem(*m0);
2015                 *m0 = NULL;
2016         }
2017         return error;
2018 }
2019
2020 static void
2021 et_txeof(struct et_softc *sc, int start)
2022 {
2023         struct ifnet *ifp = &sc->arpcom.ac_if;
2024         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
2025         struct et_txbuf_data *tbd = &sc->sc_tx_data;
2026         uint32_t tx_done;
2027         int end, wrap;
2028
2029         if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
2030                 return;
2031
2032         if (tbd->tbd_used == 0)
2033                 return;
2034
2035         tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);
2036         end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX);
2037         wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0;
2038
2039         while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) {
2040                 struct et_txbuf *tb;
2041
2042                 KKASSERT(tbd->tbd_start_index < ET_TX_NDESC);
2043                 tb = &tbd->tbd_buf[tbd->tbd_start_index];
2044
2045                 bzero(&tx_ring->tr_desc[tbd->tbd_start_index],
2046                       sizeof(struct et_txdesc));
2047
2048                 if (tb->tb_mbuf != NULL) {
2049                         bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap);
2050                         m_freem(tb->tb_mbuf);
2051                         tb->tb_mbuf = NULL;
2052                         ifp->if_opackets++;
2053                 }
2054
2055                 if (++tbd->tbd_start_index == ET_TX_NDESC) {
2056                         tbd->tbd_start_index = 0;
2057                         tbd->tbd_start_wrap ^= 1;
2058                 }
2059
2060                 KKASSERT(tbd->tbd_used > 0);
2061                 tbd->tbd_used--;
2062         }
2063
2064         if (tbd->tbd_used == 0)
2065                 ifp->if_timer = 0;
2066         if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC)
2067                 ifp->if_flags &= ~IFF_OACTIVE;
2068
2069         if (start)
2070                 if_devstart(ifp);
2071 }
2072
2073 static void
2074 et_tick(void *xsc)
2075 {
2076         struct et_softc *sc = xsc;
2077         struct ifnet *ifp = &sc->arpcom.ac_if;
2078         struct mii_data *mii = device_get_softc(sc->sc_miibus);
2079
2080         lwkt_serialize_enter(ifp->if_serializer);
2081
2082         mii_tick(mii);
2083         if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 &&
2084             (mii->mii_media_status & IFM_ACTIVE) &&
2085             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2086                 if_printf(ifp, "Link up, enable TX/RX\n");
2087                 if (et_enable_txrx(sc, 0) == 0)
2088                         if_devstart(ifp);
2089         }
2090         callout_reset(&sc->sc_tick, hz, et_tick, sc);
2091
2092         lwkt_serialize_exit(ifp->if_serializer);
2093 }
2094
2095 static int
2096 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init)
2097 {
2098         return et_newbuf(rbd, buf_idx, init, MCLBYTES);
2099 }
2100
2101 static int
2102 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init)
2103 {
2104         return et_newbuf(rbd, buf_idx, init, MHLEN);
2105 }
2106
2107 static int
2108 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0)
2109 {
2110         struct et_softc *sc = rbd->rbd_softc;
2111         struct et_rxbuf *rb;
2112         struct mbuf *m;
2113         bus_dma_segment_t seg;
2114         bus_dmamap_t dmap;
2115         int error, len, nseg;
2116
2117         KASSERT(!rbd->rbd_jumbo, ("calling %s with jumbo ring\n", __func__));
2118
2119         KKASSERT(buf_idx < ET_RX_NDESC);
2120         rb = &rbd->rbd_buf[buf_idx];
2121
2122         m = m_getl(len0, init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR, &len);
2123         if (m == NULL) {
2124                 error = ENOBUFS;
2125
2126                 if (init) {
2127                         if_printf(&sc->arpcom.ac_if,
2128                                   "m_getl failed, size %d\n", len0);
2129                         return error;
2130                 } else {
2131                         goto back;
2132                 }
2133         }
2134         m->m_len = m->m_pkthdr.len = len;
2135
2136         /*
2137          * Try load RX mbuf into temporary DMA tag
2138          */
2139         error = bus_dmamap_load_mbuf_segment(sc->sc_rxbuf_dtag,
2140                         sc->sc_rxbuf_tmp_dmap, m, &seg, 1, &nseg,
2141                         BUS_DMA_NOWAIT);
2142         if (error) {
2143                 m_freem(m);
2144                 if (init) {
2145                         if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2146                         return error;
2147                 } else {
2148                         goto back;
2149                 }
2150         }
2151
2152         if (!init) {
2153                 bus_dmamap_sync(sc->sc_rxbuf_dtag, rb->rb_dmap,
2154                                 BUS_DMASYNC_POSTREAD);
2155                 bus_dmamap_unload(sc->sc_rxbuf_dtag, rb->rb_dmap);
2156         }
2157         rb->rb_mbuf = m;
2158         rb->rb_paddr = seg.ds_addr;
2159
2160         /*
2161          * Swap RX buf's DMA map with the loaded temporary one
2162          */
2163         dmap = rb->rb_dmap;
2164         rb->rb_dmap = sc->sc_rxbuf_tmp_dmap;
2165         sc->sc_rxbuf_tmp_dmap = dmap;
2166
2167         error = 0;
2168 back:
2169         et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
2170         return error;
2171 }
2172
2173 static int
2174 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS)
2175 {
2176         struct et_softc *sc = arg1;
2177         struct ifnet *ifp = &sc->arpcom.ac_if;
2178         int error = 0, v;
2179
2180         lwkt_serialize_enter(ifp->if_serializer);
2181
2182         v = sc->sc_rx_intr_npkts;
2183         error = sysctl_handle_int(oidp, &v, 0, req);
2184         if (error || req->newptr == NULL)
2185                 goto back;
2186         if (v <= 0) {
2187                 error = EINVAL;
2188                 goto back;
2189         }
2190
2191         if (sc->sc_rx_intr_npkts != v) {
2192                 if (ifp->if_flags & IFF_RUNNING)
2193                         CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v);
2194                 sc->sc_rx_intr_npkts = v;
2195         }
2196 back:
2197         lwkt_serialize_exit(ifp->if_serializer);
2198         return error;
2199 }
2200
2201 static int
2202 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS)
2203 {
2204         struct et_softc *sc = arg1;
2205         struct ifnet *ifp = &sc->arpcom.ac_if;
2206         int error = 0, v;
2207
2208         lwkt_serialize_enter(ifp->if_serializer);
2209
2210         v = sc->sc_rx_intr_delay;
2211         error = sysctl_handle_int(oidp, &v, 0, req);
2212         if (error || req->newptr == NULL)
2213                 goto back;
2214         if (v <= 0) {
2215                 error = EINVAL;
2216                 goto back;
2217         }
2218
2219         if (sc->sc_rx_intr_delay != v) {
2220                 if (ifp->if_flags & IFF_RUNNING)
2221                         CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v);
2222                 sc->sc_rx_intr_delay = v;
2223         }
2224 back:
2225         lwkt_serialize_exit(ifp->if_serializer);
2226         return error;
2227 }
2228
2229 static void
2230 et_setmedia(struct et_softc *sc)
2231 {
2232         struct mii_data *mii = device_get_softc(sc->sc_miibus);
2233         uint32_t cfg2, ctrl;
2234
2235         cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
2236         cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
2237                   ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
2238         cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
2239                 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN);
2240
2241         ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
2242         ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
2243
2244         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
2245                 cfg2 |= ET_MAC_CFG2_MODE_GMII;
2246         } else {
2247                 cfg2 |= ET_MAC_CFG2_MODE_MII;
2248                 ctrl |= ET_MAC_CTRL_MODE_MII;
2249         }
2250
2251         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
2252                 cfg2 |= ET_MAC_CFG2_FDX;
2253         else
2254                 ctrl |= ET_MAC_CTRL_GHDX;
2255
2256         CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
2257         CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
2258 }
2259
2260 static int
2261 et_jumbo_mem_alloc(device_t dev)
2262 {
2263         struct et_softc *sc = device_get_softc(dev);
2264         struct et_jumbo_data *jd = &sc->sc_jumbo_data;
2265         bus_addr_t paddr;
2266         uint8_t *buf;
2267         int i;
2268
2269         jd->jd_buf = bus_dmamem_coherent_any(sc->sc_dtag,
2270                         ET_JUMBO_ALIGN, ET_JUMBO_MEM_SIZE, BUS_DMA_WAITOK,
2271                         &jd->jd_dtag, &jd->jd_dmap, &paddr);
2272         if (jd->jd_buf == NULL) {
2273                 device_printf(dev, "can't create jumbo DMA stuffs\n");
2274                 return ENOMEM;
2275         }
2276
2277         jd->jd_slots = kmalloc(sizeof(*jd->jd_slots) * ET_JSLOTS, M_DEVBUF,
2278                                M_WAITOK | M_ZERO);
2279         lwkt_serialize_init(&jd->jd_serializer);
2280         SLIST_INIT(&jd->jd_free_slots);
2281
2282         buf = jd->jd_buf;
2283         for (i = 0; i < ET_JSLOTS; ++i) {
2284                 struct et_jslot *jslot = &jd->jd_slots[i];
2285
2286                 jslot->jslot_data = jd;
2287                 jslot->jslot_buf = buf;
2288                 jslot->jslot_paddr = paddr;
2289                 jslot->jslot_inuse = 0;
2290                 jslot->jslot_index = i;
2291                 SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot, jslot_link);
2292
2293                 buf += ET_JLEN;
2294                 paddr += ET_JLEN;
2295         }
2296         return 0;
2297 }
2298
2299 static void
2300 et_jumbo_mem_free(device_t dev)
2301 {
2302         struct et_softc *sc = device_get_softc(dev);
2303         struct et_jumbo_data *jd = &sc->sc_jumbo_data;
2304
2305         KKASSERT(sc->sc_flags & ET_FLAG_JUMBO);
2306
2307         kfree(jd->jd_slots, M_DEVBUF);
2308         et_dma_mem_destroy(jd->jd_dtag, jd->jd_buf, jd->jd_dmap);
2309 }
2310
2311 static struct et_jslot *
2312 et_jalloc(struct et_jumbo_data *jd)
2313 {
2314         struct et_jslot *jslot;
2315
2316         lwkt_serialize_enter(&jd->jd_serializer);
2317
2318         jslot = SLIST_FIRST(&jd->jd_free_slots);
2319         if (jslot) {
2320                 SLIST_REMOVE_HEAD(&jd->jd_free_slots, jslot_link);
2321                 jslot->jslot_inuse = 1;
2322         }
2323
2324         lwkt_serialize_exit(&jd->jd_serializer);
2325         return jslot;
2326 }
2327
2328 static void
2329 et_jfree(void *xjslot)
2330 {
2331         struct et_jslot *jslot = xjslot;
2332         struct et_jumbo_data *jd = jslot->jslot_data;
2333
2334         if (&jd->jd_slots[jslot->jslot_index] != jslot) {
2335                 panic("%s wrong jslot!?\n", __func__);
2336         } else if (jslot->jslot_inuse == 0) {
2337                 panic("%s jslot already freed\n", __func__);
2338         } else {
2339                 lwkt_serialize_enter(&jd->jd_serializer);
2340
2341                 atomic_subtract_int(&jslot->jslot_inuse, 1);
2342                 if (jslot->jslot_inuse == 0) {
2343                         SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot,
2344                                           jslot_link);
2345                 }
2346
2347                 lwkt_serialize_exit(&jd->jd_serializer);
2348         }
2349 }
2350
2351 static void
2352 et_jref(void *xjslot)
2353 {
2354         struct et_jslot *jslot = xjslot;
2355         struct et_jumbo_data *jd = jslot->jslot_data;
2356
2357         if (&jd->jd_slots[jslot->jslot_index] != jslot)
2358                 panic("%s wrong jslot!?\n", __func__);
2359         else if (jslot->jslot_inuse == 0)
2360                 panic("%s jslot already freed\n", __func__);
2361         else
2362                 atomic_add_int(&jslot->jslot_inuse, 1);
2363 }
2364
2365 static int
2366 et_newbuf_jumbo(struct et_rxbuf_data *rbd, int buf_idx, int init)
2367 {
2368         struct et_softc *sc = rbd->rbd_softc;
2369         struct et_rxbuf *rb;
2370         struct mbuf *m;
2371         struct et_jslot *jslot;
2372         int error;
2373
2374         KASSERT(rbd->rbd_jumbo, ("calling %s with non-jumbo ring\n", __func__));
2375
2376         KKASSERT(buf_idx < ET_RX_NDESC);
2377         rb = &rbd->rbd_buf[buf_idx];
2378
2379         error = ENOBUFS;
2380
2381         MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2382         if (m == NULL) {
2383                 if (init) {
2384                         if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
2385                         return error;
2386                 } else {
2387                         goto back;
2388                 }
2389         }
2390
2391         jslot = et_jalloc(&sc->sc_jumbo_data);
2392         if (jslot == NULL) {
2393                 m_freem(m);
2394
2395                 if (init) {
2396                         if_printf(&sc->arpcom.ac_if,
2397                                   "jslot allocation failed\n");
2398                         return error;
2399                 } else {
2400                         goto back;
2401                 }
2402         }
2403
2404         m->m_ext.ext_arg = jslot;
2405         m->m_ext.ext_buf = jslot->jslot_buf;
2406         m->m_ext.ext_free = et_jfree;
2407         m->m_ext.ext_ref = et_jref;
2408         m->m_ext.ext_size = ET_JUMBO_FRAMELEN;
2409         m->m_flags |= M_EXT;
2410         m->m_data = m->m_ext.ext_buf;
2411         m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2412
2413         rb->rb_mbuf = m;
2414         rb->rb_paddr = jslot->jslot_paddr;
2415
2416         error = 0;
2417 back:
2418         et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
2419         return error;
2420 }
2421
2422 static void
2423 et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr)
2424 {
2425         struct et_rxdesc_ring *rx_ring = rbd->rbd_ring;
2426         struct et_rxdesc *desc;
2427
2428         KKASSERT(buf_idx < ET_RX_NDESC);
2429         desc = &rx_ring->rr_desc[buf_idx];
2430
2431         desc->rd_addr_hi = ET_ADDR_HI(paddr);
2432         desc->rd_addr_lo = ET_ADDR_LO(paddr);
2433         desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX);
2434 }