2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/syslog.h>
49 #include <sys/module.h>
52 #include <sys/thread2.h>
54 #include <net/ethernet.h>
56 #include <net/ifq_var.h>
57 #include <net/if_arp.h>
58 #include <net/if_dl.h>
59 #include <net/if_mib.h>
60 #include <net/if_media.h>
63 #include <dev/netif/mii_layer/mii.h>
64 #include <dev/netif/mii_layer/miivar.h>
69 #include <machine/md_var.h>
74 devclass_t ed_devclass;
76 static void ed_init (void *);
77 static int ed_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
78 static void ed_start (struct ifnet *);
79 static void ed_reset (struct ifnet *);
80 static void ed_watchdog (struct ifnet *);
82 static void ed_tick (void *);
85 static void ds_getmcaf (struct ed_softc *, u_int32_t *);
87 static void ed_get_packet (struct ed_softc *, char *, u_short);
89 static __inline void ed_rint (struct ed_softc *);
90 static __inline void ed_xmit (struct ed_softc *);
91 static __inline char * ed_ring_copy (struct ed_softc *, char *, char *,
93 static void ed_hpp_set_physical_link (struct ed_softc *);
94 static void ed_hpp_readmem (struct ed_softc *, u_short, u_char *, u_short);
95 static void ed_hpp_writemem (struct ed_softc *, u_char *, u_short, u_short);
96 static u_short ed_hpp_write_mbufs (struct ed_softc *, struct mbuf *, int);
98 static u_short ed_pio_write_mbufs (struct ed_softc *, struct mbuf *, int);
100 static void ed_setrcr (struct ed_softc *);
102 static uint32_t ds_mchash (const uint8_t *);
104 DECLARE_DUMMY_MODULE(if_ed);
107 * Interrupt conversion table for WD/SMC ASIC/83C584
109 static u_short ed_intr_val[] = {
121 * Interrupt conversion table for 83C790
123 static u_short ed_790_intr_val[] = {
135 * Interrupt conversion table for the HP PC LAN+
138 static u_short ed_hpp_intr_val[] = {
158 * Generic probe routine for testing for the existance of a DS8390.
159 * Must be called after the NIC has just been reset. This routine
160 * works by looking at certain register values that are guaranteed
161 * to be initialized a certain way after power-up or reset. Seems
162 * not to currently work on the 83C690.
166 * Register reset bits set bits
167 * Command Register (CR) TXP, STA RD2, STP
168 * Interrupt Status (ISR) RST
169 * Interrupt Mask (IMR) All bits
170 * Data Control (DCR) LAS
171 * Transmit Config. (TCR) LB1, LB0
173 * We only look at the CR and ISR registers, however, because looking at
174 * the others would require changing register pages (which would be
175 * intrusive if this isn't an 8390).
177 * Return 1 if 8390 was found, 0 if not.
181 ed_probe_generic8390(struct ed_softc *sc)
183 if ((ed_nic_inb(sc, ED_P0_CR) &
184 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
185 (ED_CR_RD2 | ED_CR_STP))
187 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
194 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
197 ed_probe_WD80x3_generic(device_t dev, int flags, u_short *intr_vals[])
199 struct ed_softc *sc = device_get_softc(dev);
202 u_int memsize, maddr;
203 u_char iptr, isa16bit, sum, totalsum;
204 u_long conf_maddr, conf_msize, irq, junk;
206 sc->chip_type = ED_CHIP_TYPE_DP8390;
208 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
209 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
210 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
214 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
217 * Attempt to do a checksum over the station address PROM. If it
218 * fails, it's probably not a SMC/WD board. There is a problem with
219 * this, though: some clone WD boards don't pass the checksum test.
220 * Danpex boards for one.
222 for (sum = 0, i = 0; i < 8; ++i)
223 sum += ed_asic_inb(sc, ED_WD_PROM + i);
225 if (sum != totalsum) {
228 * Checksum is invalid. This often happens with cheap WD8003E
229 * clones. In this case, the checksum byte (the eighth byte)
230 * seems to always be zero.
232 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
233 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
236 /* reset card to force it into a known state. */
237 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
238 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
240 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
243 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
244 /* wait in the case this card is reading its EEROM */
247 sc->vendor = ED_VENDOR_WD_SMC;
248 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
251 * Set initial values for width/size.
256 case ED_TYPE_WD8003S:
257 sc->type_str = "WD8003S";
259 case ED_TYPE_WD8003E:
260 sc->type_str = "WD8003E";
262 case ED_TYPE_WD8003EB:
263 sc->type_str = "WD8003EB";
265 case ED_TYPE_WD8003W:
266 sc->type_str = "WD8003W";
268 case ED_TYPE_WD8013EBT:
269 sc->type_str = "WD8013EBT";
273 case ED_TYPE_WD8013W:
274 sc->type_str = "WD8013W";
278 case ED_TYPE_WD8013EP: /* also WD8003EP */
279 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
282 sc->type_str = "WD8013EP";
284 sc->type_str = "WD8003EP";
287 case ED_TYPE_WD8013WC:
288 sc->type_str = "WD8013WC";
292 case ED_TYPE_WD8013EBP:
293 sc->type_str = "WD8013EBP";
297 case ED_TYPE_WD8013EPC:
298 sc->type_str = "WD8013EPC";
302 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
303 case ED_TYPE_SMC8216T:
304 if (sc->type == ED_TYPE_SMC8216C) {
305 sc->type_str = "SMC8216/SMC8216C";
307 sc->type_str = "SMC8216T";
310 ed_asic_outb(sc, ED_WD790_HWR,
311 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
312 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
313 case ED_WD790_RAR_SZ64:
316 case ED_WD790_RAR_SZ32:
319 case ED_WD790_RAR_SZ16:
322 case ED_WD790_RAR_SZ8:
323 /* 8216 has 16K shared mem -- 8416 has 8K */
324 if (sc->type == ED_TYPE_SMC8216C) {
325 sc->type_str = "SMC8416C/SMC8416BT";
327 sc->type_str = "SMC8416T";
332 ed_asic_outb(sc, ED_WD790_HWR,
333 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
336 sc->chip_type = ED_CHIP_TYPE_WD790;
338 case ED_TYPE_TOSHIBA1:
339 sc->type_str = "Toshiba1";
343 case ED_TYPE_TOSHIBA4:
344 sc->type_str = "Toshiba4";
354 * Make some adjustments to initial values depending on what is found
357 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
358 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
359 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
364 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
365 &conf_maddr, &conf_msize);
370 kprintf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
371 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
372 for (i = 0; i < 8; i++)
373 kprintf("%x -> %x\n", i, ed_asic_inb(sc, i));
377 * Allow the user to override the autoconfiguration
380 memsize = conf_msize;
383 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
384 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
385 maddr, maddr + memsize);
390 * (note that if the user specifies both of the following flags that
391 * '8bit' mode intentionally has precedence)
393 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
395 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
399 * If possible, get the assigned interrupt number from the card and
402 if ((sc->type & ED_WD_SOFTCONFIG) &&
403 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
406 * Assemble together the encoded interrupt number.
408 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
409 ((ed_asic_inb(sc, ED_WD_IRR) &
410 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
413 * If no interrupt specified (or "?"), use what the board tells us.
415 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
417 if (error && intr_vals[0] != NULL) {
418 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
419 intr_vals[0][iptr], 1);
425 * Enable the interrupt.
427 ed_asic_outb(sc, ED_WD_IRR,
428 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
430 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
431 ed_asic_outb(sc, ED_WD790_HWR,
432 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
433 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
434 (ed_asic_inb(sc, ED_WD790_GCR) &
435 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
436 ed_asic_outb(sc, ED_WD790_HWR,
437 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
440 * If no interrupt specified (or "?"), use what the board tells us.
442 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
444 if (error && intr_vals[1] != NULL) {
445 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
446 intr_vals[1][iptr], 1);
454 ed_asic_outb(sc, ED_WD790_ICR,
455 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
457 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
460 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
464 sc->isa16bit = isa16bit;
467 error = ed_alloc_memory(dev, 0, memsize);
469 kprintf("*** ed_alloc_memory() failed! (%d)\n", error);
472 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
475 * allocate one xmit buffer if < 16k, two buffers otherwise
477 if ((memsize < 16384) ||
478 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
483 sc->tx_page_start = ED_WD_PAGE_OFFSET;
484 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
485 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
486 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
487 sc->mem_size = memsize;
488 sc->mem_end = sc->mem_start + memsize;
491 * Get station address from on-board ROM
493 for (i = 0; i < ETHER_ADDR_LEN; ++i)
494 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
497 * Set upper address bits and 8/16 bit access to shared memory.
500 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
501 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
503 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
504 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
507 * Enable 16bit access
509 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
512 if (((sc->type & ED_WD_SOFTCONFIG) ||
513 (sc->type == ED_TYPE_TOSHIBA1) ||
514 (sc->type == ED_TYPE_TOSHIBA4) ||
515 (sc->type == ED_TYPE_WD8013EBT)) &&
516 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
517 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
519 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
524 * Set address and enable interface shared memory.
526 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
527 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
528 ed_asic_outb(sc, ED_WD_MSR + 1,
529 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
530 ed_asic_outb(sc, ED_WD_MSR + 2,
531 ((kvtop(sc->mem_start) >> 16) & 0x0f));
532 ed_asic_outb(sc, ED_WD_MSR,
533 ED_WD_MSR_MENB | ED_WD_MSR_POW);
535 ed_asic_outb(sc, ED_WD_MSR,
536 ((kvtop(sc->mem_start) >> 13) &
537 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
539 sc->cr_proto = ED_CR_RD2;
541 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
542 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
543 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
544 ((kvtop(sc->mem_start) >> 11) & 0x40) |
545 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
546 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
551 kprintf("starting memory performance test at 0x%x, size %d...\n",
552 sc->mem_start, memsize*16384);
553 for (i = 0; i < 16384; i++)
554 bzero(sc->mem_start, memsize);
555 kprintf("***DONE***\n");
559 * Now zero memory and verify that it is clear
561 bzero(sc->mem_start, memsize);
563 for (i = 0; i < memsize; ++i) {
564 if (sc->mem_start[i]) {
565 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
566 (long long)kvtop(sc->mem_start + i));
569 * Disable 16 bit access to shared memory
572 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
573 ed_asic_outb(sc, ED_WD_MSR, 0x00);
575 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
583 * Disable 16bit access to shared memory - we leave it
584 * disabled so that 1) machines reboot properly when the board
585 * is set 16 bit mode and there are conflicting 8bit
586 * devices/ROMS in the same 128k address space as this boards
587 * shared memory. and 2) so that other 8 bit devices with
588 * shared memory can be used in this 128k region, too.
591 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
592 ed_asic_outb(sc, ED_WD_MSR, 0x00);
594 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
601 ed_probe_WD80x3(device_t dev, int port_rid, int flags)
603 struct ed_softc *sc = device_get_softc(dev);
605 static u_short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
607 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
611 sc->asic_offset = ED_WD_ASIC_OFFSET;
612 sc->nic_offset = ED_WD_NIC_OFFSET;
614 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
618 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
621 ed_probe_3Com(device_t dev, int port_rid, int flags)
623 struct ed_softc *sc = device_get_softc(dev);
628 u_long conf_maddr, conf_msize, irq, junk;
630 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
634 sc->asic_offset = ED_3COM_ASIC_OFFSET;
635 sc->nic_offset = ED_3COM_NIC_OFFSET;
638 * Verify that the kernel configured I/O address matches the board
641 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
642 case ED_3COM_BCFR_300:
643 if (rman_get_start(sc->port_res) != 0x300)
646 case ED_3COM_BCFR_310:
647 if (rman_get_start(sc->port_res) != 0x310)
650 case ED_3COM_BCFR_330:
651 if (rman_get_start(sc->port_res) != 0x330)
654 case ED_3COM_BCFR_350:
655 if (rman_get_start(sc->port_res) != 0x350)
658 case ED_3COM_BCFR_250:
659 if (rman_get_start(sc->port_res) != 0x250)
662 case ED_3COM_BCFR_280:
663 if (rman_get_start(sc->port_res) != 0x280)
666 case ED_3COM_BCFR_2A0:
667 if (rman_get_start(sc->port_res) != 0x2a0)
670 case ED_3COM_BCFR_2E0:
671 if (rman_get_start(sc->port_res) != 0x2e0)
678 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
679 &conf_maddr, &conf_msize);
684 * Verify that the kernel shared memory address matches the board
685 * configured address.
687 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
688 case ED_3COM_PCFR_DC000:
689 if (conf_maddr != 0xdc000)
692 case ED_3COM_PCFR_D8000:
693 if (conf_maddr != 0xd8000)
696 case ED_3COM_PCFR_CC000:
697 if (conf_maddr != 0xcc000)
700 case ED_3COM_PCFR_C8000:
701 if (conf_maddr != 0xc8000)
710 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
711 * sequence because it'll lock up if the cable isn't connected if we
714 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
717 * Wait for a while, then un-reset it
722 * The 3Com ASIC defaults to rather strange settings for the CR after
723 * a reset - it's important to set it again after the following outb
724 * (this is done when we map the PROM below).
726 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
729 * Wait a bit for the NIC to recover from the reset
733 sc->vendor = ED_VENDOR_3COM;
734 sc->type_str = "3c503";
736 sc->cr_proto = ED_CR_RD2;
739 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
745 * Get station address from on-board ROM
749 * First, map ethernet address PROM over the top of where the NIC
750 * registers normally appear.
752 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
754 for (i = 0; i < ETHER_ADDR_LEN; ++i)
755 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
758 * Unmap PROM - select NIC registers. The proper setting of the
759 * tranceiver is set in ed_init so that the attach code is given a
760 * chance to set the default based on a compile-time config option
762 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
765 * Determine if this is an 8bit or 16bit board
769 * select page 0 registers
771 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
774 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
777 ed_nic_outb(sc, ED_P0_DCR, 0);
780 * select page 2 registers
782 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
785 * The 3c503 forces the WTS bit to a one if this is a 16bit board
787 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
793 * select page 0 registers
795 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
797 error = ed_alloc_memory(dev, 0, memsize);
801 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
802 sc->mem_size = memsize;
803 sc->mem_end = sc->mem_start + memsize;
806 * We have an entire 8k window to put the transmit buffers on the
807 * 16bit boards. But since the 16bit 3c503's shared memory is only
808 * fast enough to overlap the loading of one full-size packet, trying
809 * to load more than 2 buffers can actually leave the transmitter idle
810 * during the load. So 2 seems the best value. (Although a mix of
811 * variable-sized packets might change this assumption. Nonetheless,
812 * we optimize for linear transfers of same-size packets.)
815 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
820 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
821 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
822 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
823 ED_3COM_RX_PAGE_OFFSET_16BIT;
824 sc->mem_ring = sc->mem_start;
827 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
828 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
829 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
830 ED_3COM_TX_PAGE_OFFSET_8BIT;
831 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
834 sc->isa16bit = isa16bit;
837 * Initialize GA page start/stop registers. Probably only needed if
838 * doing DMA, but what the hell.
840 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
841 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
844 * Set IRQ. 3c503 only allows a choice of irq 2-5.
846 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
853 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
856 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
859 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
862 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
865 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
871 * Initialize GA configuration register. Set bank and enable shared
874 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
878 * Initialize "Vector Pointer" registers. These gawd-awful things are
879 * compared to 20 bits of the address on ISA, and if they match, the
880 * shared memory is disabled. We set them to 0xffff0...allegedly the
883 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
884 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
885 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
888 * Zero memory and verify that it is clear
890 bzero(sc->mem_start, memsize);
892 for (i = 0; i < memsize; ++i)
893 if (sc->mem_start[i]) {
894 device_printf(dev, "failed to clear shared memory "
895 "at %llx - check configuration\n",
896 (unsigned long long)kvtop(sc->mem_start + i));
903 * Probe and vendor-specific initialization routine for SIC boards
906 ed_probe_SIC(device_t dev, int port_rid, int flags)
908 struct ed_softc *sc = device_get_softc(dev);
912 u_long conf_maddr, conf_msize;
915 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);
919 sc->asic_offset = ED_SIC_ASIC_OFFSET;
920 sc->nic_offset = ED_SIC_NIC_OFFSET;
922 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
923 &conf_maddr, &conf_msize);
929 memsize = conf_msize;
931 error = ed_alloc_memory(dev, 0, memsize);
935 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
936 sc->mem_size = memsize;
938 /* Reset card to force it into a known state. */
939 ed_asic_outb(sc, 0, 0x00);
943 * Here we check the card ROM, if the checksum passes, and the
944 * type code and ethernet address check out, then we know we have
947 ed_asic_outb(sc, 0, 0x81);
950 sum = sc->mem_start[6];
951 for (i = 0; i < ETHER_ADDR_LEN; i++) {
952 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]);
955 device_printf(dev, "ed_probe_sic: got address %6D\n",
956 sc->arpcom.ac_enaddr, ":");
961 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] |
962 sc->arpcom.ac_enaddr[2]) == 0) {
966 sc->vendor = ED_VENDOR_SIC;
967 sc->type_str = "SIC";
972 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
974 ed_asic_outb(sc, 0, 0x80);
978 * Now zero memory and verify that it is clear
980 bzero(sc->mem_start, sc->mem_size);
982 for (i = 0; i < sc->mem_size; i++) {
983 if (sc->mem_start[i]) {
984 device_printf(dev, "failed to clear shared memory "
985 "at %llx - check configuration\n",
986 (long long)kvtop(sc->mem_start + i));
993 sc->mem_end = sc->mem_start + sc->mem_size;
996 * allocate one xmit buffer if < 16k, two buffers otherwise
998 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
1003 sc->tx_page_start = 0;
1005 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;
1006 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;
1008 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1014 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1017 ed_probe_Novell_generic(device_t dev, int flags)
1019 struct ed_softc *sc = device_get_softc(dev);
1021 u_char romdata[16], tmp;
1022 static char test_pattern[32] = "THIS is A memory TEST pattern";
1023 char test_buffer[32];
1025 /* XXX - do Novell-specific probe here */
1027 /* Reset the board */
1028 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1029 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
1032 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
1035 * I don't know if this is necessary; probably cruft leftover from
1036 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1037 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
1038 * non-invasive...but some boards don't seem to reset and I don't have
1039 * complete documentation on what the 'right' thing to do is...so we
1040 * do the invasive thing for now. Yuck.]
1042 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
1046 * This is needed because some NE clones apparently don't reset the
1047 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1048 * - this makes the probe invasive! ...Done against my better
1051 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1055 /* Make sure that we really have an 8390 based board */
1056 if (!ed_probe_generic8390(sc))
1059 sc->vendor = ED_VENDOR_NOVELL;
1061 sc->cr_proto = ED_CR_RD2;
1064 * Test the ability to read and write to the NIC memory. This has the
1065 * side affect of determining if this is an NE1000 or an NE2000.
1069 * This prevents packets from being stored in the NIC memory when the
1070 * readmem routine turns on the start bit in the CR.
1072 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1074 /* Temporarily initialize DCR for byte operations */
1075 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1077 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1078 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1083 * Write a test pattern in byte mode. If this fails, then there
1084 * probably isn't any memory at 8k - which likely means that the board
1087 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1088 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1090 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1091 sc->type = ED_TYPE_NE1000;
1092 sc->type_str = "NE1000";
1095 /* neither an NE1000 nor a Linksys - try NE2000 */
1096 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1097 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1098 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1103 * Write a test pattern in word mode. If this also fails, then
1104 * we don't know what this board is.
1106 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1107 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1108 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1109 sc->type = ED_TYPE_NE2000;
1110 sc->type_str = "NE2000";
1117 /* 8k of memory plus an additional 8k if 16bit */
1118 memsize = 8192 + sc->isa16bit * 8192;
1120 #if 0 /* probably not useful - NE boards only come two ways */
1121 /* allow kernel config file overrides */
1122 if (isa_dev->id_msize)
1123 memsize = isa_dev->id_msize;
1126 sc->mem_size = memsize;
1128 /* NIC memory doesn't start at zero on an NE board */
1129 /* The start address is tied to the bus width */
1130 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1131 sc->mem_end = sc->mem_start + memsize;
1132 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1134 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1135 int x, i, mstart = 0, msize = 0;
1136 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1138 for (i = 0; i < ED_PAGE_SIZE; i++)
1141 /* Clear all the memory. */
1142 for (x = 1; x < 256; x++)
1143 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1145 /* Search for the start of RAM. */
1146 for (x = 1; x < 256; x++) {
1147 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1148 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1149 for (i = 0; i < ED_PAGE_SIZE; i++)
1151 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1152 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1153 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1154 mstart = x * ED_PAGE_SIZE;
1155 msize = ED_PAGE_SIZE;
1162 device_printf(dev, "Cannot find start of RAM.\n");
1165 /* Search for the start of RAM. */
1166 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1167 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1168 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1169 for (i = 0; i < ED_PAGE_SIZE; i++)
1171 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1172 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1173 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1174 msize += ED_PAGE_SIZE;
1184 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1187 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1189 sc->mem_size = msize;
1190 sc->mem_start = (caddr_t) mstart;
1191 sc->mem_end = (caddr_t) (msize + mstart);
1192 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1196 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1199 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1204 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1205 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1207 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1209 ed_pio_readmem(sc, 0, romdata, 16);
1210 for (n = 0; n < ETHER_ADDR_LEN; n++)
1211 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1213 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1214 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1215 sc->type_str = "Gateway AT";
1218 /* clear any pending interrupts that might have occurred above */
1219 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1225 ed_probe_Novell(device_t dev, int port_rid, int flags)
1227 struct ed_softc *sc = device_get_softc(dev);
1230 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1234 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1235 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1237 return ed_probe_Novell_generic(dev, flags);
1240 #define ED_HPP_TEST_SIZE 16
1243 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1244 * (HP Part nos: 27247B and 27252A).
1246 * The card has an asic wrapper around a DS8390 core. The asic handles
1247 * host accesses and offers both standard register IO and memory mapped
1248 * IO. Memory mapped I/O allows better performance at the expense of greater
1249 * chance of an incompatibility with existing ISA cards.
1251 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1252 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1253 * don't allow 32 bit accesses; these are indicated by a bit in the software
1254 * ID register (see if_edreg.h).
1256 * Other caveats are: we should read the MAC address only when the card
1259 * For more information; please consult the CRYNWR packet driver.
1261 * The AUI port is turned on using the "link2" option on the ifconfig
1265 ed_probe_HP_pclanp(device_t dev, int port_rid, int flags)
1267 struct ed_softc *sc = device_get_softc(dev);
1269 int n; /* temp var */
1270 int memsize; /* mem on board */
1271 u_char checksum; /* checksum of board address */
1272 u_char irq; /* board configured IRQ */
1273 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1274 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1275 u_long conf_maddr, conf_msize, conf_irq, junk;
1277 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1281 /* Fill in basic information */
1282 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1283 sc->nic_offset = ED_HPP_NIC_OFFSET;
1285 sc->chip_type = ED_CHIP_TYPE_DP8390;
1286 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1289 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1292 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1293 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1294 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1295 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1299 * Read the MAC address and verify checksum on the address.
1302 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1303 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1304 checksum += (sc->arpcom.ac_enaddr[n] =
1305 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1307 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1309 if (checksum != 0xFF)
1313 * Verify that the software model number is 0.
1316 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1317 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1318 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1322 * Read in and save the current options configured on card.
1325 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1327 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1328 ED_HPP_OPTION_CHIP_RESET |
1329 ED_HPP_OPTION_ENABLE_IRQ);
1332 * Reset the chip. This requires writing to the option register
1333 * so take care to preserve the other bits.
1336 ed_asic_outw(sc, ED_HPP_OPTION,
1337 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1338 ED_HPP_OPTION_CHIP_RESET)));
1340 DELAY(5000); /* wait for chip reset to complete */
1342 ed_asic_outw(sc, ED_HPP_OPTION,
1343 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1344 ED_HPP_OPTION_CHIP_RESET |
1345 ED_HPP_OPTION_ENABLE_IRQ)));
1349 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1350 return ENXIO; /* reset did not complete */
1353 * Read out configuration information.
1356 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1358 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1361 * Check for impossible IRQ.
1364 if (irq >= NELEM(ed_hpp_intr_val))
1368 * If the kernel IRQ was specified with a '?' use the cards idea
1369 * of the IRQ. If the kernel IRQ was explicitly specified, it
1370 * should match that of the hardware.
1372 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1375 bus_set_resource(dev, SYS_RES_IRQ, 0,
1376 ed_hpp_intr_val[irq], 1);
1378 if (conf_irq != ed_hpp_intr_val[irq])
1383 * Fill in softconfig info.
1386 sc->vendor = ED_VENDOR_HP;
1387 sc->type = ED_TYPE_HP_PCLANPLUS;
1388 sc->type_str = "HP-PCLAN+";
1390 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1391 sc->mem_start = 0; /* we use offsets inside the card RAM */
1393 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1396 * The board has 32KB of memory. Is there a way to determine
1397 * this programmatically?
1403 * Check if memory mapping of the I/O registers possible.
1406 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1411 * determine the memory address from the board.
1414 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1415 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1418 * Check that the kernel specified start of memory and
1419 * hardware's idea of it match.
1421 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1422 &conf_maddr, &conf_msize);
1426 if (mem_addr != conf_maddr)
1429 error = ed_alloc_memory(dev, 0, memsize);
1433 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1437 * Fill in the rest of the soft config structure.
1441 * The transmit page index.
1444 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1446 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1452 * Memory description
1455 sc->mem_size = memsize;
1456 sc->mem_ring = sc->mem_start +
1457 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1458 sc->mem_end = sc->mem_start + sc->mem_size;
1461 * Receive area starts after the transmit area and
1462 * continues till the end of memory.
1465 sc->rec_page_start = sc->tx_page_start +
1466 (sc->txb_cnt * ED_TXBUF_SIZE);
1467 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1470 sc->cr_proto = 0; /* value works */
1473 * Set the wrap registers for string I/O reads.
1476 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1477 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1478 ((sc->rec_page_start / ED_PAGE_SIZE) |
1479 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1482 * Reset the register page to normal operation.
1485 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1488 * Verify that we can read/write from adapter memory.
1489 * Create test pattern.
1492 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1494 test_pattern[n] = (n*n) ^ ~n;
1497 #undef ED_HPP_TEST_SIZE
1500 * Check that the memory is accessible thru the I/O ports.
1501 * Write out the contents of "test_pattern", read back
1502 * into "test_buffer" and compare the two for any
1506 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1508 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1509 sizeof(test_pattern));
1510 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1511 test_buffer, sizeof(test_pattern));
1513 if (bcmp(test_pattern, test_buffer,
1514 sizeof(test_pattern)))
1523 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1527 ed_hpp_set_physical_link(struct ed_softc *sc)
1529 struct ifnet *ifp = &sc->arpcom.ac_if;
1532 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1533 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1535 if (ifp->if_flags & IFF_ALTPHYS) {
1541 lan_page |= ED_HPP_LAN_AUI;
1543 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1544 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1550 * Use the ThinLan interface
1553 lan_page &= ~ED_HPP_LAN_AUI;
1555 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1556 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1561 * Wait for the lan card to re-initialize itself
1564 DELAY(150000); /* wait 150 ms */
1567 * Restore normal pages.
1570 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1575 * Allocate a port resource with the given resource id.
1578 ed_alloc_port(device_t dev, int rid, int size)
1580 struct ed_softc *sc = device_get_softc(dev);
1581 struct resource *res;
1583 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1584 0ul, ~0ul, size, RF_ACTIVE);
1588 sc->port_used = size;
1596 * Allocate a memory resource with the given resource id.
1599 ed_alloc_memory(device_t dev, int rid, int size)
1601 struct ed_softc *sc = device_get_softc(dev);
1602 struct resource *res;
1604 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1605 0ul, ~0ul, size, RF_ACTIVE);
1609 sc->mem_used = size;
1617 * Allocate an irq resource with the given resource id.
1620 ed_alloc_irq(device_t dev, int rid, int flags)
1622 struct ed_softc *sc = device_get_softc(dev);
1623 struct resource *res;
1625 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1626 (RF_ACTIVE | flags));
1637 * Release all resources
1640 ed_release_resources(device_t dev)
1642 struct ed_softc *sc = device_get_softc(dev);
1645 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1646 sc->port_rid, sc->port_res);
1647 bus_release_resource(dev, SYS_RES_IOPORT,
1648 sc->port_rid, sc->port_res);
1652 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1653 sc->mem_rid, sc->mem_res);
1654 bus_release_resource(dev, SYS_RES_MEMORY,
1655 sc->mem_rid, sc->mem_res);
1659 bus_deactivate_resource(dev, SYS_RES_IRQ,
1660 sc->irq_rid, sc->irq_res);
1661 bus_release_resource(dev, SYS_RES_IRQ,
1662 sc->irq_rid, sc->irq_res);
1668 * Install interface into kernel networking data structures
1671 ed_attach(device_t dev)
1673 struct ed_softc *sc = device_get_softc(dev);
1674 struct ifnet *ifp = &sc->arpcom.ac_if;
1676 callout_init(&sc->ed_timer);
1678 * Set interface to stopped condition (reset)
1683 * Initialize ifnet structure
1686 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1687 ifp->if_mtu = ETHERMTU;
1688 ifp->if_start = ed_start;
1689 ifp->if_ioctl = ed_ioctl;
1690 ifp->if_watchdog = ed_watchdog;
1691 ifp->if_init = ed_init;
1692 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
1693 ifq_set_ready(&ifp->if_snd);
1694 ifp->if_linkmib = &sc->mibdata;
1695 ifp->if_linkmiblen = sizeof sc->mibdata;
1696 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1698 * XXX - should do a better job.
1700 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1701 sc->mibdata.dot3StatsEtherChipSet =
1702 DOT3CHIPSET(dot3VendorWesternDigital,
1703 dot3ChipSetWesternDigital83C790);
1705 sc->mibdata.dot3StatsEtherChipSet =
1706 DOT3CHIPSET(dot3VendorNational,
1707 dot3ChipSetNational8390);
1708 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1711 * Set default state for ALTPHYS flag (used to disable the
1712 * tranceiver for AUI operation), based on compile-time
1715 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
1716 ifp->if_flags |= IFF_ALTPHYS;
1719 * Attach the interface
1721 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
1723 /* device attach does transition from UNCONFIGURED to IDLE state */
1725 if (sc->type_str && (*sc->type_str != 0))
1726 kprintf("type %s ", sc->type_str);
1728 kprintf("type unknown (0x%x) ", sc->type);
1730 if (sc->vendor == ED_VENDOR_HP)
1731 kprintf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1732 "16-bit" : "32-bit",
1733 sc->hpp_mem_start ? "memory mapped" : "regular");
1735 kprintf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1737 kprintf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1738 (sc->vendor == ED_VENDOR_HP)) &&
1739 (ifp->if_flags & IFF_ALTPHYS)) ? " transceiver disabled" : "");
1748 ed_reset(struct ifnet *ifp)
1750 struct ed_softc *sc = ifp->if_softc;
1760 * Stop interface and re-initialize.
1769 * Take interface offline.
1772 ed_stop(struct ed_softc *sc)
1776 #ifndef ED_NO_MIIBUS
1777 callout_stop(&sc->ed_timer);
1782 * Stop everything on the interface, and select page 0 registers.
1784 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1787 * Wait for interface to enter stopped state, but limit # of checks to
1788 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1789 * just in case it's an old one.
1791 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1792 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1796 * Device timeout/watchdog routine. Entered if the device neglects to
1797 * generate an interrupt after a transmit has been started on it.
1800 ed_watchdog(struct ifnet *ifp)
1802 struct ed_softc *sc = ifp->if_softc;
1806 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
1812 #ifndef ED_NO_MIIBUS
1816 struct ed_softc *sc = arg;
1817 struct mii_data *mii;
1820 ifp = &sc->arpcom.ac_if;
1821 lwkt_serialize_enter(ifp->if_serializer);
1828 if (sc->miibus != NULL) {
1829 mii = device_get_softc(sc->miibus);
1833 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
1834 lwkt_serialize_exit(ifp->if_serializer);
1839 * Initialize device.
1844 struct ed_softc *sc = xsc;
1845 struct ifnet *ifp = &sc->arpcom.ac_if;
1856 * Initialize the NIC in the exact order outlined in the NS manual.
1857 * This init procedure is "mandatory"...don't change what or when
1861 /* reset transmitter flags */
1867 sc->txb_next_tx = 0;
1869 /* This variable is used below - don't move this assignment */
1870 sc->next_packet = sc->rec_page_start + 1;
1873 * Set interface for page 0, Remote DMA complete, Stopped
1875 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1880 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1881 * order=80x86, word-wide DMA xfers,
1883 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1887 * Same as above, but byte-wide DMA xfers
1889 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1893 * Clear Remote Byte Count Registers
1895 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1896 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1899 * For the moment, don't store incoming packets in memory.
1901 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1904 * Place NIC in internal loopback mode
1906 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1909 * Initialize transmit/receive (ring-buffer) Page Start
1911 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1912 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1913 /* Set lower bits of byte addressable framing to 0 */
1914 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1915 ed_nic_outb(sc, 0x09, 0);
1918 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1920 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1921 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1924 * Clear all interrupts. A '1' in each bit position clears the
1925 * corresponding flag.
1927 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1930 * Enable the following interrupts: receive/transmit complete,
1931 * receive/transmit error, and Receiver OverWrite.
1933 * Counter overflow and Remote DMA complete are *not* enabled.
1935 ed_nic_outb(sc, ED_P0_IMR,
1936 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1939 * Program Command Register for page 1
1941 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1944 * Copy out our station address
1946 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1947 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1950 * Set Current Page pointer to next_packet (initialized above)
1952 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1955 * Program Receiver Configuration Register and multicast filter. CR is
1956 * set to page 0 on return.
1961 * Take interface out of loopback
1963 ed_nic_outb(sc, ED_P0_TCR, 0);
1966 * If this is a 3Com board, the tranceiver must be software enabled
1967 * (there is no settable hardware default).
1969 if (sc->vendor == ED_VENDOR_3COM) {
1970 if (ifp->if_flags & IFF_ALTPHYS) {
1971 ed_asic_outb(sc, ED_3COM_CR, 0);
1973 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1977 #ifndef ED_NO_MIIBUS
1978 if (sc->miibus != NULL) {
1979 struct mii_data *mii;
1980 mii = device_get_softc(sc->miibus);
1985 * Set 'running' flag, and clear output active flag.
1987 ifp->if_flags |= IFF_RUNNING;
1988 ifp->if_flags &= ~IFF_OACTIVE;
1991 * ...and attempt to start output
1995 #ifndef ED_NO_MIIBUS
1996 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
2003 * This routine actually starts the transmission on the interface
2005 static __inline void
2006 ed_xmit(struct ed_softc *sc)
2008 struct ifnet *ifp = (struct ifnet *)sc;
2013 len = sc->txb_len[sc->txb_next_tx];
2016 * Set NIC for page 0 register access
2018 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2021 * Set TX buffer start page
2023 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
2024 sc->txb_next_tx * ED_TXBUF_SIZE);
2029 ed_nic_outb(sc, ED_P0_TBCR0, len);
2030 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
2033 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2035 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2039 * Point to next transmit buffer slot and wrap if necessary.
2042 if (sc->txb_next_tx == sc->txb_cnt)
2043 sc->txb_next_tx = 0;
2046 * Set a timer just in case we never hear from the board again
2052 * Start output on interface.
2053 * We make two assumptions here:
2054 * 1) that the current priority is set to splimp _before_ this code
2055 * is called *and* is returned to the appropriate priority after
2057 * 2) that the IFF_OACTIVE flag is checked before this code is called
2058 * (i.e. that the output part of the interface is idle)
2061 ed_start(struct ifnet *ifp)
2063 struct ed_softc *sc = ifp->if_softc;
2064 struct mbuf *m0, *m;
2069 kprintf("ed_start(%p) GONE\n",ifp);
2070 ifq_purge(&ifp->if_snd);
2076 * First, see if there are buffered packets and an idle transmitter -
2077 * should never happen at this point.
2079 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2080 kprintf("ed: packets buffered, but transmitter idle\n");
2085 * See if there is room to put another packet in the buffer.
2087 if (sc->txb_inuse == sc->txb_cnt) {
2090 * No room. Indicate this to the outside world and exit.
2092 ifp->if_flags |= IFF_OACTIVE;
2095 m = ifq_dequeue(&ifp->if_snd, NULL);
2099 * We are using the !OACTIVE flag to indicate to the outside
2100 * world that we can accept an additional packet rather than
2101 * that the transmitter is _actually_ active. Indeed, the
2102 * transmitter may be active, but if we haven't filled all the
2103 * buffers with data then we still want to accept more.
2105 ifp->if_flags &= ~IFF_OACTIVE;
2110 * Copy the mbuf chain into the transmit buffer
2115 /* txb_new points to next open buffer slot */
2116 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2118 if (sc->mem_shared) {
2121 * Special case setup for 16 bit boards...
2124 switch (sc->vendor) {
2127 * For 16bit 3Com boards (which have 16k of
2128 * memory), we have the xmit buffers in a
2129 * different page of memory ('page 0') - so
2132 case ED_VENDOR_3COM:
2133 ed_asic_outb(sc, ED_3COM_GACFR,
2134 ED_3COM_GACFR_RSEL);
2138 * Enable 16bit access to shared memory on
2141 case ED_VENDOR_WD_SMC:
2142 ed_asic_outb(sc, ED_WD_LAAR,
2143 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2144 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2145 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2150 for (len = 0; m != 0; m = m->m_next) {
2151 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2157 * Restore previous shared memory access
2160 switch (sc->vendor) {
2161 case ED_VENDOR_3COM:
2162 ed_asic_outb(sc, ED_3COM_GACFR,
2163 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2165 case ED_VENDOR_WD_SMC:
2166 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2167 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2169 ed_asic_outb(sc, ED_WD_LAAR,
2170 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2175 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2182 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2187 * Point to next buffer slot and wrap if necessary.
2190 if (sc->txb_new == sc->txb_cnt)
2193 if (sc->xmit_busy == 0)
2201 * Loop back to the top to possibly buffer more packets
2207 * Ethernet interface receiver interrupt.
2209 static __inline void
2210 ed_rint(struct ed_softc *sc)
2212 struct ifnet *ifp = &sc->arpcom.ac_if;
2215 struct ed_ring packet_hdr;
2222 * Set NIC to page 1 registers to get 'current' pointer
2224 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2227 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2228 * i.e. it points to where new data has been buffered. The 'CURR'
2229 * (current) register points to the logical end of the ring-buffer -
2230 * i.e. it points to where additional new data will be added. We loop
2231 * here until the logical beginning equals the logical end (or in
2232 * other words, until the ring-buffer is empty).
2234 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2236 /* get pointer to this buffer's header structure */
2237 packet_ptr = sc->mem_ring +
2238 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2241 * The byte count includes a 4 byte header that was added by
2245 packet_hdr = *(struct ed_ring *) packet_ptr;
2247 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2248 sizeof(packet_hdr));
2249 len = packet_hdr.count;
2250 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2251 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2253 * Length is a wild value. There's a good chance that
2254 * this was caused by the NIC being old and buggy.
2255 * The bug is that the length low byte is duplicated in
2256 * the high byte. Try to recalculate the length based on
2257 * the pointer to the next packet.
2260 * NOTE: sc->next_packet is pointing at the current packet.
2262 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2263 if (packet_hdr.next_packet >= sc->next_packet) {
2264 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2266 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2267 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2270 * because buffers are aligned on 256-byte boundary,
2271 * the length computed above is off by 256 in almost
2272 * all cases. Fix it...
2276 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2277 + sizeof(struct ed_ring)))
2278 sc->mibdata.dot3StatsFrameTooLongs++;
2281 * Be fairly liberal about what we allow as a "reasonable" length
2282 * so that a [crufty] packet will make it to BPF (and can thus
2283 * be analyzed). Note that all that is really important is that
2284 * we have a length that will fit into one mbuf cluster or less;
2285 * the upper layer protocols can then figure out the length from
2286 * their own length field(s).
2287 * But make sure that we have at least a full ethernet header
2288 * or we would be unable to call ether_input() later.
2290 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2291 (len <= MCLBYTES) &&
2292 (packet_hdr.next_packet >= sc->rec_page_start) &&
2293 (packet_hdr.next_packet < sc->rec_page_stop)) {
2297 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2298 len - sizeof(struct ed_ring));
2302 * Really BAD. The ring pointers are corrupted.
2305 "%s: NIC memory corrupt - invalid packet length %d\n",
2306 ifp->if_xname, len);
2313 * Update next packet pointer
2315 sc->next_packet = packet_hdr.next_packet;
2318 * Update NIC boundry pointer - being careful to keep it one
2319 * buffer behind. (as recommended by NS databook)
2321 boundry = sc->next_packet - 1;
2322 if (boundry < sc->rec_page_start)
2323 boundry = sc->rec_page_stop - 1;
2326 * Set NIC to page 0 registers to update boundry register
2328 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2330 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2333 * Set NIC to page 1 registers before looping to top (prepare
2334 * to get 'CURR' current pointer)
2336 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2341 * Ethernet interface interrupt processor
2346 struct ed_softc *sc = (struct ed_softc*) arg;
2347 struct ifnet *ifp = (struct ifnet *)sc;
2354 * Set NIC to page 0 registers
2356 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2359 * loop until there are no more new interrupts. When the card
2360 * goes away, the hardware will read back 0xff. Looking at
2361 * the interrupts, it would appear that 0xff is impossible,
2362 * or at least extremely unlikely.
2364 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
2367 * reset all the bits that we are 'acknowledging' by writing a
2368 * '1' to each bit position that was set (writing a '1'
2371 ed_nic_outb(sc, ED_P0_ISR, isr);
2374 * XXX workaround for AX88190
2375 * We limit this to 5000 iterations. At 1us per inb/outb,
2376 * this translates to about 15ms, which should be plenty
2377 * of time, and also gives protection in the card eject
2380 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2381 count = 5000; /* 15ms */
2382 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2383 ed_nic_outb(sc, ED_P0_ISR,0);
2384 ed_nic_outb(sc, ED_P0_ISR,isr);
2391 * Handle transmitter interrupts. Handle these first because
2392 * the receiver will reset the board under some conditions.
2394 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2395 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2398 * Check for transmit error. If a TX completed with an
2399 * error, we end up throwing the packet away. Really
2400 * the only error that is possible is excessive
2401 * collisions, and in this case it is best to allow
2402 * the automatic mechanisms of TCP to backoff the
2403 * flow. Of course, with UDP we're screwed, but this
2404 * is expected when a network is heavily loaded.
2406 ed_nic_inb(sc, ED_P0_TSR);
2407 if (isr & ED_ISR_TXE) {
2411 * Excessive collisions (16)
2413 tsr = ed_nic_inb(sc, ED_P0_TSR);
2414 if ((tsr & ED_TSR_ABT)
2415 && (collisions == 0)) {
2418 * When collisions total 16, the
2419 * P0_NCR will indicate 0, and the
2423 sc->mibdata.dot3StatsExcessiveCollisions++;
2424 sc->mibdata.dot3StatsCollFrequencies[15]++;
2426 if (tsr & ED_TSR_OWC)
2427 sc->mibdata.dot3StatsLateCollisions++;
2428 if (tsr & ED_TSR_CDH)
2429 sc->mibdata.dot3StatsSQETestErrors++;
2430 if (tsr & ED_TSR_CRS)
2431 sc->mibdata.dot3StatsCarrierSenseErrors++;
2432 if (tsr & ED_TSR_FU)
2433 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2436 * update output errors counter
2442 * Update total number of successfully
2443 * transmitted packets.
2449 * reset tx busy and output active flags
2452 ifp->if_flags &= ~IFF_OACTIVE;
2455 * clear watchdog timer
2460 * Add in total number of collisions on last
2463 ifp->if_collisions += collisions;
2464 switch(collisions) {
2469 sc->mibdata.dot3StatsSingleCollisionFrames++;
2470 sc->mibdata.dot3StatsCollFrequencies[0]++;
2473 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2475 dot3StatsCollFrequencies[collisions-1]
2481 * Decrement buffer in-use count if not zero (can only
2482 * be zero if a transmitter interrupt occured while
2483 * not actually transmitting). If data is ready to
2484 * transmit, start it transmitting, otherwise defer
2485 * until after handling receiver
2487 if (sc->txb_inuse && --sc->txb_inuse)
2492 * Handle receiver interrupts
2494 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2497 * Overwrite warning. In order to make sure that a
2498 * lockup of the local DMA hasn't occurred, we reset
2499 * and re-init the NIC. The NSC manual suggests only a
2500 * partial reset/re-init is necessary - but some chips
2501 * seem to want more. The DMA lockup has been seen
2502 * only with early rev chips - Methinks this bug was
2503 * fixed in later revs. -DG
2505 if (isr & ED_ISR_OVW) {
2509 "%s: warning - receiver ring buffer overrun\n",
2514 * Stop/reset/re-init NIC
2520 * Receiver Error. One or more of: CRC error,
2521 * frame alignment error FIFO overrun, or
2524 if (isr & ED_ISR_RXE) {
2526 rsr = ed_nic_inb(sc, ED_P0_RSR);
2527 if (rsr & ED_RSR_CRC)
2528 sc->mibdata.dot3StatsFCSErrors++;
2529 if (rsr & ED_RSR_FAE)
2530 sc->mibdata.dot3StatsAlignmentErrors++;
2531 if (rsr & ED_RSR_FO)
2532 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2535 if_printf("receive error %x\n",
2536 ed_nic_inb(sc, ED_P0_RSR));
2541 * Go get the packet(s) XXX - Doing this on an
2542 * error is dubious because there shouldn't be
2543 * any data to get (we've configured the
2544 * interface to not accept packets with
2549 * Enable 16bit access to shared memory first
2553 (sc->vendor == ED_VENDOR_WD_SMC)) {
2555 ed_asic_outb(sc, ED_WD_LAAR,
2556 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2557 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2558 ed_asic_outb(sc, ED_WD_MSR,
2564 /* disable 16bit access */
2566 (sc->vendor == ED_VENDOR_WD_SMC)) {
2568 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2569 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2571 ed_asic_outb(sc, ED_WD_LAAR,
2572 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2578 * If it looks like the transmitter can take more data,
2579 * attempt to start output on the interface. This is done
2580 * after handling the receiver to give the receiver priority.
2582 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2586 * return NIC CR to standard state: page 0, remote DMA
2587 * complete, start (toggling the TXP bit off, even if was just
2588 * set in the transmit routine, is *okay* - it is 'edge'
2589 * triggered from low to high)
2591 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2594 * If the Network Talley Counters overflow, read them to reset
2595 * them. It appears that old 8390's won't clear the ISR flag
2596 * otherwise - resulting in an infinite loop.
2598 if (isr & ED_ISR_CNT) {
2599 ed_nic_inb(sc, ED_P0_CNTR0);
2600 ed_nic_inb(sc, ED_P0_CNTR1);
2601 ed_nic_inb(sc, ED_P0_CNTR2);
2607 * Process an ioctl request. This code needs some work - it looks
2611 ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2613 struct ed_softc *sc = ifp->if_softc;
2614 #ifndef ED_NO_MIIBUS
2615 struct ifreq *ifr = (struct ifreq *)data;
2616 struct mii_data *mii;
2622 if (sc == NULL || sc->gone) {
2623 ifp->if_flags &= ~IFF_RUNNING;
2632 * If the interface is marked up and stopped, then start it.
2633 * If it is marked down and running, then stop it.
2635 if (ifp->if_flags & IFF_UP) {
2636 if ((ifp->if_flags & IFF_RUNNING) == 0)
2639 if (ifp->if_flags & IFF_RUNNING) {
2641 ifp->if_flags &= ~IFF_RUNNING;
2646 * Promiscuous flag may have changed, so reprogram the RCR.
2651 * An unfortunate hack to provide the (required) software
2652 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2653 * disables the tranceiver if set.
2655 if (sc->vendor == ED_VENDOR_3COM) {
2656 if (ifp->if_flags & IFF_ALTPHYS) {
2657 ed_asic_outb(sc, ED_3COM_CR, 0);
2659 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2661 } else if (sc->vendor == ED_VENDOR_HP)
2662 ed_hpp_set_physical_link(sc);
2668 * Multicast list has changed; set the hardware filter
2675 #ifndef ED_NO_MIIBUS
2678 if (sc->miibus == NULL) {
2682 mii = device_get_softc(sc->miibus);
2683 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2688 error = ether_ioctl(ifp, command, data);
2698 * Given a source and destination address, copy 'amount' of a packet from
2699 * the ring buffer into a linear destination buffer. Takes into account
2702 static __inline char *
2703 ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount)
2707 /* does copy wrap to lower addr in ring buffer? */
2708 if (src + amount > sc->mem_end) {
2709 tmp_amount = sc->mem_end - src;
2711 /* copy amount up to end of NIC memory */
2713 bcopy(src, dst, tmp_amount);
2715 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2717 amount -= tmp_amount;
2722 bcopy(src, dst, amount);
2724 ed_pio_readmem(sc, (int)src, dst, amount);
2726 return (src + amount);
2730 * Retreive packet from shared memory and send to the next level up via
2734 ed_get_packet(struct ed_softc *sc, char *buf, u_short len)
2736 struct ifnet *ifp = &sc->arpcom.ac_if;
2737 struct ether_header *eh;
2741 * Allocate a header mbuf.
2742 * We always put the received packet in a single buffer -
2743 * either with just an mbuf header or in a cluster attached
2744 * to the header. The +2 is to compensate for the alignment
2747 m = m_getl(len + 2, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
2750 m->m_pkthdr.rcvif = ifp;
2751 m->m_pkthdr.len = m->m_len = len;
2754 * The +2 is to longword align the start of the real packet.
2755 * This is important for NFS.
2758 eh = mtod(m, struct ether_header *);
2761 * Get packet, including link layer address, from interface.
2763 ed_ring_copy(sc, buf, (char *)eh, len);
2765 m->m_pkthdr.len = m->m_len = len;
2767 ifp->if_input(ifp, m);
2771 * Supporting routines
2775 * Given a NIC memory source address and a host memory destination
2776 * address, copy 'amount' from NIC to host using Programmed I/O.
2777 * The 'amount' is rounded up to a word - okay as long as mbufs
2779 * This routine is currently Novell-specific.
2782 ed_pio_readmem(struct ed_softc *sc, int src, u_char *dst, u_short amount)
2784 /* HP PC Lan+ cards need special handling */
2785 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2786 ed_hpp_readmem(sc, src, dst, amount);
2790 /* Regular Novell cards */
2791 /* select page 0 registers */
2792 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2794 /* round up to a word */
2798 /* set up DMA byte count */
2799 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2800 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2802 /* set up source address in NIC mem */
2803 ed_nic_outb(sc, ED_P0_RSAR0, src);
2804 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2806 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2809 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2811 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2816 * Stripped down routine for writing a linear buffer to NIC memory.
2817 * Only used in the probe routine to test the memory. 'len' must
2821 ed_pio_writemem(struct ed_softc *sc, char *src, u_short dst, u_short len)
2823 int maxwait = 200; /* about 240us */
2825 /* select page 0 registers */
2826 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2828 /* reset remote DMA complete flag */
2829 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2831 /* set up DMA byte count */
2832 ed_nic_outb(sc, ED_P0_RBCR0, len);
2833 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2835 /* set up destination address in NIC mem */
2836 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2837 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2839 /* set remote DMA write */
2840 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2843 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2845 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2849 * Wait for remote DMA complete. This is necessary because on the
2850 * transmit side, data is handled internally by the NIC in bursts and
2851 * we can't start another remote DMA until this one completes. Not
2852 * waiting causes really bad things to happen - like the NIC
2853 * irrecoverably jamming the ISA bus.
2855 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2859 * Write an mbuf chain to the destination NIC memory address using
2863 ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
2865 struct ifnet *ifp = (struct ifnet *)sc;
2866 u_short total_len, dma_len;
2868 int maxwait = 200; /* about 240us */
2870 /* HP PC Lan+ cards need special handling */
2871 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2872 return ed_hpp_write_mbufs(sc, m, dst);
2875 /* Regular Novell cards */
2876 /* First, count up the total number of bytes to copy */
2877 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2878 total_len += mp->m_len;
2880 dma_len = total_len;
2881 if (sc->isa16bit && (dma_len & 1))
2884 /* select page 0 registers */
2885 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2887 /* reset remote DMA complete flag */
2888 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2890 /* set up DMA byte count */
2891 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2892 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2894 /* set up destination address in NIC mem */
2895 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2896 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2898 /* set remote DMA write */
2899 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2902 * Transfer the mbuf chain to the NIC memory.
2903 * 16-bit cards require that data be transferred as words, and only words.
2904 * So that case requires some extra code to patch over odd-length mbufs.
2907 if (!sc->isa16bit) {
2908 /* NE1000s are easy */
2911 ed_asic_outsb(sc, ED_NOVELL_DATA,
2912 m->m_data, m->m_len);
2917 /* NE2000s are a pain */
2927 data = mtod(m, caddr_t);
2928 /* finish the last word */
2930 savebyte[1] = *data;
2931 ed_asic_outw(sc, ED_NOVELL_DATA,
2932 *(u_short *)savebyte);
2937 /* output contiguous words */
2939 ed_asic_outsw(sc, ED_NOVELL_DATA,
2944 /* save last byte, if necessary */
2946 savebyte[0] = *data;
2952 /* spit last byte */
2954 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2959 * Wait for remote DMA complete. This is necessary because on the
2960 * transmit side, data is handled internally by the NIC in bursts and
2961 * we can't start another remote DMA until this one completes. Not
2962 * waiting causes really bad things to happen - like the NIC
2963 * irrecoverably jamming the ISA bus.
2965 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2968 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
2977 * Support routines to handle the HP PC Lan+ card.
2981 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2986 ed_hpp_readmem(struct ed_softc *sc, u_short src, u_char *dst, u_short amount)
2989 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2992 /* Program the source address in RAM */
2993 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
2996 * The HP PC Lan+ card supports word reads as well as
2997 * a memory mapped i/o port that is aliased to every
2998 * even address on the board.
3001 if (sc->hpp_mem_start) {
3003 /* Enable memory mapped access. */
3004 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3005 ~(ED_HPP_OPTION_MEM_DISABLE |
3006 ED_HPP_OPTION_BOOT_ROM_ENB));
3008 if (use_32bit_access && (amount > 3)) {
3009 u_int32_t *dl = (u_int32_t *) dst;
3010 volatile u_int32_t *const sl =
3011 (u_int32_t *) sc->hpp_mem_start;
3012 u_int32_t *const fence = dl + (amount >> 2);
3014 /* Copy out NIC data. We could probably write this
3015 as a `movsl'. The currently generated code is lousy.
3021 dst += (amount & ~3);
3026 /* Finish off any words left, as a series of short reads */
3028 u_short *d = (u_short *) dst;
3029 volatile u_short *const s =
3030 (u_short *) sc->hpp_mem_start;
3031 u_short *const fence = d + (amount >> 1);
3033 /* Copy out NIC data. */
3038 dst += (amount & ~1);
3043 * read in a byte; however we need to always read 16 bits
3044 * at a time or the hardware gets into a funny state
3048 /* need to read in a short and copy LSB */
3049 volatile u_short *const s =
3050 (volatile u_short *) sc->hpp_mem_start;
3055 /* Restore Boot ROM access. */
3057 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3061 /* Read in data using the I/O port */
3062 if (use_32bit_access && (amount > 3)) {
3063 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3064 dst += (amount & ~3);
3068 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3069 dst += (amount & ~1);
3072 if (amount == 1) { /* read in a short and keep the LSB */
3073 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3079 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3081 * Only used in the probe routine to test the memory. 'len' must
3085 ed_hpp_writemem(struct ed_softc *sc, u_char *src, u_short dst, u_short len)
3087 /* reset remote DMA complete flag */
3088 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3090 /* program the write address in RAM */
3091 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3093 if (sc->hpp_mem_start) {
3094 u_short *s = (u_short *) src;
3095 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3096 u_short *const fence = s + (len >> 1);
3099 * Enable memory mapped access.
3102 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3103 ~(ED_HPP_OPTION_MEM_DISABLE |
3104 ED_HPP_OPTION_BOOT_ROM_ENB));
3107 * Copy to NIC memory.
3114 * Restore Boot ROM access.
3117 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3120 /* write data using I/O writes */
3121 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3126 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3127 * outsw() or via the memory mapped interface to the same register.
3128 * Writes have to be in word units; byte accesses won't work and may cause
3129 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3134 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3139 volatile u_short * const d =
3140 (volatile u_short *) sc->hpp_mem_start;
3141 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3143 /* select page 0 registers */
3144 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3146 /* reset remote DMA complete flag */
3147 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3149 /* program the write address in RAM */
3150 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3152 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3153 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3154 ~(ED_HPP_OPTION_MEM_DISABLE |
3155 ED_HPP_OPTION_BOOT_ROM_ENB));
3160 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3162 total_len += (len = m->m_len);
3164 caddr_t data = mtod(m, caddr_t);
3165 /* finish the last word of the previous mbuf */
3167 savebyte[1] = *data;
3168 *d = *((u_short *) savebyte);
3169 data++; len--; wantbyte = 0;
3171 /* output contiguous words */
3172 if ((len > 3) && (use_32bit_accesses)) {
3173 volatile u_int32_t *const dl =
3174 (volatile u_int32_t *) d;
3175 u_int32_t *sl = (u_int32_t *) data;
3176 u_int32_t *fence = sl + (len >> 2);
3184 /* finish off remain 16 bit writes */
3186 u_short *s = (u_short *) data;
3187 u_short *fence = s + (len >> 1);
3195 /* save last byte if needed */
3196 if ((wantbyte = (len == 1)) != 0)
3197 savebyte[0] = *data;
3199 m = m->m_next; /* to next mbuf */
3201 if (wantbyte) /* write last byte */
3202 *d = *((u_short *) savebyte);
3204 /* use programmed I/O */
3206 total_len += (len = m->m_len);
3208 caddr_t data = mtod(m, caddr_t);
3209 /* finish the last word of the previous mbuf */
3211 savebyte[1] = *data;
3212 ed_asic_outw(sc, ED_HPP_PAGE_4,
3213 *((u_short *)savebyte));
3218 /* output contiguous words */
3219 if ((len > 3) && use_32bit_accesses) {
3220 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3225 /* finish off remaining 16 bit accesses */
3227 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3232 if ((wantbyte = (len == 1)) != 0)
3233 savebyte[0] = *data;
3238 if (wantbyte) /* spit last byte */
3239 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3243 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3244 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3249 #ifndef ED_NO_MIIBUS
3251 * MII bus support routines.
3254 ed_miibus_readreg(device_t dev, int phy, int reg)
3256 struct ed_softc *sc = device_get_softc(dev);
3266 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3267 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3268 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3269 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3270 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3272 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3273 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3274 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3278 return (failed ? 0 : val);
3282 ed_miibus_writereg(device_t dev, int phy, int reg, int data)
3284 struct ed_softc *sc = device_get_softc(dev);
3293 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3294 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3295 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3296 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3297 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3298 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3299 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3300 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3306 ed_ifmedia_upd(struct ifnet *ifp)
3308 struct ed_softc *sc;
3309 struct mii_data *mii;
3312 if (sc->gone || sc->miibus == NULL)
3315 mii = device_get_softc(sc->miibus);
3316 return mii_mediachg(mii);
3320 ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3322 struct ed_softc *sc;
3323 struct mii_data *mii;
3326 if (sc->gone || sc->miibus == NULL)
3329 mii = device_get_softc(sc->miibus);
3331 ifmr->ifm_active = mii->mii_media_active;
3332 ifmr->ifm_status = mii->mii_media_status;
3336 ed_child_detached(device_t dev, device_t child)
3338 struct ed_softc *sc;
3340 sc = device_get_softc(dev);
3341 if (child == sc->miibus)
3347 ed_setrcr(struct ed_softc *sc)
3349 struct ifnet *ifp = (struct ifnet *)sc;
3353 /* Bit 6 in AX88190 RCR register must be set. */
3354 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3359 /* set page 1 registers */
3360 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3362 if (ifp->if_flags & IFF_PROMISC) {
3365 * Reconfigure the multicast filter.
3367 for (i = 0; i < 8; i++)
3368 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3371 * And turn on promiscuous mode. Also enable reception of
3372 * runts and packets with CRC & alignment errors.
3374 /* Set page 0 registers */
3375 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3377 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3378 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3380 /* set up multicast addresses and filter modes */
3381 if (ifp->if_flags & IFF_MULTICAST) {
3384 if (ifp->if_flags & IFF_ALLMULTI) {
3385 mcaf[0] = 0xffffffff;
3386 mcaf[1] = 0xffffffff;
3388 ds_getmcaf(sc, mcaf);
3391 * Set multicast filter on chip.
3393 for (i = 0; i < 8; i++)
3394 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3396 /* Set page 0 registers */
3397 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3399 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3403 * Initialize multicast address hashing registers to
3404 * not accept multicasts.
3406 for (i = 0; i < 8; ++i)
3407 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3409 /* Set page 0 registers */
3410 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3412 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3419 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3423 * Compute crc for ethernet address
3426 ds_mchash(const uint8_t *addr)
3428 #define ED_POLYNOMIAL 0x04c11db6
3429 uint32_t crc = 0xffffffff;
3430 int carry, idx, bit;
3433 for (idx = 6; --idx >= 0;) {
3434 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) {
3435 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
3438 crc = (crc ^ ED_POLYNOMIAL) | carry;
3446 * Compute the multicast address filter from the
3447 * list of multicast addresses we need to listen to.
3450 ds_getmcaf(struct ed_softc *sc, u_int32_t *mcaf)
3453 u_char *af = (u_char *) mcaf;
3454 struct ifmultiaddr *ifma;
3459 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) {
3460 if (ifma->ifma_addr->sa_family != AF_LINK)
3462 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3464 af[index >> 3] |= 1 << (index & 7);