2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
167 typedef int (*mptable_iter_func)(void *, const void *, int);
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int madt_probe_test;
222 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
224 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225 int current_postcode;
227 /** XXX FIXME: what system files declare these??? */
228 extern struct region_descriptor r_gdt, r_idt;
230 int mp_naps; /* # of Applications processors */
232 static int mp_nbusses; /* # of busses */
233 int mp_napics; /* # of IO APICs */
235 static vm_offset_t cpu_apic_address;
237 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
238 u_int32_t *io_apic_versions;
242 u_int32_t cpu_apic_versions[MAXCPU];
244 extern int64_t tsc_offsets[];
246 extern u_long ebda_addr;
249 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
256 int cpu_num_to_apic_id[NAPICID];
258 int io_num_to_apic_id[NAPICID];
260 int apic_id_to_logical[NAPICID];
262 /* AP uses this during bootstrap. Do not staticize. */
266 /* Hotwire a 0->4MB V==P mapping */
267 extern pt_entry_t *KPTphys;
270 * SMP page table page. Setup by locore to point to a page table
271 * page from which we allocate per-cpu privatespace areas io_apics,
275 #define IO_MAPPING_START_INDEX \
276 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
278 extern pt_entry_t *SMPpt;
279 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
281 struct pcb stoppcbs[MAXCPU];
283 static basetable_entry basetable_entry_types[] =
285 {0, 20, "Processor"},
293 * Local data and functions.
296 static u_int boot_address;
297 static u_int base_memory;
298 static int mp_finish;
300 static void mp_enable(u_int boot_addr);
302 static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
304 static int mptable_probe(void);
305 static int mptable_check(vm_paddr_t);
306 static int mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(u_int, int);
308 static void mptable_pass1(struct mptable_pos *);
309 static int mptable_pass2(struct mptable_pos *);
310 static void mptable_default(int type);
311 static void mptable_fix(void);
312 static int mptable_map(struct mptable_pos *, vm_paddr_t);
313 static void mptable_unmap(struct mptable_pos *);
314 static void mptable_lapic_enumerate(struct mptable_pos *);
315 static void mptable_lapic_default(void);
318 static void setup_apic_irq_mapping(void);
319 static int apic_int_is_bus_type(int intr, int bus_type);
321 static int start_all_aps(u_int boot_addr);
322 static void install_ap_tramp(u_int boot_addr);
323 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
324 static void lapic_init(vm_offset_t);
326 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
327 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
328 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
331 * Calculate usable address in base memory for AP trampoline code.
334 mp_bootaddress(u_int basemem)
336 POSTCODE(MP_BOOTADDRESS_POST);
338 base_memory = basemem;
340 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
341 if ((base_memory - boot_address) < bootMP_size)
342 boot_address -= 4096; /* not enough, lower by 4k */
349 * Look for an Intel MP spec table (ie, SMP capable hardware).
358 * Make sure our SMPpt[] page table is big enough to hold all the
361 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
363 POSTCODE(MP_PROBE_POST);
365 /* see if EBDA exists */
366 if (ebda_addr != 0) {
367 /* search first 1K of EBDA */
368 target = (u_int32_t)ebda_addr;
369 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
372 /* last 1K of base memory, effective 'top of base' passed in */
373 target = (u_int32_t)(base_memory - 0x400);
374 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
378 /* search the BIOS */
379 target = (u_int32_t)BIOS_BASE;
380 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
387 struct mptable_check_cbarg {
393 mptable_check_callback(void *xarg, const void *pos, int type)
395 const struct PROCENTRY *ent;
396 struct mptable_check_cbarg *arg = xarg;
402 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
406 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
407 if (arg->found_bsp) {
408 kprintf("more than one BSP in base MP table\n");
417 mptable_check(vm_paddr_t mpfps_paddr)
419 struct mptable_pos mpt;
420 struct mptable_check_cbarg arg;
424 if (mpfps_paddr == 0)
427 error = mptable_map(&mpt, mpfps_paddr);
431 if (mpt.mp_fps->mpfb1 != 0)
439 if (cth->apic_address == 0)
442 bzero(&arg, sizeof(arg));
443 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
445 if (arg.cpu_count == 0) {
446 kprintf("MP table contains no processor entries\n");
448 } else if (!arg.found_bsp) {
449 kprintf("MP table does not contains BSP entry\n");
459 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
461 int count, total_size;
462 const void *position;
464 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
465 total_size = cth->base_table_length - sizeof(struct MPCTH);
466 position = (const uint8_t *)cth + sizeof(struct MPCTH);
467 count = cth->entry_count;
472 KKASSERT(total_size >= 0);
473 if (total_size == 0) {
474 kprintf("invalid base MP table, "
475 "entry count and length mismatch\n");
479 type = *(const uint8_t *)position;
481 case 0: /* processor_entry */
482 case 1: /* bus_entry */
483 case 2: /* io_apic_entry */
484 case 3: /* int_entry */
485 case 4: /* int_entry */
488 kprintf("unknown base MP table entry type %d\n", type);
492 if (total_size < basetable_entry_types[type].length) {
493 kprintf("invalid base MP table length, "
494 "does not contain all entries\n");
497 total_size -= basetable_entry_types[type].length;
499 error = func(arg, position, type);
503 position = (const uint8_t *)position +
504 basetable_entry_types[type].length;
511 * Startup the SMP processors.
516 POSTCODE(MP_START_POST);
517 mp_enable(boot_address);
522 * Print various information about the SMP system hardware and setup.
529 POSTCODE(MP_ANNOUNCE_POST);
531 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
532 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
533 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
534 kprintf(", at 0x%08x\n", cpu_apic_address);
535 for (x = 1; x <= mp_naps; ++x) {
536 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
537 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
538 kprintf(", at 0x%08x\n", cpu_apic_address);
542 for (x = 0; x < mp_napics; ++x) {
543 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
544 kprintf(", version: 0x%08x", io_apic_versions[x]);
545 kprintf(", at 0x%08x\n", io_apic_address[x]);
548 kprintf(" Warning: APIC I/O disabled\n");
553 * AP cpu's call this to sync up protected mode.
555 * WARNING! We must ensure that the cpu is sufficiently initialized to
556 * be able to use to the FP for our optimized bzero/bcopy code before
557 * we enter more mainstream C code.
559 * WARNING! %fs is not set up on entry. This routine sets up %fs.
565 int x, myid = bootAP;
567 struct mdglobaldata *md;
568 struct privatespace *ps;
570 ps = &CPU_prvspace[myid];
572 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
573 gdt_segs[GPROC0_SEL].ssd_base =
574 (int) &ps->mdglobaldata.gd_common_tss;
575 ps->mdglobaldata.mi.gd_prvspace = ps;
577 for (x = 0; x < NGDT; x++) {
578 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
581 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
582 r_gdt.rd_base = (int) &gdt[myid * NGDT];
583 lgdt(&r_gdt); /* does magic intra-segment return */
588 mdcpu->gd_currentldt = _default_ldt;
590 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
591 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
593 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
595 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
596 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
597 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
598 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
599 md->gd_common_tssd = *md->gd_tss_gdt;
603 * Set to a known state:
604 * Set by mpboot.s: CR0_PG, CR0_PE
605 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
608 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
610 pmap_set_opt(); /* PSE/4MB pages, etc */
612 /* set up CPU registers and state */
615 /* set up FPU state on the AP */
616 npxinit(__INITIAL_NPXCW__);
618 /* set up SSE registers */
622 /*******************************************************************
623 * local functions and data
627 * start the SMP system
630 mp_enable(u_int boot_addr)
637 vm_paddr_t mpfps_paddr;
639 POSTCODE(MP_ENABLE_POST);
641 if (madt_probe_test) {
644 mpfps_paddr = mptable_probe();
645 if (mptable_check(mpfps_paddr))
650 struct mptable_pos mpt;
652 mptable_map(&mpt, mpfps_paddr);
654 mptable_lapic_enumerate(&mpt);
657 * We can safely map physical memory into SMPpt after
658 * mptable_pass1() completes.
663 * Examine the MP table for needed info
665 x = mptable_pass2(&mpt);
670 * Can't process default configs till the
671 * CPU APIC is pmapped
676 /* Post scan cleanup */
679 vm_paddr_t madt_paddr;
680 vm_offset_t lapic_addr;
683 madt_paddr = madt_probe();
685 panic("mp_enable: madt_probe failed\n");
687 lapic_addr = madt_pass1(madt_paddr);
689 panic("mp_enable: no local apic (madt)!\n");
691 lapic_init(lapic_addr);
693 bsp_apic_id = APIC_ID(lapic.id);
694 if (madt_pass2(madt_paddr, bsp_apic_id))
695 panic("mp_enable: madt_pass2 failed\n");
700 setup_apic_irq_mapping();
702 /* fill the LOGICAL io_apic_versions table */
703 for (apic = 0; apic < mp_napics; ++apic) {
704 ux = io_apic_read(apic, IOAPIC_VER);
705 io_apic_versions[apic] = ux;
706 io_apic_set_id(apic, IO_TO_ID(apic));
709 /* program each IO APIC in the system */
710 for (apic = 0; apic < mp_napics; ++apic)
711 if (io_apic_setup(apic) < 0)
712 panic("IO APIC setup failure");
717 * These are required for SMP operation
720 /* install a 'Spurious INTerrupt' vector */
721 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
722 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
724 /* install an inter-CPU IPI for TLB invalidation */
725 setidt(XINVLTLB_OFFSET, Xinvltlb,
726 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
728 /* install an inter-CPU IPI for IPIQ messaging */
729 setidt(XIPIQ_OFFSET, Xipiq,
730 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
732 /* install a timer vector */
733 setidt(XTIMER_OFFSET, Xtimer,
734 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
736 /* install an inter-CPU IPI for CPU stop/restart */
737 setidt(XCPUSTOP_OFFSET, Xcpustop,
738 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
740 /* start each Application Processor */
741 start_all_aps(boot_addr);
746 * look for the MP spec signature
749 /* string defined by the Intel MP Spec as identifying the MP table */
750 #define MP_SIG 0x5f504d5f /* _MP_ */
751 #define NEXT(X) ((X) += 4)
753 mptable_search_sig(u_int32_t target, int count)
759 KKASSERT(target != 0);
761 map_size = count * sizeof(u_int32_t);
762 addr = pmap_mapdev((vm_paddr_t)target, map_size);
765 for (x = 0; x < count; NEXT(x)) {
766 if (addr[x] == MP_SIG) {
767 /* make array index a byte index */
768 ret = target + (x * sizeof(u_int32_t));
773 pmap_unmapdev((vm_offset_t)addr, map_size);
778 typedef struct BUSDATA {
780 enum busTypes bus_type;
783 typedef struct INTDATA {
793 typedef struct BUSTYPENAME {
798 static bus_type_name bus_type_table[] =
804 {UNKNOWN_BUSTYPE, "---"},
807 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"},
809 {UNKNOWN_BUSTYPE, "---"},
810 {UNKNOWN_BUSTYPE, "---"},
811 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
818 {UNKNOWN_BUSTYPE, "---"}
820 /* from MP spec v1.4, table 5-1 */
821 static int default_data[7][5] =
823 /* nbus, id0, type0, id1, type1 */
824 {1, 0, ISA, 255, 255},
825 {1, 0, EISA, 255, 255},
826 {1, 0, EISA, 255, 255},
827 {1, 0, MCA, 255, 255},
829 {2, 0, EISA, 1, PCI},
837 static bus_datum *bus_data;
839 /* the IO INT data, one entry per possible APIC INTerrupt */
840 static io_int *io_apic_ints;
845 static int processor_entry (const struct PROCENTRY *entry, int cpu);
847 static int bus_entry (bus_entry_ptr entry, int bus);
848 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
849 static int int_entry (int_entry_ptr entry, int intr);
851 static int lookup_bus_type (char *name);
855 * 1st pass on motherboard's Intel MP specification table.
864 mptable_pass1(struct mptable_pos *mpt)
876 POSTCODE(MPTABLE_PASS1_POST);
879 KKASSERT(fps != NULL);
882 /* clear various tables */
883 for (x = 0; x < NAPICID; ++x) {
884 io_apic_address[x] = ~0; /* IO APIC address table */
894 /* check for use of 'default' configuration */
895 if (fps->mpfb1 != 0) {
897 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
898 mp_nbusses = default_data[fps->mpfb1 - 1][0];
905 KKASSERT(cth != NULL);
907 /* walk the table, recording info of interest */
908 totalSize = cth->base_table_length - sizeof(struct MPCTH);
909 position = (u_char *) cth + sizeof(struct MPCTH);
910 count = cth->entry_count;
913 switch (type = *(u_char *) position) {
914 case 0: /* processor_entry */
916 case 1: /* bus_entry */
921 case 2: /* io_apic_entry */
923 if (((io_apic_entry_ptr)position)->apic_flags
924 & IOAPICENTRY_FLAG_EN)
925 io_apic_address[mp_napics++] =
926 (vm_offset_t)((io_apic_entry_ptr)
927 position)->apic_address;
930 case 3: /* int_entry */
935 case 4: /* int_entry */
938 panic("mpfps Base Table HOSED!");
942 totalSize -= basetable_entry_types[type].length;
943 position = (uint8_t *)position +
944 basetable_entry_types[type].length;
951 * 2nd pass on motherboard's Intel MP specification table.
954 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
955 * IO_TO_ID(N), logical IO to APIC ID table
960 mptable_pass2(struct mptable_pos *mpt)
972 POSTCODE(MPTABLE_PASS2_POST);
975 KKASSERT(fps != NULL);
978 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
980 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
981 M_DEVBUF, M_WAITOK | M_ZERO);
982 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
984 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
989 for (i = 0; i < mp_napics; i++) {
990 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
994 /* clear various tables */
995 for (x = 0; x < NAPICID; ++x) {
997 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
998 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1003 /* clear bus data table */
1004 for (x = 0; x < mp_nbusses; ++x)
1005 bus_data[x].bus_id = 0xff;
1007 /* clear IO APIC INT table */
1008 for (x = 0; x < (nintrs + 1); ++x) {
1009 io_apic_ints[x].int_type = 0xff;
1010 io_apic_ints[x].int_vector = 0xff;
1014 /* record whether PIC or virtual-wire mode */
1015 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
1017 /* check for use of 'default' configuration */
1018 if (fps->mpfb1 != 0)
1019 return fps->mpfb1; /* return default configuration type */
1022 KKASSERT(cth != NULL);
1024 /* walk the table, recording info of interest */
1025 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1026 position = (u_char *) cth + sizeof(struct MPCTH);
1027 count = cth->entry_count;
1028 apic = bus = intr = 0;
1031 switch (type = *(u_char *) position) {
1036 if (bus_entry(position, bus))
1042 if (io_apic_entry(position, apic))
1048 if (int_entry(position, intr))
1053 /* int_entry(position); */
1056 panic("mpfps Base Table HOSED!");
1060 totalSize -= basetable_entry_types[type].length;
1061 position = (uint8_t *)position + basetable_entry_types[type].length;
1064 /* report fact that its NOT a default configuration */
1069 * Check if we should perform a hyperthreading "fix-up" to
1070 * enumerate any logical CPU's that aren't already listed
1073 * XXX: We assume that all of the physical CPUs in the
1074 * system have the same number of logical CPUs.
1076 * XXX: We assume that APIC ID's are allocated such that
1077 * the APIC ID's for a physical processor are aligned
1078 * with the number of logical CPU's in the processor.
1081 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1083 int i, id, lcpus_max, logical_cpus;
1085 if ((cpu_feature & CPUID_HTT) == 0)
1088 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1092 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1094 * INSTRUCTION SET REFERENCE, A-M (#253666)
1095 * Page 3-181, Table 3-20
1096 * "The nearest power-of-2 integer that is not smaller
1097 * than EBX[23:16] is the number of unique initial APIC
1098 * IDs reserved for addressing different logical
1099 * processors in a physical package."
1101 for (i = 0; ; ++i) {
1102 if ((1 << i) >= lcpus_max) {
1109 KKASSERT(cpu_count != 0);
1110 if (cpu_count == lcpus_max) {
1111 /* We have nothing to fix */
1113 } else if (cpu_count == 1) {
1114 /* XXX this may be incorrect */
1115 logical_cpus = lcpus_max;
1117 int cur, prev, dist;
1120 * Calculate the distances between two nearest
1121 * APIC IDs. If all such distances are same,
1122 * then it is the number of missing cpus that
1123 * we are going to fill later.
1125 dist = cur = prev = -1;
1126 for (id = 0; id < MAXCPU; ++id) {
1127 if ((id_mask & 1 << id) == 0)
1132 int new_dist = cur - prev;
1138 * Make sure that all distances
1139 * between two nearest APIC IDs
1142 if (dist != new_dist)
1150 /* Must be power of 2 */
1151 if (dist & (dist - 1))
1154 /* Can't exceed CPU package capacity */
1155 if (dist > lcpus_max)
1156 logical_cpus = lcpus_max;
1158 logical_cpus = dist;
1162 * For each APIC ID of a CPU that is set in the mask,
1163 * scan the other candidate APIC ID's for this
1164 * physical processor. If any of those ID's are
1165 * already in the table, then kill the fixup.
1167 for (id = 0; id < MAXCPU; id++) {
1168 if ((id_mask & 1 << id) == 0)
1170 /* First, make sure we are on a logical_cpus boundary. */
1171 if (id % logical_cpus != 0)
1173 for (i = id + 1; i < id + logical_cpus; i++)
1174 if ((id_mask & 1 << i) != 0)
1177 return logical_cpus;
1181 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1185 vm_size_t cth_mapsz = 0;
1187 bzero(mpt, sizeof(*mpt));
1189 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1190 if (fps->pap != 0) {
1192 * Map configuration table header to get
1193 * the base table size
1195 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1196 cth_mapsz = cth->base_table_length;
1197 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1199 if (cth_mapsz < sizeof(*cth)) {
1200 kprintf("invalid base MP table length %d\n",
1202 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1207 * Map the base table
1209 cth = pmap_mapdev(fps->pap, cth_mapsz);
1214 mpt->mp_cth_mapsz = cth_mapsz;
1220 mptable_unmap(struct mptable_pos *mpt)
1222 if (mpt->mp_cth != NULL) {
1223 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1225 mpt->mp_cth_mapsz = 0;
1227 if (mpt->mp_fps != NULL) {
1228 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1236 assign_apic_irq(int apic, int intpin, int irq)
1240 if (int_to_apicintpin[irq].ioapic != -1)
1241 panic("assign_apic_irq: inconsistent table");
1243 int_to_apicintpin[irq].ioapic = apic;
1244 int_to_apicintpin[irq].int_pin = intpin;
1245 int_to_apicintpin[irq].apic_address = ioapic[apic];
1246 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1248 for (x = 0; x < nintrs; x++) {
1249 if ((io_apic_ints[x].int_type == 0 ||
1250 io_apic_ints[x].int_type == 3) &&
1251 io_apic_ints[x].int_vector == 0xff &&
1252 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1253 io_apic_ints[x].dst_apic_int == intpin)
1254 io_apic_ints[x].int_vector = irq;
1259 revoke_apic_irq(int irq)
1265 if (int_to_apicintpin[irq].ioapic == -1)
1266 panic("revoke_apic_irq: inconsistent table");
1268 oldapic = int_to_apicintpin[irq].ioapic;
1269 oldintpin = int_to_apicintpin[irq].int_pin;
1271 int_to_apicintpin[irq].ioapic = -1;
1272 int_to_apicintpin[irq].int_pin = 0;
1273 int_to_apicintpin[irq].apic_address = NULL;
1274 int_to_apicintpin[irq].redirindex = 0;
1276 for (x = 0; x < nintrs; x++) {
1277 if ((io_apic_ints[x].int_type == 0 ||
1278 io_apic_ints[x].int_type == 3) &&
1279 io_apic_ints[x].int_vector != 0xff &&
1280 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1281 io_apic_ints[x].dst_apic_int == oldintpin)
1282 io_apic_ints[x].int_vector = 0xff;
1290 allocate_apic_irq(int intr)
1296 if (io_apic_ints[intr].int_vector != 0xff)
1297 return; /* Interrupt handler already assigned */
1299 if (io_apic_ints[intr].int_type != 0 &&
1300 (io_apic_ints[intr].int_type != 3 ||
1301 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1302 io_apic_ints[intr].dst_apic_int == 0)))
1303 return; /* Not INT or ExtInt on != (0, 0) */
1306 while (irq < APIC_INTMAPSIZE &&
1307 int_to_apicintpin[irq].ioapic != -1)
1310 if (irq >= APIC_INTMAPSIZE)
1311 return; /* No free interrupt handlers */
1313 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1314 intpin = io_apic_ints[intr].dst_apic_int;
1316 assign_apic_irq(apic, intpin, irq);
1317 io_apic_setup_intpin(apic, intpin);
1322 swap_apic_id(int apic, int oldid, int newid)
1329 return; /* Nothing to do */
1331 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1332 apic, oldid, newid);
1334 /* Swap physical APIC IDs in interrupt entries */
1335 for (x = 0; x < nintrs; x++) {
1336 if (io_apic_ints[x].dst_apic_id == oldid)
1337 io_apic_ints[x].dst_apic_id = newid;
1338 else if (io_apic_ints[x].dst_apic_id == newid)
1339 io_apic_ints[x].dst_apic_id = oldid;
1342 /* Swap physical APIC IDs in IO_TO_ID mappings */
1343 for (oapic = 0; oapic < mp_napics; oapic++)
1344 if (IO_TO_ID(oapic) == newid)
1347 if (oapic < mp_napics) {
1348 kprintf("Changing APIC ID for IO APIC #%d from "
1349 "%d to %d in MP table\n",
1350 oapic, newid, oldid);
1351 IO_TO_ID(oapic) = oldid;
1353 IO_TO_ID(apic) = newid;
1358 fix_id_to_io_mapping(void)
1362 for (x = 0; x < NAPICID; x++)
1365 for (x = 0; x <= mp_naps; x++)
1366 if (CPU_TO_ID(x) < NAPICID)
1367 ID_TO_IO(CPU_TO_ID(x)) = x;
1369 for (x = 0; x < mp_napics; x++)
1370 if (IO_TO_ID(x) < NAPICID)
1371 ID_TO_IO(IO_TO_ID(x)) = x;
1376 first_free_apic_id(void)
1380 for (freeid = 0; freeid < NAPICID; freeid++) {
1381 for (x = 0; x <= mp_naps; x++)
1382 if (CPU_TO_ID(x) == freeid)
1386 for (x = 0; x < mp_napics; x++)
1387 if (IO_TO_ID(x) == freeid)
1398 io_apic_id_acceptable(int apic, int id)
1400 int cpu; /* Logical CPU number */
1401 int oapic; /* Logical IO APIC number for other IO APIC */
1404 return 0; /* Out of range */
1406 for (cpu = 0; cpu <= mp_naps; cpu++)
1407 if (CPU_TO_ID(cpu) == id)
1408 return 0; /* Conflict with CPU */
1410 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1411 if (IO_TO_ID(oapic) == id)
1412 return 0; /* Conflict with other APIC */
1414 return 1; /* ID is acceptable for IO APIC */
1419 io_apic_find_int_entry(int apic, int pin)
1423 /* search each of the possible INTerrupt sources */
1424 for (x = 0; x < nintrs; ++x) {
1425 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1426 (pin == io_apic_ints[x].dst_apic_int))
1427 return (&io_apic_ints[x]);
1435 * parse an Intel MP specification table
1443 int apic; /* IO APIC unit number */
1444 int freeid; /* Free physical APIC ID */
1445 int physid; /* Current physical IO APIC ID */
1447 int bus_0 = 0; /* Stop GCC warning */
1448 int bus_pci = 0; /* Stop GCC warning */
1452 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1453 * did it wrong. The MP spec says that when more than 1 PCI bus
1454 * exists the BIOS must begin with bus entries for the PCI bus and use
1455 * actual PCI bus numbering. This implies that when only 1 PCI bus
1456 * exists the BIOS can choose to ignore this ordering, and indeed many
1457 * MP motherboards do ignore it. This causes a problem when the PCI
1458 * sub-system makes requests of the MP sub-system based on PCI bus
1459 * numbers. So here we look for the situation and renumber the
1460 * busses and associated INTs in an effort to "make it right".
1463 /* find bus 0, PCI bus, count the number of PCI busses */
1464 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1465 if (bus_data[x].bus_id == 0) {
1468 if (bus_data[x].bus_type == PCI) {
1474 * bus_0 == slot of bus with ID of 0
1475 * bus_pci == slot of last PCI bus encountered
1478 /* check the 1 PCI bus case for sanity */
1479 /* if it is number 0 all is well */
1480 if (num_pci_bus == 1 &&
1481 bus_data[bus_pci].bus_id != 0) {
1483 /* mis-numbered, swap with whichever bus uses slot 0 */
1485 /* swap the bus entry types */
1486 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1487 bus_data[bus_0].bus_type = PCI;
1489 /* swap each relavant INTerrupt entry */
1490 id = bus_data[bus_pci].bus_id;
1491 for (x = 0; x < nintrs; ++x) {
1492 if (io_apic_ints[x].src_bus_id == id) {
1493 io_apic_ints[x].src_bus_id = 0;
1495 else if (io_apic_ints[x].src_bus_id == 0) {
1496 io_apic_ints[x].src_bus_id = id;
1501 /* Assign IO APIC IDs.
1503 * First try the existing ID. If a conflict is detected, try
1504 * the ID in the MP table. If a conflict is still detected, find
1507 * We cannot use the ID_TO_IO table before all conflicts has been
1508 * resolved and the table has been corrected.
1510 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1512 /* First try to use the value set by the BIOS */
1513 physid = io_apic_get_id(apic);
1514 if (io_apic_id_acceptable(apic, physid)) {
1515 if (IO_TO_ID(apic) != physid)
1516 swap_apic_id(apic, IO_TO_ID(apic), physid);
1520 /* Then check if the value in the MP table is acceptable */
1521 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1524 /* Last resort, find a free APIC ID and use it */
1525 freeid = first_free_apic_id();
1526 if (freeid >= NAPICID)
1527 panic("No free physical APIC IDs found");
1529 if (io_apic_id_acceptable(apic, freeid)) {
1530 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1533 panic("Free physical APIC ID not usable");
1535 fix_id_to_io_mapping();
1537 /* detect and fix broken Compaq MP table */
1538 if (apic_int_type(0, 0) == -1) {
1539 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1540 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1541 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1542 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1543 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1544 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1546 } else if (apic_int_type(0, 0) == 0) {
1547 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1548 for (x = 0; x < nintrs; ++x)
1549 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1550 (0 == io_apic_ints[x].dst_apic_int)) {
1551 io_apic_ints[x].int_type = 3;
1552 io_apic_ints[x].int_vector = 0xff;
1558 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1559 * controllers universally come in pairs. If IRQ 14 is specified
1560 * as an ISA interrupt, then IRQ 15 had better be too.
1562 * [ Shuttle XPC / AMD Athlon X2 ]
1563 * The MPTable is missing an entry for IRQ 15. Note that the
1564 * ACPI table has an entry for both 14 and 15.
1566 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1567 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1568 io14 = io_apic_find_int_entry(0, 14);
1569 io_apic_ints[nintrs] = *io14;
1570 io_apic_ints[nintrs].src_bus_irq = 15;
1571 io_apic_ints[nintrs].dst_apic_int = 15;
1579 /* Assign low level interrupt handlers */
1581 setup_apic_irq_mapping(void)
1587 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1588 int_to_apicintpin[x].ioapic = -1;
1589 int_to_apicintpin[x].int_pin = 0;
1590 int_to_apicintpin[x].apic_address = NULL;
1591 int_to_apicintpin[x].redirindex = 0;
1594 /* First assign ISA/EISA interrupts */
1595 for (x = 0; x < nintrs; x++) {
1596 int_vector = io_apic_ints[x].src_bus_irq;
1597 if (int_vector < APIC_INTMAPSIZE &&
1598 io_apic_ints[x].int_vector == 0xff &&
1599 int_to_apicintpin[int_vector].ioapic == -1 &&
1600 (apic_int_is_bus_type(x, ISA) ||
1601 apic_int_is_bus_type(x, EISA)) &&
1602 io_apic_ints[x].int_type == 0) {
1603 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1604 io_apic_ints[x].dst_apic_int,
1609 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1610 for (x = 0; x < nintrs; x++) {
1611 if (io_apic_ints[x].dst_apic_int == 0 &&
1612 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1613 io_apic_ints[x].int_vector == 0xff &&
1614 int_to_apicintpin[0].ioapic == -1 &&
1615 io_apic_ints[x].int_type == 3) {
1616 assign_apic_irq(0, 0, 0);
1620 /* PCI interrupt assignment is deferred */
1626 mp_set_cpuids(int cpu_id, int apic_id)
1628 CPU_TO_ID(cpu_id) = apic_id;
1629 ID_TO_CPU(apic_id) = cpu_id;
1633 processor_entry(const struct PROCENTRY *entry, int cpu)
1637 /* check for usability */
1638 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1641 /* check for BSP flag */
1642 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1643 mp_set_cpuids(0, entry->apic_id);
1644 return 0; /* its already been counted */
1647 /* add another AP to list, if less than max number of CPUs */
1648 else if (cpu < MAXCPU) {
1649 mp_set_cpuids(cpu, entry->apic_id);
1659 bus_entry(bus_entry_ptr entry, int bus)
1664 /* encode the name into an index */
1665 for (x = 0; x < 6; ++x) {
1666 if ((c = entry->bus_type[x]) == ' ')
1672 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1673 panic("unknown bus type: '%s'", name);
1675 bus_data[bus].bus_id = entry->bus_id;
1676 bus_data[bus].bus_type = x;
1682 io_apic_entry(io_apic_entry_ptr entry, int apic)
1684 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1687 IO_TO_ID(apic) = entry->apic_id;
1688 ID_TO_IO(entry->apic_id) = apic;
1696 lookup_bus_type(char *name)
1700 for (x = 0; x < MAX_BUSTYPE; ++x)
1701 if (strcmp(bus_type_table[x].name, name) == 0)
1702 return bus_type_table[x].type;
1704 return UNKNOWN_BUSTYPE;
1710 int_entry(int_entry_ptr entry, int intr)
1714 io_apic_ints[intr].int_type = entry->int_type;
1715 io_apic_ints[intr].int_flags = entry->int_flags;
1716 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1717 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1718 if (entry->dst_apic_id == 255) {
1719 /* This signal goes to all IO APICS. Select an IO APIC
1720 with sufficient number of interrupt pins */
1721 for (apic = 0; apic < mp_napics; apic++)
1722 if (((io_apic_read(apic, IOAPIC_VER) &
1723 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1724 entry->dst_apic_int)
1726 if (apic < mp_napics)
1727 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1729 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1731 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1732 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1738 apic_int_is_bus_type(int intr, int bus_type)
1742 for (bus = 0; bus < mp_nbusses; ++bus)
1743 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1744 && ((int) bus_data[bus].bus_type == bus_type))
1751 * Given a traditional ISA INT mask, return an APIC mask.
1754 isa_apic_mask(u_int isa_mask)
1759 #if defined(SKIP_IRQ15_REDIRECT)
1760 if (isa_mask == (1 << 15)) {
1761 kprintf("skipping ISA IRQ15 redirect\n");
1764 #endif /* SKIP_IRQ15_REDIRECT */
1766 isa_irq = ffs(isa_mask); /* find its bit position */
1767 if (isa_irq == 0) /* doesn't exist */
1769 --isa_irq; /* make it zero based */
1771 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1775 return (1 << apic_pin); /* convert pin# to a mask */
1779 * Determine which APIC pin an ISA/EISA INT is attached to.
1781 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1782 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1783 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1784 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1786 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1788 isa_apic_irq(int isa_irq)
1792 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1793 if (INTTYPE(intr) == 0) { /* standard INT */
1794 if (SRCBUSIRQ(intr) == isa_irq) {
1795 if (apic_int_is_bus_type(intr, ISA) ||
1796 apic_int_is_bus_type(intr, EISA)) {
1797 if (INTIRQ(intr) == 0xff)
1798 return -1; /* unassigned */
1799 return INTIRQ(intr); /* found */
1804 return -1; /* NOT found */
1809 * Determine which APIC pin a PCI INT is attached to.
1811 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1812 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1813 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1815 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1819 --pciInt; /* zero based */
1821 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1822 if ((INTTYPE(intr) == 0) /* standard INT */
1823 && (SRCBUSID(intr) == pciBus)
1824 && (SRCBUSDEVICE(intr) == pciDevice)
1825 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1826 if (apic_int_is_bus_type(intr, PCI)) {
1827 if (INTIRQ(intr) == 0xff)
1828 allocate_apic_irq(intr);
1829 if (INTIRQ(intr) == 0xff)
1830 return -1; /* unassigned */
1831 return INTIRQ(intr); /* exact match */
1836 return -1; /* NOT found */
1840 next_apic_irq(int irq)
1847 for (intr = 0; intr < nintrs; intr++) {
1848 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1850 bus = SRCBUSID(intr);
1851 bustype = apic_bus_type(bus);
1852 if (bustype != ISA &&
1858 if (intr >= nintrs) {
1861 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1862 if (INTTYPE(ointr) != 0)
1864 if (bus != SRCBUSID(ointr))
1866 if (bustype == PCI) {
1867 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1869 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1872 if (bustype == ISA || bustype == EISA) {
1873 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1876 if (INTPIN(intr) == INTPIN(ointr))
1880 if (ointr >= nintrs) {
1883 return INTIRQ(ointr);
1898 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1901 * Exactly what this means is unclear at this point. It is a solution
1902 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1903 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1904 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1908 undirect_isa_irq(int rirq)
1912 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1913 /** FIXME: tickle the MB redirector chip */
1917 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1924 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1927 undirect_pci_irq(int rirq)
1931 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1933 /** FIXME: tickle the MB redirector chip */
1937 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1947 * given a bus ID, return:
1948 * the bus type if found
1952 apic_bus_type(int id)
1956 for (x = 0; x < mp_nbusses; ++x)
1957 if (bus_data[x].bus_id == id)
1958 return bus_data[x].bus_type;
1964 * given a LOGICAL APIC# and pin#, return:
1965 * the associated src bus ID if found
1969 apic_src_bus_id(int apic, int pin)
1973 /* search each of the possible INTerrupt sources */
1974 for (x = 0; x < nintrs; ++x)
1975 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1976 (pin == io_apic_ints[x].dst_apic_int))
1977 return (io_apic_ints[x].src_bus_id);
1979 return -1; /* NOT found */
1983 * given a LOGICAL APIC# and pin#, return:
1984 * the associated src bus IRQ if found
1988 apic_src_bus_irq(int apic, int pin)
1992 for (x = 0; x < nintrs; x++)
1993 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1994 (pin == io_apic_ints[x].dst_apic_int))
1995 return (io_apic_ints[x].src_bus_irq);
1997 return -1; /* NOT found */
2002 * given a LOGICAL APIC# and pin#, return:
2003 * the associated INTerrupt type if found
2007 apic_int_type(int apic, int pin)
2011 /* search each of the possible INTerrupt sources */
2012 for (x = 0; x < nintrs; ++x) {
2013 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2014 (pin == io_apic_ints[x].dst_apic_int))
2015 return (io_apic_ints[x].int_type);
2017 return -1; /* NOT found */
2021 * Return the IRQ associated with an APIC pin
2024 apic_irq(int apic, int pin)
2029 for (x = 0; x < nintrs; ++x) {
2030 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2031 (pin == io_apic_ints[x].dst_apic_int)) {
2032 res = io_apic_ints[x].int_vector;
2035 if (apic != int_to_apicintpin[res].ioapic)
2036 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2037 if (pin != int_to_apicintpin[res].int_pin)
2038 panic("apic_irq inconsistent table (2)");
2047 * given a LOGICAL APIC# and pin#, return:
2048 * the associated trigger mode if found
2052 apic_trigger(int apic, int pin)
2056 /* search each of the possible INTerrupt sources */
2057 for (x = 0; x < nintrs; ++x)
2058 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2059 (pin == io_apic_ints[x].dst_apic_int))
2060 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2062 return -1; /* NOT found */
2067 * given a LOGICAL APIC# and pin#, return:
2068 * the associated 'active' level if found
2072 apic_polarity(int apic, int pin)
2076 /* search each of the possible INTerrupt sources */
2077 for (x = 0; x < nintrs; ++x)
2078 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2079 (pin == io_apic_ints[x].dst_apic_int))
2080 return (io_apic_ints[x].int_flags & 0x03);
2082 return -1; /* NOT found */
2088 * set data according to MP defaults
2089 * FIXME: probably not complete yet...
2092 mptable_default(int type)
2094 #if defined(APIC_IO)
2097 #endif /* APIC_IO */
2100 kprintf(" MP default config type: %d\n", type);
2103 kprintf(" bus: ISA, APIC: 82489DX\n");
2106 kprintf(" bus: EISA, APIC: 82489DX\n");
2109 kprintf(" bus: EISA, APIC: 82489DX\n");
2112 kprintf(" bus: MCA, APIC: 82489DX\n");
2115 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2118 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2121 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2124 kprintf(" future type\n");
2130 #if defined(APIC_IO)
2131 /* one and only IO APIC */
2132 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2135 * sanity check, refer to MP spec section 3.6.6, last paragraph
2136 * necessary as some hardware isn't properly setting up the IO APIC
2138 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2139 if (io_apic_id != 2) {
2141 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2142 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2143 io_apic_set_id(0, 2);
2146 IO_TO_ID(0) = io_apic_id;
2147 ID_TO_IO(io_apic_id) = 0;
2148 #endif /* APIC_IO */
2150 /* fill out bus entries */
2160 bus_data[0].bus_id = default_data[type - 1][1];
2161 bus_data[0].bus_type = default_data[type - 1][2];
2162 bus_data[1].bus_id = default_data[type - 1][3];
2163 bus_data[1].bus_type = default_data[type - 1][4];
2167 /* case 4: case 7: MCA NOT supported */
2168 default: /* illegal/reserved */
2169 panic("BAD default MP config: %d", type);
2173 #if defined(APIC_IO)
2174 /* general cases from MP v1.4, table 5-2 */
2175 for (pin = 0; pin < 16; ++pin) {
2176 io_apic_ints[pin].int_type = 0;
2177 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2178 io_apic_ints[pin].src_bus_id = 0;
2179 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2180 io_apic_ints[pin].dst_apic_id = io_apic_id;
2181 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2184 /* special cases from MP v1.4, table 5-2 */
2186 io_apic_ints[2].int_type = 0xff; /* N/C */
2187 io_apic_ints[13].int_type = 0xff; /* N/C */
2188 #if !defined(APIC_MIXED_MODE)
2190 panic("sorry, can't support type 2 default yet");
2191 #endif /* APIC_MIXED_MODE */
2194 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2197 io_apic_ints[0].int_type = 0xff; /* N/C */
2199 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2200 #endif /* APIC_IO */
2204 * Map a physical memory address representing I/O into KVA. The I/O
2205 * block is assumed not to cross a page boundary.
2208 permanent_io_mapping(vm_paddr_t pa)
2214 KKASSERT(pa < 0x100000000LL);
2216 pgeflag = 0; /* not used for SMP yet */
2219 * If the requested physical address has already been incidently
2220 * mapped, just use the existing mapping. Otherwise create a new
2223 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2224 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2225 ((vm_offset_t)pa & PG_FRAME)) {
2229 if (i == SMPpt_alloc_index) {
2230 if (i == NPTEPG - 2) {
2231 panic("permanent_io_mapping: We ran out of space"
2234 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2235 ((vm_offset_t)pa & PG_FRAME));
2236 ++SMPpt_alloc_index;
2238 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2239 ((vm_offset_t)pa & PAGE_MASK);
2240 return ((void *)vaddr);
2244 * start each AP in our list
2247 start_all_aps(u_int boot_addr)
2251 u_char mpbiosreason;
2252 u_long mpbioswarmvec;
2253 struct mdglobaldata *gd;
2254 struct privatespace *ps;
2258 POSTCODE(START_ALL_APS_POST);
2260 /* Initialize BSP's local APIC */
2261 apic_initialize(TRUE);
2263 /* install the AP 1st level boot code */
2264 install_ap_tramp(boot_addr);
2267 /* save the current value of the warm-start vector */
2268 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2269 outb(CMOS_REG, BIOS_RESET);
2270 mpbiosreason = inb(CMOS_DATA);
2272 /* set up temporary P==V mapping for AP boot */
2273 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2274 kptbase = (uintptr_t)(void *)KPTphys;
2275 for (x = 0; x < NKPT; x++) {
2276 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2277 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2282 for (x = 1; x <= mp_naps; ++x) {
2284 /* This is a bit verbose, it will go away soon. */
2286 /* first page of AP's private space */
2287 pg = x * i386_btop(sizeof(struct privatespace));
2289 /* allocate new private data page(s) */
2290 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2291 MDGLOBALDATA_BASEALLOC_SIZE);
2292 /* wire it into the private page table page */
2293 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2294 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2295 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2297 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2299 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2300 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2301 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2302 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2304 /* allocate and set up an idle stack data page */
2305 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2306 for (i = 0; i < UPAGES; i++) {
2307 SMPpt[pg + 4 + i] = (pt_entry_t)
2308 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2311 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2312 bzero(gd, sizeof(*gd));
2313 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2315 /* prime data page for it to use */
2316 mi_gdinit(&gd->mi, x);
2318 gd->gd_CMAP1 = &SMPpt[pg + 0];
2319 gd->gd_CMAP2 = &SMPpt[pg + 1];
2320 gd->gd_CMAP3 = &SMPpt[pg + 2];
2321 gd->gd_PMAP1 = &SMPpt[pg + 3];
2322 gd->gd_CADDR1 = ps->CPAGE1;
2323 gd->gd_CADDR2 = ps->CPAGE2;
2324 gd->gd_CADDR3 = ps->CPAGE3;
2325 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2326 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2327 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2329 /* setup a vector to our boot code */
2330 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2331 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2332 outb(CMOS_REG, BIOS_RESET);
2333 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2336 * Setup the AP boot stack
2338 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2341 /* attempt to start the Application Processor */
2342 CHECK_INIT(99); /* setup checkpoints */
2343 if (!start_ap(gd, boot_addr)) {
2344 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2345 CHECK_PRINT("trace"); /* show checkpoints */
2346 /* better panic as the AP may be running loose */
2347 kprintf("panic y/n? [y] ");
2348 if (cngetc() != 'n')
2351 CHECK_PRINT("trace"); /* show checkpoints */
2353 /* record its version info */
2354 cpu_apic_versions[x] = cpu_apic_versions[0];
2357 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2360 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2361 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2364 ncpus2_shift = shift;
2365 ncpus2 = 1 << shift;
2366 ncpus2_mask = ncpus2 - 1;
2368 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2369 if ((1 << shift) < ncpus)
2371 ncpus_fit = 1 << shift;
2372 ncpus_fit_mask = ncpus_fit - 1;
2374 /* build our map of 'other' CPUs */
2375 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2376 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2377 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2379 /* fill in our (BSP) APIC version */
2380 cpu_apic_versions[0] = lapic.version;
2382 /* restore the warmstart vector */
2383 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2384 outb(CMOS_REG, BIOS_RESET);
2385 outb(CMOS_DATA, mpbiosreason);
2388 * NOTE! The idlestack for the BSP was setup by locore. Finish
2389 * up, clean out the P==V mapping we did earlier.
2391 for (x = 0; x < NKPT; x++)
2395 /* number of APs actually started */
2401 * load the 1st level AP boot code into base memory.
2404 /* targets for relocation */
2405 extern void bigJump(void);
2406 extern void bootCodeSeg(void);
2407 extern void bootDataSeg(void);
2408 extern void MPentry(void);
2409 extern u_int MP_GDT;
2410 extern u_int mp_gdtbase;
2413 install_ap_tramp(u_int boot_addr)
2416 int size = *(int *) ((u_long) & bootMP_size);
2417 u_char *src = (u_char *) ((u_long) bootMP);
2418 u_char *dst = (u_char *) boot_addr + KERNBASE;
2419 u_int boot_base = (u_int) bootMP;
2424 POSTCODE(INSTALL_AP_TRAMP_POST);
2426 for (x = 0; x < size; ++x)
2430 * modify addresses in code we just moved to basemem. unfortunately we
2431 * need fairly detailed info about mpboot.s for this to work. changes
2432 * to mpboot.s might require changes here.
2435 /* boot code is located in KERNEL space */
2436 dst = (u_char *) boot_addr + KERNBASE;
2438 /* modify the lgdt arg */
2439 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2440 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2442 /* modify the ljmp target for MPentry() */
2443 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2444 *dst32 = ((u_int) MPentry - KERNBASE);
2446 /* modify the target for boot code segment */
2447 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2448 dst8 = (u_int8_t *) (dst16 + 1);
2449 *dst16 = (u_int) boot_addr & 0xffff;
2450 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2452 /* modify the target for boot data segment */
2453 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2454 dst8 = (u_int8_t *) (dst16 + 1);
2455 *dst16 = (u_int) boot_addr & 0xffff;
2456 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2461 * this function starts the AP (application processor) identified
2462 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2463 * to accomplish this. This is necessary because of the nuances
2464 * of the different hardware we might encounter. It ain't pretty,
2465 * but it seems to work.
2467 * NOTE: eventually an AP gets to ap_init(), which is called just
2468 * before the AP goes into the LWKT scheduler's idle loop.
2471 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2475 u_long icr_lo, icr_hi;
2477 POSTCODE(START_AP_POST);
2479 /* get the PHYSICAL APIC ID# */
2480 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2482 /* calculate the vector */
2483 vector = (boot_addr >> 12) & 0xff;
2485 /* Make sure the target cpu sees everything */
2489 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2490 * and running the target CPU. OR this INIT IPI might be latched (P5
2491 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2495 /* setup the address for the target AP */
2496 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2497 icr_hi |= (physical_cpu << 24);
2498 lapic.icr_hi = icr_hi;
2500 /* do an INIT IPI: assert RESET */
2501 icr_lo = lapic.icr_lo & 0xfff00000;
2502 lapic.icr_lo = icr_lo | 0x0000c500;
2504 /* wait for pending status end */
2505 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2508 /* do an INIT IPI: deassert RESET */
2509 lapic.icr_lo = icr_lo | 0x00008500;
2511 /* wait for pending status end */
2512 u_sleep(10000); /* wait ~10mS */
2513 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2517 * next we do a STARTUP IPI: the previous INIT IPI might still be
2518 * latched, (P5 bug) this 1st STARTUP would then terminate
2519 * immediately, and the previously started INIT IPI would continue. OR
2520 * the previous INIT IPI has already run. and this STARTUP IPI will
2521 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2525 /* do a STARTUP IPI */
2526 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2527 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2529 u_sleep(200); /* wait ~200uS */
2532 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2533 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2534 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2535 * recognized after hardware RESET or INIT IPI.
2538 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2539 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2541 u_sleep(200); /* wait ~200uS */
2543 /* wait for it to start, see ap_init() */
2544 set_apic_timer(5000000);/* == 5 seconds */
2545 while (read_apic_timer()) {
2546 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2547 return 1; /* return SUCCESS */
2549 return 0; /* return FAILURE */
2554 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2556 * If for some reason we were unable to start all cpus we cannot safely
2557 * use broadcast IPIs.
2563 if (smp_startup_mask == smp_active_mask) {
2564 all_but_self_ipi(XINVLTLB_OFFSET);
2566 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2567 APIC_DELMODE_FIXED);
2573 * When called the executing CPU will send an IPI to all other CPUs
2574 * requesting that they halt execution.
2576 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2578 * - Signals all CPUs in map to stop.
2579 * - Waits for each to stop.
2586 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2587 * from executing at same time.
2590 stop_cpus(u_int map)
2592 map &= smp_active_mask;
2594 /* send the Xcpustop IPI to all CPUs in map */
2595 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2597 while ((stopped_cpus & map) != map)
2605 * Called by a CPU to restart stopped CPUs.
2607 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2609 * - Signals all CPUs in map to restart.
2610 * - Waits for each to restart.
2618 restart_cpus(u_int map)
2620 /* signal other cpus to restart */
2621 started_cpus = map & smp_active_mask;
2623 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2630 * This is called once the mpboot code has gotten us properly relocated
2631 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2632 * and when it returns the scheduler will call the real cpu_idle() main
2633 * loop for the idlethread. Interrupts are disabled on entry and should
2634 * remain disabled at return.
2642 * Adjust smp_startup_mask to signal the BSP that we have started
2643 * up successfully. Note that we do not yet hold the BGL. The BSP
2644 * is waiting for our signal.
2646 * We can't set our bit in smp_active_mask yet because we are holding
2647 * interrupts physically disabled and remote cpus could deadlock
2648 * trying to send us an IPI.
2650 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2654 * Interlock for finalization. Wait until mp_finish is non-zero,
2655 * then get the MP lock.
2657 * Note: We are in a critical section.
2659 * Note: We have to synchronize td_mpcount to our desired MP state
2660 * before calling cpu_try_mplock().
2662 * Note: we are the idle thread, we can only spin.
2664 * Note: The load fence is memory volatile and prevents the compiler
2665 * from improperly caching mp_finish, and the cpu from improperly
2668 while (mp_finish == 0)
2670 ++curthread->td_mpcount;
2671 while (cpu_try_mplock() == 0)
2674 if (cpu_feature & CPUID_TSC) {
2676 * The BSP is constantly updating tsc0_offset, figure out the
2677 * relative difference to synchronize ktrdump.
2679 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2682 /* BSP may have changed PTD while we're waiting for the lock */
2685 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2689 /* Build our map of 'other' CPUs. */
2690 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2692 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2694 /* A quick check from sanity claus */
2695 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2696 if (mycpu->gd_cpuid != apic_id) {
2697 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2698 kprintf("SMP: apic_id = %d\n", apic_id);
2699 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2700 panic("cpuid mismatch! boom!!");
2703 /* Initialize AP's local APIC for irq's */
2704 apic_initialize(FALSE);
2706 /* Set memory range attributes for this CPU to match the BSP */
2707 mem_range_AP_init();
2710 * Once we go active we must process any IPIQ messages that may
2711 * have been queued, because no actual IPI will occur until we
2712 * set our bit in the smp_active_mask. If we don't the IPI
2713 * message interlock could be left set which would also prevent
2716 * The idle loop doesn't expect the BGL to be held and while
2717 * lwkt_switch() normally cleans things up this is a special case
2718 * because we returning almost directly into the idle loop.
2720 * The idle thread is never placed on the runq, make sure
2721 * nothing we've done put it there.
2723 KKASSERT(curthread->td_mpcount == 1);
2724 smp_active_mask |= 1 << mycpu->gd_cpuid;
2727 * Enable interrupts here. idle_restore will also do it, but
2728 * doing it here lets us clean up any strays that got posted to
2729 * the CPU during the AP boot while we are still in a critical
2732 __asm __volatile("sti; pause; pause"::);
2733 mdcpu->gd_fpending = 0;
2734 mdcpu->gd_ipending = 0;
2736 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2737 lwkt_process_ipiq();
2740 * Releasing the mp lock lets the BSP finish up the SMP init
2743 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2747 * Get SMP fully working before we start initializing devices.
2755 kprintf("Finish MP startup\n");
2756 if (cpu_feature & CPUID_TSC)
2757 tsc0_offset = rdtsc();
2760 while (smp_active_mask != smp_startup_mask) {
2762 if (cpu_feature & CPUID_TSC)
2763 tsc0_offset = rdtsc();
2765 while (try_mplock() == 0)
2768 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2771 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2774 cpu_send_ipiq(int dcpu)
2776 if ((1 << dcpu) & smp_active_mask)
2777 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2780 #if 0 /* single_apic_ipi_passive() not working yet */
2782 * Returns 0 on failure, 1 on success
2785 cpu_send_ipiq_passive(int dcpu)
2788 if ((1 << dcpu) & smp_active_mask) {
2789 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2790 APIC_DELMODE_FIXED);
2796 struct mptable_lapic_cbarg1 {
2799 u_int ht_apicid_mask;
2803 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2805 const struct PROCENTRY *ent;
2806 struct mptable_lapic_cbarg1 *arg = xarg;
2812 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2816 if (ent->apic_id < 32) {
2817 arg->ht_apicid_mask |= 1 << ent->apic_id;
2818 } else if (arg->ht_fixup) {
2819 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2825 struct mptable_lapic_cbarg2 {
2832 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2834 const struct PROCENTRY *ent;
2835 struct mptable_lapic_cbarg2 *arg = xarg;
2841 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2842 KKASSERT(!arg->found_bsp);
2846 if (processor_entry(ent, arg->cpu))
2849 if (arg->logical_cpus) {
2850 struct PROCENTRY proc;
2854 * Create fake mptable processor entries
2855 * and feed them to processor_entry() to
2856 * enumerate the logical CPUs.
2858 bzero(&proc, sizeof(proc));
2860 proc.cpu_flags = PROCENTRY_FLAG_EN;
2861 proc.apic_id = ent->apic_id;
2863 for (i = 1; i < arg->logical_cpus; i++) {
2865 processor_entry(&proc, arg->cpu);
2873 mptable_lapic_default(void)
2875 int ap_apicid, bsp_apicid;
2877 mp_naps = 1; /* exclude BSP */
2879 /* Map local apic before the id field is accessed */
2880 lapic_init(DEFAULT_APIC_BASE);
2882 bsp_apicid = APIC_ID(lapic.id);
2883 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2886 mp_set_cpuids(0, bsp_apicid);
2887 /* one and only AP */
2888 mp_set_cpuids(1, ap_apicid);
2893 * cpu_apic_address (common to all CPUs)
2895 * ID_TO_CPU(N), APIC ID to logical CPU table
2896 * CPU_TO_ID(N), logical CPU to APIC ID table
2899 mptable_lapic_enumerate(struct mptable_pos *mpt)
2901 struct mptable_lapic_cbarg1 arg1;
2902 struct mptable_lapic_cbarg2 arg2;
2904 int error, logical_cpus = 0;
2905 vm_offset_t lapic_addr;
2907 KKASSERT(mpt->mp_fps != NULL);
2910 * Check for use of 'default' configuration
2912 if (mpt->mp_fps->mpfb1 != 0) {
2913 mptable_lapic_default();
2918 KKASSERT(cth != NULL);
2920 /* Save local apic address */
2921 lapic_addr = (vm_offset_t)cth->apic_address;
2922 KKASSERT(lapic_addr != 0);
2925 * Find out how many CPUs do we have
2927 bzero(&arg1, sizeof(arg1));
2928 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2930 error = mptable_iterate_entries(cth,
2931 mptable_lapic_pass1_callback, &arg1);
2933 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2934 KKASSERT(arg1.cpu_count != 0);
2936 /* See if we need to fixup HT logical CPUs. */
2937 if (arg1.ht_fixup) {
2938 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2940 if (logical_cpus != 0)
2941 arg1.cpu_count *= logical_cpus;
2943 mp_naps = arg1.cpu_count;
2945 /* Qualify the numbers again, after possible HT fixup */
2946 if (mp_naps > MAXCPU) {
2947 kprintf("Warning: only using %d of %d available CPUs!\n",
2952 --mp_naps; /* subtract the BSP */
2955 * Link logical CPU id to local apic id
2957 bzero(&arg2, sizeof(arg2));
2959 arg2.logical_cpus = logical_cpus;
2961 error = mptable_iterate_entries(cth,
2962 mptable_lapic_pass2_callback, &arg2);
2964 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2965 KKASSERT(arg2.found_bsp);
2967 /* Map local apic */
2968 lapic_init(lapic_addr);
2972 lapic_init(vm_offset_t lapic_addr)
2974 /* Local apic is mapped on last page */
2975 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
2976 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
2978 /* Just for printing */
2979 cpu_apic_address = lapic_addr;