sys/dev/serial/rc/rc.c

   1 /*
   2  * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
   3  * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
  28  * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.24 2008/08/02 01:14:43 dillon Exp $
  29  *
  30  */
  31
  32 /*
  33  * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
  34  *
  35  */
  36
  37 #include "use_rc.h"
  38
  39 /*#define RCDEBUG*/
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/tty.h>
  44 #include <sys/proc.h>
  45 #include <sys/priv.h>
  46 #include <sys/conf.h>
  47 #include <sys/dkstat.h>
  48 #include <sys/fcntl.h>
  49 #include <sys/interrupt.h>
  50 #include <sys/kernel.h>
  51 #include <sys/thread2.h>
  52 #include <machine/clock.h>
  53
  54 #include <bus/isa/isa_device.h>
  55
  56 #include <machine_base/isa/ic/cd180.h>
  57 #include "rcreg.h"
  58
  59 /* Prototypes */
  60 static int     rcprobe         (struct isa_device *);
  61 static int     rcattach        (struct isa_device *);
  62
  63 #define rcin(port)      RC_IN  (nec, port)
  64 #define rcout(port,v)   RC_OUT (nec, port, v)
  65
  66 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
  67 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
  68
  69 #define RC_IBUFSIZE     256
  70 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
  71 #define RC_OBUFSIZE     512
  72 #define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
  73 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
  74 #define LOTS_OF_EVENTS  64
  75
  76 #define RC_FAKEID       0x10
  77
  78 #define RC_PROBED 1
  79 #define RC_ATTACHED 2
  80
  81 #define GET_UNIT(dev)   (minor(dev) & 0x3F)
  82 #define CALLOUT(dev)    (minor(dev) & 0x80)
  83
  84 /* For isa routines */
  85 struct isa_driver rcdriver = {
  86         rcprobe, rcattach, "rc"
  87 };
  88
  89 static  d_open_t        rcopen;
  90 static  d_close_t       rcclose;
  91 static  d_ioctl_t       rcioctl;
  92
  93 #define CDEV_MAJOR      63
  94 static struct dev_ops rc_ops = {
  95         { "rc", CDEV_MAJOR, D_TTY | D_KQFILTER },
  96         .d_open =       rcopen,
  97         .d_close =      rcclose,
  98         .d_read =       ttyread,
  99         .d_write =      ttywrite,
 100         .d_ioctl =      rcioctl,
 101         .d_poll =       ttypoll,
 102         .d_kqfilter =   ttykqfilter,
 103         .d_revoke =     ttyrevoke
 104 };
 105
 106 /* Per-board structure */
 107 static struct rc_softc {
 108         u_int           rcb_probed;     /* 1 - probed, 2 - attached */
 109         u_int           rcb_addr;       /* Base I/O addr        */
 110         u_int           rcb_unit;       /* unit #               */
 111         u_char          rcb_dtr;        /* DTR status           */
 112         struct rc_chans *rcb_baserc;    /* base rc ptr          */
 113 } rc_softc[NRC];
 114
 115 /* Per-channel structure */
 116 static struct rc_chans  {
 117         struct rc_softc *rc_rcb;                /* back ptr             */
 118         u_short          rc_flags;              /* Misc. flags          */
 119         int              rc_chan;               /* Channel #            */
 120         u_char           rc_ier;                /* intr. enable reg     */
 121         u_char           rc_msvr;               /* modem sig. status    */
 122         u_char           rc_cor2;               /* options reg          */
 123         u_char           rc_pendcmd;            /* special cmd pending  */
 124         u_int            rc_dtrwait;            /* dtr timeout          */
 125         u_int            rc_dcdwaits;           /* how many waits DCD in open */
 126         u_char           rc_hotchar;            /* end packed optimize */
 127         struct tty      *rc_tp;                 /* tty struct           */
 128         u_char          *rc_iptr;               /* Chars input buffer         */
 129         u_char          *rc_hiwat;              /* hi-water mark        */
 130         u_char          *rc_bufend;             /* end of buffer        */
 131         u_char          *rc_optr;               /* ptr in output buf    */
 132         u_char          *rc_obufend;            /* end of output buf    */
 133         struct callout   rc_dtr_ch;
 134         u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
 135         u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
 136 } rc_chans[NRC * CD180_NCHAN];
 137
 138 static int rc_scheduled_event = 0;
 139 static struct callout rc_wakeup_ch;
 140
 141 /* for pstat -t */
 142 static struct tty rc_tty[NRC * CD180_NCHAN];
 143 static const int  nrc_tty = NRC * CD180_NCHAN;
 144
 145 /* Flags */
 146 #define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
 147 #define RC_ACTOUT       0x0002          /* Dial-out port active         */
 148 #define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
 149 #define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
 150 #define RC_DORXFER      0x0010          /* RXFER event planned          */
 151 #define RC_DOXXFER      0x0020          /* XXFER event planned          */
 152 #define RC_MODCHG       0x0040          /* Modem status changed         */
 153 #define RC_OSUSP        0x0080          /* Output suspended             */
 154 #define RC_OSBUSY       0x0100          /* start() routine in progress  */
 155 #define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
 156 #define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
 157 #define RC_SEND_RDY     0x0800          /* ready to send */
 158
 159 /* Table for translation of RCSR status bits to internal form */
 160 static int rc_rcsrt[16] = {
 161         0,             TTY_OE,               TTY_FE,
 162         TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
 163         TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
 164         TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
 165         TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
 166         TTY_BI|TTY_PE|TTY_FE|TTY_OE
 167 };
 168
 169 /* Static prototypes */
 170 static inthand2_t rcintr;
 171 static void rc_hwreset          (int, int, unsigned int);
 172 static int  rc_test             (int, int);
 173 static void rc_discard_output   (struct rc_chans *);
 174 static void rc_hardclose        (struct rc_chans *);
 175 static int  rc_modctl           (struct rc_chans *, int, int);
 176 static void rc_start            (struct tty *);
 177 static void rc_stop              (struct tty *, int rw);
 178 static int  rc_param            (struct tty *, struct termios *);
 179 static inthand2_t rcpoll;
 180 static void rc_reinit           (struct rc_softc *);
 181 #ifdef RCDEBUG
 182 static void printrcflags();
 183 #endif
 184 static timeout_t rc_dtrwakeup;
 185 static timeout_t rc_wakeup;
 186 static void disc_optim          (struct tty     *tp, struct termios *t, struct rc_chans *);
 187 static void rc_wait0            (int nec, int unit, int chan, int line);
 188
 189 /**********************************************/
 190
 191 /* Quick device probing */
 192 static int
 193 rcprobe(struct isa_device *dvp)
 194 {
 195         int             irq = ffs(dvp->id_irq) - 1;
 196         int    nec = dvp->id_iobase;
 197
 198         if (dvp->id_unit > NRC)
 199                 return 0;
 200         if (!RC_VALIDADDR(nec)) {
 201                 kprintf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
 202                 return 0;
 203         }
 204         if (!RC_VALIDIRQ(irq)) {
 205                 kprintf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
 206                 return 0;
 207         }
 208         rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
 209         rcout(CD180_PPRH, 0x11);
 210         if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
 211                 return 0;
 212         /* Now, test the board more thoroughly, with diagnostic */
 213         if (rc_test(nec, dvp->id_unit))
 214                 return 0;
 215         rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
 216
 217         return 0xF;
 218 }
 219
 220 static int
 221 rcattach(struct isa_device *dvp)
 222 {
 223         int            chan, nec = dvp->id_iobase;
 224         struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
 225         struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
 226         static int              rc_started = 0;
 227         struct tty              *tp;
 228
 229         dvp->id_intr = rcintr;
 230
 231         /* Thorooughly test the device */
 232         if (rcb->rcb_probed != RC_PROBED)
 233                 return 0;
 234         rcb->rcb_addr   = nec;
 235         rcb->rcb_dtr    = 0;
 236         rcb->rcb_baserc = rc;
 237         rcb->rcb_unit   = dvp->id_unit;
 238         /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
 239         kprintf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
 240                 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
 241
 242         for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
 243                 callout_init(&rc->rc_dtr_ch);
 244                 rc->rc_rcb     = rcb;
 245                 rc->rc_chan    = chan;
 246                 rc->rc_iptr    = rc->rc_ibuf;
 247                 rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
 248                 rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
 249                 rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
 250                 rc->rc_cor2    = rc->rc_pendcmd = 0;
 251                 rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
 252                 rc->rc_dtrwait = 3 * hz;
 253                 rc->rc_dcdwaits= 0;
 254                 rc->rc_hotchar = 0;
 255                 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
 256                 ttychars(tp);
 257                 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
 258                 tp->t_cflag = TTYDEF_CFLAG;
 259                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
 260         }
 261         rcb->rcb_probed = RC_ATTACHED;
 262         if (!rc_started) {
 263                 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll", NULL);
 264                 callout_init(&rc_wakeup_ch);
 265                 rc_wakeup(NULL);
 266                 rc_started = 1;
 267         }
 268         return 1;
 269 }
 270
 271 /* RC interrupt handling */
 272 static void
 273 rcintr(void *arg, void *frame)
 274 {
 275         int unit = (int)arg;
 276         struct rc_softc        *rcb = &rc_softc[unit];
 277         struct rc_chans        *rc;
 278         int                    nec, resid;
 279         u_char                 val, iack, bsr, ucnt, *optr;
 280         int                             good_data, t_state;
 281
 282         if (rcb->rcb_probed != RC_ATTACHED) {
 283                 kprintf("rc%d: bogus interrupt\n", unit);
 284                 return;
 285         }
 286         nec = rcb->rcb_addr;
 287
 288         bsr = ~(rcin(RC_BSR));
 289
 290         if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
 291                 kprintf("rc%d: extra interrupt\n", unit);
 292                 rcout(CD180_EOIR, 0);
 293                 return;
 294         }
 295
 296         while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
 297 #ifdef RCDEBUG_DETAILED
 298                 kprintf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
 299                         (bsr & RC_BSR_TOUT)?"TOUT ":"",
 300                         (bsr & RC_BSR_RXINT)?"RXINT ":"",
 301                         (bsr & RC_BSR_TXINT)?"TXINT ":"",
 302                         (bsr & RC_BSR_MOINT)?"MOINT":"");
 303 #endif
 304                 if (bsr & RC_BSR_TOUT) {
 305                         kprintf("rc%d: hardware failure, reset board\n", unit);
 306                         rcout(RC_CTOUT, 0);
 307                         rc_reinit(rcb);
 308                         return;
 309                 }
 310                 if (bsr & RC_BSR_RXINT) {
 311                         iack = rcin(RC_PILR_RX);
 312                         good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
 313                         if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
 314                                 kprintf("rc%d: fake rxint: %02x\n", unit, iack);
 315                                 goto more_intrs;
 316                         }
 317                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 318                         t_state = rc->rc_tp->t_state;
 319                         /* Do RTS flow control stuff */
 320                         if (  (rc->rc_flags & RC_RTSFLOW)
 321                             || !(t_state & TS_ISOPEN)
 322                            ) {
 323                                 if (  (   !(t_state & TS_ISOPEN)
 324                                        || (t_state & TS_TBLOCK)
 325                                       )
 326                                     && (rc->rc_msvr & MSVR_RTS)
 327                                    )
 328                                         rcout(CD180_MSVR,
 329                                                 rc->rc_msvr &= ~MSVR_RTS);
 330                                 else if (!(rc->rc_msvr & MSVR_RTS))
 331                                         rcout(CD180_MSVR,
 332                                                 rc->rc_msvr |= MSVR_RTS);
 333                         }
 334                         ucnt  = rcin(CD180_RDCR) & 0xF;
 335                         resid = 0;
 336
 337                         if (t_state & TS_ISOPEN) {
 338                                 /* check for input buffer overflow */
 339                                 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
 340                                         resid  = ucnt;
 341                                         ucnt   = rc->rc_bufend - rc->rc_iptr;
 342                                         resid -= ucnt;
 343                                         if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
 344                                                 rc->rc_flags |= RC_WAS_BUFOVFL;
 345                                                 rc_scheduled_event++;
 346                                         }
 347                                 }
 348                                 optr = rc->rc_iptr;
 349                                 /* check foor good data */
 350                                 if (good_data) {
 351                                         while (ucnt-- > 0) {
 352                                                 val = rcin(CD180_RDR);
 353                                                 optr[0] = val;
 354                                                 optr[INPUT_FLAGS_SHIFT] = 0;
 355                                                 optr++;
 356                                                 rc_scheduled_event++;
 357                                                 if (val != 0 && val == rc->rc_hotchar)
 358                                                         setsofttty();
 359                                         }
 360                                 } else {
 361                                         /* Store also status data */
 362                                         while (ucnt-- > 0) {
 363                                                 iack = rcin(CD180_RCSR);
 364                                                 if (iack & RCSR_Timeout)
 365                                                         break;
 366                                                 if (   (iack & RCSR_OE)
 367                                                     && !(rc->rc_flags & RC_WAS_SILOVFL)) {
 368                                                         rc->rc_flags |= RC_WAS_SILOVFL;
 369                                                         rc_scheduled_event++;
 370                                                 }
 371                                                 val = rcin(CD180_RDR);
 372                                                 /*
 373                                                   Don't store PE if IGNPAR and BREAK if IGNBRK,
 374                                                   this hack allows "raw" tty optimization
 375                                                   works even if IGN* is set.
 376                                                 */
 377                                                 if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
 378                                                     || ((!(iack & (RCSR_PE|RCSR_FE))
 379                                                     ||  !(rc->rc_tp->t_iflag & IGNPAR))
 380                                                     && (!(iack & RCSR_Break)
 381                                                     ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
 382                                                         if (   (iack & (RCSR_PE|RCSR_FE))
 383                                                             && (t_state & TS_CAN_BYPASS_L_RINT)
 384                                                             && ((iack & RCSR_FE)
 385                                                             ||  ((iack & RCSR_PE)
 386                                                             &&  (rc->rc_tp->t_iflag & INPCK))))
 387                                                                 val = 0;
 388                                                         else if (val != 0 && val == rc->rc_hotchar)
 389                                                                 setsofttty();
 390                                                         optr[0] = val;
 391                                                         optr[INPUT_FLAGS_SHIFT] = iack;
 392                                                         optr++;
 393                                                         rc_scheduled_event++;
 394                                                 }
 395                                         }
 396                                 }
 397                                 rc->rc_iptr = optr;
 398                                 rc->rc_flags |= RC_DORXFER;
 399                         } else
 400                                 resid = ucnt;
 401                         /* Clear FIFO if necessary */
 402                         while (resid-- > 0) {
 403                                 if (!good_data)
 404                                         iack = rcin(CD180_RCSR);
 405                                 else
 406                                         iack = 0;
 407                                 if (iack & RCSR_Timeout)
 408                                         break;
 409                                 (void) rcin(CD180_RDR);
 410                         }
 411                         goto more_intrs;
 412                 }
 413                 if (bsr & RC_BSR_MOINT) {
 414                         iack = rcin(RC_PILR_MODEM);
 415                         if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
 416                                 kprintf("rc%d: fake moint: %02x\n", unit, iack);
 417                                 goto more_intrs;
 418                         }
 419                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 420                         iack = rcin(CD180_MCR);
 421                         rc->rc_msvr = rcin(CD180_MSVR);
 422                         rcout(CD180_MCR, 0);
 423 #ifdef RCDEBUG
 424                         printrcflags(rc, "moint");
 425 #endif
 426                         if (rc->rc_flags & RC_CTSFLOW) {
 427                                 if (rc->rc_msvr & MSVR_CTS)
 428                                         rc->rc_flags |= RC_SEND_RDY;
 429                                 else
 430                                         rc->rc_flags &= ~RC_SEND_RDY;
 431                         } else
 432                                 rc->rc_flags |= RC_SEND_RDY;
 433                         if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
 434                                 rc_scheduled_event += LOTS_OF_EVENTS;
 435                                 rc->rc_flags |= RC_MODCHG;
 436                                 setsofttty();
 437                         }
 438                         goto more_intrs;
 439                 }
 440                 if (bsr & RC_BSR_TXINT) {
 441                         iack = rcin(RC_PILR_TX);
 442                         if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
 443                                 kprintf("rc%d: fake txint: %02x\n", unit, iack);
 444                                 goto more_intrs;
 445                         }
 446                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 447                         if (    (rc->rc_flags & RC_OSUSP)
 448                             || !(rc->rc_flags & RC_SEND_RDY)
 449                            )
 450                                 goto more_intrs;
 451                         /* Handle breaks and other stuff */
 452                         if (rc->rc_pendcmd) {
 453                                 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
 454                                 rcout(CD180_TDR,  CD180_C_ESC);
 455                                 rcout(CD180_TDR,  rc->rc_pendcmd);
 456                                 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
 457                                 rc->rc_pendcmd = 0;
 458                                 goto more_intrs;
 459                         }
 460                         optr = rc->rc_optr;
 461                         resid = rc->rc_obufend - optr;
 462                         if (resid > CD180_NFIFO)
 463                                 resid = CD180_NFIFO;
 464                         while (resid-- > 0)
 465                                 rcout(CD180_TDR, *optr++);
 466                         rc->rc_optr = optr;
 467
 468                         /* output completed? */
 469                         if (optr >= rc->rc_obufend) {
 470                                 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
 471 #ifdef RCDEBUG
 472                                 kprintf("rc%d/%d: output completed\n", unit, rc->rc_chan);
 473 #endif
 474                                 if (!(rc->rc_flags & RC_DOXXFER)) {
 475                                         rc_scheduled_event += LOTS_OF_EVENTS;
 476                                         rc->rc_flags |= RC_DOXXFER;
 477                                         setsofttty();
 478                                 }
 479                         }
 480                 }
 481         more_intrs:
 482                 rcout(CD180_EOIR, 0);   /* end of interrupt */
 483                 rcout(RC_CTOUT, 0);
 484                 bsr = ~(rcin(RC_BSR));
 485         }
 486 }
 487
 488 /* Feed characters to output buffer */
 489 static void
 490 rc_start(struct tty *tp)
 491 {
 492         struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 493         int                    nec = rc->rc_rcb->rcb_addr;
 494
 495         if (rc->rc_flags & RC_OSBUSY)
 496                 return;
 497         crit_enter();
 498         rc->rc_flags |= RC_OSBUSY;
 499         cpu_disable_intr();
 500         if (tp->t_state & TS_TTSTOP)
 501                 rc->rc_flags |= RC_OSUSP;
 502         else
 503                 rc->rc_flags &= ~RC_OSUSP;
 504         /* Do RTS flow control stuff */
 505         if (   (rc->rc_flags & RC_RTSFLOW)
 506             && (tp->t_state & TS_TBLOCK)
 507             && (rc->rc_msvr & MSVR_RTS)
 508            ) {
 509                 rcout(CD180_CAR, rc->rc_chan);
 510                 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
 511         } else if (!(rc->rc_msvr & MSVR_RTS)) {
 512                 rcout(CD180_CAR, rc->rc_chan);
 513                 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
 514         }
 515         cpu_enable_intr();
 516         if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
 517                 goto out;
 518 #ifdef RCDEBUG
 519         printrcflags(rc, "rcstart");
 520 #endif
 521         ttwwakeup(tp);
 522 #ifdef RCDEBUG
 523         kprintf("rcstart: outq = %d obuf = %d\n",
 524                 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
 525 #endif
 526         if (tp->t_state & TS_BUSY)
 527                 goto    out;    /* output still in progress ... */
 528
 529         if (tp->t_outq.c_cc > 0) {
 530                 u_int   ocnt;
 531
 532                 tp->t_state |= TS_BUSY;
 533                 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
 534                 cpu_disable_intr();
 535                 rc->rc_optr = rc->rc_obuf;
 536                 rc->rc_obufend = rc->rc_optr + ocnt;
 537                 cpu_enable_intr();
 538                 if (!(rc->rc_ier & IER_TxRdy)) {
 539 #ifdef RCDEBUG
 540                         kprintf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
 541 #endif
 542                         rcout(CD180_CAR, rc->rc_chan);
 543                         rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
 544                 }
 545         }
 546 out:
 547         rc->rc_flags &= ~RC_OSBUSY;
 548         crit_exit();
 549 }
 550
 551 /* Handle delayed events. */
 552 void
 553 rcpoll(void *dummy, void *frame)
 554 {
 555         struct rc_chans *rc;
 556         struct rc_softc *rcb;
 557         u_char        *tptr, *eptr;
 558         struct tty    *tp;
 559         int            chan, icnt, nec, unit;
 560
 561         if (rc_scheduled_event == 0)
 562                 return;
 563 repeat:
 564         for (unit = 0; unit < NRC; unit++) {
 565                 rcb = &rc_softc[unit];
 566                 rc = rcb->rcb_baserc;
 567                 nec = rc->rc_rcb->rcb_addr;
 568                 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
 569                         tp = rc->rc_tp;
 570 #ifdef RCDEBUG
 571                         if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
 572                             RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
 573                                 printrcflags(rc, "rcevent");
 574 #endif
 575                         if (rc->rc_flags & RC_WAS_BUFOVFL) {
 576                                 cpu_disable_intr();
 577                                 rc->rc_flags &= ~RC_WAS_BUFOVFL;
 578                                 rc_scheduled_event--;
 579                                 cpu_enable_intr();
 580                                 kprintf("rc%d/%d: interrupt-level buffer overflow\n",
 581                                         unit, chan);
 582                         }
 583                         if (rc->rc_flags & RC_WAS_SILOVFL) {
 584                                 cpu_disable_intr();
 585                                 rc->rc_flags &= ~RC_WAS_SILOVFL;
 586                                 rc_scheduled_event--;
 587                                 cpu_enable_intr();
 588                                 kprintf("rc%d/%d: silo overflow\n",
 589                                         unit, chan);
 590                         }
 591                         if (rc->rc_flags & RC_MODCHG) {
 592                                 cpu_disable_intr();
 593                                 rc->rc_flags &= ~RC_MODCHG;
 594                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 595                                 cpu_enable_intr();
 596                                 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
 597                         }
 598                         if (rc->rc_flags & RC_DORXFER) {
 599                                 cpu_disable_intr();
 600                                 rc->rc_flags &= ~RC_DORXFER;
 601                                 eptr = rc->rc_iptr;
 602                                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
 603                                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 604                                 else
 605                                         tptr = rc->rc_ibuf;
 606                                 icnt = eptr - tptr;
 607                                 if (icnt > 0) {
 608                                         if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 609                                                 rc->rc_iptr   = rc->rc_ibuf;
 610                                                 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
 611                                                 rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
 612                                         } else {
 613                                                 rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
 614                                                 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
 615                                                 rc->rc_hiwat  =
 616                                                         &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
 617                                         }
 618                                         if (   (rc->rc_flags & RC_RTSFLOW)
 619                                             && (tp->t_state & TS_ISOPEN)
 620                                             && !(tp->t_state & TS_TBLOCK)
 621                                             && !(rc->rc_msvr & MSVR_RTS)
 622                                             ) {
 623                                                 rcout(CD180_CAR, chan);
 624                                                 rcout(CD180_MSVR,
 625                                                         rc->rc_msvr |= MSVR_RTS);
 626                                         }
 627                                         rc_scheduled_event -= icnt;
 628                                 }
 629                                 cpu_enable_intr();
 630
 631                                 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
 632                                         goto done1;
 633
 634                                 if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
 635                                     && !(tp->t_state & TS_LOCAL)) {
 636                                         if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
 637                                             && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
 638                                             && !(tp->t_state & TS_TBLOCK))
 639                                                 ttyblock(tp);
 640                                         tk_nin += icnt;
 641                                         tk_rawcc += icnt;
 642                                         tp->t_rawcc += icnt;
 643                                         if (b_to_q(tptr, icnt, &tp->t_rawq))
 644                                                 kprintf("rc%d/%d: tty-level buffer overflow\n",
 645                                                         unit, chan);
 646                                         ttwakeup(tp);
 647                                         if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
 648                                             || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
 649                                                 tp->t_state &= ~TS_TTSTOP;
 650                                                 tp->t_lflag &= ~FLUSHO;
 651                                                 rc_start(tp);
 652                                         }
 653                                 } else {
 654                                         for (; tptr < eptr; tptr++)
 655                                                 (*linesw[tp->t_line].l_rint)
 656                                                     (tptr[0] |
 657                                                     rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
 658                                 }
 659 done1: ;
 660                         }
 661                         if (rc->rc_flags & RC_DOXXFER) {
 662                                 cpu_disable_intr();
 663                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 664                                 rc->rc_flags &= ~RC_DOXXFER;
 665                                 rc->rc_tp->t_state &= ~TS_BUSY;
 666                                 cpu_enable_intr();
 667                                 (*linesw[tp->t_line].l_start)(tp);
 668                         }
 669                 }
 670                 if (rc_scheduled_event == 0)
 671                         break;
 672         }
 673         if (rc_scheduled_event >= LOTS_OF_EVENTS)
 674                 goto repeat;
 675 }
 676
 677 static  void
 678 rc_stop(struct tty *tp, int rw)
 679 {
 680         struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 681         u_char *tptr, *eptr;
 682
 683 #ifdef RCDEBUG
 684         kprintf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
 685                 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
 686 #endif
 687         if (rw & FWRITE)
 688                 rc_discard_output(rc);
 689         cpu_disable_intr();
 690         if (rw & FREAD) {
 691                 rc->rc_flags &= ~RC_DORXFER;
 692                 eptr = rc->rc_iptr;
 693                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 694                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 695                         rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
 696                 } else {
 697                         tptr = rc->rc_ibuf;
 698                         rc->rc_iptr = rc->rc_ibuf;
 699                 }
 700                 rc_scheduled_event -= eptr - tptr;
 701         }
 702         if (tp->t_state & TS_TTSTOP)
 703                 rc->rc_flags |= RC_OSUSP;
 704         else
 705                 rc->rc_flags &= ~RC_OSUSP;
 706         cpu_enable_intr();
 707 }
 708
 709 static  int
 710 rcopen(struct dev_open_args *ap)
 711 {
 712         cdev_t dev = ap->a_head.a_dev;
 713         struct rc_chans *rc;
 714         struct tty      *tp;
 715         int             unit, nec, error = 0;
 716
 717         unit = GET_UNIT(dev);
 718         if (unit >= NRC * CD180_NCHAN)
 719                 return ENXIO;
 720         if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
 721                 return ENXIO;
 722         rc  = &rc_chans[unit];
 723         tp  = rc->rc_tp;
 724         dev->si_tty = tp;
 725         nec = rc->rc_rcb->rcb_addr;
 726 #ifdef RCDEBUG
 727         kprintf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 728 #endif
 729         crit_enter();
 730
 731 again:
 732         while (rc->rc_flags & RC_DTR_OFF) {
 733                 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
 734                 if (error != 0)
 735                         goto out;
 736         }
 737         if (tp->t_state & TS_ISOPEN) {
 738                 if (CALLOUT(dev)) {
 739                         if (!(rc->rc_flags & RC_ACTOUT)) {
 740                                 error = EBUSY;
 741                                 goto out;
 742                         }
 743                 } else {
 744                         if (rc->rc_flags & RC_ACTOUT) {
 745                                 if (ap->a_oflags & O_NONBLOCK) {
 746                                         error = EBUSY;
 747                                         goto out;
 748                                 }
 749                                 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
 750                                 if (error)
 751                                         goto out;
 752                                 goto again;
 753                         }
 754                 }
 755                 if (tp->t_state & TS_XCLUDE &&
 756                     priv_check_cred(ap->a_cred, PRIV_ROOT, 0)) {
 757                         error = EBUSY;
 758                         goto out;
 759                 }
 760         } else {
 761                 tp->t_oproc   = rc_start;
 762                 tp->t_param   = rc_param;
 763                 tp->t_stop    = rc_stop;
 764                 tp->t_dev     = dev;
 765
 766                 if (CALLOUT(dev))
 767                         tp->t_cflag |= CLOCAL;
 768                 else
 769                         tp->t_cflag &= ~CLOCAL;
 770
 771                 error = rc_param(tp, &tp->t_termios);
 772                 if (error)
 773                         goto out;
 774                 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
 775
 776                 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
 777                         (*linesw[tp->t_line].l_modem)(tp, 1);
 778         }
 779         if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
 780             && !(tp->t_cflag & CLOCAL) && !(ap->a_oflags & O_NONBLOCK)) {
 781                 rc->rc_dcdwaits++;
 782                 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
 783                 rc->rc_dcdwaits--;
 784                 if (error != 0)
 785                         goto out;
 786                 goto again;
 787         }
 788         error = (*linesw[tp->t_line].l_open)(dev, tp);
 789         disc_optim(tp, &tp->t_termios, rc);
 790         if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
 791                 rc->rc_flags |= RC_ACTOUT;
 792 out:
 793         crit_exit();
 794
 795         if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
 796                 rc_hardclose(rc);
 797
 798         return error;
 799 }
 800
 801 static int
 802 rcclose(struct dev_close_args *ap)
 803 {
 804         cdev_t dev = ap->a_head.a_dev;
 805         struct rc_chans *rc;
 806         struct tty      *tp;
 807         int unit = GET_UNIT(dev);
 808
 809         if (unit >= NRC * CD180_NCHAN)
 810                 return ENXIO;
 811         rc  = &rc_chans[unit];
 812         tp  = rc->rc_tp;
 813 #ifdef RCDEBUG
 814         kprintf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 815 #endif
 816         crit_enter();
 817         (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
 818         disc_optim(tp, &tp->t_termios, rc);
 819         rc_stop(tp, FREAD | FWRITE);
 820         rc_hardclose(rc);
 821         ttyclose(tp);
 822         crit_exit();
 823         return 0;
 824 }
 825
 826 static void
 827 rc_hardclose(struct rc_chans *rc)
 828 {
 829         int nec = rc->rc_rcb->rcb_addr;
 830         struct tty *tp = rc->rc_tp;
 831
 832         crit_enter();
 833         rcout(CD180_CAR, rc->rc_chan);
 834
 835         /* Disable rx/tx intrs */
 836         rcout(CD180_IER, rc->rc_ier = 0);
 837         if (   (tp->t_cflag & HUPCL)
 838             || (!(rc->rc_flags & RC_ACTOUT)
 839                && !(rc->rc_msvr & MSVR_CD)
 840                && !(tp->t_cflag & CLOCAL))
 841             || !(tp->t_state & TS_ISOPEN)
 842            ) {
 843                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 844                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 845                 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
 846                 if (rc->rc_dtrwait) {
 847                         callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
 848                                 rc_dtrwakeup, rc);
 849                         rc->rc_flags |= RC_DTR_OFF;
 850                 }
 851         }
 852         rc->rc_flags &= ~RC_ACTOUT;
 853         wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
 854         wakeup(TSA_CARR_ON(tp));
 855         crit_exit();
 856 }
 857
 858 /* Reset the bastard */
 859 static void
 860 rc_hwreset(int unit, int nec, unsigned int chipid)
 861 {
 862         CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
 863         DELAY(20000);
 864         WAITFORCCR(unit, -1);
 865
 866         rcout(RC_CTOUT, 0);             /* Clear timeout  */
 867         rcout(CD180_GIVR,  chipid);
 868         rcout(CD180_GICR,  0);
 869
 870         /* Set Prescaler Registers (1 msec) */
 871         rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
 872         rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
 873
 874         /* Initialize Priority Interrupt Level Registers */
 875         rcout(CD180_PILR1, RC_PILR_MODEM);
 876         rcout(CD180_PILR2, RC_PILR_TX);
 877         rcout(CD180_PILR3, RC_PILR_RX);
 878
 879         /* Reset DTR */
 880         rcout(RC_DTREG, ~0);
 881 }
 882
 883 /* Set channel parameters */
 884 static int
 885 rc_param(struct tty *tp, struct termios *ts)
 886 {
 887         struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 888         int    nec = rc->rc_rcb->rcb_addr;
 889         int      idivs, odivs, val, cflag, iflag, lflag, inpflow;
 890
 891         if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
 892             || ts->c_ispeed < 0 || ts->c_ispeed > 76800
 893            )
 894                 return (EINVAL);
 895         if (ts->c_ispeed == 0)
 896                 ts->c_ispeed = ts->c_ospeed;
 897         odivs = RC_BRD(ts->c_ospeed);
 898         idivs = RC_BRD(ts->c_ispeed);
 899
 900         crit_enter();
 901
 902         /* Select channel */
 903         rcout(CD180_CAR, rc->rc_chan);
 904
 905         /* If speed == 0, hangup line */
 906         if (ts->c_ospeed == 0) {
 907                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 908                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 909                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
 910         }
 911
 912         tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
 913         cflag = ts->c_cflag;
 914         iflag = ts->c_iflag;
 915         lflag = ts->c_lflag;
 916
 917         if (idivs > 0) {
 918                 rcout(CD180_RBPRL, idivs & 0xFF);
 919                 rcout(CD180_RBPRH, idivs >> 8);
 920         }
 921         if (odivs > 0) {
 922                 rcout(CD180_TBPRL, odivs & 0xFF);
 923                 rcout(CD180_TBPRH, odivs >> 8);
 924         }
 925
 926         /* set timeout value */
 927         if (ts->c_ispeed > 0) {
 928                 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
 929
 930                 if (   !(lflag & ICANON)
 931                     && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
 932                     && ts->c_cc[VTIME] * 10 > itm)
 933                         itm = ts->c_cc[VTIME] * 10;
 934
 935                 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
 936         }
 937
 938         switch (cflag & CSIZE) {
 939                 case CS5:       val = COR1_5BITS;      break;
 940                 case CS6:       val = COR1_6BITS;      break;
 941                 case CS7:       val = COR1_7BITS;      break;
 942                 default:
 943                 case CS8:       val = COR1_8BITS;      break;
 944         }
 945         if (cflag & PARENB) {
 946                 val |= COR1_NORMPAR;
 947                 if (cflag & PARODD)
 948                         val |= COR1_ODDP;
 949                 if (!(cflag & INPCK))
 950                         val |= COR1_Ignore;
 951         } else
 952                 val |= COR1_Ignore;
 953         if (cflag & CSTOPB)
 954                 val |= COR1_2SB;
 955         rcout(CD180_COR1, val);
 956
 957         /* Set FIFO threshold */
 958         val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
 959         inpflow = 0;
 960         if (   (iflag & IXOFF)
 961             && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
 962                 && (   ts->c_cc[VSTART] != _POSIX_VDISABLE
 963                     || (iflag & IXANY)
 964                    )
 965                )
 966            ) {
 967                 inpflow = 1;
 968                 val |= COR3_SCDE|COR3_FCT;
 969         }
 970         rcout(CD180_COR3, val);
 971
 972         /* Initialize on-chip automatic flow control */
 973         val = 0;
 974         rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
 975         if (cflag & CCTS_OFLOW) {
 976                 rc->rc_flags |= RC_CTSFLOW;
 977                 val |= COR2_CtsAE;
 978         } else
 979                 rc->rc_flags |= RC_SEND_RDY;
 980         if (tp->t_state & TS_TTSTOP)
 981                 rc->rc_flags |= RC_OSUSP;
 982         else
 983                 rc->rc_flags &= ~RC_OSUSP;
 984         if (cflag & CRTS_IFLOW)
 985                 rc->rc_flags |= RC_RTSFLOW;
 986         else
 987                 rc->rc_flags &= ~RC_RTSFLOW;
 988
 989         if (inpflow) {
 990                 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
 991                         rcout(CD180_SCHR1, ts->c_cc[VSTART]);
 992                 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
 993                 val |= COR2_TxIBE;
 994                 if (iflag & IXANY)
 995                         val |= COR2_IXM;
 996         }
 997
 998         rcout(CD180_COR2, rc->rc_cor2 = val);
 999
1000         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1001                 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1002
1003         disc_optim(tp, ts, rc);
1004
1005         /* modem ctl */
1006         val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1007         if (cflag & CCTS_OFLOW)
1008                 val |= MCOR1_CTSzd;
1009         rcout(CD180_MCOR1, val);
1010
1011         val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1012         if (cflag & CCTS_OFLOW)
1013                 val |= MCOR2_CTSod;
1014         rcout(CD180_MCOR2, val);
1015
1016         /* enable i/o and interrupts */
1017         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1018                 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1019         WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1020
1021         rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1022         if (cflag & CCTS_OFLOW)
1023                 rc->rc_ier |= IER_CTS;
1024         if (cflag & CREAD)
1025                 rc->rc_ier |= IER_RxData;
1026         if (tp->t_state & TS_BUSY)
1027                 rc->rc_ier |= IER_TxRdy;
1028         if (ts->c_ospeed != 0)
1029                 rc_modctl(rc, TIOCM_DTR, DMBIS);
1030         if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1031                 rc->rc_flags |= RC_SEND_RDY;
1032         rcout(CD180_IER, rc->rc_ier);
1033         crit_exit();
1034         return 0;
1035 }
1036
1037 /* Re-initialize board after bogus interrupts */
1038 static void
1039 rc_reinit(struct rc_softc *rcb)
1040 {
1041         struct rc_chans       *rc, *rce;
1042         int                    nec;
1043
1044         nec = rcb->rcb_addr;
1045         rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1046         rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1047         rce = rc + CD180_NCHAN;
1048         for (; rc < rce; rc++)
1049                 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1050 }
1051
1052 static  int
1053 rcioctl(struct dev_ioctl_args *ap)
1054 {
1055         cdev_t dev = ap->a_head.a_dev;
1056         struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1057         int                   error;
1058         struct tty                     *tp = rc->rc_tp;
1059
1060         error = (*linesw[tp->t_line].l_ioctl)(tp, ap->a_cmd, ap->a_data,
1061                                               ap->a_fflag, ap->a_cred);
1062         if (error != ENOIOCTL)
1063                 return (error);
1064         error = ttioctl(tp, ap->a_cmd, ap->a_data, ap->a_fflag);
1065         disc_optim(tp, &tp->t_termios, rc);
1066         if (error != ENOIOCTL)
1067                 return (error);
1068         crit_enter();
1069
1070         switch (ap->a_cmd) {
1071             case TIOCSBRK:
1072                 rc->rc_pendcmd = CD180_C_SBRK;
1073                 break;
1074
1075             case TIOCCBRK:
1076                 rc->rc_pendcmd = CD180_C_EBRK;
1077                 break;
1078
1079             case TIOCSDTR:
1080                 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1081                 break;
1082
1083             case TIOCCDTR:
1084                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1085                 break;
1086
1087             case TIOCMGET:
1088                 *(int *) ap->a_data = rc_modctl(rc, 0, DMGET);
1089                 break;
1090
1091             case TIOCMSET:
1092                 (void) rc_modctl(rc, *(int *) ap->a_data, DMSET);
1093                 break;
1094
1095             case TIOCMBIC:
1096                 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIC);
1097                 break;
1098
1099             case TIOCMBIS:
1100                 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIS);
1101                 break;
1102
1103             case TIOCMSDTRWAIT:
1104                 error = priv_check_cred(ap->a_cred, PRIV_ROOT, 0);
1105                 if (error != 0) {
1106                         crit_exit();
1107                         return (error);
1108                 }
1109                 rc->rc_dtrwait = *(int *)ap->a_data * hz / 100;
1110                 break;
1111
1112             case TIOCMGDTRWAIT:
1113                 *(int *)ap->a_data = rc->rc_dtrwait * 100 / hz;
1114                 break;
1115
1116             default:
1117                 crit_exit();
1118                 return ENOTTY;
1119         }
1120         crit_exit();
1121         return 0;
1122 }
1123
1124
1125 /* Modem control routines */
1126
1127 static int
1128 rc_modctl(struct rc_chans *rc, int bits, int cmd)
1129 {
1130         int    nec = rc->rc_rcb->rcb_addr;
1131         u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1132
1133         rcout(CD180_CAR, rc->rc_chan);
1134
1135         switch (cmd) {
1136             case DMSET:
1137                 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1138                                 ~(*dtr |= 1 << rc->rc_chan) :
1139                                 ~(*dtr &= ~(1 << rc->rc_chan)));
1140                 msvr = rcin(CD180_MSVR);
1141                 if (bits & TIOCM_RTS)
1142                         msvr |= MSVR_RTS;
1143                 else
1144                         msvr &= ~MSVR_RTS;
1145                 if (bits & TIOCM_DTR)
1146                         msvr |= MSVR_DTR;
1147                 else
1148                         msvr &= ~MSVR_DTR;
1149                 rcout(CD180_MSVR, msvr);
1150                 break;
1151
1152             case DMBIS:
1153                 if (bits & TIOCM_DTR)
1154                         rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1155                 msvr = rcin(CD180_MSVR);
1156                 if (bits & TIOCM_RTS)
1157                         msvr |= MSVR_RTS;
1158                 if (bits & TIOCM_DTR)
1159                         msvr |= MSVR_DTR;
1160                 rcout(CD180_MSVR, msvr);
1161                 break;
1162
1163             case DMGET:
1164                 bits = TIOCM_LE;
1165                 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1166
1167                 if (msvr & MSVR_RTS)
1168                         bits |= TIOCM_RTS;
1169                 if (msvr & MSVR_CTS)
1170                         bits |= TIOCM_CTS;
1171                 if (msvr & MSVR_DSR)
1172                         bits |= TIOCM_DSR;
1173                 if (msvr & MSVR_DTR)
1174                         bits |= TIOCM_DTR;
1175                 if (msvr & MSVR_CD)
1176                         bits |= TIOCM_CD;
1177                 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1178                         bits |= TIOCM_RI;
1179                 return bits;
1180
1181             case DMBIC:
1182                 if (bits & TIOCM_DTR)
1183                         rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1184                 msvr = rcin(CD180_MSVR);
1185                 if (bits & TIOCM_RTS)
1186                         msvr &= ~MSVR_RTS;
1187                 if (bits & TIOCM_DTR)
1188                         msvr &= ~MSVR_DTR;
1189                 rcout(CD180_MSVR, msvr);
1190                 break;
1191         }
1192         rc->rc_msvr = rcin(CD180_MSVR);
1193         return 0;
1194 }
1195
1196 /* Test the board. */
1197 int
1198 rc_test(int nec, int unit)
1199 {
1200         int     chan = 0;
1201         int     i = 0, rcnt;
1202         unsigned int    iack, chipid;
1203         unsigned short  divs;
1204         static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1205 #define CTLEN   8
1206 #define ERR(s)  { \
1207                 kprintf("rc%d: ", unit); kprintf s ; kprintf("\n"); \
1208                 crit_exit(); return 1; }
1209
1210         struct rtest {
1211                 u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1212                 u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1213                 int     rxptr;                  /* RX pointer */
1214                 int     txptr;                  /* TX pointer */
1215         } tchans[CD180_NCHAN];
1216
1217         crit_enter();
1218
1219         chipid = RC_FAKEID;
1220
1221         /* First, reset board to inital state */
1222         rc_hwreset(unit, nec, chipid);
1223
1224         divs = RC_BRD(19200);
1225
1226         /* Initialize channels */
1227         for (chan = 0; chan < CD180_NCHAN; chan++) {
1228
1229                 /* Select and reset channel */
1230                 rcout(CD180_CAR, chan);
1231                 CCRCMD(unit, chan, CCR_ResetChan);
1232                 WAITFORCCR(unit, chan);
1233
1234                 /* Set speed */
1235                 rcout(CD180_RBPRL, divs & 0xFF);
1236                 rcout(CD180_RBPRH, divs >> 8);
1237                 rcout(CD180_TBPRL, divs & 0xFF);
1238                 rcout(CD180_TBPRH, divs >> 8);
1239
1240                 /* set timeout value */
1241                 rcout(CD180_RTPR,  0);
1242
1243                 /* Establish local loopback */
1244                 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1245                 rcout(CD180_COR2, COR2_LLM);
1246                 rcout(CD180_COR3, CD180_NFIFO);
1247                 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1248                 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1249                 WAITFORCCR(unit, chan);
1250                 rcout(CD180_MSVR, MSVR_RTS);
1251
1252                 /* Fill TXBUF with test data */
1253                 for (i = 0; i < CD180_NFIFO; i++) {
1254                         tchans[chan].txbuf[i] = ctest[i];
1255                         tchans[chan].rxbuf[i] = 0;
1256                 }
1257                 tchans[chan].txptr = tchans[chan].rxptr = 0;
1258
1259                 /* Now, start transmit */
1260                 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1261         }
1262         /* Pseudo-interrupt poll stuff */
1263         for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1264                 i = ~(rcin(RC_BSR));
1265                 if (i & RC_BSR_TOUT)
1266                         ERR(("BSR timeout bit set\n"))
1267                 else if (i & RC_BSR_TXINT) {
1268                         iack = rcin(RC_PILR_TX);
1269                         if (iack != (GIVR_IT_TDI | chipid))
1270                                 ERR(("Bad TX intr ack (%02x != %02x)\n",
1271                                         iack, GIVR_IT_TDI | chipid));
1272                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1273                         /* If no more data to transmit, disable TX intr */
1274                         if (tchans[chan].txptr >= CD180_NFIFO) {
1275                                 iack = rcin(CD180_IER);
1276                                 rcout(CD180_IER, iack & ~IER_TxMpty);
1277                         } else {
1278                                 for (iack = tchans[chan].txptr;
1279                                     iack < CD180_NFIFO; iack++)
1280                                         rcout(CD180_TDR,
1281                                             tchans[chan].txbuf[iack]);
1282                                 tchans[chan].txptr = iack;
1283                         }
1284                         rcout(CD180_EOIR, 0);
1285                 } else if (i & RC_BSR_RXINT) {
1286                         u_char ucnt;
1287
1288                         iack = rcin(RC_PILR_RX);
1289                         if (iack != (GIVR_IT_RGDI | chipid) &&
1290                             iack != (GIVR_IT_REI  | chipid))
1291                                 ERR(("Bad RX intr ack (%02x != %02x)\n",
1292                                         iack, GIVR_IT_RGDI | chipid))
1293                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1294                         ucnt = rcin(CD180_RDCR) & 0xF;
1295                         while (ucnt-- > 0) {
1296                                 iack = rcin(CD180_RCSR);
1297                                 if (iack & RCSR_Timeout)
1298                                         break;
1299                                 if (iack & 0xF)
1300                                         ERR(("Bad char chan %d (RCSR = %02X)\n",
1301                                             chan, iack))
1302                                 if (tchans[chan].rxptr > CD180_NFIFO)
1303                                         ERR(("Got extra chars chan %d\n",
1304                                             chan))
1305                                 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1306                                         rcin(CD180_RDR);
1307                         }
1308                         rcout(CD180_EOIR, 0);
1309                 }
1310                 rcout(RC_CTOUT, 0);
1311                 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1312                         if (tchans[chan].rxptr >= CD180_NFIFO)
1313                                 iack++;
1314                 if (iack == CD180_NCHAN)
1315                         break;
1316         }
1317         for (chan = 0; chan < CD180_NCHAN; chan++) {
1318                 /* Select and reset channel */
1319                 rcout(CD180_CAR, chan);
1320                 CCRCMD(unit, chan, CCR_ResetChan);
1321         }
1322
1323         if (!rcnt)
1324                 ERR(("looses characters during local loopback\n"))
1325         /* Now, check data */
1326         for (chan = 0; chan < CD180_NCHAN; chan++)
1327                 for (i = 0; i < CD180_NFIFO; i++)
1328                         if (ctest[i] != tchans[chan].rxbuf[i])
1329                                 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1330                                     chan, i, ctest[i], tchans[chan].rxbuf[i]))
1331         crit_exit();
1332         return 0;
1333 }
1334
1335 #ifdef RCDEBUG
1336 static void
1337 printrcflags(struct rc_chans *rc, char *comment)
1338 {
1339         u_short f = rc->rc_flags;
1340         int    nec = rc->rc_rcb->rcb_addr;
1341
1342         kprintf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1343                 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1344                 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1345                 (f & RC_ACTOUT) ?"ACTOUT " :"",
1346                 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1347                 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1348                 (f & RC_DORXFER)?"DORXFER " :"",
1349                 (f & RC_DOXXFER)?"DOXXFER " :"",
1350                 (f & RC_MODCHG) ?"MODCHG "  :"",
1351                 (f & RC_OSUSP)  ?"OSUSP " :"",
1352                 (f & RC_OSBUSY) ?"OSBUSY " :"",
1353                 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1354                 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1355                 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1356
1357         rcout(CD180_CAR, rc->rc_chan);
1358
1359         kprintf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1360                 rc->rc_rcb->rcb_unit, rc->rc_chan,
1361                 rcin(CD180_MSVR),
1362                 rcin(CD180_IER),
1363                 rcin(CD180_CCSR));
1364 }
1365 #endif /* RCDEBUG */
1366
1367 static void
1368 rc_dtrwakeup(void *chan)
1369 {
1370         struct rc_chans  *rc;
1371
1372         rc = (struct rc_chans *)chan;
1373         rc->rc_flags &= ~RC_DTR_OFF;
1374         wakeup(&rc->rc_dtrwait);
1375 }
1376
1377 static void
1378 rc_discard_output(struct rc_chans *rc)
1379 {
1380         cpu_disable_intr();
1381         if (rc->rc_flags & RC_DOXXFER) {
1382                 rc_scheduled_event -= LOTS_OF_EVENTS;
1383                 rc->rc_flags &= ~RC_DOXXFER;
1384         }
1385         rc->rc_optr = rc->rc_obufend;
1386         rc->rc_tp->t_state &= ~TS_BUSY;
1387         cpu_enable_intr();
1388         ttwwakeup(rc->rc_tp);
1389 }
1390
1391 static void
1392 rc_wakeup(void *chan)
1393 {
1394         if (rc_scheduled_event != 0) {
1395                 crit_enter();
1396                 rcpoll(NULL, NULL);
1397                 crit_exit();
1398         }
1399         callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
1400 }
1401
1402 static void
1403 disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc)
1404 {
1405
1406         if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1407             && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1408             && (!(t->c_iflag & PARMRK)
1409                 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1410             && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1411             && linesw[tp->t_line].l_rint == ttyinput)
1412                 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1413         else
1414                 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1415         rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1416 }
1417
1418 static void
1419 rc_wait0(int nec, int unit, int chan, int line)
1420 {
1421         int rcnt;
1422
1423         for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1424                 DELAY(30);
1425         if (rcnt == 0)
1426                 kprintf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1427                       unit, chan, line);
1428 }