sys/dev/netif/sk/if_sk.c

   1 /*
   2  * Copyright (c) 1997, 1998, 1999, 2000
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $
  33  * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
  34  * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.55 2008/03/16 15:50:22 hasso Exp $
  35  */
  36
  37 /*
  38  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  39  *
  40  * Permission to use, copy, modify, and distribute this software for any
  41  * purpose with or without fee is hereby granted, provided that the above
  42  * copyright notice and this permission notice appear in all copies.
  43  *
  44  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  45  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  46  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  47  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  48  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  49  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  50  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  51  */
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71
  72 /*
  73  * The SysKonnect gigabit ethernet adapters consist of two main
  74  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  75  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  76  * components and a PHY while the GEnesis controller provides a PCI
  77  * interface with DMA support. Each card may have between 512K and
  78  * 2MB of SRAM on board depending on the configuration.
  79  *
  80  * The SysKonnect GEnesis controller can have either one or two XMAC
  81  * chips connected to it, allowing single or dual port NIC configurations.
  82  * SysKonnect has the distinction of being the only vendor on the market
  83  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  84  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  85  * XMAC registers. This driver takes advantage of these features to allow
  86  * both XMACs to operate as independent interfaces.
  87  */
  88
  89 #include <sys/param.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/in_cksum.h>
  93 #include <sys/kernel.h>
  94 #include <sys/mbuf.h>
  95 #include <sys/malloc.h>
  96 #include <sys/queue.h>
  97 #include <sys/rman.h>
  98 #include <sys/serialize.h>
  99 #include <sys/socket.h>
 100 #include <sys/sockio.h>
 101 #include <sys/sysctl.h>
 102
 103 #include <net/bpf.h>
 104 #include <net/ethernet.h>
 105 #include <net/if.h>
 106 #include <net/if_arp.h>
 107 #include <net/if_dl.h>
 108 #include <net/if_media.h>
 109 #include <net/ifq_var.h>
 110 #include <net/vlan/if_vlan_var.h>
 111
 112 #include <netinet/ip.h>
 113 #include <netinet/udp.h>
 114
 115 #include <dev/netif/mii_layer/mii.h>
 116 #include <dev/netif/mii_layer/miivar.h>
 117 #include <dev/netif/mii_layer/brgphyreg.h>
 118
 119 #include <bus/pci/pcireg.h>
 120 #include <bus/pci/pcivar.h>
 121 #include <bus/pci/pcidevs.h>
 122
 123 #include <dev/netif/sk/if_skreg.h>
 124 #include <dev/netif/sk/yukonreg.h>
 125 #include <dev/netif/sk/xmaciireg.h>
 126 #include <dev/netif/sk/if_skvar.h>
 127
 128 #include "miibus_if.h"
 129
 130 #if 0
 131 #define SK_DEBUG
 132 #endif
 133
 134 #if 0
 135 #define SK_RXCSUM
 136 #endif
 137
 138 /* supported device vendors */
 139 static const struct skc_type {
 140         uint16_t        skc_vid;
 141         uint16_t        skc_did;
 142         const char      *skc_name;
 143 } skc_devs[] = {
 144         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940,
 145           "3Com 3C940" },
 146         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940B,
 147           "3Com 3C940B" },
 148
 149         { PCI_VENDOR_CNET,              PCI_PRODUCT_CNET_GIGACARD,
 150           "CNet GigaCard" },
 151
 152         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_A1,
 153           "D-Link DGE-530T A1" },
 154         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_B1,
 155           "D-Link DGE-530T B1" },
 156
 157         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1032,
 158           "Linksys EG1032 v2" },
 159         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1064,
 160           "Linksys EG1064" },
 161
 162         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON,
 163           "Marvell Yukon 88E8001/8003/8010" },
 164         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_BELKIN,
 165           "Belkin F5D5005" },
 166
 167         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE,
 168           "SysKonnect SK-NET" },
 169         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2,
 170           "SysKonnect SK9821 v2" },
 171
 172         { 0, 0, NULL }
 173 };
 174
 175 static int      skc_probe(device_t);
 176 static int      skc_attach(device_t);
 177 static int      skc_detach(device_t);
 178 static void     skc_shutdown(device_t);
 179 static int      skc_sysctl_imtime(SYSCTL_HANDLER_ARGS);
 180
 181 static int      sk_probe(device_t);
 182 static int      sk_attach(device_t);
 183 static int      sk_detach(device_t);
 184 static void     sk_tick(void *);
 185 static void     sk_yukon_tick(void *);
 186 static void     sk_intr(void *);
 187 static void     sk_intr_bcom(struct sk_if_softc *);
 188 static void     sk_intr_xmac(struct sk_if_softc *);
 189 static void     sk_intr_yukon(struct sk_if_softc *);
 190 static void     sk_rxeof(struct sk_if_softc *);
 191 static void     sk_txeof(struct sk_if_softc *);
 192 static int      sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *);
 193 static void     sk_start(struct ifnet *);
 194 static int      sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 195 static void     sk_init(void *);
 196 static void     sk_init_xmac(struct sk_if_softc *);
 197 static void     sk_init_yukon(struct sk_if_softc *);
 198 static void     sk_stop(struct sk_if_softc *);
 199 static void     sk_watchdog(struct ifnet *);
 200 static int      sk_ifmedia_upd(struct ifnet *);
 201 static void     sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 202 static void     sk_reset(struct sk_softc *);
 203 static int      sk_newbuf_jumbo(struct sk_if_softc *, int, int);
 204 static int      sk_newbuf_std(struct sk_if_softc *, int, int);
 205 static int      sk_jpool_alloc(device_t);
 206 static void     sk_jpool_free(struct sk_if_softc *);
 207 static struct sk_jpool_entry
 208                 *sk_jalloc(struct sk_if_softc *);
 209 static void     sk_jfree(void *);
 210 static void     sk_jref(void *);
 211 static int      sk_init_rx_ring(struct sk_if_softc *);
 212 static int      sk_init_tx_ring(struct sk_if_softc *);
 213
 214 static int      sk_miibus_readreg(device_t, int, int);
 215 static int      sk_miibus_writereg(device_t, int, int, int);
 216 static void     sk_miibus_statchg(device_t);
 217
 218 static int      sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 219 static int      sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
 220 static void     sk_xmac_miibus_statchg(struct sk_if_softc *);
 221
 222 static int      sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 223 static int      sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
 224 static void     sk_marv_miibus_statchg(struct sk_if_softc *);
 225
 226 static void     sk_setfilt(struct sk_if_softc *, caddr_t, int);
 227 static void     sk_setmulti(struct sk_if_softc *);
 228 static void     sk_setpromisc(struct sk_if_softc *);
 229
 230 #ifdef SK_RXCSUM
 231 static void     sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t,
 232                           const uint16_t);
 233 #endif
 234 static int      sk_dma_alloc(device_t);
 235 static void     sk_dma_free(device_t);
 236
 237 static void     sk_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
 238                                 int);
 239 static void     sk_dmamem_addr(void *, bus_dma_segment_t *, int, int);
 240
 241 #ifdef SK_DEBUG
 242 #define DPRINTF(x)      if (skdebug) kprintf x
 243 #define DPRINTFN(n,x)   if (skdebug >= (n)) kprintf x
 244 static int      skdebug = 2;
 245
 246 static void     sk_dump_txdesc(struct sk_tx_desc *, int);
 247 static void     sk_dump_mbuf(struct mbuf *);
 248 static void     sk_dump_bytes(const char *, int);
 249 #else
 250 #define DPRINTF(x)
 251 #define DPRINTFN(n,x)
 252 #endif
 253
 254 /* Interrupt moderation time. */
 255 static int      skc_imtime = SK_IMTIME_DEFAULT;
 256 TUNABLE_INT("hw.skc.imtime", &skc_imtime);
 257
 258 /*
 259  * Note that we have newbus methods for both the GEnesis controller
 260  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 261  * the miibus code is a child of the XMACs. We need to do it this way
 262  * so that the miibus drivers can access the PHY registers on the
 263  * right PHY. It's not quite what I had in mind, but it's the only
 264  * design that achieves the desired effect.
 265  */
 266 static device_method_t skc_methods[] = {
 267         /* Device interface */
 268         DEVMETHOD(device_probe,         skc_probe),
 269         DEVMETHOD(device_attach,        skc_attach),
 270         DEVMETHOD(device_detach,        skc_detach),
 271         DEVMETHOD(device_shutdown,      skc_shutdown),
 272
 273         /* bus interface */
 274         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 275         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 276
 277         { 0, 0 }
 278 };
 279
 280 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
 281 static devclass_t skc_devclass;
 282
 283 static device_method_t sk_methods[] = {
 284         /* Device interface */
 285         DEVMETHOD(device_probe,         sk_probe),
 286         DEVMETHOD(device_attach,        sk_attach),
 287         DEVMETHOD(device_detach,        sk_detach),
 288         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 289
 290         /* bus interface */
 291         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 292         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 293
 294         /* MII interface */
 295         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 296         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 297         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 298
 299         { 0, 0 }
 300 };
 301
 302 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
 303 static devclass_t sk_devclass;
 304
 305 DECLARE_DUMMY_MODULE(if_sk);
 306 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
 307 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
 308 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 309
 310 static __inline uint32_t
 311 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
 312 {
 313         return CSR_READ_4(sc, reg);
 314 }
 315
 316 static __inline uint16_t
 317 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
 318 {
 319         return CSR_READ_2(sc, reg);
 320 }
 321
 322 static __inline uint8_t
 323 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
 324 {
 325         return CSR_READ_1(sc, reg);
 326 }
 327
 328 static __inline void
 329 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
 330 {
 331         CSR_WRITE_4(sc, reg, x);
 332 }
 333
 334 static __inline void
 335 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
 336 {
 337         CSR_WRITE_2(sc, reg, x);
 338 }
 339
 340 static __inline void
 341 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
 342 {
 343         CSR_WRITE_1(sc, reg, x);
 344 }
 345
 346 static __inline int
 347 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait)
 348 {
 349         int ret;
 350
 351         if (sc_if->sk_use_jumbo)
 352                 ret = sk_newbuf_jumbo(sc_if, idx, wait);
 353         else
 354                 ret = sk_newbuf_std(sc_if, idx, wait);
 355         return ret;
 356 }
 357
 358 static int
 359 sk_miibus_readreg(device_t dev, int phy, int reg)
 360 {
 361         struct sk_if_softc *sc_if = device_get_softc(dev);
 362
 363         if (SK_IS_GENESIS(sc_if->sk_softc))
 364                 return sk_xmac_miibus_readreg(sc_if, phy, reg);
 365         else
 366                 return sk_marv_miibus_readreg(sc_if, phy, reg);
 367 }
 368
 369 static int
 370 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
 371 {
 372         struct sk_if_softc *sc_if = device_get_softc(dev);
 373
 374         if (SK_IS_GENESIS(sc_if->sk_softc))
 375                 return sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 376         else
 377                 return sk_marv_miibus_writereg(sc_if, phy, reg, val);
 378 }
 379
 380 static void
 381 sk_miibus_statchg(device_t dev)
 382 {
 383         struct sk_if_softc *sc_if = device_get_softc(dev);
 384
 385         if (SK_IS_GENESIS(sc_if->sk_softc))
 386                 sk_xmac_miibus_statchg(sc_if);
 387         else
 388                 sk_marv_miibus_statchg(sc_if);
 389 }
 390
 391 static int
 392 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
 393 {
 394         int i;
 395
 396         DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
 397
 398         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 399                 return(0);
 400
 401         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 402         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 403         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 404                 for (i = 0; i < SK_TIMEOUT; i++) {
 405                         DELAY(1);
 406                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 407                             XM_MMUCMD_PHYDATARDY)
 408                                 break;
 409                 }
 410
 411                 if (i == SK_TIMEOUT) {
 412                         if_printf(&sc_if->arpcom.ac_if,
 413                                   "phy failed to come ready\n");
 414                         return(0);
 415                 }
 416         }
 417         DELAY(1);
 418         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 419 }
 420
 421 static int
 422 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
 423 {
 424         int i;
 425
 426         DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
 427
 428         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 429         for (i = 0; i < SK_TIMEOUT; i++) {
 430                 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
 431                         break;
 432         }
 433
 434         if (i == SK_TIMEOUT) {
 435                 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
 436                 return(ETIMEDOUT);
 437         }
 438
 439         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 440         for (i = 0; i < SK_TIMEOUT; i++) {
 441                 DELAY(1);
 442                 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
 443                         break;
 444         }
 445
 446         if (i == SK_TIMEOUT)
 447                 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
 448         return(0);
 449 }
 450
 451 static void
 452 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
 453 {
 454         struct mii_data *mii;
 455
 456         mii = device_get_softc(sc_if->sk_miibus);
 457         DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
 458
 459         /*
 460          * If this is a GMII PHY, manually set the XMAC's
 461          * duplex mode accordingly.
 462          */
 463         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 464                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 465                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 466                 else
 467                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 468         }
 469 }
 470
 471 static int
 472 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
 473 {
 474         uint16_t val;
 475         int i;
 476
 477         if (phy != 0 ||
 478             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 479              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 480                 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
 481                              phy, reg));
 482                 return(0);
 483         }
 484
 485         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 486                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 487
 488         for (i = 0; i < SK_TIMEOUT; i++) {
 489                 DELAY(1);
 490                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 491                 if (val & YU_SMICR_READ_VALID)
 492                         break;
 493         }
 494
 495         if (i == SK_TIMEOUT) {
 496                 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
 497                 return(0);
 498         }
 499
 500         DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
 501                      SK_TIMEOUT));
 502
 503         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 504
 505         DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
 506                      phy, reg, val));
 507
 508         return(val);
 509 }
 510
 511 static int
 512 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
 513 {
 514         int i;
 515
 516         DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
 517                      phy, reg, val));
 518
 519         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 520         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 521                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 522
 523         for (i = 0; i < SK_TIMEOUT; i++) {
 524                 DELAY(1);
 525                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 526                         break;
 527         }
 528
 529         if (i == SK_TIMEOUT)
 530                 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
 531
 532         return(0);
 533 }
 534
 535 static void
 536 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
 537 {
 538         DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
 539                      SK_YU_READ_2(sc_if, YUKON_GPCR)));
 540 }
 541
 542 #define HASH_BITS       6
 543
 544 static uint32_t
 545 sk_xmac_hash(caddr_t addr)
 546 {
 547         uint32_t crc;
 548
 549         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 550         return (~crc & ((1 << HASH_BITS) - 1));
 551 }
 552
 553 static uint32_t
 554 sk_yukon_hash(caddr_t addr)
 555 {
 556         uint32_t crc;
 557
 558         crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
 559         return (crc & ((1 << HASH_BITS) - 1));
 560 }
 561
 562 static void
 563 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
 564 {
 565         int base;
 566
 567         base = XM_RXFILT_ENTRY(slot);
 568
 569         SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
 570         SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
 571         SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
 572 }
 573
 574 static void
 575 sk_setmulti(struct sk_if_softc *sc_if)
 576 {
 577         struct sk_softc *sc = sc_if->sk_softc;
 578         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 579         uint32_t hashes[2] = { 0, 0 };
 580         int h = 0, i;
 581         struct ifmultiaddr *ifma;
 582         uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
 583
 584         /* First, zot all the existing filters. */
 585         switch(sc->sk_type) {
 586         case SK_GENESIS:
 587                 for (i = 1; i < XM_RXFILT_MAX; i++)
 588                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 589
 590                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 591                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 592                 break;
 593         case SK_YUKON:
 594         case SK_YUKON_LITE:
 595         case SK_YUKON_LP:
 596                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 597                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 598                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 599                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 600                 break;
 601         }
 602
 603         /* Now program new ones. */
 604         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 605                 hashes[0] = 0xFFFFFFFF;
 606                 hashes[1] = 0xFFFFFFFF;
 607         } else {
 608                 i = 1;
 609                 /* First find the tail of the list. */
 610                 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 611                         if (ifma->ifma_link.le_next == NULL)
 612                                 break;
 613                 }
 614                 /* Now traverse the list backwards. */
 615                 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
 616                         ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
 617                         caddr_t maddr;
 618
 619                         if (ifma->ifma_addr->sa_family != AF_LINK)
 620                                 continue;
 621
 622                         maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
 623
 624                         /*
 625                          * Program the first XM_RXFILT_MAX multicast groups
 626                          * into the perfect filter. For all others,
 627                          * use the hash table.
 628                          */
 629                         if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
 630                                 sk_setfilt(sc_if, maddr, i);
 631                                 i++;
 632                                 continue;
 633                         }
 634
 635                         switch(sc->sk_type) {
 636                         case SK_GENESIS:
 637                                 h = sk_xmac_hash(maddr);
 638                                 break;
 639
 640                         case SK_YUKON:
 641                         case SK_YUKON_LITE:
 642                         case SK_YUKON_LP:
 643                                 h = sk_yukon_hash(maddr);
 644                                 break;
 645                         }
 646                         if (h < 32)
 647                                 hashes[0] |= (1 << h);
 648                         else
 649                                 hashes[1] |= (1 << (h - 32));
 650                 }
 651         }
 652
 653         switch(sc->sk_type) {
 654         case SK_GENESIS:
 655                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 656                                XM_MODE_RX_USE_PERFECT);
 657                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 658                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 659                 break;
 660         case SK_YUKON:
 661         case SK_YUKON_LITE:
 662         case SK_YUKON_LP:
 663                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 664                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 665                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 666                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 667                 break;
 668         }
 669 }
 670
 671 static void
 672 sk_setpromisc(struct sk_if_softc *sc_if)
 673 {
 674         struct sk_softc *sc = sc_if->sk_softc;
 675         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 676
 677         switch(sc->sk_type) {
 678         case SK_GENESIS:
 679                 if (ifp->if_flags & IFF_PROMISC)
 680                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 681                 else
 682                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 683                 break;
 684         case SK_YUKON:
 685         case SK_YUKON_LITE:
 686         case SK_YUKON_LP:
 687                 if (ifp->if_flags & IFF_PROMISC) {
 688                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 689                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 690                 } else {
 691                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 692                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 693                 }
 694                 break;
 695         }
 696 }
 697
 698 static int
 699 sk_init_rx_ring(struct sk_if_softc *sc_if)
 700 {
 701         struct sk_chain_data *cd = &sc_if->sk_cdata;
 702         struct sk_ring_data *rd = sc_if->sk_rdata;
 703         int i, nexti, error;
 704
 705         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 706
 707         for (i = 0; i < SK_RX_RING_CNT; i++) {
 708                 if (i == (SK_RX_RING_CNT - 1))
 709                         nexti = 0;
 710                 else
 711                         nexti = i + 1;
 712                 rd->sk_rx_ring[i].sk_next =
 713                         htole32(SK_RX_RING_ADDR(sc_if, nexti));
 714                 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
 715                 rd->sk_rx_ring[i].sk_csum2_start =
 716                         htole16(ETHER_HDR_LEN + sizeof(struct ip));
 717
 718                 error = sk_newbuf(sc_if, i, 1);
 719                 if (error) {
 720                         if_printf(&sc_if->arpcom.ac_if,
 721                                   "failed alloc of %dth mbuf\n", i);
 722                         return error;
 723                 }
 724         }
 725
 726         cd->sk_rx_prod = 0;
 727         cd->sk_rx_cons = 0;
 728
 729         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
 730                         BUS_DMASYNC_PREWRITE);
 731
 732         return (0);
 733 }
 734
 735 static int
 736 sk_init_tx_ring(struct sk_if_softc *sc_if)
 737 {
 738         struct sk_ring_data *rd = sc_if->sk_rdata;
 739         int i, nexti;
 740
 741         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 742
 743         for (i = 0; i < SK_TX_RING_CNT; i++) {
 744                 if (i == (SK_TX_RING_CNT - 1))
 745                         nexti = 0;
 746                 else
 747                         nexti = i + 1;
 748                 rd->sk_tx_ring[i].sk_next = htole32(SK_TX_RING_ADDR(sc_if, nexti));
 749         }
 750
 751         sc_if->sk_cdata.sk_tx_prod = 0;
 752         sc_if->sk_cdata.sk_tx_cons = 0;
 753         sc_if->sk_cdata.sk_tx_cnt = 0;
 754
 755         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
 756                         BUS_DMASYNC_PREWRITE);
 757
 758         return (0);
 759 }
 760
 761 static int
 762 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait)
 763 {
 764         struct sk_jpool_entry *entry;
 765         struct mbuf *m_new = NULL;
 766         struct sk_rx_desc *r;
 767
 768         KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
 769
 770         MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 771         if (m_new == NULL)
 772                 return ENOBUFS;
 773
 774         /* Allocate the jumbo buffer */
 775         entry = sk_jalloc(sc_if);
 776         if (entry == NULL) {
 777                 m_freem(m_new);
 778                 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
 779                     "dropped!\n", sc_if->arpcom.ac_if.if_xname));
 780                 return ENOBUFS;
 781         }
 782
 783         m_new->m_ext.ext_arg = entry;
 784         m_new->m_ext.ext_buf = entry->buf;
 785         m_new->m_ext.ext_free = sk_jfree;
 786         m_new->m_ext.ext_ref = sk_jref;
 787         m_new->m_ext.ext_size = SK_JLEN;
 788
 789         m_new->m_flags |= M_EXT;
 790
 791         m_new->m_data = m_new->m_ext.ext_buf;
 792         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 793
 794         /*
 795          * Adjust alignment so packet payload begins on a
 796          * longword boundary. Mandatory for Alpha, useful on
 797          * x86 too.
 798          */
 799         m_adj(m_new, ETHER_ALIGN);
 800
 801         sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new;
 802
 803         r = &sc_if->sk_rdata->sk_rx_ring[idx];
 804         r->sk_data_lo = htole32(entry->paddr + ETHER_ALIGN);
 805         r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
 806
 807         return 0;
 808 }
 809
 810 static int
 811 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait)
 812 {
 813         struct mbuf *m_new = NULL;
 814         struct sk_chain_data *cd = &sc_if->sk_cdata;
 815         struct sk_rx_desc *r;
 816         struct sk_dma_ctx ctx;
 817         bus_dma_segment_t seg;
 818         bus_dmamap_t map;
 819         int error;
 820
 821         KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
 822
 823         m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 824         if (m_new == NULL)
 825                 return ENOBUFS;
 826
 827         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 828
 829         /*
 830          * Adjust alignment so packet payload begins on a
 831          * longword boundary. Mandatory for Alpha, useful on
 832          * x86 too.
 833          */
 834         m_adj(m_new, ETHER_ALIGN);
 835
 836         bzero(&ctx, sizeof(ctx));
 837         ctx.nsegs = 1;
 838         ctx.segs = &seg;
 839         error = bus_dmamap_load_mbuf(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp,
 840                                      m_new, sk_buf_dma_addr, &ctx,
 841                                      wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
 842         if (error) {
 843                 if_printf(&sc_if->arpcom.ac_if, "could not map RX mbuf\n");
 844                 m_freem(m_new);
 845                 return error;
 846         }
 847
 848         /* Unload originally mapped mbuf */
 849         if (cd->sk_rx_mbuf[idx] != NULL)
 850                 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]);
 851
 852         /* Switch DMA map with tmp DMA map */
 853         map = cd->sk_rx_dmap_tmp;
 854         cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx];
 855         cd->sk_rx_dmap[idx] = map;
 856
 857         cd->sk_rx_mbuf[idx] = m_new;
 858
 859         r = &sc_if->sk_rdata->sk_rx_ring[idx];
 860         r->sk_data_lo = htole32(seg.ds_addr);
 861         r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
 862
 863         return 0;
 864 }
 865
 866 /*
 867  * Allocate a jumbo buffer.
 868  */
 869 struct sk_jpool_entry *
 870 sk_jalloc(struct sk_if_softc *sc_if)
 871 {
 872         struct sk_chain_data *cd = &sc_if->sk_cdata;
 873         struct sk_jpool_entry *entry;
 874
 875         lwkt_serialize_enter(&cd->sk_jpool_serializer);
 876
 877         entry = SLIST_FIRST(&cd->sk_jpool_free_ent);
 878         if (entry != NULL) {
 879                 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next);
 880                 entry->inuse = 1;
 881         } else {
 882                 DPRINTF(("no free jumbo buffer\n"));
 883         }
 884
 885         lwkt_serialize_exit(&cd->sk_jpool_serializer);
 886         return entry;
 887 }
 888
 889 /*
 890  * Release a jumbo buffer.
 891  */
 892 void
 893 sk_jfree(void *arg)
 894 {
 895         struct sk_jpool_entry *entry = arg;
 896         struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
 897
 898         if (&cd->sk_jpool_ent[entry->slot] != entry)
 899                 panic("%s: free wrong jumbo buffer\n", __func__);
 900         else if (entry->inuse == 0)
 901                 panic("%s: jumbo buffer already freed\n", __func__);
 902
 903         lwkt_serialize_enter(&cd->sk_jpool_serializer);
 904
 905         atomic_subtract_int(&entry->inuse, 1);
 906         if (entry->inuse == 0)
 907                 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
 908
 909         lwkt_serialize_exit(&cd->sk_jpool_serializer);
 910 }
 911
 912 static void
 913 sk_jref(void *arg)
 914 {
 915         struct sk_jpool_entry *entry = arg;
 916         struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
 917
 918         if (&cd->sk_jpool_ent[entry->slot] != entry)
 919                 panic("%s: free wrong jumbo buffer\n", __func__);
 920         else if (entry->inuse == 0)
 921                 panic("%s: jumbo buffer already freed\n", __func__);
 922
 923         atomic_add_int(&entry->inuse, 1);
 924 }
 925
 926 /*
 927  * Set media options.
 928  */
 929 static int
 930 sk_ifmedia_upd(struct ifnet *ifp)
 931 {
 932         struct sk_if_softc *sc_if = ifp->if_softc;
 933         struct mii_data *mii;
 934
 935         mii = device_get_softc(sc_if->sk_miibus);
 936         sk_init(sc_if);
 937         mii_mediachg(mii);
 938
 939         return(0);
 940 }
 941
 942 /*
 943  * Report current media status.
 944  */
 945 static void
 946 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 947 {
 948         struct sk_if_softc *sc_if;
 949         struct mii_data *mii;
 950
 951         sc_if = ifp->if_softc;
 952         mii = device_get_softc(sc_if->sk_miibus);
 953
 954         mii_pollstat(mii);
 955         ifmr->ifm_active = mii->mii_media_active;
 956         ifmr->ifm_status = mii->mii_media_status;
 957 }
 958
 959 static int
 960 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 961 {
 962         struct sk_if_softc *sc_if = ifp->if_softc;
 963         struct ifreq *ifr = (struct ifreq *)data;
 964         struct mii_data *mii;
 965         int error = 0;
 966
 967         ASSERT_SERIALIZED(ifp->if_serializer);
 968
 969         switch(command) {
 970         case SIOCSIFMTU:
 971                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
 972                         error = EINVAL;
 973                 else {
 974                         ifp->if_mtu = ifr->ifr_mtu;
 975                         ifp->if_flags &= ~IFF_RUNNING;
 976                         sk_init(sc_if);
 977                 }
 978                 break;
 979         case SIOCSIFFLAGS:
 980                 if (ifp->if_flags & IFF_UP) {
 981                         if (ifp->if_flags & IFF_RUNNING) {
 982                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
 983                                     & IFF_PROMISC) {
 984                                         sk_setpromisc(sc_if);
 985                                         sk_setmulti(sc_if);
 986                                 }
 987                         } else
 988                                 sk_init(sc_if);
 989                 } else {
 990                         if (ifp->if_flags & IFF_RUNNING)
 991                                 sk_stop(sc_if);
 992                 }
 993                 sc_if->sk_if_flags = ifp->if_flags;
 994                 break;
 995         case SIOCADDMULTI:
 996         case SIOCDELMULTI:
 997                 sk_setmulti(sc_if);
 998                 break;
 999         case SIOCGIFMEDIA:
1000         case SIOCSIFMEDIA:
1001                 mii = device_get_softc(sc_if->sk_miibus);
1002                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1003                 break;
1004         default:
1005                 error = ether_ioctl(ifp, command, data);
1006                 break;
1007         }
1008
1009         return(error);
1010 }
1011
1012 /*
1013  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1014  * IDs against our list and return a device name if we find a match.
1015  */
1016 static int
1017 skc_probe(device_t dev)
1018 {
1019         const struct skc_type *t;
1020         uint16_t vid, did;
1021
1022         vid = pci_get_vendor(dev);
1023         did = pci_get_device(dev);
1024
1025         /*
1026          * Only attach to rev.2 of the Linksys EG1032 adapter.
1027          * Rev.3 is supported by re(4).
1028          */
1029         if (vid == PCI_VENDOR_LINKSYS &&
1030             did == PCI_PRODUCT_LINKSYS_EG1032 &&
1031             pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2)
1032                 return ENXIO;
1033
1034         for (t = skc_devs; t->skc_name != NULL; t++) {
1035                 if (vid == t->skc_vid && did == t->skc_did) {
1036                         device_set_desc(dev, t->skc_name);
1037                         return 0;
1038                 }
1039         }
1040         return ENXIO;
1041 }
1042
1043 /*
1044  * Force the GEnesis into reset, then bring it out of reset.
1045  */
1046 static void
1047 sk_reset(struct sk_softc *sc)
1048 {
1049         DPRINTFN(2, ("sk_reset\n"));
1050
1051         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1052         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1053         if (SK_IS_YUKON(sc))
1054                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1055
1056         DELAY(1000);
1057         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1058         DELAY(2);
1059         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1060         if (SK_IS_YUKON(sc))
1061                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1062
1063         DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1064         DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1065                      CSR_READ_2(sc, SK_LINK_CTRL)));
1066
1067         if (SK_IS_GENESIS(sc)) {
1068                 /* Configure packet arbiter */
1069                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1070                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1071                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1072                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1073                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1074         }
1075
1076         /* Enable RAM interface */
1077         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1078
1079         /*
1080          * Configure interrupt moderation. The moderation timer
1081          * defers interrupts specified in the interrupt moderation
1082          * timer mask based on the timeout specified in the interrupt
1083          * moderation timer init register. Each bit in the timer
1084          * register represents one tick, so to specify a timeout in
1085          * microseconds, we have to multiply by the correct number of
1086          * ticks-per-microsecond.
1087          */
1088         KKASSERT(sc->sk_imtimer_ticks != 0 && sc->sk_imtime != 0);
1089         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc, sc->sk_imtime));
1090         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1091             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1092         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1093 }
1094
1095 static int
1096 sk_probe(device_t dev)
1097 {
1098         struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1099         const char *revstr = "", *name = NULL;
1100         char devname[80];
1101
1102         switch (sc->sk_type) {
1103         case SK_GENESIS:
1104                 name = "SysKonnect GEnesis";
1105                 break;
1106         case SK_YUKON:
1107                 name = "Marvell Yukon";
1108                 break;
1109         case SK_YUKON_LITE:
1110                 name = "Marvell Yukon Lite";
1111                 switch (sc->sk_rev) {
1112                 case SK_YUKON_LITE_REV_A0:
1113                         revstr = " rev.A0";
1114                         break;
1115                 case SK_YUKON_LITE_REV_A1:
1116                         revstr = " rev.A1";
1117                         break;
1118                 case SK_YUKON_LITE_REV_A3:
1119                         revstr = " rev.A3";
1120                         break;
1121                 }
1122                 break;
1123         case SK_YUKON_LP:
1124                 name = "Marvell Yukon LP";
1125                 break;
1126         default:
1127                 return ENXIO;
1128         }
1129
1130         ksnprintf(devname, sizeof(devname), "%s%s (0x%x)",
1131                  name, revstr, sc->sk_rev);
1132         device_set_desc_copy(dev, devname);
1133         return 0;
1134 }
1135
1136 /*
1137  * Each XMAC chip is attached as a separate logical IP interface.
1138  * Single port cards will have only one logical interface of course.
1139  */
1140 static int
1141 sk_attach(device_t dev)
1142 {
1143         struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1144         struct sk_if_softc *sc_if = device_get_softc(dev);
1145         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1146         int i, error;
1147
1148         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1149
1150         sc_if->sk_port = *(int *)device_get_ivars(dev);
1151         KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B);
1152
1153         sc_if->sk_softc = sc;
1154         sc->sk_if[sc_if->sk_port] = sc_if;
1155
1156         kfree(device_get_ivars(dev), M_DEVBUF);
1157         device_set_ivars(dev, NULL);
1158
1159         if (sc_if->sk_port == SK_PORT_A)
1160                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1161         if (sc_if->sk_port == SK_PORT_B)
1162                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1163
1164         DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1165
1166         /*
1167          * Get station address for this interface. Note that
1168          * dual port cards actually come with three station
1169          * addresses: one for each port, plus an extra. The
1170          * extra one is used by the SysKonnect driver software
1171          * as a 'virtual' station address for when both ports
1172          * are operating in failover mode. Currently we don't
1173          * use this extra address.
1174          */
1175         for (i = 0; i < ETHER_ADDR_LEN; i++) {
1176                 /* XXX */
1177                 sc_if->arpcom.ac_enaddr[i] =
1178                     sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i);
1179         }
1180
1181         /*
1182          * Set up RAM buffer addresses. The NIC will have a certain
1183          * amount of SRAM on it, somewhere between 512K and 2MB. We
1184          * need to divide this up a) between the transmitter and
1185          * receiver and b) between the two XMACs, if this is a
1186          * dual port NIC. Our algorithm is to divide up the memory
1187          * evenly so that everyone gets a fair share.
1188          */
1189         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1190                 uint32_t chunk, val;
1191
1192                 chunk = sc->sk_ramsize / 2;
1193                 val = sc->sk_rboff / sizeof(uint64_t);
1194                 sc_if->sk_rx_ramstart = val;
1195                 val += (chunk / sizeof(uint64_t));
1196                 sc_if->sk_rx_ramend = val - 1;
1197                 sc_if->sk_tx_ramstart = val;
1198                 val += (chunk / sizeof(uint64_t));
1199                 sc_if->sk_tx_ramend = val - 1;
1200         } else {
1201                 uint32_t chunk, val;
1202
1203                 chunk = sc->sk_ramsize / 4;
1204                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1205                     sizeof(uint64_t);
1206                 sc_if->sk_rx_ramstart = val;
1207                 val += (chunk / sizeof(uint64_t));
1208                 sc_if->sk_rx_ramend = val - 1;
1209                 sc_if->sk_tx_ramstart = val;
1210                 val += (chunk / sizeof(uint64_t));
1211                 sc_if->sk_tx_ramend = val - 1;
1212         }
1213
1214         DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1215                      "           tx_ramstart=%#x tx_ramend=%#x\n",
1216                      sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1217                      sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1218
1219         /* Read and save PHY type */
1220         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1221
1222         /* Set PHY address */
1223         if (SK_IS_GENESIS(sc)) {
1224                 switch (sc_if->sk_phytype) {
1225                 case SK_PHYTYPE_XMAC:
1226                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1227                         break;
1228                 case SK_PHYTYPE_BCOM:
1229                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1230                         break;
1231                 default:
1232                         device_printf(dev, "unsupported PHY type: %d\n",
1233                             sc_if->sk_phytype);
1234                         error = ENXIO;
1235                         goto fail;
1236                 }
1237         }
1238
1239         if (SK_IS_YUKON(sc)) {
1240                 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1241                     sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
1242                         /* not initialized, punt */
1243                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1244                         sc->sk_coppertype = 1;
1245                 }
1246
1247                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1248
1249                 if (!(sc->sk_coppertype))
1250                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1251         }
1252
1253         error = sk_dma_alloc(dev);
1254         if (error)
1255                 goto fail;
1256
1257         ifp->if_softc = sc_if;
1258         ifp->if_mtu = ETHERMTU;
1259         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1260         ifp->if_ioctl = sk_ioctl;
1261         ifp->if_start = sk_start;
1262         ifp->if_watchdog = sk_watchdog;
1263         ifp->if_init = sk_init;
1264         ifp->if_baudrate = 1000000000;
1265         ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1266         ifq_set_ready(&ifp->if_snd);
1267
1268         ifp->if_capabilities = IFCAP_VLAN_MTU;
1269
1270         /* Don't use jumbo buffers by default */
1271         sc_if->sk_use_jumbo = 0;
1272
1273         /*
1274          * Do miibus setup.
1275          */
1276         switch (sc->sk_type) {
1277         case SK_GENESIS:
1278                 sk_init_xmac(sc_if);
1279                 break;
1280         case SK_YUKON:
1281         case SK_YUKON_LITE:
1282         case SK_YUKON_LP:
1283                 sk_init_yukon(sc_if);
1284                 break;
1285         default:
1286                 device_printf(dev, "unknown device type %d\n", sc->sk_type);
1287                 error = ENXIO;
1288                 goto fail;
1289         }
1290
1291         DPRINTFN(2, ("sk_attach: 1\n"));
1292
1293         error = mii_phy_probe(dev, &sc_if->sk_miibus,
1294                               sk_ifmedia_upd, sk_ifmedia_sts);
1295         if (error) {
1296                 device_printf(dev, "no PHY found!\n");
1297                 goto fail;
1298         }
1299
1300         callout_init(&sc_if->sk_tick_timer);
1301
1302         /*
1303          * Call MI attach routines.
1304          */
1305         ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer);
1306
1307         DPRINTFN(2, ("sk_attach: end\n"));
1308         return 0;
1309 fail:
1310         sk_detach(dev);
1311         sc->sk_if[sc_if->sk_port] = NULL;
1312         return error;
1313 }
1314
1315 /*
1316  * Attach the interface. Allocate softc structures, do ifmedia
1317  * setup and ethernet/BPF attach.
1318  */
1319 static int
1320 skc_attach(device_t dev)
1321 {
1322         struct sk_softc *sc = device_get_softc(dev);
1323         uint8_t skrs;
1324         int *port;
1325         int error;
1326
1327         DPRINTFN(2, ("begin skc_attach\n"));
1328
1329         sc->sk_dev = dev;
1330         lwkt_serialize_init(&sc->sk_serializer);
1331
1332 #ifndef BURN_BRIDGES
1333         /*
1334          * Handle power management nonsense.
1335          */
1336         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1337                 uint32_t iobase, membase, irq;
1338
1339                 /* Save important PCI config data. */
1340                 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1341                 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1342                 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1343
1344                 /* Reset the power state. */
1345                 device_printf(dev, "chip is in D%d power mode "
1346                               "-- setting to D0\n", pci_get_powerstate(dev));
1347
1348                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1349
1350                 /* Restore PCI config data. */
1351                 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1352                 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1353                 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1354         }
1355 #endif  /* BURN_BRIDGES */
1356
1357         /*
1358          * Map control/status registers.
1359          */
1360         pci_enable_busmaster(dev);
1361
1362         sc->sk_res_rid = SK_PCI_LOMEM;
1363         sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1364                                             &sc->sk_res_rid, RF_ACTIVE);
1365         if (sc->sk_res == NULL) {
1366                 device_printf(dev, "couldn't map memory\n");
1367                 error = ENXIO;
1368                 goto fail;
1369         }
1370         sc->sk_btag = rman_get_bustag(sc->sk_res);
1371         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1372
1373         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1374         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1375
1376         /* Bail out here if chip is not recognized */
1377         if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) {
1378                 device_printf(dev, "unknown chip type: %d\n", sc->sk_type);
1379                 error = ENXIO;
1380                 goto fail;
1381         }
1382
1383         DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1384
1385         /* Allocate interrupt */
1386         sc->sk_irq_rid = 0;
1387         sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid,
1388                                             RF_SHAREABLE | RF_ACTIVE);
1389         if (sc->sk_irq == NULL) {
1390                 device_printf(dev, "couldn't map interrupt\n");
1391                 error = ENXIO;
1392                 goto fail;
1393         }
1394
1395         switch (sc->sk_type) {
1396         case SK_GENESIS:
1397                 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1398                 break;
1399         default:
1400                 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1401                 break;
1402         }
1403         sc->sk_imtime = skc_imtime;
1404
1405         /* Reset the adapter. */
1406         sk_reset(sc);
1407
1408         skrs = sk_win_read_1(sc, SK_EPROM0);
1409         if (SK_IS_GENESIS(sc)) {
1410                 /* Read and save RAM size and RAMbuffer offset */
1411                 switch(skrs) {
1412                 case SK_RAMSIZE_512K_64:
1413                         sc->sk_ramsize = 0x80000;
1414                         sc->sk_rboff = SK_RBOFF_0;
1415                         break;
1416                 case SK_RAMSIZE_1024K_64:
1417                         sc->sk_ramsize = 0x100000;
1418                         sc->sk_rboff = SK_RBOFF_80000;
1419                         break;
1420                 case SK_RAMSIZE_1024K_128:
1421                         sc->sk_ramsize = 0x100000;
1422                         sc->sk_rboff = SK_RBOFF_0;
1423                         break;
1424                 case SK_RAMSIZE_2048K_128:
1425                         sc->sk_ramsize = 0x200000;
1426                         sc->sk_rboff = SK_RBOFF_0;
1427                         break;
1428                 default:
1429                         device_printf(dev, "unknown ram size: %d\n", skrs);
1430                         error = ENXIO;
1431                         goto fail;
1432                 }
1433         } else {
1434                 if (skrs == 0x00)
1435                         sc->sk_ramsize = 0x20000;
1436                 else
1437                         sc->sk_ramsize = skrs * (1<<12);
1438                 sc->sk_rboff = SK_RBOFF_0;
1439         }
1440
1441         DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1442                      sc->sk_ramsize, sc->sk_ramsize / 1024,
1443                      sc->sk_rboff));
1444
1445         /* Read and save physical media type */
1446         sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1447
1448         if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1449                 sc->sk_coppertype = 1;
1450         else
1451                 sc->sk_coppertype = 0;
1452
1453         /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1454         if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1455                 uint32_t flashaddr;
1456                 uint8_t testbyte;
1457
1458                 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1459
1460                 /* Test Flash-Address Register */
1461                 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1462                 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1463
1464                 if (testbyte != 0) {
1465                         /* This is a Yukon Lite Rev A0 */
1466                         sc->sk_type = SK_YUKON_LITE;
1467                         sc->sk_rev = SK_YUKON_LITE_REV_A0;
1468                         /* Restore Flash-Address Register */
1469                         sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1470                 }
1471         }
1472
1473         /*
1474          * Create sysctl nodes.
1475          */
1476         sysctl_ctx_init(&sc->sk_sysctl_ctx);
1477         sc->sk_sysctl_tree = SYSCTL_ADD_NODE(&sc->sk_sysctl_ctx,
1478                                              SYSCTL_STATIC_CHILDREN(_hw),
1479                                              OID_AUTO,
1480                                              device_get_nameunit(dev),
1481                                              CTLFLAG_RD, 0, "");
1482         if (sc->sk_sysctl_tree == NULL) {
1483                 device_printf(dev, "can't add sysctl node\n");
1484                 error = ENXIO;
1485                 goto fail;
1486         }
1487         SYSCTL_ADD_PROC(&sc->sk_sysctl_ctx,
1488                         SYSCTL_CHILDREN(sc->sk_sysctl_tree),
1489                         OID_AUTO, "imtime", CTLTYPE_INT | CTLFLAG_RW,
1490                         sc, 0, skc_sysctl_imtime, "I",
1491                         "Interrupt moderation time (usec).");
1492
1493         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1494         port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1495         *port = SK_PORT_A;
1496         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1497
1498         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1499                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1500                 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1501                 *port = SK_PORT_B;
1502                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1503         }
1504
1505         /* Turn on the 'driver is loaded' LED. */
1506         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1507
1508         bus_generic_attach(dev);
1509
1510         error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE, sk_intr, sc,
1511                                &sc->sk_intrhand, &sc->sk_serializer);
1512         if (error) {
1513                 device_printf(dev, "couldn't set up irq\n");
1514                 goto fail;
1515         }
1516         return 0;
1517 fail:
1518         skc_detach(dev);
1519         return error;
1520 }
1521
1522 static int
1523 sk_detach(device_t dev)
1524 {
1525         struct sk_if_softc *sc_if = device_get_softc(dev);
1526
1527         if (device_is_attached(dev)) {
1528                 struct sk_softc *sc = sc_if->sk_softc;
1529                 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1530
1531                 lwkt_serialize_enter(ifp->if_serializer);
1532
1533                 if (sc->sk_intrhand != NULL) {
1534                         if (sc->sk_if[SK_PORT_A] != NULL)
1535                                 sk_stop(sc->sk_if[SK_PORT_A]);
1536                         if (sc->sk_if[SK_PORT_B] != NULL)
1537                                 sk_stop(sc->sk_if[SK_PORT_B]);
1538
1539                         bus_teardown_intr(sc->sk_dev, sc->sk_irq,
1540                                           sc->sk_intrhand);
1541                         sc->sk_intrhand = NULL;
1542                 }
1543
1544                 lwkt_serialize_exit(ifp->if_serializer);
1545
1546                 ether_ifdetach(ifp);
1547         }
1548
1549         if (sc_if->sk_miibus != NULL)
1550                 device_delete_child(dev, sc_if->sk_miibus);
1551
1552         sk_dma_free(dev);
1553         return 0;
1554 }
1555
1556 static int
1557 skc_detach(device_t dev)
1558 {
1559         struct sk_softc *sc = device_get_softc(dev);
1560         int *port;
1561
1562 #ifdef INVARIANTS
1563         if (device_is_attached(dev)) {
1564                 KASSERT(sc->sk_intrhand == NULL,
1565                         ("intr has not been torn down yet"));
1566         }
1567 #endif
1568
1569         if (sc->sk_devs[SK_PORT_A] != NULL) {
1570                 port = device_get_ivars(sc->sk_devs[SK_PORT_A]);
1571                 if (port != NULL) {
1572                         kfree(port, M_DEVBUF);
1573                         device_set_ivars(sc->sk_devs[SK_PORT_A], NULL);
1574                 }
1575                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1576         }
1577         if (sc->sk_devs[SK_PORT_B] != NULL) {
1578                 port = device_get_ivars(sc->sk_devs[SK_PORT_B]);
1579                 if (port != NULL) {
1580                         kfree(port, M_DEVBUF);
1581                         device_set_ivars(sc->sk_devs[SK_PORT_B], NULL);
1582                 }
1583                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1584         }
1585
1586         if (sc->sk_irq != NULL) {
1587                 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid,
1588                                      sc->sk_irq);
1589         }
1590         if (sc->sk_res != NULL) {
1591                 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid,
1592                                      sc->sk_res);
1593         }
1594
1595         if (sc->sk_sysctl_tree != NULL)
1596                 sysctl_ctx_free(&sc->sk_sysctl_ctx);
1597
1598         return 0;
1599 }
1600
1601 static int
1602 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1603 {
1604         struct sk_chain_data *cd = &sc_if->sk_cdata;
1605         struct sk_ring_data *rd = sc_if->sk_rdata;
1606         struct sk_tx_desc *f = NULL;
1607         uint32_t frag, cur, sk_ctl;
1608         struct sk_dma_ctx ctx;
1609         bus_dma_segment_t segs[SK_NTXSEG];
1610         bus_dmamap_t map;
1611         int i, error;
1612
1613         DPRINTFN(2, ("sk_encap\n"));
1614
1615         cur = frag = *txidx;
1616
1617 #ifdef SK_DEBUG
1618         if (skdebug >= 2)
1619                 sk_dump_mbuf(m_head);
1620 #endif
1621
1622         map = cd->sk_tx_dmap[*txidx];
1623
1624         /*
1625          * Start packing the mbufs in this chain into
1626          * the fragment pointers. Stop when we run out
1627          * of fragments or hit the end of the mbuf chain.
1628          */
1629         ctx.nsegs = SK_NTXSEG;
1630         ctx.segs = segs;
1631         error = bus_dmamap_load_mbuf(cd->sk_tx_dtag, map, m_head,
1632                                      sk_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1633         if (error) {
1634                 if_printf(&sc_if->arpcom.ac_if, "could not map TX mbuf\n");
1635                 return ENOBUFS;
1636         }
1637
1638         if ((SK_TX_RING_CNT - (cd->sk_tx_cnt + ctx.nsegs)) < 2) {
1639                 bus_dmamap_unload(cd->sk_tx_dtag, map);
1640                 DPRINTFN(2, ("sk_encap: too few descriptors free\n"));
1641                 return ENOBUFS;
1642         }
1643
1644         DPRINTFN(2, ("sk_encap: nsegs=%d\n", ctx.nsegs));
1645
1646         /* Sync the DMA map. */
1647         bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE);
1648
1649         for (i = 0; i < ctx.nsegs; i++) {
1650                 f = &rd->sk_tx_ring[frag];
1651                 f->sk_data_lo = htole32(segs[i].ds_addr);
1652                 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT;
1653                 if (i == 0)
1654                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
1655                 else
1656                         sk_ctl |= SK_TXCTL_OWN;
1657                 f->sk_ctl = htole32(sk_ctl);
1658                 cur = frag;
1659                 SK_INC(frag, SK_TX_RING_CNT);
1660         }
1661
1662         cd->sk_tx_mbuf[cur] = m_head;
1663         /* Switch DMA map */
1664         cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur];
1665         cd->sk_tx_dmap[cur] = map;
1666
1667         rd->sk_tx_ring[cur].sk_ctl |=
1668                 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1669         rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN);
1670
1671         /* Sync first descriptor to hand it off */
1672         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1673                         BUS_DMASYNC_PREWRITE);
1674
1675         sc_if->sk_cdata.sk_tx_cnt += ctx.nsegs;
1676
1677 #ifdef SK_DEBUG
1678         if (skdebug >= 2) {
1679                 struct sk_tx_desc *desc;
1680                 uint32_t idx;
1681
1682                 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1683                         desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1684                         sk_dump_txdesc(desc, idx);
1685                 }
1686         }
1687 #endif
1688
1689         *txidx = frag;
1690
1691         DPRINTFN(2, ("sk_encap: completed successfully\n"));
1692
1693         return (0);
1694 }
1695
1696 static void
1697 sk_start(struct ifnet *ifp)
1698 {
1699         struct sk_if_softc *sc_if = ifp->if_softc;
1700         struct sk_softc *sc = sc_if->sk_softc;
1701         struct mbuf *m_head = NULL;
1702         uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1703         int pkts = 0;
1704
1705         DPRINTFN(2, ("sk_start\n"));
1706
1707         while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) {
1708                 m_head = ifq_poll(&ifp->if_snd);
1709                 if (m_head == NULL)
1710                         break;
1711
1712                 /*
1713                  * Pack the data into the transmit ring. If we
1714                  * don't have room, set the OACTIVE flag and wait
1715                  * for the NIC to drain the ring.
1716                  */
1717                 if (sk_encap(sc_if, m_head, &idx)) {
1718                         ifp->if_flags |= IFF_OACTIVE;
1719                         break;
1720                 }
1721
1722                 /* now we are committed to transmit the packet */
1723                 ifq_dequeue(&ifp->if_snd, m_head);
1724                 pkts++;
1725
1726                 BPF_MTAP(ifp, m_head);
1727         }
1728         if (pkts == 0)
1729                 return;
1730
1731         /* Transmit */
1732         if (idx != sc_if->sk_cdata.sk_tx_prod) {
1733                 sc_if->sk_cdata.sk_tx_prod = idx;
1734                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1735
1736                 /* Set a timeout in case the chip goes out to lunch. */
1737                 ifp->if_timer = 5;
1738         }
1739 }
1740
1741 static void
1742 sk_watchdog(struct ifnet *ifp)
1743 {
1744         struct sk_if_softc *sc_if = ifp->if_softc;
1745
1746         ASSERT_SERIALIZED(ifp->if_serializer);
1747         /*
1748          * Reclaim first as there is a possibility of losing Tx completion
1749          * interrupts.
1750          */
1751         sk_txeof(sc_if);
1752         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1753                 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n");
1754                 ifp->if_oerrors++;
1755                 ifp->if_flags &= ~IFF_RUNNING;
1756                 sk_init(sc_if);
1757         }
1758 }
1759
1760 static void
1761 skc_shutdown(device_t dev)
1762 {
1763         struct sk_softc *sc = device_get_softc(dev);
1764
1765         DPRINTFN(2, ("sk_shutdown\n"));
1766
1767         lwkt_serialize_enter(&sc->sk_serializer);
1768
1769         /* Turn off the 'driver is loaded' LED. */
1770         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1771
1772         /*
1773          * Reset the GEnesis controller. Doing this should also
1774          * assert the resets on the attached XMAC(s).
1775          */
1776         sk_reset(sc);
1777
1778         lwkt_serialize_exit(&sc->sk_serializer);
1779 }
1780
1781 static __inline int
1782 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
1783 {
1784         if (sc->sk_type == SK_GENESIS) {
1785                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1786                     XM_RXSTAT_BYTES(stat) != len)
1787                         return (0);
1788         } else {
1789                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1790                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1791                     YU_RXSTAT_JABBER)) != 0 ||
1792                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1793                     YU_RXSTAT_BYTES(stat) != len)
1794                         return (0);
1795         }
1796
1797         return (1);
1798 }
1799
1800 static void
1801 sk_rxeof(struct sk_if_softc *sc_if)
1802 {
1803         struct sk_softc *sc = sc_if->sk_softc;
1804         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1805         struct sk_chain_data *cd = &sc_if->sk_cdata;
1806         struct sk_ring_data *rd = sc_if->sk_rdata;
1807         int i, reap, max_frmlen;
1808
1809         DPRINTFN(2, ("sk_rxeof\n"));
1810
1811         i = cd->sk_rx_prod;
1812
1813         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1814                         BUS_DMASYNC_POSTREAD);
1815         if (sc_if->sk_use_jumbo) {
1816                 bus_dmamap_sync(cd->sk_jpool_dtag, cd->sk_jpool_dmap,
1817                                 BUS_DMASYNC_POSTREAD);
1818                 max_frmlen = SK_JUMBO_FRAMELEN;
1819         } else {
1820                 max_frmlen = ETHER_MAX_LEN;
1821         }
1822
1823         reap = 0;
1824         for (;;) {
1825                 struct sk_rx_desc *cur_desc;
1826                 uint32_t rxstat, sk_ctl;
1827 #ifdef SK_RXCSUM
1828                 uint16_t csum1, csum2;
1829 #endif
1830                 int cur, total_len;
1831                 struct mbuf *m;
1832
1833                 cur = i;
1834                 cur_desc = &rd->sk_rx_ring[cur];
1835
1836                 sk_ctl = le32toh(cur_desc->sk_ctl);
1837                 if (sk_ctl & SK_RXCTL_OWN) {
1838                         /* Invalidate the descriptor -- it's not ready yet */
1839                         cd->sk_rx_prod = cur;
1840                         break;
1841                 }
1842
1843                 rxstat = le32toh(cur_desc->sk_xmac_rxstat);
1844                 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
1845
1846 #ifdef SK_RXCSUM
1847                 csum1 = le16toh(cur_desc->sk_csum1);
1848                 csum2 = le16toh(cur_desc->sk_csum2);
1849 #endif
1850
1851                 m = cd->sk_rx_mbuf[cur];
1852
1853                 /*
1854                  * Bump 'i' here, so we can keep going, even if the current
1855                  * RX descriptor reaping fails later.  'i' shoult NOT be used
1856                  * in the following processing any more.
1857                  */
1858                 SK_INC(i, SK_RX_RING_CNT);
1859                 reap = 1;
1860
1861                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1862                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1863                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
1864                     total_len < SK_MIN_FRAMELEN || total_len > max_frmlen ||
1865                     sk_rxvalid(sc, rxstat, total_len) == 0) {
1866                         ifp->if_ierrors++;
1867                         cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1868                         continue;
1869                 }
1870
1871                 if (!sc_if->sk_use_jumbo) {
1872                         bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[cur],
1873                                         BUS_DMASYNC_POSTREAD);
1874                 }
1875
1876                 /*
1877                  * Try to allocate a new RX buffer. If that fails,
1878                  * copy the packet to mbufs and put the RX buffer
1879                  * back in the ring so it can be re-used. If
1880                  * allocating mbufs fails, then we have to drop
1881                  * the packet.
1882                  */
1883                 if (sk_newbuf(sc_if, cur, 0)) {
1884                         struct mbuf *m0;
1885
1886                         cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1887
1888                         m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1889                             total_len + ETHER_ALIGN, 0, ifp, NULL);
1890                         if (m0 == NULL) {
1891                                 ifp->if_ierrors++;
1892                                 continue;
1893                         }
1894                         m_adj(m0, ETHER_ALIGN);
1895                         m = m0;
1896                 } else {
1897                         m->m_pkthdr.rcvif = ifp;
1898                         m->m_pkthdr.len = m->m_len = total_len;
1899                 }
1900
1901 #ifdef SK_RXCSUM
1902                 sk_rxcsum(ifp, m, csum1, csum2);
1903 #endif
1904
1905                 ifp->if_ipackets++;
1906                 ifp->if_input(ifp, m);
1907         }
1908
1909         if (reap) {
1910                 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1911                                 BUS_DMASYNC_PREWRITE);
1912         }
1913 }
1914
1915 #ifdef SK_RXCSUM
1916 static void
1917 sk_rxcsum(struct ifnet *ifp, struct mbuf *m,
1918           const uint16_t csum1, const uint16_t csum2)
1919 {
1920         struct ether_header *eh;
1921         struct ip *ip;
1922         uint8_t *pp;
1923         int hlen, len, plen;
1924         uint16_t iph_csum, ipo_csum, ipd_csum, csum;
1925
1926         pp = mtod(m, uint8_t *);
1927         plen = m->m_pkthdr.len;
1928         if (plen < sizeof(*eh))
1929                 return;
1930         eh = (struct ether_header *)pp;
1931         iph_csum = in_addword(csum1, (~csum2 & 0xffff));
1932
1933         if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1934                 uint16_t *xp = (uint16_t *)pp;
1935
1936                 xp = (uint16_t *)pp;
1937                 if (xp[1] != htons(ETHERTYPE_IP))
1938                         return;
1939                 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff));
1940                 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff));
1941                 xp = (uint16_t *)(pp + sizeof(struct ip));
1942                 iph_csum = in_addword(iph_csum, xp[0]);
1943                 iph_csum = in_addword(iph_csum, xp[1]);
1944                 pp += EVL_ENCAPLEN;
1945         } else if (eh->ether_type != htons(ETHERTYPE_IP)) {
1946                 return;
1947         }
1948
1949         pp += sizeof(*eh);
1950         plen -= sizeof(*eh);
1951
1952         ip = (struct ip *)pp;
1953
1954         if (ip->ip_v != IPVERSION)
1955                 return;
1956
1957         hlen = ip->ip_hl << 2;
1958         if (hlen < sizeof(struct ip))
1959                 return;
1960         if (hlen > ntohs(ip->ip_len))
1961                 return;
1962
1963         /* Don't deal with truncated or padded packets. */
1964         if (plen != ntohs(ip->ip_len))
1965                 return;
1966
1967         len = hlen - sizeof(struct ip);
1968         if (len > 0) {
1969                 uint16_t *p;
1970
1971                 p = (uint16_t *)(ip + 1);
1972                 ipo_csum = 0;
1973                 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
1974                         ipo_csum = in_addword(ipo_csum, *p);
1975                 iph_csum = in_addword(iph_csum, ipo_csum);
1976                 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff));
1977         } else {
1978                 ipd_csum = csum2;
1979         }
1980
1981         if (iph_csum != 0xffff)
1982                 return;
1983         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
1984
1985         if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1986                 return;                 /* ip frag, we're done for now */
1987
1988         pp += hlen;
1989
1990         /* Only know checksum protocol for udp/tcp */
1991         if (ip->ip_p == IPPROTO_UDP) {
1992                 struct udphdr *uh = (struct udphdr *)pp;
1993
1994                 if (uh->uh_sum == 0)    /* udp with no checksum */
1995                         return;
1996         } else if (ip->ip_p != IPPROTO_TCP) {
1997                 return;
1998         }
1999
2000         csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
2001             htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
2002         if (csum == 0xffff) {
2003                 m->m_pkthdr.csum_data = csum;
2004                 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
2005         }
2006 }
2007 #endif
2008
2009 static void
2010 sk_txeof(struct sk_if_softc *sc_if)
2011 {
2012         struct sk_chain_data *cd = &sc_if->sk_cdata;
2013         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2014         uint32_t idx;
2015         int reap = 0;
2016
2017         DPRINTFN(2, ("sk_txeof\n"));
2018
2019         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
2020                         BUS_DMASYNC_POSTREAD);
2021
2022         /*
2023          * Go through our tx ring and free mbufs for those
2024          * frames that have been sent.
2025          */
2026         idx = cd->sk_tx_cons;
2027         while (idx != cd->sk_tx_prod) {
2028                 struct sk_tx_desc *cur_tx;
2029                 uint32_t sk_ctl;
2030
2031                 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
2032                 sk_ctl = le32toh(cur_tx->sk_ctl);
2033 #ifdef SK_DEBUG
2034                 if (skdebug >= 2)
2035                         sk_dump_txdesc(cur_tx, idx);
2036 #endif
2037                 if (sk_ctl & SK_TXCTL_OWN)
2038                         break;
2039                 if (sk_ctl & SK_TXCTL_LASTFRAG)
2040                         ifp->if_opackets++;
2041                 if (cd->sk_tx_mbuf[idx] != NULL) {
2042                         bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]);
2043                         m_freem(cd->sk_tx_mbuf[idx]);
2044                         cd->sk_tx_mbuf[idx] = NULL;
2045                 }
2046                 sc_if->sk_cdata.sk_tx_cnt--;
2047                 reap = 1;
2048                 SK_INC(idx, SK_TX_RING_CNT);
2049         }
2050         ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2051
2052         if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2)
2053                 ifp->if_flags &= ~IFF_OACTIVE;
2054
2055         sc_if->sk_cdata.sk_tx_cons = idx;
2056
2057         if (reap) {
2058                 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
2059                                 BUS_DMASYNC_PREWRITE);
2060         }
2061 }
2062
2063 static void
2064 sk_tick(void *xsc_if)
2065 {
2066         struct sk_if_softc *sc_if = xsc_if;
2067         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2068         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2069         int i;
2070
2071         DPRINTFN(2, ("sk_tick\n"));
2072
2073         lwkt_serialize_enter(ifp->if_serializer);
2074
2075         if ((ifp->if_flags & IFF_UP) == 0) {
2076                 lwkt_serialize_exit(ifp->if_serializer);
2077                 return;
2078         }
2079
2080         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2081                 sk_intr_bcom(sc_if);
2082                 lwkt_serialize_exit(ifp->if_serializer);
2083                 return;
2084         }
2085
2086         /*
2087          * According to SysKonnect, the correct way to verify that
2088          * the link has come back up is to poll bit 0 of the GPIO
2089          * register three times. This pin has the signal from the
2090          * link sync pin connected to it; if we read the same link
2091          * state 3 times in a row, we know the link is up.
2092          */
2093         for (i = 0; i < 3; i++) {
2094                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2095                         break;
2096         }
2097
2098         if (i != 3) {
2099                 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2100                 lwkt_serialize_exit(ifp->if_serializer);
2101                 return;
2102         }
2103
2104         /* Turn the GP0 interrupt back on. */
2105         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2106         SK_XM_READ_2(sc_if, XM_ISR);
2107         mii_tick(mii);
2108         callout_stop(&sc_if->sk_tick_timer);
2109         lwkt_serialize_exit(ifp->if_serializer);
2110 }
2111
2112 static void
2113 sk_yukon_tick(void *xsc_if)
2114 {
2115         struct sk_if_softc *sc_if = xsc_if;
2116         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2117         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2118
2119         lwkt_serialize_enter(ifp->if_serializer);
2120         mii_tick(mii);
2121         callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2122         lwkt_serialize_exit(ifp->if_serializer);
2123 }
2124
2125 static void
2126 sk_intr_bcom(struct sk_if_softc *sc_if)
2127 {
2128         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2129         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2130         int status;
2131
2132         DPRINTFN(2, ("sk_intr_bcom\n"));
2133
2134         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2135
2136         /*
2137          * Read the PHY interrupt register to make sure
2138          * we clear any pending interrupts.
2139          */
2140         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2141
2142         if ((ifp->if_flags & IFF_RUNNING) == 0) {
2143                 sk_init_xmac(sc_if);
2144                 return;
2145         }
2146
2147         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2148                 int lstat;
2149
2150                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2151                     BRGPHY_MII_AUXSTS);
2152
2153                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2154                         mii_mediachg(mii);
2155                         /* Turn off the link LED. */
2156                         SK_IF_WRITE_1(sc_if, 0,
2157                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2158                         sc_if->sk_link = 0;
2159                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2160                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2161                             BRGPHY_MII_IMR, 0xFF00);
2162                         mii_tick(mii);
2163                         sc_if->sk_link = 1;
2164                         /* Turn on the link LED. */
2165                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2166                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2167                             SK_LINKLED_BLINK_OFF);
2168                 } else {
2169                         mii_tick(mii);
2170                         callout_reset(&sc_if->sk_tick_timer, hz,
2171                                       sk_tick, sc_if);
2172                 }
2173         }
2174
2175         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2176 }
2177
2178 static void
2179 sk_intr_xmac(struct sk_if_softc *sc_if)
2180 {
2181         uint16_t status;
2182
2183         status = SK_XM_READ_2(sc_if, XM_ISR);
2184         DPRINTFN(2, ("sk_intr_xmac\n"));
2185
2186         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC &&
2187             (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) {
2188                 if (status & XM_ISR_GP0_SET)
2189                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2190
2191                 callout_reset(&sc_if->sk_tick_timer, hz,
2192                               sk_tick, sc_if);
2193         }
2194
2195         if (status & XM_IMR_TX_UNDERRUN)
2196                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2197
2198         if (status & XM_IMR_RX_OVERRUN)
2199                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2200 }
2201
2202 static void
2203 sk_intr_yukon(struct sk_if_softc *sc_if)
2204 {
2205         uint8_t status;
2206
2207         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2208         /* RX overrun */
2209         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2210                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2211                     SK_RFCTL_RX_FIFO_OVER);
2212         }
2213         /* TX underrun */
2214         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2215                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2216                     SK_TFCTL_TX_FIFO_UNDER);
2217         }
2218
2219         DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
2220 }
2221
2222 static void
2223 sk_intr(void *xsc)
2224 {
2225         struct sk_softc *sc = xsc;
2226         struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2227         struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2228         struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2229         uint32_t status;
2230
2231         ASSERT_SERIALIZED(&sc->sk_serializer);
2232
2233         status = CSR_READ_4(sc, SK_ISSR);
2234         if (status == 0 || status == 0xffffffff)
2235                 return;
2236
2237         if (sc_if0 != NULL)
2238                 ifp0 = &sc_if0->arpcom.ac_if;
2239         if (sc_if1 != NULL)
2240                 ifp1 = &sc_if1->arpcom.ac_if;
2241
2242         for (; (status &= sc->sk_intrmask) != 0;) {
2243                 /* Handle receive interrupts first. */
2244                 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
2245                         sk_rxeof(sc_if0);
2246                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2247                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2248                 }
2249                 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
2250                         sk_rxeof(sc_if1);
2251                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2252                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2253                 }
2254
2255                 /* Then transmit interrupts. */
2256                 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
2257                         sk_txeof(sc_if0);
2258                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2259                             SK_TXBMU_CLR_IRQ_EOF);
2260                 }
2261                 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
2262                         sk_txeof(sc_if1);
2263                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2264                             SK_TXBMU_CLR_IRQ_EOF);
2265                 }
2266
2267                 /* Then MAC interrupts. */
2268                 if (sc_if0 && (status & SK_ISR_MAC1) &&
2269                     (ifp0->if_flags & IFF_RUNNING)) {
2270                         if (SK_IS_GENESIS(sc))
2271                                 sk_intr_xmac(sc_if0);
2272                         else
2273                                 sk_intr_yukon(sc_if0);
2274                 }
2275
2276                 if (sc_if1 && (status & SK_ISR_MAC2) &&
2277                     (ifp1->if_flags & IFF_RUNNING)) {
2278                         if (SK_IS_GENESIS(sc))
2279                                 sk_intr_xmac(sc_if1);
2280                         else
2281                                 sk_intr_yukon(sc_if1);
2282                 }
2283
2284                 if (status & SK_ISR_EXTERNAL_REG) {
2285                         if (sc_if0 != NULL &&
2286                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2287                                 sk_intr_bcom(sc_if0);
2288
2289                         if (sc_if1 != NULL &&
2290                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2291                                 sk_intr_bcom(sc_if1);
2292                 }
2293                 status = CSR_READ_4(sc, SK_ISSR);
2294         }
2295
2296         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2297
2298         if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2299                 sk_start(ifp0);
2300         if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd))
2301                 sk_start(ifp1);
2302 }
2303
2304 static void
2305 sk_init_xmac(struct sk_if_softc *sc_if)
2306 {
2307         struct sk_softc *sc = sc_if->sk_softc;
2308         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2309         static const struct sk_bcom_hack bhack[] = {
2310         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2311         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2312         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2313         { 0, 0 } };
2314
2315         DPRINTFN(2, ("sk_init_xmac\n"));
2316
2317         /* Unreset the XMAC. */
2318         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2319         DELAY(1000);
2320
2321         /* Reset the XMAC's internal state. */
2322         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2323
2324         /* Save the XMAC II revision */
2325         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2326
2327         /*
2328          * Perform additional initialization for external PHYs,
2329          * namely for the 1000baseT cards that use the XMAC's
2330          * GMII mode.
2331          */
2332         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2333                 int i = 0;
2334                 uint32_t val;
2335
2336                 /* Take PHY out of reset. */
2337                 val = sk_win_read_4(sc, SK_GPIO);
2338                 if (sc_if->sk_port == SK_PORT_A)
2339                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2340                 else
2341                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2342                 sk_win_write_4(sc, SK_GPIO, val);
2343
2344                 /* Enable GMII mode on the XMAC. */
2345                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2346
2347                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2348                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2349                 DELAY(10000);
2350                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2351                     BRGPHY_MII_IMR, 0xFFF0);
2352
2353                 /*
2354                  * Early versions of the BCM5400 apparently have
2355                  * a bug that requires them to have their reserved
2356                  * registers initialized to some magic values. I don't
2357                  * know what the numbers do, I'm just the messenger.
2358                  */
2359                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2360                     == 0x6041) {
2361                         while(bhack[i].reg) {
2362                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2363                                     bhack[i].reg, bhack[i].val);
2364                                 i++;
2365                         }
2366                 }
2367         }
2368
2369         /* Set station address */
2370         SK_XM_WRITE_2(sc_if, XM_PAR0,
2371             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2372         SK_XM_WRITE_2(sc_if, XM_PAR1,
2373             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2374         SK_XM_WRITE_2(sc_if, XM_PAR2,
2375             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2376         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2377
2378         if (ifp->if_flags & IFF_BROADCAST)
2379                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2380         else
2381                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2382
2383         /* We don't need the FCS appended to the packet. */
2384         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2385
2386         /* We want short frames padded to 60 bytes. */
2387         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2388
2389         /*
2390          * Enable the reception of all error frames. This is
2391          * a necessary evil due to the design of the XMAC. The
2392          * XMAC's receive FIFO is only 8K in size, however jumbo
2393          * frames can be up to 9000 bytes in length. When bad
2394          * frame filtering is enabled, the XMAC's RX FIFO operates
2395          * in 'store and forward' mode. For this to work, the
2396          * entire frame has to fit into the FIFO, but that means
2397          * that jumbo frames larger than 8192 bytes will be
2398          * truncated. Disabling all bad frame filtering causes
2399          * the RX FIFO to operate in streaming mode, in which
2400          * case the XMAC will start transfering frames out of the
2401          * RX FIFO as soon as the FIFO threshold is reached.
2402          */
2403         if (sc_if->sk_use_jumbo) {
2404                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2405                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2406                     XM_MODE_RX_INRANGELEN);
2407         }
2408
2409         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2410
2411         /*
2412          * Bump up the transmit threshold. This helps hold off transmit
2413          * underruns when we're blasting traffic from both ports at once.
2414          */
2415         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2416
2417         /* Set promiscuous mode */
2418         sk_setpromisc(sc_if);
2419
2420         /* Set multicast filter */
2421         sk_setmulti(sc_if);
2422
2423         /* Clear and enable interrupts */
2424         SK_XM_READ_2(sc_if, XM_ISR);
2425         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2426                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2427         else
2428                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2429
2430         /* Configure MAC arbiter */
2431         switch(sc_if->sk_xmac_rev) {
2432         case XM_XMAC_REV_B2:
2433                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2434                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2435                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2436                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2437                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2438                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2439                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2440                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2441                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2442                 break;
2443         case XM_XMAC_REV_C1:
2444                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2445                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2446                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2447                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2448                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2449                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2450                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2451                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2452                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2453                 break;
2454         default:
2455                 break;
2456         }
2457         sk_win_write_2(sc, SK_MACARB_CTL,
2458             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2459
2460         sc_if->sk_link = 1;
2461 }
2462
2463 static void
2464 sk_init_yukon(struct sk_if_softc *sc_if)
2465 {
2466         uint32_t phy, v;
2467         uint16_t reg;
2468         struct sk_softc *sc;
2469         int i;
2470
2471         sc = sc_if->sk_softc;
2472
2473         DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2474                      CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2475
2476         if (sc->sk_type == SK_YUKON_LITE &&
2477             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2478                 /*
2479                  * Workaround code for COMA mode, set PHY reset.
2480                  * Otherwise it will not correctly take chip out of
2481                  * powerdown (coma)
2482                  */
2483                 v = sk_win_read_4(sc, SK_GPIO);
2484                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2485                 sk_win_write_4(sc, SK_GPIO, v);
2486         }
2487
2488         DPRINTFN(6, ("sk_init_yukon: 1\n"));
2489
2490         /* GMAC and GPHY Reset */
2491         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2492         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2493         DELAY(1000);
2494
2495         DPRINTFN(6, ("sk_init_yukon: 2\n"));
2496
2497         if (sc->sk_type == SK_YUKON_LITE &&
2498             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2499                 /*
2500                  * Workaround code for COMA mode, clear PHY reset
2501                  */
2502                 v = sk_win_read_4(sc, SK_GPIO);
2503                 v |= SK_GPIO_DIR9;
2504                 v &= ~SK_GPIO_DAT9;
2505                 sk_win_write_4(sc, SK_GPIO, v);
2506         }
2507
2508         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2509                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2510
2511         if (sc->sk_coppertype)
2512                 phy |= SK_GPHY_COPPER;
2513         else
2514                 phy |= SK_GPHY_FIBER;
2515
2516         DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2517
2518         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2519         DELAY(1000);
2520         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2521         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2522                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2523
2524         DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2525                      SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2526
2527         DPRINTFN(6, ("sk_init_yukon: 3\n"));
2528
2529         /* unused read of the interrupt source register */
2530         DPRINTFN(6, ("sk_init_yukon: 4\n"));
2531         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2532
2533         DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2534         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2535         DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2536
2537         /* MIB Counter Clear Mode set */
2538         reg |= YU_PAR_MIB_CLR;
2539         DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2540         DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2541         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2542
2543         /* MIB Counter Clear Mode clear */
2544         DPRINTFN(6, ("sk_init_yukon: 5\n"));
2545         reg &= ~YU_PAR_MIB_CLR;
2546         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2547
2548         /* receive control reg */
2549         DPRINTFN(6, ("sk_init_yukon: 7\n"));
2550         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2551
2552         /* transmit parameter register */
2553         DPRINTFN(6, ("sk_init_yukon: 8\n"));
2554         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2555                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2556
2557         /* serial mode register */
2558         DPRINTFN(6, ("sk_init_yukon: 9\n"));
2559         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2560         if (sc_if->sk_use_jumbo)
2561                 reg |= YU_SMR_MFL_JUMBO;
2562         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2563
2564         DPRINTFN(6, ("sk_init_yukon: 10\n"));
2565         /* Setup Yukon's address */
2566         for (i = 0; i < 3; i++) {
2567                 /* Write Source Address 1 (unicast filter) */
2568                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2569                               sc_if->arpcom.ac_enaddr[i * 2] |
2570                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2571         }
2572
2573         for (i = 0; i < 3; i++) {
2574                 reg = sk_win_read_2(sc_if->sk_softc,
2575                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2576                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2577         }
2578
2579         /* Set promiscuous mode */
2580         sk_setpromisc(sc_if);
2581
2582         /* Set multicast filter */
2583         DPRINTFN(6, ("sk_init_yukon: 11\n"));
2584         sk_setmulti(sc_if);
2585
2586         /* enable interrupt mask for counter overflows */
2587         DPRINTFN(6, ("sk_init_yukon: 12\n"));
2588         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2589         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2590         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2591
2592         /* Configure RX MAC FIFO Flush Mask */
2593         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2594             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2595             YU_RXSTAT_JABBER;
2596         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2597
2598         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2599         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2600                 v = SK_TFCTL_OPERATION_ON;
2601         else
2602                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2603         /* Configure RX MAC FIFO */
2604         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2605         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2606
2607         /* Increase flush threshould to 64 bytes */
2608         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2609             SK_RFCTL_FIFO_THRESHOLD + 1);
2610
2611         /* Configure TX MAC FIFO */
2612         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2613         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2614
2615         DPRINTFN(6, ("sk_init_yukon: end\n"));
2616 }
2617
2618 /*
2619  * Note that to properly initialize any part of the GEnesis chip,
2620  * you first have to take it out of reset mode.
2621  */
2622 static void
2623 sk_init(void *xsc_if)
2624 {
2625         struct sk_if_softc *sc_if = xsc_if;
2626         struct sk_softc *sc = sc_if->sk_softc;
2627         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2628         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2629
2630         DPRINTFN(2, ("sk_init\n"));
2631
2632         ASSERT_SERIALIZED(ifp->if_serializer);
2633
2634         if (ifp->if_flags & IFF_RUNNING)
2635                 return;
2636
2637         /* Cancel pending I/O and free all RX/TX buffers. */
2638         sk_stop(sc_if);
2639
2640         /*
2641          * NOTE: Change sk_use_jumbo after sk_stop(),
2642          *       but before real initialization.
2643          */
2644         if (ifp->if_mtu > ETHER_MAX_LEN)
2645                 sc_if->sk_use_jumbo = 1;
2646         else
2647                 sc_if->sk_use_jumbo = 0;
2648         DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO"));
2649
2650         if (SK_IS_GENESIS(sc)) {
2651                 /* Configure LINK_SYNC LED */
2652                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2653                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2654                         SK_LINKLED_LINKSYNC_ON);
2655
2656                 /* Configure RX LED */
2657                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2658                         SK_RXLEDCTL_COUNTER_START);
2659
2660                 /* Configure TX LED */
2661                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2662                         SK_TXLEDCTL_COUNTER_START);
2663         }
2664
2665         /*
2666          * Configure descriptor poll timer
2667          *
2668          * SK-NET GENESIS data sheet says that possibility of losing Start
2669          * transmit command due to CPU/cache related interim storage problems
2670          * under certain conditions. The document recommends a polling
2671          * mechanism to send a Start transmit command to initiate transfer
2672          * of ready descriptors regulary. To cope with this issue sk(4) now
2673          * enables descriptor poll timer to initiate descriptor processing
2674          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2675          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2676          * command instead of waiting for next descriptor polling time.
2677          * The same rule may apply to Rx side too but it seems that is not
2678          * needed at the moment.
2679          * Since sk(4) uses descriptor polling as a last resort there is no
2680          * need to set smaller polling time than maximum allowable one.
2681          */
2682         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2683
2684         /* Configure I2C registers */
2685
2686         /* Configure XMAC(s) */
2687         switch (sc->sk_type) {
2688         case SK_GENESIS:
2689                 sk_init_xmac(sc_if);
2690                 break;
2691         case SK_YUKON:
2692         case SK_YUKON_LITE:
2693         case SK_YUKON_LP:
2694                 sk_init_yukon(sc_if);
2695                 break;
2696         }
2697         mii_mediachg(mii);
2698
2699         if (SK_IS_GENESIS(sc)) {
2700                 /* Configure MAC FIFOs */
2701                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2702                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2703                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2704
2705                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2706                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2707                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2708         }
2709
2710         /* Configure transmit arbiter(s) */
2711         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2712             SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2713
2714         /* Configure RAMbuffers */
2715         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2716         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2717         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2718         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2719         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2720         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2721
2722         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2723         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2724         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2725         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2726         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2727         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2728         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2729
2730         /* Configure BMUs */
2731         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2732         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2733             SK_RX_RING_ADDR(sc_if, 0));
2734         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2735
2736         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2737         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2738             SK_TX_RING_ADDR(sc_if, 0));
2739         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2740
2741         /* Init descriptors */
2742         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2743                 if_printf(ifp, "initialization failed: "
2744                           "no memory for rx buffers\n");
2745                 sk_stop(sc_if);
2746                 return;
2747         }
2748
2749         if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2750                 if_printf(ifp, "initialization failed: "
2751                           "no memory for tx buffers\n");
2752                 sk_stop(sc_if);
2753                 return;
2754         }
2755
2756         /* Configure interrupt handling */
2757         CSR_READ_4(sc, SK_ISSR);
2758         if (sc_if->sk_port == SK_PORT_A)
2759                 sc->sk_intrmask |= SK_INTRS1;
2760         else
2761                 sc->sk_intrmask |= SK_INTRS2;
2762
2763         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2764
2765         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2766
2767         /* Start BMUs. */
2768         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2769
2770         if (SK_IS_GENESIS(sc)) {
2771                 /* Enable XMACs TX and RX state machines */
2772                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2773                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2774                                XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2775         }
2776
2777         if (SK_IS_YUKON(sc)) {
2778                 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2779                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2780 #if 0
2781                 /* XXX disable 100Mbps and full duplex mode? */
2782                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
2783 #endif
2784                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2785         }
2786
2787         /* Activate descriptor polling timer */
2788         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2789         /* Start transfer of Tx descriptors */
2790         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2791
2792         ifp->if_flags |= IFF_RUNNING;
2793         ifp->if_flags &= ~IFF_OACTIVE;
2794
2795         if (SK_IS_YUKON(sc))
2796                 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2797 }
2798
2799 static void
2800 sk_stop(struct sk_if_softc *sc_if)
2801 {
2802         struct sk_softc *sc = sc_if->sk_softc;
2803         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2804         struct sk_chain_data *cd = &sc_if->sk_cdata;
2805         uint32_t val;
2806         int i;
2807
2808         ASSERT_SERIALIZED(ifp->if_serializer);
2809
2810         DPRINTFN(2, ("sk_stop\n"));
2811
2812         callout_stop(&sc_if->sk_tick_timer);
2813
2814         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2815
2816         /* Stop Tx descriptor polling timer */
2817         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2818
2819         /* Stop transfer of Tx descriptors */
2820         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2821         for (i = 0; i < SK_TIMEOUT; i++) {
2822                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2823                 if (!(val & SK_TXBMU_TX_STOP))
2824                         break;
2825                 DELAY(1);
2826         }
2827         if (i == SK_TIMEOUT)
2828                 if_printf(ifp, "cannot stop transfer of Tx descriptors\n");
2829
2830         /* Stop transfer of Rx descriptors */
2831         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2832         for (i = 0; i < SK_TIMEOUT; i++) {
2833                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2834                 if (!(val & SK_RXBMU_RX_STOP))
2835                         break;
2836                 DELAY(1);
2837         }
2838         if (i == SK_TIMEOUT)
2839                 if_printf(ifp, "cannot stop transfer of Rx descriptors\n");
2840
2841         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2842                 /* Put PHY back into reset. */
2843                 val = sk_win_read_4(sc, SK_GPIO);
2844                 if (sc_if->sk_port == SK_PORT_A) {
2845                         val |= SK_GPIO_DIR0;
2846                         val &= ~SK_GPIO_DAT0;
2847                 } else {
2848                         val |= SK_GPIO_DIR2;
2849                         val &= ~SK_GPIO_DAT2;
2850                 }
2851                 sk_win_write_4(sc, SK_GPIO, val);
2852         }
2853
2854         /* Turn off various components of this interface. */
2855         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2856         switch (sc->sk_type) {
2857         case SK_GENESIS:
2858                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2859                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2860                 break;
2861         case SK_YUKON:
2862         case SK_YUKON_LITE:
2863         case SK_YUKON_LP:
2864                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2865                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2866                 break;
2867         }
2868         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2869         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2870         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2871         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2872             SK_RBCTL_RESET | SK_RBCTL_OFF);
2873         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2874         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2875         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2876         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2877         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2878
2879         /* Disable interrupts */
2880         if (sc_if->sk_port == SK_PORT_A)
2881                 sc->sk_intrmask &= ~SK_INTRS1;
2882         else
2883                 sc->sk_intrmask &= ~SK_INTRS2;
2884         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2885
2886         SK_XM_READ_2(sc_if, XM_ISR);
2887         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2888
2889         /* Free RX and TX mbufs still in the queues. */
2890         for (i = 0; i < SK_RX_RING_CNT; i++) {
2891                 if (cd->sk_rx_mbuf[i] != NULL) {
2892                         if (!sc_if->sk_use_jumbo) {
2893                                 bus_dmamap_unload(cd->sk_rx_dtag,
2894                                                   cd->sk_rx_dmap[i]);
2895                         }
2896                         m_freem(cd->sk_rx_mbuf[i]);
2897                         cd->sk_rx_mbuf[i] = NULL;
2898                 }
2899         }
2900         for (i = 0; i < SK_TX_RING_CNT; i++) {
2901                 if (cd->sk_tx_mbuf[i] != NULL) {
2902                         bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
2903                         m_freem(cd->sk_tx_mbuf[i]);
2904                         cd->sk_tx_mbuf[i] = NULL;
2905                 }
2906         }
2907 }
2908
2909 #ifdef SK_DEBUG
2910 static void
2911 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2912 {
2913 #define DESC_PRINT(X)                                   \
2914         if (X)                                  \
2915                 kprintf("txdesc[%d]." #X "=%#x\n",      \
2916                        idx, X);
2917
2918         DESC_PRINT(le32toh(desc->sk_ctl));
2919         DESC_PRINT(le32toh(desc->sk_next));
2920         DESC_PRINT(le32toh(desc->sk_data_lo));
2921         DESC_PRINT(le32toh(desc->sk_data_hi));
2922         DESC_PRINT(le32toh(desc->sk_xmac_txstat));
2923         DESC_PRINT(le16toh(desc->sk_rsvd0));
2924         DESC_PRINT(le16toh(desc->sk_csum_startval));
2925         DESC_PRINT(le16toh(desc->sk_csum_startpos));
2926         DESC_PRINT(le16toh(desc->sk_csum_writepos));
2927         DESC_PRINT(le16toh(desc->sk_rsvd1));
2928 #undef PRINT
2929 }
2930
2931 static void
2932 sk_dump_bytes(const char *data, int len)
2933 {
2934         int c, i, j;
2935
2936         for (i = 0; i < len; i += 16) {
2937                 kprintf("%08x  ", i);
2938                 c = len - i;
2939                 if (c > 16) c = 16;
2940
2941                 for (j = 0; j < c; j++) {
2942                         kprintf("%02x ", data[i + j] & 0xff);
2943                         if ((j & 0xf) == 7 && j > 0)
2944                                 kprintf(" ");
2945                 }
2946
2947                 for (; j < 16; j++)
2948                         kprintf("   ");
2949                 kprintf("  ");
2950
2951                 for (j = 0; j < c; j++) {
2952                         int ch = data[i + j] & 0xff;
2953                         kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2954                 }
2955
2956                 kprintf("\n");
2957
2958                 if (c < 16)
2959                         break;
2960         }
2961 }
2962
2963 static void
2964 sk_dump_mbuf(struct mbuf *m)
2965 {
2966         int count = m->m_pkthdr.len;
2967
2968         kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2969
2970         while (count > 0 && m) {
2971                 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n",
2972                        m, m->m_data, m->m_len);
2973                 sk_dump_bytes(mtod(m, char *), m->m_len);
2974
2975                 count -= m->m_len;
2976                 m = m->m_next;
2977         }
2978 }
2979 #endif
2980
2981 /*
2982  * Allocate jumbo buffer storage. The SysKonnect adapters support
2983  * "jumbograms" (9K frames), although SysKonnect doesn't currently
2984  * use them in their drivers. In order for us to use them, we need
2985  * large 9K receive buffers, however standard mbuf clusters are only
2986  * 2048 bytes in size. Consequently, we need to allocate and manage
2987  * our own jumbo buffer pool. Fortunately, this does not require an
2988  * excessive amount of additional code.
2989  */
2990 static int
2991 sk_jpool_alloc(device_t dev)
2992 {
2993         struct sk_if_softc *sc_if = device_get_softc(dev);
2994         struct sk_chain_data *cd = &sc_if->sk_cdata;
2995         bus_addr_t paddr;
2996         caddr_t buf;
2997         int error, i;
2998
2999         lwkt_serialize_init(&cd->sk_jpool_serializer);
3000
3001         error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
3002                                    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3003                                    NULL, NULL, SK_JMEM, 1, SK_JMEM,
3004                                    0, &cd->sk_jpool_dtag);
3005         if (error) {
3006                 device_printf(dev, "can't create jpool DMA tag\n");
3007                 return error;
3008         }
3009
3010         error = bus_dmamem_alloc(cd->sk_jpool_dtag, &cd->sk_jpool,
3011                                  BUS_DMA_WAITOK, &cd->sk_jpool_dmap);
3012         if (error) {
3013                 device_printf(dev, "can't alloc jpool DMA mem\n");
3014                 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3015                 cd->sk_jpool_dtag = NULL;
3016                 return error;
3017         }
3018
3019         error = bus_dmamap_load(cd->sk_jpool_dtag, cd->sk_jpool_dmap,
3020                                 cd->sk_jpool, SK_JMEM,
3021                                 sk_dmamem_addr, &paddr, BUS_DMA_WAITOK);
3022         if (error) {
3023                 device_printf(dev, "can't load DMA mem\n");
3024                 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3025                                 cd->sk_jpool_dmap);
3026                 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3027                 cd->sk_jpool_dtag = NULL;
3028                 return error;
3029         }
3030
3031         SLIST_INIT(&cd->sk_jpool_free_ent);
3032         buf = cd->sk_jpool;
3033
3034         /*
3035          * Now divide it up into SK_JLEN pieces.
3036          */
3037         for (i = 0; i < SK_JSLOTS; i++) {
3038                 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i];
3039
3040                 entry->sc_if = sc_if;
3041                 entry->inuse = 0;
3042                 entry->slot = i;
3043                 entry->buf = buf;
3044                 entry->paddr = paddr;
3045
3046                 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
3047
3048                 buf += SK_JLEN;
3049                 paddr += SK_JLEN;
3050         }
3051         return 0;
3052 }
3053
3054 static void
3055 sk_jpool_free(struct sk_if_softc *sc_if)
3056 {
3057         struct sk_chain_data *cd = &sc_if->sk_cdata;
3058
3059         if (cd->sk_jpool_dtag != NULL) {
3060                 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap);
3061                 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3062                                 cd->sk_jpool_dmap);
3063                 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3064                 cd->sk_jpool_dtag = NULL;
3065         }
3066 }
3067
3068 static int
3069 sk_dma_alloc(device_t dev)
3070 {
3071         struct sk_if_softc *sc_if = device_get_softc(dev);
3072         struct sk_chain_data *cd = &sc_if->sk_cdata;
3073         int i, j, error;
3074
3075         /*
3076          * Allocate the descriptor queues.
3077          * TODO: split into RX/TX rings
3078          */
3079         error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
3080                                    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3081                                    NULL, NULL,
3082                                    sizeof(struct sk_ring_data), 1,
3083                                    sizeof(struct sk_ring_data), 0,
3084                                    &sc_if->sk_rdata_dtag);
3085         if (error) {
3086                 device_printf(dev, "can't create desc DMA tag\n");
3087                 return error;
3088         }
3089
3090         error = bus_dmamem_alloc(sc_if->sk_rdata_dtag,
3091                                  (void **)&sc_if->sk_rdata,
3092                                  BUS_DMA_WAITOK | BUS_DMA_ZERO,
3093                                  &sc_if->sk_rdata_dmap);
3094         if (error) {
3095                 device_printf(dev, "can't alloc desc DMA mem\n");
3096                 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3097                 sc_if->sk_rdata_dtag = NULL;
3098                 return error;
3099         }
3100
3101         error = bus_dmamap_load(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
3102                                 sc_if->sk_rdata, sizeof(struct sk_ring_data),
3103                                 sk_dmamem_addr, &sc_if->sk_rdata_paddr,
3104                                 BUS_DMA_WAITOK);
3105         if (error) {
3106                 device_printf(dev, "can't load desc DMA mem\n");
3107                 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata,
3108                                 sc_if->sk_rdata_dmap);
3109                 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3110                 sc_if->sk_rdata_dtag = NULL;
3111                 return error;
3112         }
3113
3114         /* Try to allocate memory for jumbo buffers. */
3115         error = sk_jpool_alloc(dev);
3116         if (error) {
3117                 device_printf(dev, "jumbo buffer allocation failed\n");
3118                 return error;
3119         }
3120
3121         /* Create DMA tag for TX. */
3122         error = bus_dma_tag_create(NULL, 1, 0,
3123                                    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3124                                    NULL, NULL,
3125                                    SK_JLEN, SK_NTXSEG, SK_JLEN,
3126                                    0, &cd->sk_tx_dtag);
3127         if (error) {
3128                 device_printf(dev, "can't create TX DMA tag\n");
3129                 return error;
3130         }
3131
3132         /* Create DMA maps for TX. */
3133         for (i = 0; i < SK_TX_RING_CNT; i++) {
3134                 error = bus_dmamap_create(cd->sk_tx_dtag, 0,
3135                                           &cd->sk_tx_dmap[i]);
3136                 if (error) {
3137                         device_printf(dev, "can't create %dth TX DMA map\n", i);
3138
3139                         for (j = 0; j < i; ++j) {
3140                                 bus_dmamap_destroy(cd->sk_tx_dtag,
3141                                                    cd->sk_tx_dmap[i]);
3142                         }
3143                         bus_dma_tag_destroy(cd->sk_tx_dtag);
3144                         cd->sk_tx_dtag = NULL;
3145                         return error;
3146                 }
3147         }
3148
3149         /* Create DMA tag for RX. */
3150         error = bus_dma_tag_create(NULL, 1, 0,
3151                                    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3152                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3153                                    0, &cd->sk_rx_dtag);
3154         if (error) {
3155                 device_printf(dev, "can't create RX DMA tag\n");
3156                 return error;
3157         }
3158
3159         /* Create a spare RX DMA map. */
3160         error = bus_dmamap_create(cd->sk_rx_dtag, 0, &cd->sk_rx_dmap_tmp);
3161         if (error) {
3162                 device_printf(dev, "can't create spare RX DMA map\n");
3163                 bus_dma_tag_destroy(cd->sk_rx_dtag);
3164                 cd->sk_rx_dtag = NULL;
3165                 return error;
3166         }
3167
3168         /* Create DMA maps for RX. */
3169         for (i = 0; i < SK_RX_RING_CNT; ++i) {
3170                 error = bus_dmamap_create(cd->sk_rx_dtag, 0,
3171                                           &cd->sk_rx_dmap[i]);
3172                 if (error) {
3173                         device_printf(dev, "can't create %dth RX DMA map\n", i);
3174
3175                         for (j = 0; j < i; ++j) {
3176                                 bus_dmamap_destroy(cd->sk_rx_dtag,
3177                                                    cd->sk_rx_dmap[i]);
3178                         }
3179                         bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3180                         bus_dma_tag_destroy(cd->sk_rx_dtag);
3181                         cd->sk_rx_dtag = NULL;
3182                         return error;
3183                 }
3184         }
3185         return 0;
3186 }
3187
3188 static void
3189 sk_dma_free(device_t dev)
3190 {
3191         struct sk_if_softc *sc_if = device_get_softc(dev);
3192         struct sk_chain_data *cd = &sc_if->sk_cdata;
3193         int i;
3194
3195         if (cd->sk_tx_dtag != NULL) {
3196                 for (i = 0; i < SK_TX_RING_CNT; ++i) {
3197                         KASSERT(cd->sk_tx_mbuf[i] == NULL,
3198                                 ("sk_stop() is not called before %s()",
3199                                  __func__));
3200                         bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
3201                 }
3202                 bus_dma_tag_destroy(cd->sk_tx_dtag);
3203                 cd->sk_tx_dtag = NULL;
3204         }
3205
3206         if (cd->sk_rx_dtag != NULL) {
3207                 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3208                         KASSERT(cd->sk_rx_mbuf[i] == NULL,
3209                                 ("sk_stop() is not called before %s()",
3210                                  __func__));
3211                         bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]);
3212                 }
3213                 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3214                 bus_dma_tag_destroy(cd->sk_rx_dtag);
3215                 cd->sk_rx_dtag = NULL;
3216         }
3217
3218         sk_jpool_free(sc_if);
3219
3220         if (sc_if->sk_rdata_dtag != NULL) {
3221                 bus_dmamap_unload(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap);
3222                 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata,
3223                                 sc_if->sk_rdata_dmap);
3224                 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3225                 sc_if->sk_rdata_dtag = NULL;
3226         }
3227 }
3228
3229 static void
3230 sk_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
3231                 bus_size_t mapsz __unused, int error)
3232 {
3233         struct sk_dma_ctx *ctx = arg;
3234         int i;
3235
3236         if (error)
3237                 return;
3238
3239         KASSERT(nsegs <= ctx->nsegs,
3240                 ("too many segments(%d), should be <= %d\n",
3241                  nsegs, ctx->nsegs));
3242
3243         ctx->nsegs = nsegs;
3244         for (i = 0; i < nsegs; ++i)
3245                 ctx->segs[i] = segs[i];
3246 }
3247
3248 static void
3249 sk_dmamem_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3250 {
3251         KASSERT(nseg == 1, ("too many segments %d", nseg));
3252         *((bus_addr_t *)arg) = seg->ds_addr;
3253 }
3254
3255 static int
3256 skc_sysctl_imtime(SYSCTL_HANDLER_ARGS)
3257 {
3258         struct sk_softc *sc = arg1;
3259         struct lwkt_serialize *slize = &sc->sk_serializer;
3260         int error = 0, v;
3261
3262         lwkt_serialize_enter(slize);
3263
3264         v = sc->sk_imtime;
3265         error = sysctl_handle_int(oidp, &v, 0, req);
3266         if (error || req->newptr == NULL)
3267                 goto back;
3268         if (v <= 0) {
3269                 error = EINVAL;
3270                 goto back;
3271         }
3272
3273         if (sc->sk_imtime != v) {
3274                 sc->sk_imtime = v;
3275                 sk_win_write_4(sc, SK_IMTIMERINIT,
3276                                SK_IM_USECS(sc, sc->sk_imtime));
3277
3278                 /*
3279                  * Force interrupt moderation timer to
3280                  * reload new value.
3281                  */
3282                 sk_win_write_4(sc, SK_IMTIMER, 0);
3283         }
3284 back:
3285         lwkt_serialize_exit(slize);
3286         return error;
3287 }