2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
46 #include <sys/machintr.h>
48 #include <machine/msi_machdep.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 extern struct dev_ops pcic_ops; /* XXX */
75 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
77 static uint32_t pci_mapbase(unsigned mapreg);
78 static const char *pci_maptype(unsigned mapreg);
79 static int pci_mapsize(unsigned testval);
80 static int pci_maprange(unsigned mapreg);
81 static void pci_fixancient(pcicfgregs *cfg);
83 static int pci_porten(device_t pcib, int b, int s, int f);
84 static int pci_memen(device_t pcib, int b, int s, int f);
85 static void pci_assign_interrupt(device_t bus, device_t dev,
87 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
88 int b, int s, int f, int reg,
89 struct resource_list *rl, int force, int prefetch);
90 static int pci_probe(device_t dev);
91 static int pci_attach(device_t dev);
92 static void pci_child_detached(device_t, device_t);
93 static void pci_load_vendor_data(void);
94 static int pci_describe_parse_line(char **ptr, int *vendor,
95 int *device, char **desc);
96 static char *pci_describe_device(device_t dev);
97 static int pci_modevent(module_t mod, int what, void *arg);
98 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
100 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
101 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t *data);
104 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
105 int reg, uint32_t data);
107 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
108 static void pci_disable_msi(device_t dev);
109 static void pci_enable_msi(device_t dev, uint64_t address,
111 static void pci_setup_msix_vector(device_t dev, u_int index,
112 uint64_t address, uint32_t data);
113 static void pci_mask_msix_vector(device_t dev, u_int index);
114 static void pci_unmask_msix_vector(device_t dev, u_int index);
115 static void pci_mask_msix_allvectors(device_t dev);
116 static struct msix_vector *pci_find_msix_vector(device_t dev, int rid);
117 static int pci_msi_blacklisted(void);
118 static void pci_resume_msi(device_t dev);
119 static void pci_resume_msix(device_t dev);
120 static int pcie_slotimpl(const pcicfgregs *);
121 static void pci_print_verbose_expr(const pcicfgregs *);
123 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
127 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
128 static void pci_read_cap_subvendor(device_t, int, int,
130 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
131 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
133 static device_method_t pci_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, pci_probe),
136 DEVMETHOD(device_attach, pci_attach),
137 DEVMETHOD(device_detach, bus_generic_detach),
138 DEVMETHOD(device_shutdown, bus_generic_shutdown),
139 DEVMETHOD(device_suspend, pci_suspend),
140 DEVMETHOD(device_resume, pci_resume),
143 DEVMETHOD(bus_print_child, pci_print_child),
144 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
145 DEVMETHOD(bus_read_ivar, pci_read_ivar),
146 DEVMETHOD(bus_write_ivar, pci_write_ivar),
147 DEVMETHOD(bus_driver_added, pci_driver_added),
148 DEVMETHOD(bus_child_detached, pci_child_detached),
149 DEVMETHOD(bus_setup_intr, pci_setup_intr),
150 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
152 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
153 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
154 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
155 DEVMETHOD(bus_delete_resource, pci_delete_resource),
156 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
157 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
158 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
159 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
160 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
161 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
164 DEVMETHOD(pci_read_config, pci_read_config_method),
165 DEVMETHOD(pci_write_config, pci_write_config_method),
166 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
167 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
168 DEVMETHOD(pci_enable_io, pci_enable_io_method),
169 DEVMETHOD(pci_disable_io, pci_disable_io_method),
170 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
171 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
172 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
173 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
174 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
175 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
176 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
177 DEVMETHOD(pci_release_msi, pci_release_msi_method),
178 DEVMETHOD(pci_alloc_msix_vector, pci_alloc_msix_vector_method),
179 DEVMETHOD(pci_release_msix_vector, pci_release_msix_vector_method),
180 DEVMETHOD(pci_msi_count, pci_msi_count_method),
181 DEVMETHOD(pci_msix_count, pci_msix_count_method),
186 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
188 static devclass_t pci_devclass;
189 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
190 MODULE_VERSION(pci, 1);
192 static char *pci_vendordata;
193 static size_t pci_vendordata_size;
196 static const struct pci_read_cap {
198 pci_read_cap_t read_cap;
199 } pci_read_caps[] = {
200 { PCIY_PMG, pci_read_cap_pmgt },
201 { PCIY_HT, pci_read_cap_ht },
202 { PCIY_MSI, pci_read_cap_msi },
203 { PCIY_MSIX, pci_read_cap_msix },
204 { PCIY_VPD, pci_read_cap_vpd },
205 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
206 { PCIY_PCIX, pci_read_cap_pcix },
207 { PCIY_EXPRESS, pci_read_cap_express },
208 { 0, NULL } /* required last entry */
212 uint32_t devid; /* Vendor/device of the card */
214 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
215 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
220 struct pci_quirk pci_quirks[] = {
221 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
222 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
223 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
224 /* As does the Serverworks OSB4 (the SMBus mapping register) */
225 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
228 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
229 * or the CMIC-SL (AKA ServerWorks GC_LE).
231 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
232 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 * MSI doesn't work on earlier Intel chipsets including
236 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
238 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
243 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
244 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
247 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
250 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
255 /* map register information */
256 #define PCI_MAPMEM 0x01 /* memory map */
257 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
258 #define PCI_MAPPORT 0x04 /* port map */
260 #define PCI_MSIX_RID2VEC(rid) ((rid) - 1) /* rid -> MSI-X vector # */
261 #define PCI_MSIX_VEC2RID(vec) ((vec) + 1) /* MSI-X vector # -> rid */
263 struct devlist pci_devq;
264 uint32_t pci_generation;
265 uint32_t pci_numdevs = 0;
266 static int pcie_chipset, pcix_chipset;
269 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
271 static int pci_enable_io_modes = 1;
272 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
273 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
274 &pci_enable_io_modes, 1,
275 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
276 enable these bits correctly. We'd like to do this all the time, but there\n\
277 are some peripherals that this causes problems with.");
279 static int pci_do_power_nodriver = 0;
280 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
281 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
282 &pci_do_power_nodriver, 0,
283 "Place a function into D3 state when no driver attaches to it. 0 means\n\
284 disable. 1 means conservatively place devices into D3 state. 2 means\n\
285 aggressively place devices into D3 state. 3 means put absolutely everything\n\
288 static int pci_do_power_resume = 1;
289 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
290 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
291 &pci_do_power_resume, 1,
292 "Transition from D3 -> D0 on resume.");
294 static int pci_do_msi = 1;
295 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
296 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
297 "Enable support for MSI interrupts");
299 static int pci_do_msix = 0;
301 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
302 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
303 "Enable support for MSI-X interrupts");
306 static int pci_honor_msi_blacklist = 1;
307 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
308 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
309 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
311 static int pci_msi_cpuid;
313 /* Find a device_t by bus/slot/function in domain 0 */
316 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
319 return (pci_find_dbsf(0, bus, slot, func));
322 /* Find a device_t by domain/bus/slot/function */
325 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
327 struct pci_devinfo *dinfo;
329 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
330 if ((dinfo->cfg.domain == domain) &&
331 (dinfo->cfg.bus == bus) &&
332 (dinfo->cfg.slot == slot) &&
333 (dinfo->cfg.func == func)) {
334 return (dinfo->cfg.dev);
341 /* Find a device_t by vendor/device ID */
344 pci_find_device(uint16_t vendor, uint16_t device)
346 struct pci_devinfo *dinfo;
348 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
349 if ((dinfo->cfg.vendor == vendor) &&
350 (dinfo->cfg.device == device)) {
351 return (dinfo->cfg.dev);
358 /* return base address of memory or port map */
361 pci_mapbase(uint32_t mapreg)
364 if (PCI_BAR_MEM(mapreg))
365 return (mapreg & PCIM_BAR_MEM_BASE);
367 return (mapreg & PCIM_BAR_IO_BASE);
370 /* return map type of memory or port map */
373 pci_maptype(unsigned mapreg)
376 if (PCI_BAR_IO(mapreg))
378 if (mapreg & PCIM_BAR_MEM_PREFETCH)
379 return ("Prefetchable Memory");
383 /* return log2 of map size decoded for memory or port map */
386 pci_mapsize(uint32_t testval)
390 testval = pci_mapbase(testval);
393 while ((testval & 1) == 0)
402 /* return log2 of address range supported by map register */
405 pci_maprange(unsigned mapreg)
409 if (PCI_BAR_IO(mapreg))
412 switch (mapreg & PCIM_BAR_MEM_TYPE) {
413 case PCIM_BAR_MEM_32:
416 case PCIM_BAR_MEM_1MB:
419 case PCIM_BAR_MEM_64:
426 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
429 pci_fixancient(pcicfgregs *cfg)
431 if (cfg->hdrtype != 0)
434 /* PCI to PCI bridges use header type 1 */
435 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
439 /* extract header type specific config data */
442 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
444 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
445 switch (cfg->hdrtype) {
447 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
448 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
449 cfg->nummaps = PCI_MAXMAPS_0;
452 cfg->nummaps = PCI_MAXMAPS_1;
454 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
458 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
459 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
460 cfg->nummaps = PCI_MAXMAPS_2;
462 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
469 /* read configuration header into pcicfgregs structure */
471 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
473 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
474 pcicfgregs *cfg = NULL;
475 struct pci_devinfo *devlist_entry;
476 struct devlist *devlist_head;
478 devlist_head = &pci_devq;
480 devlist_entry = NULL;
482 if (REG(PCIR_DEVVENDOR, 4) != -1) {
483 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
485 cfg = &devlist_entry->cfg;
491 cfg->vendor = REG(PCIR_VENDOR, 2);
492 cfg->device = REG(PCIR_DEVICE, 2);
493 cfg->cmdreg = REG(PCIR_COMMAND, 2);
494 cfg->statreg = REG(PCIR_STATUS, 2);
495 cfg->baseclass = REG(PCIR_CLASS, 1);
496 cfg->subclass = REG(PCIR_SUBCLASS, 1);
497 cfg->progif = REG(PCIR_PROGIF, 1);
498 cfg->revid = REG(PCIR_REVID, 1);
499 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
500 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
501 cfg->lattimer = REG(PCIR_LATTIMER, 1);
502 cfg->intpin = REG(PCIR_INTPIN, 1);
503 cfg->intline = REG(PCIR_INTLINE, 1);
505 cfg->mingnt = REG(PCIR_MINGNT, 1);
506 cfg->maxlat = REG(PCIR_MAXLAT, 1);
508 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
509 cfg->hdrtype &= ~PCIM_MFDEV;
512 pci_hdrtypedata(pcib, b, s, f, cfg);
514 pci_read_capabilities(pcib, cfg);
516 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
518 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
519 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
520 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
521 devlist_entry->conf.pc_sel.pc_func = cfg->func;
522 devlist_entry->conf.pc_hdr = cfg->hdrtype;
524 devlist_entry->conf.pc_subvendor = cfg->subvendor;
525 devlist_entry->conf.pc_subdevice = cfg->subdevice;
526 devlist_entry->conf.pc_vendor = cfg->vendor;
527 devlist_entry->conf.pc_device = cfg->device;
529 devlist_entry->conf.pc_class = cfg->baseclass;
530 devlist_entry->conf.pc_subclass = cfg->subclass;
531 devlist_entry->conf.pc_progif = cfg->progif;
532 devlist_entry->conf.pc_revid = cfg->revid;
537 return (devlist_entry);
542 pci_fixup_nextptr(int *nextptr0)
544 int nextptr = *nextptr0;
546 /* "Next pointer" is only one byte */
547 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
551 * PCI local bus spec 3.0:
553 * "... The bottom two bits of all pointers are reserved
554 * and must be implemented as 00b although software must
555 * mask them to allow for future uses of these bits ..."
558 kprintf("Illegal PCI extended capability "
559 "offset, fixup 0x%02x -> 0x%02x\n",
560 nextptr, nextptr & ~0x3);
566 if (nextptr < 0x40) {
568 kprintf("Illegal PCI extended capability "
569 "offset 0x%02x", nextptr);
577 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
580 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
582 struct pcicfg_pp *pp = &cfg->pp;
587 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
588 pp->pp_status = ptr + PCIR_POWER_STATUS;
589 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
591 if ((nextptr - ptr) > PCIR_POWER_DATA) {
594 * We should write to data_select and read back from
595 * data_scale to determine whether data register is
599 pp->pp_data = ptr + PCIR_POWER_DATA;
609 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
611 #if defined(__i386__) || defined(__x86_64__)
614 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
616 struct pcicfg_ht *ht = &cfg->ht;
620 /* Determine HT-specific capability type. */
621 val = REG(ptr + PCIR_HT_COMMAND, 2);
623 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
624 cfg->ht.ht_slave = ptr;
626 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
629 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
630 /* Sanity check the mapping window. */
631 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
633 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
634 if (addr != MSI_X86_ADDR_BASE) {
635 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
636 "has non-default MSI window 0x%llx\n",
637 cfg->domain, cfg->bus, cfg->slot, cfg->func,
641 addr = MSI_X86_ADDR_BASE;
645 ht->ht_msictrl = val;
646 ht->ht_msiaddr = addr;
650 #endif /* __i386__ || __x86_64__ */
654 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
657 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
659 struct pcicfg_msi *msi = &cfg->msi;
661 msi->msi_location = ptr;
662 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
663 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
669 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
672 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
674 struct pcicfg_msix *msix = &cfg->msix;
677 msix->msix_location = ptr;
678 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
679 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
681 val = REG(ptr + PCIR_MSIX_TABLE, 4);
682 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
683 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
685 val = REG(ptr + PCIR_MSIX_PBA, 4);
686 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
687 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
689 TAILQ_INIT(&msix->msix_vectors);
695 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
697 cfg->vpd.vpd_reg = ptr;
701 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
704 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
706 /* Should always be true. */
707 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
710 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
711 cfg->subvendor = val & 0xffff;
712 cfg->subdevice = val >> 16;
719 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
722 * Assume we have a PCI-X chipset if we have
723 * at least one PCI-PCI bridge with a PCI-X
724 * capability. Note that some systems with
725 * PCI-express or HT chipsets might match on
726 * this check as well.
728 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
731 cfg->pcix.pcix_ptr = ptr;
735 pcie_slotimpl(const pcicfgregs *cfg)
737 const struct pcicfg_expr *expr = &cfg->expr;
741 * Only version 1 can be parsed currently
743 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
747 * - Slot implemented bit is meaningful iff current port is
748 * root port or down stream port.
749 * - Testing for root port or down stream port is meanningful
750 * iff PCI configure has type 1 header.
753 if (cfg->hdrtype != 1)
756 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
757 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
760 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
767 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
770 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
772 struct pcicfg_expr *expr = &cfg->expr;
775 * Assume we have a PCI-express chipset if we have
776 * at least one PCI-express device.
780 expr->expr_ptr = ptr;
781 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
784 * Only version 1 can be parsed currently
786 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
790 * Read slot capabilities. Slot capabilities exists iff
791 * current port's slot is implemented
793 if (pcie_slotimpl(cfg))
794 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
800 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
802 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
803 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
808 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
809 /* No capabilities */
813 switch (cfg->hdrtype & PCIM_HDRTYPE) {
816 ptrptr = PCIR_CAP_PTR;
819 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
822 return; /* no capabilities support */
824 nextptr = REG(ptrptr, 1); /* sanity check? */
827 * Read capability entries.
829 while (pci_fixup_nextptr(&nextptr)) {
830 const struct pci_read_cap *rc;
833 /* Find the next entry */
834 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
836 /* Process this entry */
837 val = REG(ptr + PCICAP_ID, 1);
838 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
839 if (rc->cap == val) {
840 rc->read_cap(pcib, ptr, nextptr, cfg);
846 #if defined(__i386__) || defined(__x86_64__)
848 * Enable the MSI mapping window for all HyperTransport
849 * slaves. PCI-PCI bridges have their windows enabled via
852 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
853 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
855 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
856 cfg->domain, cfg->bus, cfg->slot, cfg->func);
857 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
858 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
863 /* REG and WREG use carry through to next functions */
867 * PCI Vital Product Data
870 #define PCI_VPD_TIMEOUT 1000000
873 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
875 int count = PCI_VPD_TIMEOUT;
877 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
879 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
881 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
884 DELAY(1); /* limit looping */
886 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
893 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
895 int count = PCI_VPD_TIMEOUT;
897 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
899 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
900 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
901 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
904 DELAY(1); /* limit looping */
911 #undef PCI_VPD_TIMEOUT
913 struct vpd_readstate {
923 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
928 if (vrs->bytesinval == 0) {
929 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
931 vrs->val = le32toh(reg);
933 byte = vrs->val & 0xff;
936 vrs->val = vrs->val >> 8;
937 byte = vrs->val & 0xff;
947 pcie_slot_implemented(device_t dev)
949 struct pci_devinfo *dinfo = device_get_ivars(dev);
951 return pcie_slotimpl(&dinfo->cfg);
955 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
960 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
961 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
962 panic("%s: invalid max read request size 0x%02x\n",
963 device_get_nameunit(dev), rqsize);
966 expr_ptr = pci_get_pciecap_ptr(dev);
968 panic("%s: not PCIe device\n", device_get_nameunit(dev));
970 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
971 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
973 device_printf(dev, "adjust device control 0x%04x", val);
975 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
977 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
980 kprintf(" -> 0x%04x\n", val);
985 pcie_get_max_readrq(device_t dev)
990 expr_ptr = pci_get_pciecap_ptr(dev);
992 panic("%s: not PCIe device\n", device_get_nameunit(dev));
994 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
995 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
999 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
1001 struct vpd_readstate vrs;
1006 int alloc, off; /* alloc/off for RO/W arrays */
1012 /* init vpd reader */
1020 name = remain = i = 0; /* shut up stupid gcc */
1021 alloc = off = 0; /* shut up stupid gcc */
1022 dflen = 0; /* shut up stupid gcc */
1024 while (state >= 0) {
1025 if (vpd_nextbyte(&vrs, &byte)) {
1030 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1031 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1032 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1035 case 0: /* item name */
1037 if (vpd_nextbyte(&vrs, &byte2)) {
1042 if (vpd_nextbyte(&vrs, &byte2)) {
1046 remain |= byte2 << 8;
1047 if (remain > (0x7f*4 - vrs.off)) {
1050 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1051 cfg->domain, cfg->bus, cfg->slot,
1056 remain = byte & 0x7;
1057 name = (byte >> 3) & 0xf;
1060 case 0x2: /* String */
1061 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1062 M_DEVBUF, M_WAITOK);
1069 case 0x10: /* VPD-R */
1072 cfg->vpd.vpd_ros = kmalloc(alloc *
1073 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1077 case 0x11: /* VPD-W */
1080 cfg->vpd.vpd_w = kmalloc(alloc *
1081 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1085 default: /* Invalid data, abort */
1091 case 1: /* Identifier String */
1092 cfg->vpd.vpd_ident[i++] = byte;
1095 cfg->vpd.vpd_ident[i] = '\0';
1100 case 2: /* VPD-R Keyword Header */
1102 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1103 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1104 M_DEVBUF, M_WAITOK | M_ZERO);
1106 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1107 if (vpd_nextbyte(&vrs, &byte2)) {
1111 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1112 if (vpd_nextbyte(&vrs, &byte2)) {
1118 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1121 * if this happens, we can't trust the rest
1125 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1126 cfg->domain, cfg->bus, cfg->slot,
1131 } else if (dflen == 0) {
1132 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1133 sizeof(*cfg->vpd.vpd_ros[off].value),
1134 M_DEVBUF, M_WAITOK);
1135 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1137 cfg->vpd.vpd_ros[off].value = kmalloc(
1139 sizeof(*cfg->vpd.vpd_ros[off].value),
1140 M_DEVBUF, M_WAITOK);
1143 /* keep in sync w/ state 3's transistions */
1144 if (dflen == 0 && remain == 0)
1146 else if (dflen == 0)
1152 case 3: /* VPD-R Keyword Value */
1153 cfg->vpd.vpd_ros[off].value[i++] = byte;
1154 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1155 "RV", 2) == 0 && cksumvalid == -1) {
1161 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1162 cfg->domain, cfg->bus,
1163 cfg->slot, cfg->func,
1172 /* keep in sync w/ state 2's transistions */
1174 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1175 if (dflen == 0 && remain == 0) {
1176 cfg->vpd.vpd_rocnt = off;
1177 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1178 off * sizeof(*cfg->vpd.vpd_ros),
1179 M_DEVBUF, M_WAITOK | M_ZERO);
1181 } else if (dflen == 0)
1191 case 5: /* VPD-W Keyword Header */
1193 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1194 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1195 M_DEVBUF, M_WAITOK | M_ZERO);
1197 cfg->vpd.vpd_w[off].keyword[0] = byte;
1198 if (vpd_nextbyte(&vrs, &byte2)) {
1202 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1203 if (vpd_nextbyte(&vrs, &byte2)) {
1207 cfg->vpd.vpd_w[off].len = dflen = byte2;
1208 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1209 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1210 sizeof(*cfg->vpd.vpd_w[off].value),
1211 M_DEVBUF, M_WAITOK);
1214 /* keep in sync w/ state 6's transistions */
1215 if (dflen == 0 && remain == 0)
1217 else if (dflen == 0)
1223 case 6: /* VPD-W Keyword Value */
1224 cfg->vpd.vpd_w[off].value[i++] = byte;
1227 /* keep in sync w/ state 5's transistions */
1229 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1230 if (dflen == 0 && remain == 0) {
1231 cfg->vpd.vpd_wcnt = off;
1232 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1233 off * sizeof(*cfg->vpd.vpd_w),
1234 M_DEVBUF, M_WAITOK | M_ZERO);
1236 } else if (dflen == 0)
1241 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1242 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1249 if (cksumvalid == 0 || state < -1) {
1250 /* read-only data bad, clean up */
1251 if (cfg->vpd.vpd_ros != NULL) {
1252 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1253 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1254 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1255 cfg->vpd.vpd_ros = NULL;
1259 /* I/O error, clean up */
1260 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1261 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1262 if (cfg->vpd.vpd_ident != NULL) {
1263 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1264 cfg->vpd.vpd_ident = NULL;
1266 if (cfg->vpd.vpd_w != NULL) {
1267 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1268 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1269 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1270 cfg->vpd.vpd_w = NULL;
1273 cfg->vpd.vpd_cached = 1;
1279 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1281 struct pci_devinfo *dinfo = device_get_ivars(child);
1282 pcicfgregs *cfg = &dinfo->cfg;
1284 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1285 pci_read_vpd(device_get_parent(dev), cfg);
1287 *identptr = cfg->vpd.vpd_ident;
1289 if (*identptr == NULL)
1296 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1299 struct pci_devinfo *dinfo = device_get_ivars(child);
1300 pcicfgregs *cfg = &dinfo->cfg;
1303 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1304 pci_read_vpd(device_get_parent(dev), cfg);
1306 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1307 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1308 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1309 *vptr = cfg->vpd.vpd_ros[i].value;
1312 if (i != cfg->vpd.vpd_rocnt)
1320 * Return the offset in configuration space of the requested extended
1321 * capability entry or 0 if the specified capability was not found.
1324 pci_find_extcap_method(device_t dev, device_t child, int capability,
1327 struct pci_devinfo *dinfo = device_get_ivars(child);
1328 pcicfgregs *cfg = &dinfo->cfg;
1333 * Check the CAP_LIST bit of the PCI status register first.
1335 status = pci_read_config(child, PCIR_STATUS, 2);
1336 if (!(status & PCIM_STATUS_CAPPRESENT))
1340 * Determine the start pointer of the capabilities list.
1342 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1348 ptr = PCIR_CAP_PTR_2;
1352 return (ENXIO); /* no extended capabilities support */
1354 ptr = pci_read_config(child, ptr, 1);
1357 * Traverse the capabilities list.
1360 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1365 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1372 * Support for MSI-X message interrupts.
1375 pci_setup_msix_vector(device_t dev, u_int index, uint64_t address,
1378 struct pci_devinfo *dinfo = device_get_ivars(dev);
1379 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1382 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1383 offset = msix->msix_table_offset + index * 16;
1384 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1385 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1386 bus_write_4(msix->msix_table_res, offset + 8, data);
1388 /* Enable MSI -> HT mapping. */
1389 pci_ht_map_msi(dev, address);
1393 pci_mask_msix_vector(device_t dev, u_int index)
1395 struct pci_devinfo *dinfo = device_get_ivars(dev);
1396 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1397 uint32_t offset, val;
1399 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1400 offset = msix->msix_table_offset + index * 16 + 12;
1401 val = bus_read_4(msix->msix_table_res, offset);
1402 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1403 val |= PCIM_MSIX_VCTRL_MASK;
1404 bus_write_4(msix->msix_table_res, offset, val);
1409 pci_unmask_msix_vector(device_t dev, u_int index)
1411 struct pci_devinfo *dinfo = device_get_ivars(dev);
1412 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1413 uint32_t offset, val;
1415 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1416 offset = msix->msix_table_offset + index * 16 + 12;
1417 val = bus_read_4(msix->msix_table_res, offset);
1418 if (val & PCIM_MSIX_VCTRL_MASK) {
1419 val &= ~PCIM_MSIX_VCTRL_MASK;
1420 bus_write_4(msix->msix_table_res, offset, val);
1425 pci_pending_msix_vector(device_t dev, u_int index)
1427 struct pci_devinfo *dinfo = device_get_ivars(dev);
1428 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1429 uint32_t offset, bit;
1431 KASSERT(msix->msix_table_res != NULL && msix->msix_pba_res != NULL,
1432 ("MSI-X is not setup yet\n"));
1434 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1435 offset = msix->msix_pba_offset + (index / 32) * 4;
1436 bit = 1 << index % 32;
1437 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1441 * Restore MSI-X registers and table during resume. If MSI-X is
1442 * enabled then walk the virtual table to restore the actual MSI-X
1446 pci_resume_msix(device_t dev)
1448 struct pci_devinfo *dinfo = device_get_ivars(dev);
1449 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1451 if (msix->msix_alloc > 0) {
1452 const struct msix_vector *mv;
1454 pci_mask_msix_allvectors(dev);
1456 TAILQ_FOREACH(mv, &msix->msix_vectors, mv_link) {
1459 if (mv->mv_address == 0)
1462 vector = PCI_MSIX_RID2VEC(mv->mv_rid);
1463 pci_setup_msix_vector(dev, vector,
1464 mv->mv_address, mv->mv_data);
1465 pci_unmask_msix_vector(dev, vector);
1468 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1469 msix->msix_ctrl, 2);
1473 * Attempt to allocate one MSI-X message at the specified vector on cpuid.
1475 * After this function returns, the MSI-X's rid will be saved in rid0.
1478 pci_alloc_msix_vector_method(device_t dev, device_t child, u_int vector,
1479 int *rid0, int cpuid)
1481 struct pci_devinfo *dinfo = device_get_ivars(child);
1482 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1483 struct msix_vector *mv;
1484 struct resource_list_entry *rle;
1485 int error, irq, rid;
1487 KASSERT(msix->msix_table_res != NULL &&
1488 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1489 KASSERT(cpuid >= 0 && cpuid < ncpus, ("invalid cpuid %d\n", cpuid));
1490 KASSERT(vector < msix->msix_msgnum,
1491 ("invalid MSI-X vector %u, total %d\n", vector, msix->msix_msgnum));
1494 device_printf(child,
1495 "attempting to allocate MSI-X #%u vector (%d supported)\n",
1496 vector, msix->msix_msgnum);
1499 /* Set rid according to vector number */
1500 rid = PCI_MSIX_VEC2RID(vector);
1502 /* Vector has already been allocated */
1503 mv = pci_find_msix_vector(child, rid);
1507 /* Allocate a message. */
1508 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq, cpuid);
1511 resource_list_add(&dinfo->resources, SYS_RES_IRQ, rid,
1512 irq, irq, 1, cpuid);
1515 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
1516 device_printf(child, "using IRQ %lu for MSI-X on cpu%d\n",
1520 /* Update counts of alloc'd messages. */
1523 mv = kmalloc(sizeof(*mv), M_DEVBUF, M_WAITOK | M_ZERO);
1525 TAILQ_INSERT_TAIL(&msix->msix_vectors, mv, mv_link);
1532 pci_release_msix_vector_method(device_t dev, device_t child, int rid)
1534 struct pci_devinfo *dinfo = device_get_ivars(child);
1535 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1536 struct resource_list_entry *rle;
1537 struct msix_vector *mv;
1540 KASSERT(msix->msix_table_res != NULL &&
1541 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1542 KASSERT(msix->msix_alloc > 0, ("No MSI-X allocated\n"));
1543 KASSERT(rid > 0, ("invalid rid %d\n", rid));
1545 mv = pci_find_msix_vector(child, rid);
1546 KASSERT(mv != NULL, ("MSI-X rid %d is not allocated\n", rid));
1547 KASSERT(mv->mv_address == 0, ("MSI-X rid %d not teardown\n", rid));
1549 /* Make sure resource is no longer allocated. */
1550 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
1551 KASSERT(rle != NULL, ("missing MSI-X resource, rid %d\n", rid));
1552 KASSERT(rle->res == NULL,
1553 ("MSI-X resource is still allocated, rid %d\n", rid));
1558 /* Free the resource list entries. */
1559 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, rid);
1561 /* Release the IRQ. */
1562 PCIB_RELEASE_MSIX(device_get_parent(dev), child, irq, cpuid);
1564 TAILQ_REMOVE(&msix->msix_vectors, mv, mv_link);
1565 kfree(mv, M_DEVBUF);
1572 * Return the max supported MSI-X messages this device supports.
1573 * Basically, assuming the MD code can alloc messages, this function
1574 * should return the maximum value that pci_alloc_msix() can return.
1575 * Thus, it is subject to the tunables, etc.
1578 pci_msix_count_method(device_t dev, device_t child)
1580 struct pci_devinfo *dinfo = device_get_ivars(child);
1581 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1583 if (pci_do_msix && msix->msix_location != 0)
1584 return (msix->msix_msgnum);
1589 pci_setup_msix(device_t dev)
1591 struct pci_devinfo *dinfo = device_get_ivars(dev);
1592 pcicfgregs *cfg = &dinfo->cfg;
1593 struct resource_list_entry *rle;
1594 struct resource *table_res, *pba_res;
1596 KASSERT(cfg->msix.msix_table_res == NULL &&
1597 cfg->msix.msix_pba_res == NULL, ("MSI-X has been setup yet\n"));
1599 /* If rid 0 is allocated, then fail. */
1600 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1601 if (rle != NULL && rle->res != NULL)
1604 /* Already have allocated MSIs? */
1605 if (cfg->msi.msi_alloc != 0)
1608 /* If MSI is blacklisted for this system, fail. */
1609 if (pci_msi_blacklisted())
1612 /* MSI-X capability present? */
1613 if (cfg->msix.msix_location == 0 || cfg->msix.msix_msgnum == 0 ||
1617 KASSERT(cfg->msix.msix_alloc == 0 &&
1618 TAILQ_EMPTY(&cfg->msix.msix_vectors),
1619 ("MSI-X vector has been allocated\n"));
1621 /* Make sure the appropriate BARs are mapped. */
1622 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1623 cfg->msix.msix_table_bar);
1624 if (rle == NULL || rle->res == NULL ||
1625 !(rman_get_flags(rle->res) & RF_ACTIVE))
1627 table_res = rle->res;
1628 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1629 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1630 cfg->msix.msix_pba_bar);
1631 if (rle == NULL || rle->res == NULL ||
1632 !(rman_get_flags(rle->res) & RF_ACTIVE))
1637 cfg->msix.msix_table_res = table_res;
1638 cfg->msix.msix_pba_res = pba_res;
1640 pci_mask_msix_allvectors(dev);
1646 pci_teardown_msix(device_t dev)
1648 struct pci_devinfo *dinfo = device_get_ivars(dev);
1649 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1651 KASSERT(msix->msix_table_res != NULL &&
1652 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1653 KASSERT(msix->msix_alloc == 0 && TAILQ_EMPTY(&msix->msix_vectors),
1654 ("MSI-X vector is still allocated\n"));
1656 pci_mask_msix_allvectors(dev);
1658 msix->msix_table_res = NULL;
1659 msix->msix_pba_res = NULL;
1663 pci_enable_msix(device_t dev)
1665 struct pci_devinfo *dinfo = device_get_ivars(dev);
1666 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1668 KASSERT(msix->msix_table_res != NULL &&
1669 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1671 /* Update control register to enable MSI-X. */
1672 msix->msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1673 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1674 msix->msix_ctrl, 2);
1678 pci_disable_msix(device_t dev)
1680 struct pci_devinfo *dinfo = device_get_ivars(dev);
1681 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1683 KASSERT(msix->msix_table_res != NULL &&
1684 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1686 /* Disable MSI -> HT mapping. */
1687 pci_ht_map_msi(dev, 0);
1689 /* Update control register to disable MSI-X. */
1690 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1691 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1692 msix->msix_ctrl, 2);
1696 pci_mask_msix_allvectors(device_t dev)
1698 struct pci_devinfo *dinfo = device_get_ivars(dev);
1701 for (i = 0; i < dinfo->cfg.msix.msix_msgnum; ++i)
1702 pci_mask_msix_vector(dev, i);
1705 static struct msix_vector *
1706 pci_find_msix_vector(device_t dev, int rid)
1708 struct pci_devinfo *dinfo = device_get_ivars(dev);
1709 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1710 struct msix_vector *mv;
1712 TAILQ_FOREACH(mv, &msix->msix_vectors, mv_link) {
1713 if (mv->mv_rid == rid)
1720 * HyperTransport MSI mapping control
1723 pci_ht_map_msi(device_t dev, uint64_t addr)
1725 struct pci_devinfo *dinfo = device_get_ivars(dev);
1726 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1731 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1732 ht->ht_msiaddr >> 20 == addr >> 20) {
1733 /* Enable MSI -> HT mapping. */
1734 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1735 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1739 if (!addr && (ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
1740 /* Disable MSI -> HT mapping. */
1741 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1742 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1748 * Support for MSI message signalled interrupts.
1751 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1753 struct pci_devinfo *dinfo = device_get_ivars(dev);
1754 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1756 /* Write data and address values. */
1757 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1758 address & 0xffffffff, 4);
1759 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1760 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1762 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1765 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1768 /* Enable MSI in the control register. */
1769 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1770 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1773 /* Enable MSI -> HT mapping. */
1774 pci_ht_map_msi(dev, address);
1778 pci_disable_msi(device_t dev)
1780 struct pci_devinfo *dinfo = device_get_ivars(dev);
1781 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1783 /* Disable MSI -> HT mapping. */
1784 pci_ht_map_msi(dev, 0);
1786 /* Disable MSI in the control register. */
1787 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1788 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1793 * Restore MSI registers during resume. If MSI is enabled then
1794 * restore the data and address registers in addition to the control
1798 pci_resume_msi(device_t dev)
1800 struct pci_devinfo *dinfo = device_get_ivars(dev);
1801 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1805 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1806 address = msi->msi_addr;
1807 data = msi->msi_data;
1808 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1809 address & 0xffffffff, 4);
1810 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1811 pci_write_config(dev, msi->msi_location +
1812 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1813 pci_write_config(dev, msi->msi_location +
1814 PCIR_MSI_DATA_64BIT, data, 2);
1816 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1819 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1824 * Returns true if the specified device is blacklisted because MSI
1828 pci_msi_device_blacklisted(device_t dev)
1830 struct pci_quirk *q;
1832 if (!pci_honor_msi_blacklist)
1835 for (q = &pci_quirks[0]; q->devid; q++) {
1836 if (q->devid == pci_get_devid(dev) &&
1837 q->type == PCI_QUIRK_DISABLE_MSI)
1844 * Determine if MSI is blacklisted globally on this sytem. Currently,
1845 * we just check for blacklisted chipsets as represented by the
1846 * host-PCI bridge at device 0:0:0. In the future, it may become
1847 * necessary to check other system attributes, such as the kenv values
1848 * that give the motherboard manufacturer and model number.
1851 pci_msi_blacklisted(void)
1855 if (!pci_honor_msi_blacklist)
1858 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1859 if (!(pcie_chipset || pcix_chipset))
1862 dev = pci_find_bsf(0, 0, 0);
1864 return (pci_msi_device_blacklisted(dev));
1869 * Attempt to allocate count MSI messages on start_cpuid.
1871 * If start_cpuid < 0, then the MSI messages' target CPU will be
1872 * selected automaticly.
1874 * If the caller explicitly specified the MSI messages' target CPU,
1875 * i.e. start_cpuid >= 0, then we will try to allocate the count MSI
1876 * messages on the specified CPU, if the allocation fails due to MD
1877 * does not have enough vectors (EMSGSIZE), then we will try next
1878 * available CPU, until the allocation fails on all CPUs.
1880 * EMSGSIZE will be returned, if all available CPUs does not have
1881 * enough vectors for the requested amount of MSI messages. Caller
1882 * should either reduce the amount of MSI messages to be requested,
1883 * or simply giving up using MSI.
1885 * The available SYS_RES_IRQ resources' rids, which are >= 1, are
1886 * returned in 'rid' array, if the allocation succeeds.
1889 pci_alloc_msi_method(device_t dev, device_t child, int *rid, int count,
1892 struct pci_devinfo *dinfo = device_get_ivars(child);
1893 pcicfgregs *cfg = &dinfo->cfg;
1894 struct resource_list_entry *rle;
1895 int error, i, irqs[32], cpuid = 0;
1898 KASSERT(count != 0 && count <= 32 && powerof2(count),
1899 ("invalid MSI count %d\n", count));
1900 KASSERT(start_cpuid < ncpus, ("invalid cpuid %d\n", start_cpuid));
1902 /* If rid 0 is allocated, then fail. */
1903 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1904 if (rle != NULL && rle->res != NULL)
1907 /* Already have allocated messages? */
1908 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1911 /* If MSI is blacklisted for this system, fail. */
1912 if (pci_msi_blacklisted())
1915 /* MSI capability present? */
1916 if (cfg->msi.msi_location == 0 || cfg->msi.msi_msgnum == 0 ||
1920 KASSERT(count <= cfg->msi.msi_msgnum, ("large MSI count %d, max %d\n",
1921 count, cfg->msi.msi_msgnum));
1924 device_printf(child,
1925 "attempting to allocate %d MSI vectors (%d supported)\n",
1926 count, cfg->msi.msi_msgnum);
1929 if (start_cpuid < 0)
1930 start_cpuid = atomic_fetchadd_int(&pci_msi_cpuid, 1) % ncpus;
1933 for (i = 0; i < ncpus; ++i) {
1934 cpuid = (start_cpuid + i) % ncpus;
1936 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, count,
1937 cfg->msi.msi_msgnum, irqs, cpuid);
1940 else if (error != EMSGSIZE)
1947 * We now have N messages mapped onto SYS_RES_IRQ resources in
1948 * the irqs[] array, so add new resources starting at rid 1.
1950 for (i = 0; i < count; i++) {
1952 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1953 irqs[i], irqs[i], 1, cpuid);
1958 device_printf(child, "using IRQ %d on cpu%d for MSI\n",
1964 * Be fancy and try to print contiguous runs
1965 * of IRQ values as ranges. 'run' is true if
1966 * we are in a range.
1968 device_printf(child, "using IRQs %d", irqs[0]);
1970 for (i = 1; i < count; i++) {
1972 /* Still in a run? */
1973 if (irqs[i] == irqs[i - 1] + 1) {
1978 /* Finish previous range. */
1980 kprintf("-%d", irqs[i - 1]);
1984 /* Start new range. */
1985 kprintf(",%d", irqs[i]);
1988 /* Unfinished range? */
1990 kprintf("-%d", irqs[count - 1]);
1991 kprintf(" for MSI on cpu%d\n", cpuid);
1995 /* Update control register with count. */
1996 ctrl = cfg->msi.msi_ctrl;
1997 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1998 ctrl |= (ffs(count) - 1) << 4;
1999 cfg->msi.msi_ctrl = ctrl;
2000 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2002 /* Update counts of alloc'd messages. */
2003 cfg->msi.msi_alloc = count;
2004 cfg->msi.msi_handlers = 0;
2008 /* Release the MSI messages associated with this device. */
2010 pci_release_msi_method(device_t dev, device_t child)
2012 struct pci_devinfo *dinfo = device_get_ivars(child);
2013 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2014 struct resource_list_entry *rle;
2015 int i, irqs[32], cpuid = -1;
2017 /* Do we have any messages to release? */
2018 if (msi->msi_alloc == 0)
2020 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2022 /* Make sure none of the resources are allocated. */
2023 if (msi->msi_handlers > 0)
2025 for (i = 0; i < msi->msi_alloc; i++) {
2026 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2027 KASSERT(rle != NULL, ("missing MSI resource"));
2028 if (rle->res != NULL)
2032 KASSERT(cpuid >= 0 && cpuid < ncpus,
2033 ("invalid MSI target cpuid %d\n", cpuid));
2035 KASSERT(rle->cpuid == cpuid,
2036 ("MSI targets different cpus, "
2037 "was cpu%d, now cpu%d", cpuid, rle->cpuid));
2039 irqs[i] = rle->start;
2042 /* Update control register with 0 count. */
2043 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2044 ("%s: MSI still enabled", __func__));
2045 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2046 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2049 /* Release the messages. */
2050 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs,
2052 for (i = 0; i < msi->msi_alloc; i++)
2053 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2055 /* Update alloc count. */
2063 * Return the max supported MSI messages this device supports.
2064 * Basically, assuming the MD code can alloc messages, this function
2065 * should return the maximum value that pci_alloc_msi() can return.
2066 * Thus, it is subject to the tunables, etc.
2069 pci_msi_count_method(device_t dev, device_t child)
2071 struct pci_devinfo *dinfo = device_get_ivars(child);
2072 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2074 if (pci_do_msi && msi->msi_location != 0)
2075 return (msi->msi_msgnum);
2079 /* kfree pcicfgregs structure and all depending data structures */
2082 pci_freecfg(struct pci_devinfo *dinfo)
2084 struct devlist *devlist_head;
2087 devlist_head = &pci_devq;
2089 if (dinfo->cfg.vpd.vpd_reg) {
2090 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2091 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2092 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2093 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2094 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2095 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2096 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2098 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2099 kfree(dinfo, M_DEVBUF);
2101 /* increment the generation count */
2104 /* we're losing one device */
2110 * PCI power manangement
2113 pci_set_powerstate_method(device_t dev, device_t child, int state)
2115 struct pci_devinfo *dinfo = device_get_ivars(child);
2116 pcicfgregs *cfg = &dinfo->cfg;
2118 int result, oldstate, highest, delay;
2120 if (cfg->pp.pp_cap == 0)
2121 return (EOPNOTSUPP);
2124 * Optimize a no state change request away. While it would be OK to
2125 * write to the hardware in theory, some devices have shown odd
2126 * behavior when going from D3 -> D3.
2128 oldstate = pci_get_powerstate(child);
2129 if (oldstate == state)
2133 * The PCI power management specification states that after a state
2134 * transition between PCI power states, system software must
2135 * guarantee a minimal delay before the function accesses the device.
2136 * Compute the worst case delay that we need to guarantee before we
2137 * access the device. Many devices will be responsive much more
2138 * quickly than this delay, but there are some that don't respond
2139 * instantly to state changes. Transitions to/from D3 state require
2140 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2141 * is done below with DELAY rather than a sleeper function because
2142 * this function can be called from contexts where we cannot sleep.
2144 highest = (oldstate > state) ? oldstate : state;
2145 if (highest == PCI_POWERSTATE_D3)
2147 else if (highest == PCI_POWERSTATE_D2)
2151 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2152 & ~PCIM_PSTAT_DMASK;
2155 case PCI_POWERSTATE_D0:
2156 status |= PCIM_PSTAT_D0;
2158 case PCI_POWERSTATE_D1:
2159 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2160 return (EOPNOTSUPP);
2161 status |= PCIM_PSTAT_D1;
2163 case PCI_POWERSTATE_D2:
2164 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2165 return (EOPNOTSUPP);
2166 status |= PCIM_PSTAT_D2;
2168 case PCI_POWERSTATE_D3:
2169 status |= PCIM_PSTAT_D3;
2177 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2178 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2179 dinfo->cfg.func, oldstate, state);
2181 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2188 pci_get_powerstate_method(device_t dev, device_t child)
2190 struct pci_devinfo *dinfo = device_get_ivars(child);
2191 pcicfgregs *cfg = &dinfo->cfg;
2195 if (cfg->pp.pp_cap != 0) {
2196 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2197 switch (status & PCIM_PSTAT_DMASK) {
2199 result = PCI_POWERSTATE_D0;
2202 result = PCI_POWERSTATE_D1;
2205 result = PCI_POWERSTATE_D2;
2208 result = PCI_POWERSTATE_D3;
2211 result = PCI_POWERSTATE_UNKNOWN;
2215 /* No support, device is always at D0 */
2216 result = PCI_POWERSTATE_D0;
2222 * Some convenience functions for PCI device drivers.
2225 static __inline void
2226 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2230 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2232 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2235 static __inline void
2236 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2240 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2242 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2246 pci_enable_busmaster_method(device_t dev, device_t child)
2248 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2253 pci_disable_busmaster_method(device_t dev, device_t child)
2255 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2260 pci_enable_io_method(device_t dev, device_t child, int space)
2270 case SYS_RES_IOPORT:
2271 bit = PCIM_CMD_PORTEN;
2274 case SYS_RES_MEMORY:
2275 bit = PCIM_CMD_MEMEN;
2281 pci_set_command_bit(dev, child, bit);
2282 /* Some devices seem to need a brief stall here, what do to? */
2283 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2286 device_printf(child, "failed to enable %s mapping!\n", error);
2291 pci_disable_io_method(device_t dev, device_t child, int space)
2301 case SYS_RES_IOPORT:
2302 bit = PCIM_CMD_PORTEN;
2305 case SYS_RES_MEMORY:
2306 bit = PCIM_CMD_MEMEN;
2312 pci_clear_command_bit(dev, child, bit);
2313 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2314 if (command & bit) {
2315 device_printf(child, "failed to disable %s mapping!\n", error);
2322 * New style pci driver. Parent device is either a pci-host-bridge or a
2323 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2327 pci_print_verbose(struct pci_devinfo *dinfo)
2331 pcicfgregs *cfg = &dinfo->cfg;
2333 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2334 cfg->vendor, cfg->device, cfg->revid);
2335 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2336 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2337 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2338 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2340 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2341 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2342 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2343 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2344 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2345 if (cfg->intpin > 0)
2346 kprintf("\tintpin=%c, irq=%d\n",
2347 cfg->intpin +'a' -1, cfg->intline);
2348 if (cfg->pp.pp_cap) {
2351 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2352 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2353 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2354 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2355 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2356 status & PCIM_PSTAT_DMASK);
2358 if (cfg->msi.msi_location) {
2361 ctrl = cfg->msi.msi_ctrl;
2362 kprintf("\tMSI supports %d message%s%s%s\n",
2363 cfg->msi.msi_msgnum,
2364 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2365 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2366 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2368 if (cfg->msix.msix_location) {
2369 kprintf("\tMSI-X supports %d message%s ",
2370 cfg->msix.msix_msgnum,
2371 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2372 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2373 kprintf("in map 0x%x\n",
2374 cfg->msix.msix_table_bar);
2376 kprintf("in maps 0x%x and 0x%x\n",
2377 cfg->msix.msix_table_bar,
2378 cfg->msix.msix_pba_bar);
2380 pci_print_verbose_expr(cfg);
2385 pci_print_verbose_expr(const pcicfgregs *cfg)
2387 const struct pcicfg_expr *expr = &cfg->expr;
2388 const char *port_name;
2394 if (expr->expr_ptr == 0) /* No PCI Express capability */
2397 kprintf("\tPCI Express ver.%d cap=0x%04x",
2398 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2399 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2402 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2404 switch (port_type) {
2405 case PCIE_END_POINT:
2406 port_name = "DEVICE";
2408 case PCIE_LEG_END_POINT:
2409 port_name = "LEGDEV";
2411 case PCIE_ROOT_PORT:
2414 case PCIE_UP_STREAM_PORT:
2415 port_name = "UPSTREAM";
2417 case PCIE_DOWN_STREAM_PORT:
2418 port_name = "DOWNSTRM";
2420 case PCIE_PCIE2PCI_BRIDGE:
2421 port_name = "PCIE2PCI";
2423 case PCIE_PCI2PCIE_BRIDGE:
2424 port_name = "PCI2PCIE";
2430 if ((port_type == PCIE_ROOT_PORT ||
2431 port_type == PCIE_DOWN_STREAM_PORT) &&
2432 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2434 if (port_name != NULL)
2435 kprintf("[%s]", port_name);
2437 if (pcie_slotimpl(cfg)) {
2438 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2439 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2440 kprintf("[HOTPLUG]");
2447 pci_porten(device_t pcib, int b, int s, int f)
2449 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2450 & PCIM_CMD_PORTEN) != 0;
2454 pci_memen(device_t pcib, int b, int s, int f)
2456 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2457 & PCIM_CMD_MEMEN) != 0;
2461 * Add a resource based on a pci map register. Return 1 if the map
2462 * register is a 32bit map register or 2 if it is a 64bit register.
2465 pci_add_map(device_t pcib, device_t bus, device_t dev,
2466 int b, int s, int f, int reg, struct resource_list *rl, int force,
2471 pci_addr_t start, end, count;
2478 struct resource *res;
2480 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2481 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2482 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2483 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2485 if (PCI_BAR_MEM(map)) {
2486 type = SYS_RES_MEMORY;
2487 if (map & PCIM_BAR_MEM_PREFETCH)
2490 type = SYS_RES_IOPORT;
2491 ln2size = pci_mapsize(testval);
2492 ln2range = pci_maprange(testval);
2493 base = pci_mapbase(map);
2494 barlen = ln2range == 64 ? 2 : 1;
2497 * For I/O registers, if bottom bit is set, and the next bit up
2498 * isn't clear, we know we have a BAR that doesn't conform to the
2499 * spec, so ignore it. Also, sanity check the size of the data
2500 * areas to the type of memory involved. Memory must be at least
2501 * 16 bytes in size, while I/O ranges must be at least 4.
2503 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2505 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2506 (type == SYS_RES_IOPORT && ln2size < 2))
2510 /* Read the other half of a 64bit map register */
2511 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2513 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2514 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2515 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2516 kprintf(", port disabled\n");
2517 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2518 kprintf(", memory disabled\n");
2520 kprintf(", enabled\n");
2524 * If base is 0, then we have problems. It is best to ignore
2525 * such entries for the moment. These will be allocated later if
2526 * the driver specifically requests them. However, some
2527 * removable busses look better when all resources are allocated,
2528 * so allow '0' to be overriden.
2530 * Similarly treat maps whose values is the same as the test value
2531 * read back. These maps have had all f's written to them by the
2532 * BIOS in an attempt to disable the resources.
2534 if (!force && (base == 0 || map == testval))
2536 if ((u_long)base != base) {
2538 "pci%d:%d:%d:%d bar %#x too many address bits",
2539 pci_get_domain(dev), b, s, f, reg);
2544 * This code theoretically does the right thing, but has
2545 * undesirable side effects in some cases where peripherals
2546 * respond oddly to having these bits enabled. Let the user
2547 * be able to turn them off (since pci_enable_io_modes is 1 by
2550 if (pci_enable_io_modes) {
2551 /* Turn on resources that have been left off by a lazy BIOS */
2552 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2553 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2554 cmd |= PCIM_CMD_PORTEN;
2555 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2557 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2558 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2559 cmd |= PCIM_CMD_MEMEN;
2560 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2563 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2565 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2569 count = 1 << ln2size;
2570 if (base == 0 || base == pci_mapbase(testval)) {
2571 start = 0; /* Let the parent decide. */
2575 end = base + (1 << ln2size) - 1;
2577 resource_list_add(rl, type, reg, start, end, count, -1);
2580 * Try to allocate the resource for this BAR from our parent
2581 * so that this resource range is already reserved. The
2582 * driver for this device will later inherit this resource in
2583 * pci_alloc_resource().
2585 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2586 prefetch ? RF_PREFETCHABLE : 0, -1);
2589 * If the allocation fails, delete the resource list
2590 * entry to force pci_alloc_resource() to allocate
2591 * resources from the parent.
2593 resource_list_delete(rl, type, reg);
2594 #ifdef PCI_BAR_CLEAR
2597 #else /* !PCI_BAR_CLEAR */
2599 * Don't clear BAR here. Some BIOS lists HPET as a
2600 * PCI function, clearing the BAR causes HPET timer
2604 kprintf("pci:%d:%d:%d: resource reservation failed "
2605 "%#jx - %#jx\n", b, s, f,
2606 (intmax_t)start, (intmax_t)end);
2609 #endif /* PCI_BAR_CLEAR */
2611 start = rman_get_start(res);
2613 pci_write_config(dev, reg, start, 4);
2615 pci_write_config(dev, reg + 4, start >> 32, 4);
2620 * For ATA devices we need to decide early what addressing mode to use.
2621 * Legacy demands that the primary and secondary ATA ports sits on the
2622 * same addresses that old ISA hardware did. This dictates that we use
2623 * those addresses and ignore the BAR's if we cannot set PCI native
2627 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2628 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2630 int rid, type, progif;
2632 /* if this device supports PCI native addressing use it */
2633 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2634 if ((progif & 0x8a) == 0x8a) {
2635 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2636 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2637 kprintf("Trying ATA native PCI addressing mode\n");
2638 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2642 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2643 type = SYS_RES_IOPORT;
2644 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2645 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2646 prefetchmask & (1 << 0));
2647 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2648 prefetchmask & (1 << 1));
2651 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
2652 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2655 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
2656 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2659 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2660 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2661 prefetchmask & (1 << 2));
2662 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2663 prefetchmask & (1 << 3));
2666 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
2667 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2670 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
2671 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2674 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2675 prefetchmask & (1 << 4));
2676 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2677 prefetchmask & (1 << 5));
2681 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2683 struct pci_devinfo *dinfo = device_get_ivars(dev);
2684 pcicfgregs *cfg = &dinfo->cfg;
2685 char tunable_name[64];
2688 /* Has to have an intpin to have an interrupt. */
2689 if (cfg->intpin == 0)
2692 /* Let the user override the IRQ with a tunable. */
2693 irq = PCI_INVALID_IRQ;
2694 ksnprintf(tunable_name, sizeof(tunable_name),
2695 "hw.pci%d.%d.%d.INT%c.irq",
2696 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2697 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2698 irq = PCI_INVALID_IRQ;
2701 * If we didn't get an IRQ via the tunable, then we either use the
2702 * IRQ value in the intline register or we ask the bus to route an
2703 * interrupt for us. If force_route is true, then we only use the
2704 * value in the intline register if the bus was unable to assign an
2707 if (!PCI_INTERRUPT_VALID(irq)) {
2708 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2709 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2710 if (!PCI_INTERRUPT_VALID(irq))
2714 /* If after all that we don't have an IRQ, just bail. */
2715 if (!PCI_INTERRUPT_VALID(irq))
2718 /* Update the config register if it changed. */
2719 if (irq != cfg->intline) {
2721 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2724 /* Add this IRQ as rid 0 interrupt resource. */
2725 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1,
2726 machintr_legacy_intr_cpuid(irq));
2730 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2732 struct pci_devinfo *dinfo = device_get_ivars(dev);
2733 pcicfgregs *cfg = &dinfo->cfg;
2734 struct resource_list *rl = &dinfo->resources;
2735 struct pci_quirk *q;
2742 /* ATA devices needs special map treatment */
2743 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2744 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2745 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2746 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2747 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2748 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2750 for (i = 0; i < cfg->nummaps;)
2751 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2752 rl, force, prefetchmask & (1 << i));
2755 * Add additional, quirked resources.
2757 for (q = &pci_quirks[0]; q->devid; q++) {
2758 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2759 && q->type == PCI_QUIRK_MAP_REG)
2760 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2764 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2766 * Try to re-route interrupts. Sometimes the BIOS or
2767 * firmware may leave bogus values in these registers.
2768 * If the re-route fails, then just stick with what we
2771 pci_assign_interrupt(bus, dev, 1);
2776 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2778 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2779 device_t pcib = device_get_parent(dev);
2780 struct pci_devinfo *dinfo;
2782 int s, f, pcifunchigh;
2785 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2786 ("dinfo_size too small"));
2787 maxslots = PCIB_MAXSLOTS(pcib);
2788 for (s = 0; s <= maxslots; s++) {
2792 hdrtype = REG(PCIR_HDRTYPE, 1);
2793 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2795 if (hdrtype & PCIM_MFDEV)
2796 pcifunchigh = PCI_FUNCMAX;
2797 for (f = 0; f <= pcifunchigh; f++) {
2798 dinfo = pci_read_device(pcib, domain, busno, s, f,
2800 if (dinfo != NULL) {
2801 pci_add_child(dev, dinfo);
2809 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2813 pcib = device_get_parent(bus);
2814 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2815 device_set_ivars(dinfo->cfg.dev, dinfo);
2816 resource_list_init(&dinfo->resources);
2817 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2818 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2819 pci_print_verbose(dinfo);
2820 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2824 pci_probe(device_t dev)
2826 device_set_desc(dev, "PCI bus");
2828 /* Allow other subclasses to override this driver. */
2833 pci_attach(device_t dev)
2838 * Since there can be multiple independantly numbered PCI
2839 * busses on systems with multiple PCI domains, we can't use
2840 * the unit number to decide which bus we are probing. We ask
2841 * the parent pcib what our domain and bus numbers are.
2843 domain = pcib_get_domain(dev);
2844 busno = pcib_get_bus(dev);
2846 device_printf(dev, "domain=%d, physical bus=%d\n",
2849 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2851 return (bus_generic_attach(dev));
2855 pci_suspend(device_t dev)
2857 int dstate, error, i, numdevs;
2858 device_t acpi_dev, child, *devlist;
2859 struct pci_devinfo *dinfo;
2862 * Save the PCI configuration space for each child and set the
2863 * device in the appropriate power state for this sleep state.
2866 if (pci_do_power_resume)
2867 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2868 device_get_children(dev, &devlist, &numdevs);
2869 for (i = 0; i < numdevs; i++) {
2871 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2872 pci_cfg_save(child, dinfo, 0);
2875 /* Suspend devices before potentially powering them down. */
2876 error = bus_generic_suspend(dev);
2878 kfree(devlist, M_TEMP);
2883 * Always set the device to D3. If ACPI suggests a different
2884 * power state, use it instead. If ACPI is not present, the
2885 * firmware is responsible for managing device power. Skip
2886 * children who aren't attached since they are powered down
2887 * separately. Only manage type 0 devices for now.
2889 for (i = 0; acpi_dev && i < numdevs; i++) {
2891 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2892 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2893 dstate = PCI_POWERSTATE_D3;
2894 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2895 pci_set_powerstate(child, dstate);
2898 kfree(devlist, M_TEMP);
2903 pci_resume(device_t dev)
2906 device_t acpi_dev, child, *devlist;
2907 struct pci_devinfo *dinfo;
2910 * Set each child to D0 and restore its PCI configuration space.
2913 if (pci_do_power_resume)
2914 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2915 device_get_children(dev, &devlist, &numdevs);
2916 for (i = 0; i < numdevs; i++) {
2918 * Notify ACPI we're going to D0 but ignore the result. If
2919 * ACPI is not present, the firmware is responsible for
2920 * managing device power. Only manage type 0 devices for now.
2923 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2924 if (acpi_dev && device_is_attached(child) &&
2925 dinfo->cfg.hdrtype == 0) {
2926 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2927 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2930 /* Now the device is powered up, restore its config space. */
2931 pci_cfg_restore(child, dinfo);
2933 kfree(devlist, M_TEMP);
2934 return (bus_generic_resume(dev));
2938 pci_load_vendor_data(void)
2940 caddr_t vendordata, info;
2942 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2943 info = preload_search_info(vendordata, MODINFO_ADDR);
2944 pci_vendordata = *(char **)info;
2945 info = preload_search_info(vendordata, MODINFO_SIZE);
2946 pci_vendordata_size = *(size_t *)info;
2947 /* terminate the database */
2948 pci_vendordata[pci_vendordata_size] = '\n';
2953 pci_driver_added(device_t dev, driver_t *driver)
2958 struct pci_devinfo *dinfo;
2962 device_printf(dev, "driver added\n");
2963 DEVICE_IDENTIFY(driver, dev);
2964 device_get_children(dev, &devlist, &numdevs);
2965 for (i = 0; i < numdevs; i++) {
2967 if (device_get_state(child) != DS_NOTPRESENT)
2969 dinfo = device_get_ivars(child);
2970 pci_print_verbose(dinfo);
2972 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2973 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2975 pci_cfg_restore(child, dinfo);
2976 if (device_probe_and_attach(child) != 0)
2977 pci_cfg_save(child, dinfo, 1);
2979 kfree(devlist, M_TEMP);
2983 pci_child_detached(device_t parent __unused, device_t child)
2985 /* Turn child's power off */
2986 pci_cfg_save(child, device_get_ivars(child), 1);
2990 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2991 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
2996 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
2997 arg, &cookie, serializer);
3001 /* If this is not a direct child, just bail out. */
3002 if (device_get_parent(child) != dev) {
3007 rid = rman_get_rid(irq);
3009 /* Make sure that INTx is enabled */
3010 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3012 struct pci_devinfo *dinfo = device_get_ivars(child);
3017 * Check to see if the interrupt is MSI or MSI-X.
3018 * Ask our parent to map the MSI and give
3019 * us the address and data register values.
3020 * If we fail for some reason, teardown the
3021 * interrupt handler.
3023 if (dinfo->cfg.msi.msi_alloc > 0) {
3024 struct pcicfg_msi *msi = &dinfo->cfg.msi;
3026 if (msi->msi_addr == 0) {
3027 KASSERT(msi->msi_handlers == 0,
3028 ("MSI has handlers, but vectors not mapped"));
3029 error = PCIB_MAP_MSI(device_get_parent(dev),
3030 child, rman_get_start(irq), &addr, &data,
3031 rman_get_cpuid(irq));
3034 msi->msi_addr = addr;
3035 msi->msi_data = data;
3036 pci_enable_msi(child, addr, data);
3038 msi->msi_handlers++;
3040 struct msix_vector *mv;
3043 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3044 ("No MSI-X or MSI rid %d allocated\n", rid));
3046 mv = pci_find_msix_vector(child, rid);
3048 ("MSI-X rid %d is not allocated\n", rid));
3049 KASSERT(mv->mv_address == 0,
3050 ("MSI-X rid %d has been setup\n", rid));
3052 error = PCIB_MAP_MSI(device_get_parent(dev),
3053 child, rman_get_start(irq), &addr, &data,
3054 rman_get_cpuid(irq));
3057 mv->mv_address = addr;
3060 vector = PCI_MSIX_RID2VEC(rid);
3061 pci_setup_msix_vector(child, vector,
3062 mv->mv_address, mv->mv_data);
3063 pci_unmask_msix_vector(child, vector);
3066 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3067 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3070 (void)bus_generic_teardown_intr(dev, child, irq,
3080 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3085 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3088 /* If this isn't a direct child, just bail out */
3089 if (device_get_parent(child) != dev)
3090 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3092 rid = rman_get_rid(irq);
3095 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3097 struct pci_devinfo *dinfo = device_get_ivars(child);
3100 * Check to see if the interrupt is MSI or MSI-X. If so,
3101 * decrement the appropriate handlers count and mask the
3102 * MSI-X message, or disable MSI messages if the count
3105 if (dinfo->cfg.msi.msi_alloc > 0) {
3106 struct pcicfg_msi *msi = &dinfo->cfg.msi;
3108 KASSERT(rid <= msi->msi_alloc,
3109 ("MSI-X index too high\n"));
3110 KASSERT(msi->msi_handlers > 0,
3111 ("MSI rid %d is not setup\n", rid));
3113 msi->msi_handlers--;
3114 if (msi->msi_handlers == 0)
3115 pci_disable_msi(child);
3117 struct msix_vector *mv;
3119 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3120 ("No MSI or MSI-X rid %d allocated", rid));
3122 mv = pci_find_msix_vector(child, rid);
3124 ("MSI-X rid %d is not allocated\n", rid));
3125 KASSERT(mv->mv_address != 0,
3126 ("MSI-X rid %d has not been setup\n", rid));
3128 pci_mask_msix_vector(child, PCI_MSIX_RID2VEC(rid));
3133 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3136 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3141 pci_print_child(device_t dev, device_t child)
3143 struct pci_devinfo *dinfo;
3144 struct resource_list *rl;
3147 dinfo = device_get_ivars(child);
3148 rl = &dinfo->resources;
3150 retval += bus_print_child_header(dev, child);
3152 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3153 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3154 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3155 if (device_get_flags(dev))
3156 retval += kprintf(" flags %#x", device_get_flags(dev));
3158 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3159 pci_get_function(child));
3161 retval += bus_print_child_footer(dev, child);
3171 } pci_nomatch_tab[] = {
3172 {PCIC_OLD, -1, "old"},
3173 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3174 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3175 {PCIC_STORAGE, -1, "mass storage"},
3176 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3177 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3178 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3179 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3180 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3181 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3182 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3183 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3184 {PCIC_NETWORK, -1, "network"},
3185 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3186 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3187 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3188 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3189 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3190 {PCIC_DISPLAY, -1, "display"},
3191 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3192 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3193 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3194 {PCIC_MULTIMEDIA, -1, "multimedia"},
3195 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3196 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3197 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3198 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3199 {PCIC_MEMORY, -1, "memory"},
3200 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3201 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3202 {PCIC_BRIDGE, -1, "bridge"},
3203 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3204 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3205 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3206 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3207 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3208 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3209 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3210 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3211 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3212 {PCIC_SIMPLECOMM, -1, "simple comms"},
3213 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3214 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3215 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3216 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3217 {PCIC_BASEPERIPH, -1, "base peripheral"},
3218 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3219 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3220 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3221 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3222 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3223 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3224 {PCIC_INPUTDEV, -1, "input device"},
3225 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3226 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3227 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3228 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3229 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3230 {PCIC_DOCKING, -1, "docking station"},
3231 {PCIC_PROCESSOR, -1, "processor"},
3232 {PCIC_SERIALBUS, -1, "serial bus"},
3233 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3234 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3235 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3236 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3237 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3238 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3239 {PCIC_WIRELESS, -1, "wireless controller"},
3240 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3241 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3242 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3243 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3244 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3245 {PCIC_SATCOM, -1, "satellite communication"},
3246 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3247 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3248 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3249 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3250 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3251 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3252 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3253 {PCIC_DASP, -1, "dasp"},
3254 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3259 pci_probe_nomatch(device_t dev, device_t child)
3262 char *cp, *scp, *device;
3265 * Look for a listing for this device in a loaded device database.
3267 if ((device = pci_describe_device(child)) != NULL) {
3268 device_printf(dev, "<%s>", device);
3269 kfree(device, M_DEVBUF);
3272 * Scan the class/subclass descriptions for a general
3277 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3278 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3279 if (pci_nomatch_tab[i].subclass == -1) {
3280 cp = pci_nomatch_tab[i].desc;
3281 } else if (pci_nomatch_tab[i].subclass ==
3282 pci_get_subclass(child)) {
3283 scp = pci_nomatch_tab[i].desc;
3287 device_printf(dev, "<%s%s%s>",
3289 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3292 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3293 pci_get_vendor(child), pci_get_device(child),
3294 pci_get_slot(child), pci_get_function(child));
3295 if (pci_get_intpin(child) > 0) {
3298 irq = pci_get_irq(child);
3299 if (PCI_INTERRUPT_VALID(irq))
3300 kprintf(" irq %d", irq);
3304 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3308 * Parse the PCI device database, if loaded, and return a pointer to a
3309 * description of the device.
3311 * The database is flat text formatted as follows:
3313 * Any line not in a valid format is ignored.
3314 * Lines are terminated with newline '\n' characters.
3316 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3319 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3320 * - devices cannot be listed without a corresponding VENDOR line.
3321 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3322 * another TAB, then the device name.
3326 * Assuming (ptr) points to the beginning of a line in the database,
3327 * return the vendor or device and description of the next entry.
3328 * The value of (vendor) or (device) inappropriate for the entry type
3329 * is set to -1. Returns nonzero at the end of the database.
3331 * Note that this is slightly unrobust in the face of corrupt data;
3332 * we attempt to safeguard against this by spamming the end of the
3333 * database with a newline when we initialise.
3336 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3345 left = pci_vendordata_size - (cp - pci_vendordata);
3353 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3357 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3360 /* skip to next line */
3361 while (*cp != '\n' && left > 0) {
3370 /* skip to next line */
3371 while (*cp != '\n' && left > 0) {
3375 if (*cp == '\n' && left > 0)
3382 pci_describe_device(device_t dev)
3385 char *desc, *vp, *dp, *line;
3387 desc = vp = dp = NULL;
3390 * If we have no vendor data, we can't do anything.
3392 if (pci_vendordata == NULL)
3396 * Scan the vendor data looking for this device
3398 line = pci_vendordata;
3399 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3402 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3404 if (vendor == pci_get_vendor(dev))
3407 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3410 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3418 if (device == pci_get_device(dev))
3422 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3423 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3425 ksprintf(desc, "%s, %s", vp, dp);
3428 kfree(vp, M_DEVBUF);
3430 kfree(dp, M_DEVBUF);
3435 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3437 struct pci_devinfo *dinfo;
3440 dinfo = device_get_ivars(child);
3444 case PCI_IVAR_ETHADDR:
3446 * The generic accessor doesn't deal with failure, so
3447 * we set the return value, then return an error.
3449 *((uint8_t **) result) = NULL;
3451 case PCI_IVAR_SUBVENDOR:
3452 *result = cfg->subvendor;
3454 case PCI_IVAR_SUBDEVICE:
3455 *result = cfg->subdevice;
3457 case PCI_IVAR_VENDOR:
3458 *result = cfg->vendor;
3460 case PCI_IVAR_DEVICE:
3461 *result = cfg->device;
3463 case PCI_IVAR_DEVID:
3464 *result = (cfg->device << 16) | cfg->vendor;
3466 case PCI_IVAR_CLASS:
3467 *result = cfg->baseclass;
3469 case PCI_IVAR_SUBCLASS:
3470 *result = cfg->subclass;
3472 case PCI_IVAR_PROGIF:
3473 *result = cfg->progif;
3475 case PCI_IVAR_REVID:
3476 *result = cfg->revid;
3478 case PCI_IVAR_INTPIN:
3479 *result = cfg->intpin;
3482 *result = cfg->intline;
3484 case PCI_IVAR_DOMAIN:
3485 *result = cfg->domain;
3491 *result = cfg->slot;
3493 case PCI_IVAR_FUNCTION:
3494 *result = cfg->func;
3496 case PCI_IVAR_CMDREG:
3497 *result = cfg->cmdreg;
3499 case PCI_IVAR_CACHELNSZ:
3500 *result = cfg->cachelnsz;
3502 case PCI_IVAR_MINGNT:
3503 *result = cfg->mingnt;
3505 case PCI_IVAR_MAXLAT:
3506 *result = cfg->maxlat;
3508 case PCI_IVAR_LATTIMER:
3509 *result = cfg->lattimer;
3511 case PCI_IVAR_PCIXCAP_PTR:
3512 *result = cfg->pcix.pcix_ptr;
3514 case PCI_IVAR_PCIECAP_PTR:
3515 *result = cfg->expr.expr_ptr;
3517 case PCI_IVAR_VPDCAP_PTR:
3518 *result = cfg->vpd.vpd_reg;
3527 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3529 struct pci_devinfo *dinfo;
3531 dinfo = device_get_ivars(child);
3534 case PCI_IVAR_INTPIN:
3535 dinfo->cfg.intpin = value;
3537 case PCI_IVAR_ETHADDR:
3538 case PCI_IVAR_SUBVENDOR:
3539 case PCI_IVAR_SUBDEVICE:
3540 case PCI_IVAR_VENDOR:
3541 case PCI_IVAR_DEVICE:
3542 case PCI_IVAR_DEVID:
3543 case PCI_IVAR_CLASS:
3544 case PCI_IVAR_SUBCLASS:
3545 case PCI_IVAR_PROGIF:
3546 case PCI_IVAR_REVID:
3548 case PCI_IVAR_DOMAIN:
3551 case PCI_IVAR_FUNCTION:
3552 return (EINVAL); /* disallow for now */
3559 #include "opt_ddb.h"
3561 #include <ddb/ddb.h>
3562 #include <sys/cons.h>
3565 * List resources based on pci map registers, used for within ddb
3568 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3570 struct pci_devinfo *dinfo;
3571 struct devlist *devlist_head;
3574 int i, error, none_count;
3577 /* get the head of the device queue */
3578 devlist_head = &pci_devq;
3581 * Go through the list of devices and print out devices
3583 for (error = 0, i = 0,
3584 dinfo = STAILQ_FIRST(devlist_head);
3585 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3586 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3588 /* Populate pd_name and pd_unit */
3591 name = device_get_name(dinfo->cfg.dev);
3594 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3595 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3596 (name && *name) ? name : "none",
3597 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3599 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3600 p->pc_sel.pc_func, (p->pc_class << 16) |
3601 (p->pc_subclass << 8) | p->pc_progif,
3602 (p->pc_subdevice << 16) | p->pc_subvendor,
3603 (p->pc_device << 16) | p->pc_vendor,
3604 p->pc_revid, p->pc_hdr);
3610 static struct resource *
3611 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3612 u_long start, u_long end, u_long count, u_int flags)
3614 struct pci_devinfo *dinfo = device_get_ivars(child);
3615 struct resource_list *rl = &dinfo->resources;
3616 struct resource_list_entry *rle;
3617 struct resource *res;
3618 pci_addr_t map, testval;
3622 * Weed out the bogons, and figure out how large the BAR/map
3623 * is. Bars that read back 0 here are bogus and unimplemented.
3624 * Note: atapci in legacy mode are special and handled elsewhere
3625 * in the code. If you have a atapci device in legacy mode and
3626 * it fails here, that other code is broken.
3629 map = pci_read_config(child, *rid, 4);
3630 pci_write_config(child, *rid, 0xffffffff, 4);
3631 testval = pci_read_config(child, *rid, 4);
3632 if (pci_maprange(testval) == 64)
3633 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3634 if (pci_mapbase(testval) == 0)
3638 * Restore the original value of the BAR. We may have reprogrammed
3639 * the BAR of the low-level console device and when booting verbose,
3640 * we need the console device addressable.
3642 pci_write_config(child, *rid, map, 4);
3644 if (PCI_BAR_MEM(testval)) {
3645 if (type != SYS_RES_MEMORY) {
3648 "child %s requested type %d for rid %#x,"
3649 " but the BAR says it is an memio\n",
3650 device_get_nameunit(child), type, *rid);
3654 if (type != SYS_RES_IOPORT) {
3657 "child %s requested type %d for rid %#x,"
3658 " but the BAR says it is an ioport\n",
3659 device_get_nameunit(child), type, *rid);
3664 * For real BARs, we need to override the size that
3665 * the driver requests, because that's what the BAR
3666 * actually uses and we would otherwise have a
3667 * situation where we might allocate the excess to
3668 * another driver, which won't work.
3670 mapsize = pci_mapsize(testval);
3671 count = 1UL << mapsize;
3672 if (RF_ALIGNMENT(flags) < mapsize)
3673 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3674 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3675 flags |= RF_PREFETCHABLE;
3678 * Allocate enough resource, and then write back the
3679 * appropriate bar for that resource.
3681 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3682 start, end, count, flags, -1);
3684 device_printf(child,
3685 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3686 count, *rid, type, start, end);
3689 resource_list_add(rl, type, *rid, start, end, count, -1);
3690 rle = resource_list_find(rl, type, *rid);
3692 panic("pci_alloc_map: unexpectedly can't find resource.");
3694 rle->start = rman_get_start(res);
3695 rle->end = rman_get_end(res);
3698 device_printf(child,
3699 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3700 count, *rid, type, rman_get_start(res));
3701 map = rman_get_start(res);
3703 pci_write_config(child, *rid, map, 4);
3704 if (pci_maprange(testval) == 64)
3705 pci_write_config(child, *rid + 4, map >> 32, 4);
3711 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3712 u_long start, u_long end, u_long count, u_int flags, int cpuid)
3714 struct pci_devinfo *dinfo = device_get_ivars(child);
3715 struct resource_list *rl = &dinfo->resources;
3716 struct resource_list_entry *rle;
3717 pcicfgregs *cfg = &dinfo->cfg;
3720 * Perform lazy resource allocation
3722 if (device_get_parent(child) == dev) {
3726 * Can't alloc legacy interrupt once MSI messages
3727 * have been allocated.
3729 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3730 cfg->msix.msix_alloc > 0))
3733 * If the child device doesn't have an
3734 * interrupt routed and is deserving of an
3735 * interrupt, try to assign it one.
3737 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3739 pci_assign_interrupt(dev, child, 0);
3741 case SYS_RES_IOPORT:
3742 case SYS_RES_MEMORY:
3743 if (*rid < PCIR_BAR(cfg->nummaps)) {
3745 * Enable the I/O mode. We should
3746 * also be assigning resources too
3747 * when none are present. The
3748 * resource_list_alloc kind of sorta does
3751 if (PCI_ENABLE_IO(dev, child, type))
3754 rle = resource_list_find(rl, type, *rid);
3756 return (pci_alloc_map(dev, child, type, rid,
3757 start, end, count, flags));
3761 * If we've already allocated the resource, then
3762 * return it now. But first we may need to activate
3763 * it, since we don't allocate the resource as active
3764 * above. Normally this would be done down in the
3765 * nexus, but since we short-circuit that path we have
3766 * to do its job here. Not sure if we should kfree the
3767 * resource if it fails to activate.
3769 rle = resource_list_find(rl, type, *rid);
3770 if (rle != NULL && rle->res != NULL) {
3772 device_printf(child,
3773 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3774 rman_get_size(rle->res), *rid, type,
3775 rman_get_start(rle->res));
3776 if ((flags & RF_ACTIVE) &&
3777 bus_generic_activate_resource(dev, child, type,
3778 *rid, rle->res) != 0)
3783 return (resource_list_alloc(rl, dev, child, type, rid,
3784 start, end, count, flags, cpuid));
3788 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3790 struct pci_devinfo *dinfo;
3791 struct resource_list *rl;
3792 struct resource_list_entry *rle;
3794 if (device_get_parent(child) != dev)
3797 dinfo = device_get_ivars(child);
3798 rl = &dinfo->resources;
3799 rle = resource_list_find(rl, type, rid);
3802 if (rman_get_device(rle->res) != dev ||
3803 rman_get_flags(rle->res) & RF_ACTIVE) {
3804 device_printf(dev, "delete_resource: "
3805 "Resource still owned by child, oops. "
3806 "(type=%d, rid=%d, addr=%lx)\n",
3807 rle->type, rle->rid,
3808 rman_get_start(rle->res));
3811 bus_release_resource(dev, type, rid, rle->res);
3813 resource_list_delete(rl, type, rid);
3816 * Why do we turn off the PCI configuration BAR when we delete a
3819 pci_write_config(child, rid, 0, 4);
3820 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3823 struct resource_list *
3824 pci_get_resource_list (device_t dev, device_t child)
3826 struct pci_devinfo *dinfo = device_get_ivars(child);
3831 return (&dinfo->resources);
3835 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3837 struct pci_devinfo *dinfo = device_get_ivars(child);
3838 pcicfgregs *cfg = &dinfo->cfg;
3840 return (PCIB_READ_CONFIG(device_get_parent(dev),
3841 cfg->bus, cfg->slot, cfg->func, reg, width));
3845 pci_write_config_method(device_t dev, device_t child, int reg,
3846 uint32_t val, int width)
3848 struct pci_devinfo *dinfo = device_get_ivars(child);
3849 pcicfgregs *cfg = &dinfo->cfg;
3851 PCIB_WRITE_CONFIG(device_get_parent(dev),
3852 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3856 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3860 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3861 pci_get_function(child));
3866 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3869 struct pci_devinfo *dinfo;
3872 dinfo = device_get_ivars(child);
3874 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3875 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3876 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3882 pci_assign_interrupt_method(device_t dev, device_t child)
3884 struct pci_devinfo *dinfo = device_get_ivars(child);
3885 pcicfgregs *cfg = &dinfo->cfg;
3887 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3892 pci_modevent(module_t mod, int what, void *arg)
3894 static struct cdev *pci_cdev;
3898 STAILQ_INIT(&pci_devq);
3900 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3902 pci_load_vendor_data();
3906 destroy_dev(pci_cdev);
3914 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3919 * Only do header type 0 devices. Type 1 devices are bridges,
3920 * which we know need special treatment. Type 2 devices are
3921 * cardbus bridges which also require special treatment.
3922 * Other types are unknown, and we err on the side of safety
3925 if (dinfo->cfg.hdrtype != 0)
3929 * Restore the device to full power mode. We must do this
3930 * before we restore the registers because moving from D3 to
3931 * D0 will cause the chip's BARs and some other registers to
3932 * be reset to some unknown power on reset values. Cut down
3933 * the noise on boot by doing nothing if we are already in
3936 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3937 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3939 for (i = 0; i < dinfo->cfg.nummaps; i++)
3940 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3941 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3942 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3943 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3944 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3945 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3946 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3947 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3948 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3949 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3950 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3952 /* Restore MSI and MSI-X configurations if they are present. */
3953 if (dinfo->cfg.msi.msi_location != 0)
3954 pci_resume_msi(dev);
3955 if (dinfo->cfg.msix.msix_location != 0)
3956 pci_resume_msix(dev);
3960 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3967 * Only do header type 0 devices. Type 1 devices are bridges, which
3968 * we know need special treatment. Type 2 devices are cardbus bridges
3969 * which also require special treatment. Other types are unknown, and
3970 * we err on the side of safety by ignoring them. Powering down
3971 * bridges should not be undertaken lightly.
3973 if (dinfo->cfg.hdrtype != 0)
3975 for (i = 0; i < dinfo->cfg.nummaps; i++)
3976 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3977 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3980 * Some drivers apparently write to these registers w/o updating our
3981 * cached copy. No harm happens if we update the copy, so do so here
3982 * so we can restore them. The COMMAND register is modified by the
3983 * bus w/o updating the cache. This should represent the normally
3984 * writable portion of the 'defined' part of type 0 headers. In
3985 * theory we also need to save/restore the PCI capability structures
3986 * we know about, but apart from power we don't know any that are
3989 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3990 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3991 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3992 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3993 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3994 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3995 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3996 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3997 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3998 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3999 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4000 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4001 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4002 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4003 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4006 * don't set the state for display devices, base peripherals and
4007 * memory devices since bad things happen when they are powered down.
4008 * We should (a) have drivers that can easily detach and (b) use
4009 * generic drivers for these devices so that some device actually
4010 * attaches. We need to make sure that when we implement (a) we don't
4011 * power the device down on a reattach.
4013 cls = pci_get_class(dev);
4016 switch (pci_do_power_nodriver)
4018 case 0: /* NO powerdown at all */
4020 case 1: /* Conservative about what to power down */
4021 if (cls == PCIC_STORAGE)
4024 case 2: /* Agressive about what to power down */
4025 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4026 cls == PCIC_BASEPERIPH)
4029 case 3: /* Power down everything */
4033 * PCI spec says we can only go into D3 state from D0 state.
4034 * Transition from D[12] into D0 before going to D3 state.
4036 ps = pci_get_powerstate(dev);
4037 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4038 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4039 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4040 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4043 #ifdef COMPAT_OLDPCI
4046 * Locate the parent of a PCI device by scanning the PCI devlist
4047 * and return the entry for the parent.
4048 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4049 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4052 pci_devlist_get_parent(pcicfgregs *cfg)
4054 struct devlist *devlist_head;
4055 struct pci_devinfo *dinfo;
4056 pcicfgregs *bridge_cfg;
4059 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4061 /* If the device is on PCI bus 0, look for the host */
4062 if (cfg->bus == 0) {
4063 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4064 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4065 bridge_cfg = &dinfo->cfg;
4066 if (bridge_cfg->baseclass == PCIC_BRIDGE
4067 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4068 && bridge_cfg->bus == cfg->bus) {
4074 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4076 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4077 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4078 bridge_cfg = &dinfo->cfg;
4079 if (bridge_cfg->baseclass == PCIC_BRIDGE
4080 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4081 && bridge_cfg->secondarybus == cfg->bus) {
4090 #endif /* COMPAT_OLDPCI */
4093 pci_alloc_1intr(device_t dev, int msi_enable, int *rid0, u_int *flags0)
4100 type = PCI_INTR_TYPE_LEGACY;
4101 flags = RF_SHAREABLE | RF_ACTIVE;
4103 ksnprintf(env, sizeof(env), "hw.%s.msi.enable",
4104 device_get_nameunit(dev));
4105 kgetenv_int(env, &msi_enable);
4110 ksnprintf(env, sizeof(env), "hw.%s.msi.cpu",
4111 device_get_nameunit(dev));
4112 kgetenv_int(env, &cpu);
4116 if (pci_alloc_msi(dev, &rid, 1, cpu) == 0) {
4117 flags &= ~RF_SHAREABLE;
4118 type = PCI_INTR_TYPE_MSI;