2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
46 #include <sys/machintr.h>
48 #include <machine/msi_machdep.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 extern struct dev_ops pcic_ops; /* XXX */
75 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
77 static uint32_t pci_mapbase(unsigned mapreg);
78 static const char *pci_maptype(unsigned mapreg);
79 static int pci_mapsize(unsigned testval);
80 static int pci_maprange(unsigned mapreg);
81 static void pci_fixancient(pcicfgregs *cfg);
83 static int pci_porten(device_t pcib, int b, int s, int f);
84 static int pci_memen(device_t pcib, int b, int s, int f);
85 static void pci_assign_interrupt(device_t bus, device_t dev,
87 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
88 int b, int s, int f, int reg,
89 struct resource_list *rl, int force, int prefetch);
90 static int pci_probe(device_t dev);
91 static int pci_attach(device_t dev);
92 static void pci_child_detached(device_t, device_t);
93 static void pci_load_vendor_data(void);
94 static int pci_describe_parse_line(char **ptr, int *vendor,
95 int *device, char **desc);
96 static char *pci_describe_device(device_t dev);
97 static int pci_modevent(module_t mod, int what, void *arg);
98 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
100 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
101 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t *data);
104 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
105 int reg, uint32_t data);
107 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
108 static void pci_disable_msi(device_t dev);
109 static void pci_enable_msi(device_t dev, uint64_t address,
111 static void pci_setup_msix_vector(device_t dev, u_int index,
112 uint64_t address, uint32_t data);
113 static void pci_mask_msix_vector(device_t dev, u_int index);
114 static void pci_unmask_msix_vector(device_t dev, u_int index);
115 static void pci_mask_msix_allvectors(device_t dev);
116 static struct msix_vector *pci_find_msix_vector(device_t dev, int rid);
117 static int pci_msi_blacklisted(void);
118 static void pci_resume_msi(device_t dev);
119 static void pci_resume_msix(device_t dev);
120 static int pcie_slotimpl(const pcicfgregs *);
121 static void pci_print_verbose_expr(const pcicfgregs *);
123 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
127 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
128 static void pci_read_cap_subvendor(device_t, int, int,
130 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
131 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
133 static device_method_t pci_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, pci_probe),
136 DEVMETHOD(device_attach, pci_attach),
137 DEVMETHOD(device_detach, bus_generic_detach),
138 DEVMETHOD(device_shutdown, bus_generic_shutdown),
139 DEVMETHOD(device_suspend, pci_suspend),
140 DEVMETHOD(device_resume, pci_resume),
143 DEVMETHOD(bus_print_child, pci_print_child),
144 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
145 DEVMETHOD(bus_read_ivar, pci_read_ivar),
146 DEVMETHOD(bus_write_ivar, pci_write_ivar),
147 DEVMETHOD(bus_driver_added, pci_driver_added),
148 DEVMETHOD(bus_child_detached, pci_child_detached),
149 DEVMETHOD(bus_setup_intr, pci_setup_intr),
150 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
152 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
153 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
154 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
155 DEVMETHOD(bus_delete_resource, pci_delete_resource),
156 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
157 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
158 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
159 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
160 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
161 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
164 DEVMETHOD(pci_read_config, pci_read_config_method),
165 DEVMETHOD(pci_write_config, pci_write_config_method),
166 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
167 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
168 DEVMETHOD(pci_enable_io, pci_enable_io_method),
169 DEVMETHOD(pci_disable_io, pci_disable_io_method),
170 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
171 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
172 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
173 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
174 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
175 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
176 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
177 DEVMETHOD(pci_alloc_msix_vector, pci_alloc_msix_vector_method),
178 DEVMETHOD(pci_release_msi, pci_release_msi_method),
179 DEVMETHOD(pci_msi_count, pci_msi_count_method),
180 DEVMETHOD(pci_msix_count, pci_msix_count_method),
185 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
187 static devclass_t pci_devclass;
188 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
189 MODULE_VERSION(pci, 1);
191 static char *pci_vendordata;
192 static size_t pci_vendordata_size;
195 static const struct pci_read_cap {
197 pci_read_cap_t read_cap;
198 } pci_read_caps[] = {
199 { PCIY_PMG, pci_read_cap_pmgt },
200 { PCIY_HT, pci_read_cap_ht },
201 { PCIY_MSI, pci_read_cap_msi },
202 { PCIY_MSIX, pci_read_cap_msix },
203 { PCIY_VPD, pci_read_cap_vpd },
204 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
205 { PCIY_PCIX, pci_read_cap_pcix },
206 { PCIY_EXPRESS, pci_read_cap_express },
207 { 0, NULL } /* required last entry */
211 uint32_t devid; /* Vendor/device of the card */
213 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
214 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
219 struct pci_quirk pci_quirks[] = {
220 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
221 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
223 /* As does the Serverworks OSB4 (the SMBus mapping register) */
224 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
227 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
228 * or the CMIC-SL (AKA ServerWorks GC_LE).
230 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
231 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 * MSI doesn't work on earlier Intel chipsets including
235 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
237 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
243 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
246 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
249 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
254 /* map register information */
255 #define PCI_MAPMEM 0x01 /* memory map */
256 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
257 #define PCI_MAPPORT 0x04 /* port map */
259 #define PCI_MSIX_RID2VEC(rid) ((rid) - 1) /* rid -> MSI-X vector # */
260 #define PCI_MSIX_VEC2RID(vec) ((vec) + 1) /* MSI-X vector # -> rid */
262 struct devlist pci_devq;
263 uint32_t pci_generation;
264 uint32_t pci_numdevs = 0;
265 static int pcie_chipset, pcix_chipset;
268 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
270 static int pci_enable_io_modes = 1;
271 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
272 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
273 &pci_enable_io_modes, 1,
274 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
275 enable these bits correctly. We'd like to do this all the time, but there\n\
276 are some peripherals that this causes problems with.");
278 static int pci_do_power_nodriver = 0;
279 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
280 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
281 &pci_do_power_nodriver, 0,
282 "Place a function into D3 state when no driver attaches to it. 0 means\n\
283 disable. 1 means conservatively place devices into D3 state. 2 means\n\
284 aggressively place devices into D3 state. 3 means put absolutely everything\n\
287 static int pci_do_power_resume = 1;
288 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
289 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
290 &pci_do_power_resume, 1,
291 "Transition from D3 -> D0 on resume.");
293 static int pci_do_msi = 1;
294 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
295 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
296 "Enable support for MSI interrupts");
298 static int pci_do_msix = 0;
300 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
301 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
302 "Enable support for MSI-X interrupts");
305 static int pci_honor_msi_blacklist = 1;
306 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
307 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
308 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
310 static int pci_msi_cpuid;
312 /* Find a device_t by bus/slot/function in domain 0 */
315 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
318 return (pci_find_dbsf(0, bus, slot, func));
321 /* Find a device_t by domain/bus/slot/function */
324 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
326 struct pci_devinfo *dinfo;
328 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
329 if ((dinfo->cfg.domain == domain) &&
330 (dinfo->cfg.bus == bus) &&
331 (dinfo->cfg.slot == slot) &&
332 (dinfo->cfg.func == func)) {
333 return (dinfo->cfg.dev);
340 /* Find a device_t by vendor/device ID */
343 pci_find_device(uint16_t vendor, uint16_t device)
345 struct pci_devinfo *dinfo;
347 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
348 if ((dinfo->cfg.vendor == vendor) &&
349 (dinfo->cfg.device == device)) {
350 return (dinfo->cfg.dev);
357 /* return base address of memory or port map */
360 pci_mapbase(uint32_t mapreg)
363 if (PCI_BAR_MEM(mapreg))
364 return (mapreg & PCIM_BAR_MEM_BASE);
366 return (mapreg & PCIM_BAR_IO_BASE);
369 /* return map type of memory or port map */
372 pci_maptype(unsigned mapreg)
375 if (PCI_BAR_IO(mapreg))
377 if (mapreg & PCIM_BAR_MEM_PREFETCH)
378 return ("Prefetchable Memory");
382 /* return log2 of map size decoded for memory or port map */
385 pci_mapsize(uint32_t testval)
389 testval = pci_mapbase(testval);
392 while ((testval & 1) == 0)
401 /* return log2 of address range supported by map register */
404 pci_maprange(unsigned mapreg)
408 if (PCI_BAR_IO(mapreg))
411 switch (mapreg & PCIM_BAR_MEM_TYPE) {
412 case PCIM_BAR_MEM_32:
415 case PCIM_BAR_MEM_1MB:
418 case PCIM_BAR_MEM_64:
425 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
428 pci_fixancient(pcicfgregs *cfg)
430 if (cfg->hdrtype != 0)
433 /* PCI to PCI bridges use header type 1 */
434 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
438 /* extract header type specific config data */
441 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
443 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
444 switch (cfg->hdrtype) {
446 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
447 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
448 cfg->nummaps = PCI_MAXMAPS_0;
451 cfg->nummaps = PCI_MAXMAPS_1;
453 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
457 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
458 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
459 cfg->nummaps = PCI_MAXMAPS_2;
461 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
468 /* read configuration header into pcicfgregs structure */
470 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
472 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
473 pcicfgregs *cfg = NULL;
474 struct pci_devinfo *devlist_entry;
475 struct devlist *devlist_head;
477 devlist_head = &pci_devq;
479 devlist_entry = NULL;
481 if (REG(PCIR_DEVVENDOR, 4) != -1) {
482 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
484 cfg = &devlist_entry->cfg;
490 cfg->vendor = REG(PCIR_VENDOR, 2);
491 cfg->device = REG(PCIR_DEVICE, 2);
492 cfg->cmdreg = REG(PCIR_COMMAND, 2);
493 cfg->statreg = REG(PCIR_STATUS, 2);
494 cfg->baseclass = REG(PCIR_CLASS, 1);
495 cfg->subclass = REG(PCIR_SUBCLASS, 1);
496 cfg->progif = REG(PCIR_PROGIF, 1);
497 cfg->revid = REG(PCIR_REVID, 1);
498 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
499 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
500 cfg->lattimer = REG(PCIR_LATTIMER, 1);
501 cfg->intpin = REG(PCIR_INTPIN, 1);
502 cfg->intline = REG(PCIR_INTLINE, 1);
504 cfg->mingnt = REG(PCIR_MINGNT, 1);
505 cfg->maxlat = REG(PCIR_MAXLAT, 1);
507 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
508 cfg->hdrtype &= ~PCIM_MFDEV;
511 pci_hdrtypedata(pcib, b, s, f, cfg);
513 pci_read_capabilities(pcib, cfg);
515 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
517 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
518 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
519 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
520 devlist_entry->conf.pc_sel.pc_func = cfg->func;
521 devlist_entry->conf.pc_hdr = cfg->hdrtype;
523 devlist_entry->conf.pc_subvendor = cfg->subvendor;
524 devlist_entry->conf.pc_subdevice = cfg->subdevice;
525 devlist_entry->conf.pc_vendor = cfg->vendor;
526 devlist_entry->conf.pc_device = cfg->device;
528 devlist_entry->conf.pc_class = cfg->baseclass;
529 devlist_entry->conf.pc_subclass = cfg->subclass;
530 devlist_entry->conf.pc_progif = cfg->progif;
531 devlist_entry->conf.pc_revid = cfg->revid;
536 return (devlist_entry);
541 pci_fixup_nextptr(int *nextptr0)
543 int nextptr = *nextptr0;
545 /* "Next pointer" is only one byte */
546 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
550 * PCI local bus spec 3.0:
552 * "... The bottom two bits of all pointers are reserved
553 * and must be implemented as 00b although software must
554 * mask them to allow for future uses of these bits ..."
557 kprintf("Illegal PCI extended capability "
558 "offset, fixup 0x%02x -> 0x%02x\n",
559 nextptr, nextptr & ~0x3);
565 if (nextptr < 0x40) {
567 kprintf("Illegal PCI extended capability "
568 "offset 0x%02x", nextptr);
576 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
579 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
581 struct pcicfg_pp *pp = &cfg->pp;
586 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
587 pp->pp_status = ptr + PCIR_POWER_STATUS;
588 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
590 if ((nextptr - ptr) > PCIR_POWER_DATA) {
593 * We should write to data_select and read back from
594 * data_scale to determine whether data register is
598 pp->pp_data = ptr + PCIR_POWER_DATA;
608 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
610 #if defined(__i386__) || defined(__x86_64__)
613 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
615 struct pcicfg_ht *ht = &cfg->ht;
619 /* Determine HT-specific capability type. */
620 val = REG(ptr + PCIR_HT_COMMAND, 2);
622 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
623 cfg->ht.ht_slave = ptr;
625 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
628 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
629 /* Sanity check the mapping window. */
630 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
632 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
633 if (addr != MSI_X86_ADDR_BASE) {
634 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
635 "has non-default MSI window 0x%llx\n",
636 cfg->domain, cfg->bus, cfg->slot, cfg->func,
640 addr = MSI_X86_ADDR_BASE;
644 ht->ht_msictrl = val;
645 ht->ht_msiaddr = addr;
649 #endif /* __i386__ || __x86_64__ */
653 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
656 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
658 struct pcicfg_msi *msi = &cfg->msi;
660 msi->msi_location = ptr;
661 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
662 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
668 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
671 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
673 struct pcicfg_msix *msix = &cfg->msix;
676 msix->msix_location = ptr;
677 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
678 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
680 val = REG(ptr + PCIR_MSIX_TABLE, 4);
681 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
682 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
684 val = REG(ptr + PCIR_MSIX_PBA, 4);
685 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
686 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
688 TAILQ_INIT(&msix->msix_vectors);
694 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
696 cfg->vpd.vpd_reg = ptr;
700 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
703 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
705 /* Should always be true. */
706 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
709 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
710 cfg->subvendor = val & 0xffff;
711 cfg->subdevice = val >> 16;
718 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
721 * Assume we have a PCI-X chipset if we have
722 * at least one PCI-PCI bridge with a PCI-X
723 * capability. Note that some systems with
724 * PCI-express or HT chipsets might match on
725 * this check as well.
727 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
730 cfg->pcix.pcix_ptr = ptr;
734 pcie_slotimpl(const pcicfgregs *cfg)
736 const struct pcicfg_expr *expr = &cfg->expr;
740 * Only version 1 can be parsed currently
742 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
746 * - Slot implemented bit is meaningful iff current port is
747 * root port or down stream port.
748 * - Testing for root port or down stream port is meanningful
749 * iff PCI configure has type 1 header.
752 if (cfg->hdrtype != 1)
755 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
756 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
759 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
766 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
769 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
771 struct pcicfg_expr *expr = &cfg->expr;
774 * Assume we have a PCI-express chipset if we have
775 * at least one PCI-express device.
779 expr->expr_ptr = ptr;
780 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
783 * Only version 1 can be parsed currently
785 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
789 * Read slot capabilities. Slot capabilities exists iff
790 * current port's slot is implemented
792 if (pcie_slotimpl(cfg))
793 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
799 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
801 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
802 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
807 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
808 /* No capabilities */
812 switch (cfg->hdrtype & PCIM_HDRTYPE) {
815 ptrptr = PCIR_CAP_PTR;
818 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
821 return; /* no capabilities support */
823 nextptr = REG(ptrptr, 1); /* sanity check? */
826 * Read capability entries.
828 while (pci_fixup_nextptr(&nextptr)) {
829 const struct pci_read_cap *rc;
832 /* Find the next entry */
833 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
835 /* Process this entry */
836 val = REG(ptr + PCICAP_ID, 1);
837 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
838 if (rc->cap == val) {
839 rc->read_cap(pcib, ptr, nextptr, cfg);
845 #if defined(__i386__) || defined(__x86_64__)
847 * Enable the MSI mapping window for all HyperTransport
848 * slaves. PCI-PCI bridges have their windows enabled via
851 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
852 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
854 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
855 cfg->domain, cfg->bus, cfg->slot, cfg->func);
856 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
857 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
862 /* REG and WREG use carry through to next functions */
866 * PCI Vital Product Data
869 #define PCI_VPD_TIMEOUT 1000000
872 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
874 int count = PCI_VPD_TIMEOUT;
876 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
878 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
880 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
883 DELAY(1); /* limit looping */
885 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
892 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
894 int count = PCI_VPD_TIMEOUT;
896 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
898 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
899 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
900 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
903 DELAY(1); /* limit looping */
910 #undef PCI_VPD_TIMEOUT
912 struct vpd_readstate {
922 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
927 if (vrs->bytesinval == 0) {
928 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
930 vrs->val = le32toh(reg);
932 byte = vrs->val & 0xff;
935 vrs->val = vrs->val >> 8;
936 byte = vrs->val & 0xff;
946 pcie_slot_implemented(device_t dev)
948 struct pci_devinfo *dinfo = device_get_ivars(dev);
950 return pcie_slotimpl(&dinfo->cfg);
954 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
959 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
960 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
961 panic("%s: invalid max read request size 0x%02x\n",
962 device_get_nameunit(dev), rqsize);
965 expr_ptr = pci_get_pciecap_ptr(dev);
967 panic("%s: not PCIe device\n", device_get_nameunit(dev));
969 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
970 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
972 device_printf(dev, "adjust device control 0x%04x", val);
974 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
976 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
979 kprintf(" -> 0x%04x\n", val);
984 pcie_get_max_readrq(device_t dev)
989 expr_ptr = pci_get_pciecap_ptr(dev);
991 panic("%s: not PCIe device\n", device_get_nameunit(dev));
993 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
994 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
998 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
1000 struct vpd_readstate vrs;
1005 int alloc, off; /* alloc/off for RO/W arrays */
1011 /* init vpd reader */
1019 name = remain = i = 0; /* shut up stupid gcc */
1020 alloc = off = 0; /* shut up stupid gcc */
1021 dflen = 0; /* shut up stupid gcc */
1023 while (state >= 0) {
1024 if (vpd_nextbyte(&vrs, &byte)) {
1029 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1030 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1031 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1034 case 0: /* item name */
1036 if (vpd_nextbyte(&vrs, &byte2)) {
1041 if (vpd_nextbyte(&vrs, &byte2)) {
1045 remain |= byte2 << 8;
1046 if (remain > (0x7f*4 - vrs.off)) {
1049 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1050 cfg->domain, cfg->bus, cfg->slot,
1055 remain = byte & 0x7;
1056 name = (byte >> 3) & 0xf;
1059 case 0x2: /* String */
1060 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1061 M_DEVBUF, M_WAITOK);
1068 case 0x10: /* VPD-R */
1071 cfg->vpd.vpd_ros = kmalloc(alloc *
1072 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1076 case 0x11: /* VPD-W */
1079 cfg->vpd.vpd_w = kmalloc(alloc *
1080 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1084 default: /* Invalid data, abort */
1090 case 1: /* Identifier String */
1091 cfg->vpd.vpd_ident[i++] = byte;
1094 cfg->vpd.vpd_ident[i] = '\0';
1099 case 2: /* VPD-R Keyword Header */
1101 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1102 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1103 M_DEVBUF, M_WAITOK | M_ZERO);
1105 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1106 if (vpd_nextbyte(&vrs, &byte2)) {
1110 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1111 if (vpd_nextbyte(&vrs, &byte2)) {
1117 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1120 * if this happens, we can't trust the rest
1124 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1125 cfg->domain, cfg->bus, cfg->slot,
1130 } else if (dflen == 0) {
1131 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1132 sizeof(*cfg->vpd.vpd_ros[off].value),
1133 M_DEVBUF, M_WAITOK);
1134 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1136 cfg->vpd.vpd_ros[off].value = kmalloc(
1138 sizeof(*cfg->vpd.vpd_ros[off].value),
1139 M_DEVBUF, M_WAITOK);
1142 /* keep in sync w/ state 3's transistions */
1143 if (dflen == 0 && remain == 0)
1145 else if (dflen == 0)
1151 case 3: /* VPD-R Keyword Value */
1152 cfg->vpd.vpd_ros[off].value[i++] = byte;
1153 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1154 "RV", 2) == 0 && cksumvalid == -1) {
1160 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1161 cfg->domain, cfg->bus,
1162 cfg->slot, cfg->func,
1171 /* keep in sync w/ state 2's transistions */
1173 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1174 if (dflen == 0 && remain == 0) {
1175 cfg->vpd.vpd_rocnt = off;
1176 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1177 off * sizeof(*cfg->vpd.vpd_ros),
1178 M_DEVBUF, M_WAITOK | M_ZERO);
1180 } else if (dflen == 0)
1190 case 5: /* VPD-W Keyword Header */
1192 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1193 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1194 M_DEVBUF, M_WAITOK | M_ZERO);
1196 cfg->vpd.vpd_w[off].keyword[0] = byte;
1197 if (vpd_nextbyte(&vrs, &byte2)) {
1201 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1202 if (vpd_nextbyte(&vrs, &byte2)) {
1206 cfg->vpd.vpd_w[off].len = dflen = byte2;
1207 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1208 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1209 sizeof(*cfg->vpd.vpd_w[off].value),
1210 M_DEVBUF, M_WAITOK);
1213 /* keep in sync w/ state 6's transistions */
1214 if (dflen == 0 && remain == 0)
1216 else if (dflen == 0)
1222 case 6: /* VPD-W Keyword Value */
1223 cfg->vpd.vpd_w[off].value[i++] = byte;
1226 /* keep in sync w/ state 5's transistions */
1228 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1229 if (dflen == 0 && remain == 0) {
1230 cfg->vpd.vpd_wcnt = off;
1231 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1232 off * sizeof(*cfg->vpd.vpd_w),
1233 M_DEVBUF, M_WAITOK | M_ZERO);
1235 } else if (dflen == 0)
1240 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1241 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1248 if (cksumvalid == 0 || state < -1) {
1249 /* read-only data bad, clean up */
1250 if (cfg->vpd.vpd_ros != NULL) {
1251 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1252 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1253 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1254 cfg->vpd.vpd_ros = NULL;
1258 /* I/O error, clean up */
1259 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1260 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1261 if (cfg->vpd.vpd_ident != NULL) {
1262 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1263 cfg->vpd.vpd_ident = NULL;
1265 if (cfg->vpd.vpd_w != NULL) {
1266 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1267 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1268 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1269 cfg->vpd.vpd_w = NULL;
1272 cfg->vpd.vpd_cached = 1;
1278 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1280 struct pci_devinfo *dinfo = device_get_ivars(child);
1281 pcicfgregs *cfg = &dinfo->cfg;
1283 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1284 pci_read_vpd(device_get_parent(dev), cfg);
1286 *identptr = cfg->vpd.vpd_ident;
1288 if (*identptr == NULL)
1295 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1298 struct pci_devinfo *dinfo = device_get_ivars(child);
1299 pcicfgregs *cfg = &dinfo->cfg;
1302 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1303 pci_read_vpd(device_get_parent(dev), cfg);
1305 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1306 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1307 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1308 *vptr = cfg->vpd.vpd_ros[i].value;
1311 if (i != cfg->vpd.vpd_rocnt)
1319 * Return the offset in configuration space of the requested extended
1320 * capability entry or 0 if the specified capability was not found.
1323 pci_find_extcap_method(device_t dev, device_t child, int capability,
1326 struct pci_devinfo *dinfo = device_get_ivars(child);
1327 pcicfgregs *cfg = &dinfo->cfg;
1332 * Check the CAP_LIST bit of the PCI status register first.
1334 status = pci_read_config(child, PCIR_STATUS, 2);
1335 if (!(status & PCIM_STATUS_CAPPRESENT))
1339 * Determine the start pointer of the capabilities list.
1341 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1347 ptr = PCIR_CAP_PTR_2;
1351 return (ENXIO); /* no extended capabilities support */
1353 ptr = pci_read_config(child, ptr, 1);
1356 * Traverse the capabilities list.
1359 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1364 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1371 * Support for MSI-X message interrupts.
1374 pci_setup_msix_vector(device_t dev, u_int index, uint64_t address,
1377 struct pci_devinfo *dinfo = device_get_ivars(dev);
1378 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1381 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1382 offset = msix->msix_table_offset + index * 16;
1383 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1384 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1385 bus_write_4(msix->msix_table_res, offset + 8, data);
1387 /* Enable MSI -> HT mapping. */
1388 pci_ht_map_msi(dev, address);
1392 pci_mask_msix_vector(device_t dev, u_int index)
1394 struct pci_devinfo *dinfo = device_get_ivars(dev);
1395 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1396 uint32_t offset, val;
1398 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1399 offset = msix->msix_table_offset + index * 16 + 12;
1400 val = bus_read_4(msix->msix_table_res, offset);
1401 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1402 val |= PCIM_MSIX_VCTRL_MASK;
1403 bus_write_4(msix->msix_table_res, offset, val);
1408 pci_unmask_msix_vector(device_t dev, u_int index)
1410 struct pci_devinfo *dinfo = device_get_ivars(dev);
1411 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1412 uint32_t offset, val;
1414 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1415 offset = msix->msix_table_offset + index * 16 + 12;
1416 val = bus_read_4(msix->msix_table_res, offset);
1417 if (val & PCIM_MSIX_VCTRL_MASK) {
1418 val &= ~PCIM_MSIX_VCTRL_MASK;
1419 bus_write_4(msix->msix_table_res, offset, val);
1424 pci_pending_msix_vector(device_t dev, u_int index)
1426 struct pci_devinfo *dinfo = device_get_ivars(dev);
1427 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1428 uint32_t offset, bit;
1430 KASSERT(msix->msix_table_res != NULL && msix->msix_pba_res != NULL,
1431 ("MSI-X is not setup yet\n"));
1433 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1434 offset = msix->msix_pba_offset + (index / 32) * 4;
1435 bit = 1 << index % 32;
1436 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1440 * Restore MSI-X registers and table during resume. If MSI-X is
1441 * enabled then walk the virtual table to restore the actual MSI-X
1445 pci_resume_msix(device_t dev)
1447 struct pci_devinfo *dinfo = device_get_ivars(dev);
1448 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1450 if (msix->msix_alloc > 0) {
1451 const struct msix_vector *mv;
1453 pci_mask_msix_allvectors(dev);
1455 TAILQ_FOREACH(mv, &msix->msix_vectors, mv_link) {
1458 if (mv->mv_address == 0)
1461 vector = PCI_MSIX_RID2VEC(mv->mv_rid);
1462 pci_setup_msix_vector(dev, vector,
1463 mv->mv_address, mv->mv_data);
1464 pci_unmask_msix_vector(dev, vector);
1467 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1468 msix->msix_ctrl, 2);
1472 * Attempt to allocate one MSI-X message at the specified vector on cpuid.
1474 * After this function returns, the MSI-X's rid will be saved in rid0.
1477 pci_alloc_msix_vector_method(device_t dev, device_t child, u_int vector,
1478 int *rid0, int cpuid)
1480 struct pci_devinfo *dinfo = device_get_ivars(child);
1481 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1482 struct msix_vector *mv;
1483 struct resource_list_entry *rle;
1484 int error, irq, rid;
1486 KASSERT(msix->msix_table_res != NULL &&
1487 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1488 KASSERT(cpuid >= 0 && cpuid < ncpus, ("invalid cpuid %d\n", cpuid));
1489 KASSERT(vector < msix->msix_msgnum,
1490 ("invalid MSI-X vector %u, total %d\n", vector, msix->msix_msgnum));
1493 device_printf(child,
1494 "attempting to allocate MSI-X #%u vector (%d supported)\n",
1495 vector, msix->msix_msgnum);
1498 /* Set rid according to vector number */
1499 rid = PCI_MSIX_VEC2RID(vector);
1501 /* Vector has already been allocated */
1502 mv = pci_find_msix_vector(child, rid);
1506 /* Allocate a message. */
1507 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq, cpuid);
1510 resource_list_add(&dinfo->resources, SYS_RES_IRQ, rid,
1511 irq, irq, 1, cpuid);
1514 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
1515 device_printf(child, "using IRQ %lu for MSI-X on cpu%d\n",
1519 /* Update counts of alloc'd messages. */
1522 mv = kmalloc(sizeof(*mv), M_DEVBUF, M_WAITOK | M_ZERO);
1524 TAILQ_INSERT_TAIL(&msix->msix_vectors, mv, mv_link);
1532 pci_release_msix(device_t dev, device_t child)
1534 struct pci_devinfo *dinfo = device_get_ivars(child);
1535 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1536 struct resource_list_entry *rle;
1539 /* Do we have any messages to release? */
1540 if (msix->msix_alloc == 0)
1543 /* Make sure none of the resources are allocated. */
1544 for (i = 0; i < msix->msix_table_len; i++) {
1545 if (msix->msix_table[i].mte_vector == 0)
1547 if (msix->msix_table[i].mte_handlers > 0)
1549 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1550 KASSERT(rle != NULL, ("missing resource"));
1551 if (rle->res != NULL)
1555 /* Update control register to disable MSI-X. */
1556 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1557 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1558 msix->msix_ctrl, 2);
1560 /* Free the resource list entries. */
1561 for (i = 0; i < msix->msix_table_len; i++) {
1562 if (msix->msix_table[i].mte_vector == 0)
1564 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1566 kfree(msix->msix_table, M_DEVBUF);
1567 msix->msix_table_len = 0;
1569 /* Release the IRQs. */
1570 for (i = 0; i < msix->msix_alloc; i++)
1571 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1572 msix->msix_vectors[i].mv_irq, -1 /* XXX */);
1573 kfree(msix->msix_vectors, M_DEVBUF);
1574 msix->msix_alloc = 0;
1580 * Return the max supported MSI-X messages this device supports.
1581 * Basically, assuming the MD code can alloc messages, this function
1582 * should return the maximum value that pci_alloc_msix() can return.
1583 * Thus, it is subject to the tunables, etc.
1586 pci_msix_count_method(device_t dev, device_t child)
1588 struct pci_devinfo *dinfo = device_get_ivars(child);
1589 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1591 if (pci_do_msix && msix->msix_location != 0)
1592 return (msix->msix_msgnum);
1597 pci_setup_msix(device_t dev)
1599 struct pci_devinfo *dinfo = device_get_ivars(dev);
1600 pcicfgregs *cfg = &dinfo->cfg;
1601 struct resource_list_entry *rle;
1602 struct resource *table_res, *pba_res;
1604 KASSERT(cfg->msix.msix_table_res == NULL &&
1605 cfg->msix.msix_pba_res == NULL, ("MSI-X has been setup yet\n"));
1607 /* If rid 0 is allocated, then fail. */
1608 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1609 if (rle != NULL && rle->res != NULL)
1612 /* Already have allocated MSIs? */
1613 if (cfg->msi.msi_alloc != 0)
1616 /* If MSI is blacklisted for this system, fail. */
1617 if (pci_msi_blacklisted())
1620 /* MSI-X capability present? */
1621 if (cfg->msix.msix_location == 0 || cfg->msix.msix_msgnum == 0 ||
1625 /* Make sure the appropriate BARs are mapped. */
1626 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1627 cfg->msix.msix_table_bar);
1628 if (rle == NULL || rle->res == NULL ||
1629 !(rman_get_flags(rle->res) & RF_ACTIVE))
1631 table_res = rle->res;
1632 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1633 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1634 cfg->msix.msix_pba_bar);
1635 if (rle == NULL || rle->res == NULL ||
1636 !(rman_get_flags(rle->res) & RF_ACTIVE))
1641 cfg->msix.msix_table_res = table_res;
1642 cfg->msix.msix_pba_res = pba_res;
1644 pci_mask_msix_allvectors(dev);
1650 pci_teardown_msix(device_t dev)
1652 struct pci_devinfo *dinfo = device_get_ivars(dev);
1653 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1655 KASSERT(msix->msix_table_res != NULL &&
1656 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1658 pci_mask_msix_allvectors(dev);
1660 msix->msix_table_res = NULL;
1661 msix->msix_pba_res = NULL;
1665 pci_enable_msix(device_t dev)
1667 struct pci_devinfo *dinfo = device_get_ivars(dev);
1668 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1670 KASSERT(msix->msix_table_res != NULL &&
1671 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1673 /* Update control register to enable MSI-X. */
1674 msix->msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1675 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1676 msix->msix_ctrl, 2);
1680 pci_disable_msix(device_t dev)
1682 struct pci_devinfo *dinfo = device_get_ivars(dev);
1683 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1685 KASSERT(msix->msix_table_res != NULL &&
1686 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1688 /* Disable MSI -> HT mapping. */
1689 pci_ht_map_msi(dev, 0);
1691 /* Update control register to disable MSI-X. */
1692 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1693 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1694 msix->msix_ctrl, 2);
1698 pci_mask_msix_allvectors(device_t dev)
1700 struct pci_devinfo *dinfo = device_get_ivars(dev);
1703 for (i = 0; i < dinfo->cfg.msix.msix_msgnum; ++i)
1704 pci_mask_msix_vector(dev, i);
1707 static struct msix_vector *
1708 pci_find_msix_vector(device_t dev, int rid)
1710 struct pci_devinfo *dinfo = device_get_ivars(dev);
1711 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1712 struct msix_vector *mv;
1714 TAILQ_FOREACH(mv, &msix->msix_vectors, mv_link) {
1715 if (mv->mv_rid == rid)
1722 * HyperTransport MSI mapping control
1725 pci_ht_map_msi(device_t dev, uint64_t addr)
1727 struct pci_devinfo *dinfo = device_get_ivars(dev);
1728 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1733 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1734 ht->ht_msiaddr >> 20 == addr >> 20) {
1735 /* Enable MSI -> HT mapping. */
1736 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1737 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1741 if (!addr && (ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
1742 /* Disable MSI -> HT mapping. */
1743 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1744 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1750 * Support for MSI message signalled interrupts.
1753 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1755 struct pci_devinfo *dinfo = device_get_ivars(dev);
1756 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1758 /* Write data and address values. */
1759 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1760 address & 0xffffffff, 4);
1761 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1762 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1764 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1767 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1770 /* Enable MSI in the control register. */
1771 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1772 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1775 /* Enable MSI -> HT mapping. */
1776 pci_ht_map_msi(dev, address);
1780 pci_disable_msi(device_t dev)
1782 struct pci_devinfo *dinfo = device_get_ivars(dev);
1783 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1785 /* Disable MSI -> HT mapping. */
1786 pci_ht_map_msi(dev, 0);
1788 /* Disable MSI in the control register. */
1789 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1790 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1795 * Restore MSI registers during resume. If MSI is enabled then
1796 * restore the data and address registers in addition to the control
1800 pci_resume_msi(device_t dev)
1802 struct pci_devinfo *dinfo = device_get_ivars(dev);
1803 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1807 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1808 address = msi->msi_addr;
1809 data = msi->msi_data;
1810 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1811 address & 0xffffffff, 4);
1812 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1813 pci_write_config(dev, msi->msi_location +
1814 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1815 pci_write_config(dev, msi->msi_location +
1816 PCIR_MSI_DATA_64BIT, data, 2);
1818 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1821 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1826 * Returns true if the specified device is blacklisted because MSI
1830 pci_msi_device_blacklisted(device_t dev)
1832 struct pci_quirk *q;
1834 if (!pci_honor_msi_blacklist)
1837 for (q = &pci_quirks[0]; q->devid; q++) {
1838 if (q->devid == pci_get_devid(dev) &&
1839 q->type == PCI_QUIRK_DISABLE_MSI)
1846 * Determine if MSI is blacklisted globally on this sytem. Currently,
1847 * we just check for blacklisted chipsets as represented by the
1848 * host-PCI bridge at device 0:0:0. In the future, it may become
1849 * necessary to check other system attributes, such as the kenv values
1850 * that give the motherboard manufacturer and model number.
1853 pci_msi_blacklisted(void)
1857 if (!pci_honor_msi_blacklist)
1860 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1861 if (!(pcie_chipset || pcix_chipset))
1864 dev = pci_find_bsf(0, 0, 0);
1866 return (pci_msi_device_blacklisted(dev));
1871 * Attempt to allocate count MSI messages on start_cpuid.
1873 * If start_cpuid < 0, then the MSI messages' target CPU will be
1874 * selected automaticly.
1876 * If the caller explicitly specified the MSI messages' target CPU,
1877 * i.e. start_cpuid >= 0, then we will try to allocate the count MSI
1878 * messages on the specified CPU, if the allocation fails due to MD
1879 * does not have enough vectors (EMSGSIZE), then we will try next
1880 * available CPU, until the allocation fails on all CPUs.
1882 * EMSGSIZE will be returned, if all available CPUs does not have
1883 * enough vectors for the requested amount of MSI messages. Caller
1884 * should either reduce the amount of MSI messages to be requested,
1885 * or simply giving up using MSI.
1887 * The available SYS_RES_IRQ resources' rids, which are >= 1, are
1888 * returned in 'rid' array, if the allocation succeeds.
1891 pci_alloc_msi_method(device_t dev, device_t child, int *rid, int count,
1894 struct pci_devinfo *dinfo = device_get_ivars(child);
1895 pcicfgregs *cfg = &dinfo->cfg;
1896 struct resource_list_entry *rle;
1897 int error, i, irqs[32], cpuid = 0;
1900 KASSERT(count != 0 && count <= 32 && powerof2(count),
1901 ("invalid MSI count %d\n", count));
1902 KASSERT(start_cpuid < ncpus, ("invalid cpuid %d\n", start_cpuid));
1904 /* If rid 0 is allocated, then fail. */
1905 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1906 if (rle != NULL && rle->res != NULL)
1909 /* Already have allocated messages? */
1910 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1913 /* If MSI is blacklisted for this system, fail. */
1914 if (pci_msi_blacklisted())
1917 /* MSI capability present? */
1918 if (cfg->msi.msi_location == 0 || cfg->msi.msi_msgnum == 0 ||
1922 KASSERT(count <= cfg->msi.msi_msgnum, ("large MSI count %d, max %d\n",
1923 count, cfg->msi.msi_msgnum));
1926 device_printf(child,
1927 "attempting to allocate %d MSI vectors (%d supported)\n",
1928 count, cfg->msi.msi_msgnum);
1931 if (start_cpuid < 0)
1932 start_cpuid = atomic_fetchadd_int(&pci_msi_cpuid, 1) % ncpus;
1935 for (i = 0; i < ncpus; ++i) {
1936 cpuid = (start_cpuid + i) % ncpus;
1938 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, count,
1939 cfg->msi.msi_msgnum, irqs, cpuid);
1942 else if (error != EMSGSIZE)
1949 * We now have N messages mapped onto SYS_RES_IRQ resources in
1950 * the irqs[] array, so add new resources starting at rid 1.
1952 for (i = 0; i < count; i++) {
1954 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1955 irqs[i], irqs[i], 1, cpuid);
1960 device_printf(child, "using IRQ %d on cpu%d for MSI\n",
1966 * Be fancy and try to print contiguous runs
1967 * of IRQ values as ranges. 'run' is true if
1968 * we are in a range.
1970 device_printf(child, "using IRQs %d", irqs[0]);
1972 for (i = 1; i < count; i++) {
1974 /* Still in a run? */
1975 if (irqs[i] == irqs[i - 1] + 1) {
1980 /* Finish previous range. */
1982 kprintf("-%d", irqs[i - 1]);
1986 /* Start new range. */
1987 kprintf(",%d", irqs[i]);
1990 /* Unfinished range? */
1992 kprintf("-%d", irqs[count - 1]);
1993 kprintf(" for MSI on cpu%d\n", cpuid);
1997 /* Update control register with count. */
1998 ctrl = cfg->msi.msi_ctrl;
1999 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2000 ctrl |= (ffs(count) - 1) << 4;
2001 cfg->msi.msi_ctrl = ctrl;
2002 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2004 /* Update counts of alloc'd messages. */
2005 cfg->msi.msi_alloc = count;
2006 cfg->msi.msi_handlers = 0;
2010 /* Release the MSI messages associated with this device. */
2012 pci_release_msi_method(device_t dev, device_t child)
2014 struct pci_devinfo *dinfo = device_get_ivars(child);
2015 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2016 struct resource_list_entry *rle;
2017 int i, irqs[32], cpuid = -1;
2019 /* Do we have any messages to release? */
2020 if (msi->msi_alloc == 0)
2022 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2024 /* Make sure none of the resources are allocated. */
2025 if (msi->msi_handlers > 0)
2027 for (i = 0; i < msi->msi_alloc; i++) {
2028 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2029 KASSERT(rle != NULL, ("missing MSI resource"));
2030 if (rle->res != NULL)
2034 KASSERT(cpuid >= 0 && cpuid < ncpus,
2035 ("invalid MSI target cpuid %d\n", cpuid));
2037 KASSERT(rle->cpuid == cpuid,
2038 ("MSI targets different cpus, "
2039 "was cpu%d, now cpu%d", cpuid, rle->cpuid));
2041 irqs[i] = rle->start;
2044 /* Update control register with 0 count. */
2045 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2046 ("%s: MSI still enabled", __func__));
2047 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2048 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2051 /* Release the messages. */
2052 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs,
2054 for (i = 0; i < msi->msi_alloc; i++)
2055 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2057 /* Update alloc count. */
2065 * Return the max supported MSI messages this device supports.
2066 * Basically, assuming the MD code can alloc messages, this function
2067 * should return the maximum value that pci_alloc_msi() can return.
2068 * Thus, it is subject to the tunables, etc.
2071 pci_msi_count_method(device_t dev, device_t child)
2073 struct pci_devinfo *dinfo = device_get_ivars(child);
2074 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2076 if (pci_do_msi && msi->msi_location != 0)
2077 return (msi->msi_msgnum);
2081 /* kfree pcicfgregs structure and all depending data structures */
2084 pci_freecfg(struct pci_devinfo *dinfo)
2086 struct devlist *devlist_head;
2089 devlist_head = &pci_devq;
2091 if (dinfo->cfg.vpd.vpd_reg) {
2092 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2093 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2094 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2095 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2096 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2097 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2098 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2100 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2101 kfree(dinfo, M_DEVBUF);
2103 /* increment the generation count */
2106 /* we're losing one device */
2112 * PCI power manangement
2115 pci_set_powerstate_method(device_t dev, device_t child, int state)
2117 struct pci_devinfo *dinfo = device_get_ivars(child);
2118 pcicfgregs *cfg = &dinfo->cfg;
2120 int result, oldstate, highest, delay;
2122 if (cfg->pp.pp_cap == 0)
2123 return (EOPNOTSUPP);
2126 * Optimize a no state change request away. While it would be OK to
2127 * write to the hardware in theory, some devices have shown odd
2128 * behavior when going from D3 -> D3.
2130 oldstate = pci_get_powerstate(child);
2131 if (oldstate == state)
2135 * The PCI power management specification states that after a state
2136 * transition between PCI power states, system software must
2137 * guarantee a minimal delay before the function accesses the device.
2138 * Compute the worst case delay that we need to guarantee before we
2139 * access the device. Many devices will be responsive much more
2140 * quickly than this delay, but there are some that don't respond
2141 * instantly to state changes. Transitions to/from D3 state require
2142 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2143 * is done below with DELAY rather than a sleeper function because
2144 * this function can be called from contexts where we cannot sleep.
2146 highest = (oldstate > state) ? oldstate : state;
2147 if (highest == PCI_POWERSTATE_D3)
2149 else if (highest == PCI_POWERSTATE_D2)
2153 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2154 & ~PCIM_PSTAT_DMASK;
2157 case PCI_POWERSTATE_D0:
2158 status |= PCIM_PSTAT_D0;
2160 case PCI_POWERSTATE_D1:
2161 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2162 return (EOPNOTSUPP);
2163 status |= PCIM_PSTAT_D1;
2165 case PCI_POWERSTATE_D2:
2166 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2167 return (EOPNOTSUPP);
2168 status |= PCIM_PSTAT_D2;
2170 case PCI_POWERSTATE_D3:
2171 status |= PCIM_PSTAT_D3;
2179 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2180 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2181 dinfo->cfg.func, oldstate, state);
2183 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2190 pci_get_powerstate_method(device_t dev, device_t child)
2192 struct pci_devinfo *dinfo = device_get_ivars(child);
2193 pcicfgregs *cfg = &dinfo->cfg;
2197 if (cfg->pp.pp_cap != 0) {
2198 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2199 switch (status & PCIM_PSTAT_DMASK) {
2201 result = PCI_POWERSTATE_D0;
2204 result = PCI_POWERSTATE_D1;
2207 result = PCI_POWERSTATE_D2;
2210 result = PCI_POWERSTATE_D3;
2213 result = PCI_POWERSTATE_UNKNOWN;
2217 /* No support, device is always at D0 */
2218 result = PCI_POWERSTATE_D0;
2224 * Some convenience functions for PCI device drivers.
2227 static __inline void
2228 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2232 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2234 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2237 static __inline void
2238 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2242 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2244 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2248 pci_enable_busmaster_method(device_t dev, device_t child)
2250 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2255 pci_disable_busmaster_method(device_t dev, device_t child)
2257 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2262 pci_enable_io_method(device_t dev, device_t child, int space)
2272 case SYS_RES_IOPORT:
2273 bit = PCIM_CMD_PORTEN;
2276 case SYS_RES_MEMORY:
2277 bit = PCIM_CMD_MEMEN;
2283 pci_set_command_bit(dev, child, bit);
2284 /* Some devices seem to need a brief stall here, what do to? */
2285 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2288 device_printf(child, "failed to enable %s mapping!\n", error);
2293 pci_disable_io_method(device_t dev, device_t child, int space)
2303 case SYS_RES_IOPORT:
2304 bit = PCIM_CMD_PORTEN;
2307 case SYS_RES_MEMORY:
2308 bit = PCIM_CMD_MEMEN;
2314 pci_clear_command_bit(dev, child, bit);
2315 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2316 if (command & bit) {
2317 device_printf(child, "failed to disable %s mapping!\n", error);
2324 * New style pci driver. Parent device is either a pci-host-bridge or a
2325 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2329 pci_print_verbose(struct pci_devinfo *dinfo)
2333 pcicfgregs *cfg = &dinfo->cfg;
2335 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2336 cfg->vendor, cfg->device, cfg->revid);
2337 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2338 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2339 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2340 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2342 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2343 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2344 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2345 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2346 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2347 if (cfg->intpin > 0)
2348 kprintf("\tintpin=%c, irq=%d\n",
2349 cfg->intpin +'a' -1, cfg->intline);
2350 if (cfg->pp.pp_cap) {
2353 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2354 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2355 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2356 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2357 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2358 status & PCIM_PSTAT_DMASK);
2360 if (cfg->msi.msi_location) {
2363 ctrl = cfg->msi.msi_ctrl;
2364 kprintf("\tMSI supports %d message%s%s%s\n",
2365 cfg->msi.msi_msgnum,
2366 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2367 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2368 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2370 if (cfg->msix.msix_location) {
2371 kprintf("\tMSI-X supports %d message%s ",
2372 cfg->msix.msix_msgnum,
2373 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2374 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2375 kprintf("in map 0x%x\n",
2376 cfg->msix.msix_table_bar);
2378 kprintf("in maps 0x%x and 0x%x\n",
2379 cfg->msix.msix_table_bar,
2380 cfg->msix.msix_pba_bar);
2382 pci_print_verbose_expr(cfg);
2387 pci_print_verbose_expr(const pcicfgregs *cfg)
2389 const struct pcicfg_expr *expr = &cfg->expr;
2390 const char *port_name;
2396 if (expr->expr_ptr == 0) /* No PCI Express capability */
2399 kprintf("\tPCI Express ver.%d cap=0x%04x",
2400 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2401 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2404 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2406 switch (port_type) {
2407 case PCIE_END_POINT:
2408 port_name = "DEVICE";
2410 case PCIE_LEG_END_POINT:
2411 port_name = "LEGDEV";
2413 case PCIE_ROOT_PORT:
2416 case PCIE_UP_STREAM_PORT:
2417 port_name = "UPSTREAM";
2419 case PCIE_DOWN_STREAM_PORT:
2420 port_name = "DOWNSTRM";
2422 case PCIE_PCIE2PCI_BRIDGE:
2423 port_name = "PCIE2PCI";
2425 case PCIE_PCI2PCIE_BRIDGE:
2426 port_name = "PCI2PCIE";
2432 if ((port_type == PCIE_ROOT_PORT ||
2433 port_type == PCIE_DOWN_STREAM_PORT) &&
2434 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2436 if (port_name != NULL)
2437 kprintf("[%s]", port_name);
2439 if (pcie_slotimpl(cfg)) {
2440 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2441 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2442 kprintf("[HOTPLUG]");
2449 pci_porten(device_t pcib, int b, int s, int f)
2451 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2452 & PCIM_CMD_PORTEN) != 0;
2456 pci_memen(device_t pcib, int b, int s, int f)
2458 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2459 & PCIM_CMD_MEMEN) != 0;
2463 * Add a resource based on a pci map register. Return 1 if the map
2464 * register is a 32bit map register or 2 if it is a 64bit register.
2467 pci_add_map(device_t pcib, device_t bus, device_t dev,
2468 int b, int s, int f, int reg, struct resource_list *rl, int force,
2473 pci_addr_t start, end, count;
2480 struct resource *res;
2482 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2483 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2484 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2485 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2487 if (PCI_BAR_MEM(map)) {
2488 type = SYS_RES_MEMORY;
2489 if (map & PCIM_BAR_MEM_PREFETCH)
2492 type = SYS_RES_IOPORT;
2493 ln2size = pci_mapsize(testval);
2494 ln2range = pci_maprange(testval);
2495 base = pci_mapbase(map);
2496 barlen = ln2range == 64 ? 2 : 1;
2499 * For I/O registers, if bottom bit is set, and the next bit up
2500 * isn't clear, we know we have a BAR that doesn't conform to the
2501 * spec, so ignore it. Also, sanity check the size of the data
2502 * areas to the type of memory involved. Memory must be at least
2503 * 16 bytes in size, while I/O ranges must be at least 4.
2505 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2507 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2508 (type == SYS_RES_IOPORT && ln2size < 2))
2512 /* Read the other half of a 64bit map register */
2513 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2515 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2516 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2517 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2518 kprintf(", port disabled\n");
2519 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2520 kprintf(", memory disabled\n");
2522 kprintf(", enabled\n");
2526 * If base is 0, then we have problems. It is best to ignore
2527 * such entries for the moment. These will be allocated later if
2528 * the driver specifically requests them. However, some
2529 * removable busses look better when all resources are allocated,
2530 * so allow '0' to be overriden.
2532 * Similarly treat maps whose values is the same as the test value
2533 * read back. These maps have had all f's written to them by the
2534 * BIOS in an attempt to disable the resources.
2536 if (!force && (base == 0 || map == testval))
2538 if ((u_long)base != base) {
2540 "pci%d:%d:%d:%d bar %#x too many address bits",
2541 pci_get_domain(dev), b, s, f, reg);
2546 * This code theoretically does the right thing, but has
2547 * undesirable side effects in some cases where peripherals
2548 * respond oddly to having these bits enabled. Let the user
2549 * be able to turn them off (since pci_enable_io_modes is 1 by
2552 if (pci_enable_io_modes) {
2553 /* Turn on resources that have been left off by a lazy BIOS */
2554 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2555 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2556 cmd |= PCIM_CMD_PORTEN;
2557 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2559 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2560 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2561 cmd |= PCIM_CMD_MEMEN;
2562 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2565 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2567 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2571 count = 1 << ln2size;
2572 if (base == 0 || base == pci_mapbase(testval)) {
2573 start = 0; /* Let the parent decide. */
2577 end = base + (1 << ln2size) - 1;
2579 resource_list_add(rl, type, reg, start, end, count, -1);
2582 * Try to allocate the resource for this BAR from our parent
2583 * so that this resource range is already reserved. The
2584 * driver for this device will later inherit this resource in
2585 * pci_alloc_resource().
2587 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2588 prefetch ? RF_PREFETCHABLE : 0, -1);
2591 * If the allocation fails, delete the resource list
2592 * entry to force pci_alloc_resource() to allocate
2593 * resources from the parent.
2595 resource_list_delete(rl, type, reg);
2596 #ifdef PCI_BAR_CLEAR
2599 #else /* !PCI_BAR_CLEAR */
2601 * Don't clear BAR here. Some BIOS lists HPET as a
2602 * PCI function, clearing the BAR causes HPET timer
2606 kprintf("pci:%d:%d:%d: resource reservation failed "
2607 "%#jx - %#jx\n", b, s, f,
2608 (intmax_t)start, (intmax_t)end);
2611 #endif /* PCI_BAR_CLEAR */
2613 start = rman_get_start(res);
2615 pci_write_config(dev, reg, start, 4);
2617 pci_write_config(dev, reg + 4, start >> 32, 4);
2622 * For ATA devices we need to decide early what addressing mode to use.
2623 * Legacy demands that the primary and secondary ATA ports sits on the
2624 * same addresses that old ISA hardware did. This dictates that we use
2625 * those addresses and ignore the BAR's if we cannot set PCI native
2629 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2630 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2632 int rid, type, progif;
2634 /* if this device supports PCI native addressing use it */
2635 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2636 if ((progif & 0x8a) == 0x8a) {
2637 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2638 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2639 kprintf("Trying ATA native PCI addressing mode\n");
2640 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2644 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2645 type = SYS_RES_IOPORT;
2646 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2647 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2648 prefetchmask & (1 << 0));
2649 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2650 prefetchmask & (1 << 1));
2653 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
2654 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2657 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
2658 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2661 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2662 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2663 prefetchmask & (1 << 2));
2664 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2665 prefetchmask & (1 << 3));
2668 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
2669 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2672 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
2673 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2676 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2677 prefetchmask & (1 << 4));
2678 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2679 prefetchmask & (1 << 5));
2683 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2685 struct pci_devinfo *dinfo = device_get_ivars(dev);
2686 pcicfgregs *cfg = &dinfo->cfg;
2687 char tunable_name[64];
2690 /* Has to have an intpin to have an interrupt. */
2691 if (cfg->intpin == 0)
2694 /* Let the user override the IRQ with a tunable. */
2695 irq = PCI_INVALID_IRQ;
2696 ksnprintf(tunable_name, sizeof(tunable_name),
2697 "hw.pci%d.%d.%d.INT%c.irq",
2698 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2699 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2700 irq = PCI_INVALID_IRQ;
2703 * If we didn't get an IRQ via the tunable, then we either use the
2704 * IRQ value in the intline register or we ask the bus to route an
2705 * interrupt for us. If force_route is true, then we only use the
2706 * value in the intline register if the bus was unable to assign an
2709 if (!PCI_INTERRUPT_VALID(irq)) {
2710 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2711 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2712 if (!PCI_INTERRUPT_VALID(irq))
2716 /* If after all that we don't have an IRQ, just bail. */
2717 if (!PCI_INTERRUPT_VALID(irq))
2720 /* Update the config register if it changed. */
2721 if (irq != cfg->intline) {
2723 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2726 /* Add this IRQ as rid 0 interrupt resource. */
2727 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1,
2728 machintr_legacy_intr_cpuid(irq));
2732 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2734 struct pci_devinfo *dinfo = device_get_ivars(dev);
2735 pcicfgregs *cfg = &dinfo->cfg;
2736 struct resource_list *rl = &dinfo->resources;
2737 struct pci_quirk *q;
2744 /* ATA devices needs special map treatment */
2745 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2746 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2747 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2748 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2749 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2750 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2752 for (i = 0; i < cfg->nummaps;)
2753 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2754 rl, force, prefetchmask & (1 << i));
2757 * Add additional, quirked resources.
2759 for (q = &pci_quirks[0]; q->devid; q++) {
2760 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2761 && q->type == PCI_QUIRK_MAP_REG)
2762 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2766 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2768 * Try to re-route interrupts. Sometimes the BIOS or
2769 * firmware may leave bogus values in these registers.
2770 * If the re-route fails, then just stick with what we
2773 pci_assign_interrupt(bus, dev, 1);
2778 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2780 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2781 device_t pcib = device_get_parent(dev);
2782 struct pci_devinfo *dinfo;
2784 int s, f, pcifunchigh;
2787 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2788 ("dinfo_size too small"));
2789 maxslots = PCIB_MAXSLOTS(pcib);
2790 for (s = 0; s <= maxslots; s++) {
2794 hdrtype = REG(PCIR_HDRTYPE, 1);
2795 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2797 if (hdrtype & PCIM_MFDEV)
2798 pcifunchigh = PCI_FUNCMAX;
2799 for (f = 0; f <= pcifunchigh; f++) {
2800 dinfo = pci_read_device(pcib, domain, busno, s, f,
2802 if (dinfo != NULL) {
2803 pci_add_child(dev, dinfo);
2811 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2815 pcib = device_get_parent(bus);
2816 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2817 device_set_ivars(dinfo->cfg.dev, dinfo);
2818 resource_list_init(&dinfo->resources);
2819 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2820 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2821 pci_print_verbose(dinfo);
2822 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2826 pci_probe(device_t dev)
2828 device_set_desc(dev, "PCI bus");
2830 /* Allow other subclasses to override this driver. */
2835 pci_attach(device_t dev)
2840 * Since there can be multiple independantly numbered PCI
2841 * busses on systems with multiple PCI domains, we can't use
2842 * the unit number to decide which bus we are probing. We ask
2843 * the parent pcib what our domain and bus numbers are.
2845 domain = pcib_get_domain(dev);
2846 busno = pcib_get_bus(dev);
2848 device_printf(dev, "domain=%d, physical bus=%d\n",
2851 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2853 return (bus_generic_attach(dev));
2857 pci_suspend(device_t dev)
2859 int dstate, error, i, numdevs;
2860 device_t acpi_dev, child, *devlist;
2861 struct pci_devinfo *dinfo;
2864 * Save the PCI configuration space for each child and set the
2865 * device in the appropriate power state for this sleep state.
2868 if (pci_do_power_resume)
2869 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2870 device_get_children(dev, &devlist, &numdevs);
2871 for (i = 0; i < numdevs; i++) {
2873 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2874 pci_cfg_save(child, dinfo, 0);
2877 /* Suspend devices before potentially powering them down. */
2878 error = bus_generic_suspend(dev);
2880 kfree(devlist, M_TEMP);
2885 * Always set the device to D3. If ACPI suggests a different
2886 * power state, use it instead. If ACPI is not present, the
2887 * firmware is responsible for managing device power. Skip
2888 * children who aren't attached since they are powered down
2889 * separately. Only manage type 0 devices for now.
2891 for (i = 0; acpi_dev && i < numdevs; i++) {
2893 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2894 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2895 dstate = PCI_POWERSTATE_D3;
2896 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2897 pci_set_powerstate(child, dstate);
2900 kfree(devlist, M_TEMP);
2905 pci_resume(device_t dev)
2908 device_t acpi_dev, child, *devlist;
2909 struct pci_devinfo *dinfo;
2912 * Set each child to D0 and restore its PCI configuration space.
2915 if (pci_do_power_resume)
2916 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2917 device_get_children(dev, &devlist, &numdevs);
2918 for (i = 0; i < numdevs; i++) {
2920 * Notify ACPI we're going to D0 but ignore the result. If
2921 * ACPI is not present, the firmware is responsible for
2922 * managing device power. Only manage type 0 devices for now.
2925 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2926 if (acpi_dev && device_is_attached(child) &&
2927 dinfo->cfg.hdrtype == 0) {
2928 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2929 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2932 /* Now the device is powered up, restore its config space. */
2933 pci_cfg_restore(child, dinfo);
2935 kfree(devlist, M_TEMP);
2936 return (bus_generic_resume(dev));
2940 pci_load_vendor_data(void)
2942 caddr_t vendordata, info;
2944 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2945 info = preload_search_info(vendordata, MODINFO_ADDR);
2946 pci_vendordata = *(char **)info;
2947 info = preload_search_info(vendordata, MODINFO_SIZE);
2948 pci_vendordata_size = *(size_t *)info;
2949 /* terminate the database */
2950 pci_vendordata[pci_vendordata_size] = '\n';
2955 pci_driver_added(device_t dev, driver_t *driver)
2960 struct pci_devinfo *dinfo;
2964 device_printf(dev, "driver added\n");
2965 DEVICE_IDENTIFY(driver, dev);
2966 device_get_children(dev, &devlist, &numdevs);
2967 for (i = 0; i < numdevs; i++) {
2969 if (device_get_state(child) != DS_NOTPRESENT)
2971 dinfo = device_get_ivars(child);
2972 pci_print_verbose(dinfo);
2974 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2975 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2977 pci_cfg_restore(child, dinfo);
2978 if (device_probe_and_attach(child) != 0)
2979 pci_cfg_save(child, dinfo, 1);
2981 kfree(devlist, M_TEMP);
2985 pci_child_detached(device_t parent __unused, device_t child)
2987 /* Turn child's power off */
2988 pci_cfg_save(child, device_get_ivars(child), 1);
2992 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2993 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
2998 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
2999 arg, &cookie, serializer);
3003 /* If this is not a direct child, just bail out. */
3004 if (device_get_parent(child) != dev) {
3009 rid = rman_get_rid(irq);
3011 /* Make sure that INTx is enabled */
3012 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3014 struct pci_devinfo *dinfo = device_get_ivars(child);
3019 * Check to see if the interrupt is MSI or MSI-X.
3020 * Ask our parent to map the MSI and give
3021 * us the address and data register values.
3022 * If we fail for some reason, teardown the
3023 * interrupt handler.
3025 if (dinfo->cfg.msi.msi_alloc > 0) {
3026 struct pcicfg_msi *msi = &dinfo->cfg.msi;
3028 if (msi->msi_addr == 0) {
3029 KASSERT(msi->msi_handlers == 0,
3030 ("MSI has handlers, but vectors not mapped"));
3031 error = PCIB_MAP_MSI(device_get_parent(dev),
3032 child, rman_get_start(irq), &addr, &data,
3033 rman_get_cpuid(irq));
3036 msi->msi_addr = addr;
3037 msi->msi_data = data;
3038 pci_enable_msi(child, addr, data);
3040 msi->msi_handlers++;
3042 struct msix_vector *mv;
3045 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3046 ("No MSI-X or MSI rid %d allocated\n", rid));
3048 mv = pci_find_msix_vector(child, rid);
3050 ("MSI-X rid %d is not allocated\n", rid));
3051 KASSERT(mv->mv_address == 0,
3052 ("MSI-X rid %d has been setup\n", rid));
3054 error = PCIB_MAP_MSI(device_get_parent(dev),
3055 child, rman_get_start(irq), &addr, &data,
3056 rman_get_cpuid(irq));
3059 mv->mv_address = addr;
3062 vector = PCI_MSIX_RID2VEC(rid);
3063 pci_setup_msix_vector(child, vector,
3064 mv->mv_address, mv->mv_data);
3065 pci_unmask_msix_vector(child, vector);
3068 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3069 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3072 (void)bus_generic_teardown_intr(dev, child, irq,
3082 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3087 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3090 /* If this isn't a direct child, just bail out */
3091 if (device_get_parent(child) != dev)
3092 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3094 rid = rman_get_rid(irq);
3097 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3099 struct pci_devinfo *dinfo = device_get_ivars(child);
3102 * Check to see if the interrupt is MSI or MSI-X. If so,
3103 * decrement the appropriate handlers count and mask the
3104 * MSI-X message, or disable MSI messages if the count
3107 if (dinfo->cfg.msi.msi_alloc > 0) {
3108 struct pcicfg_msi *msi = &dinfo->cfg.msi;
3110 KASSERT(rid <= msi->msi_alloc,
3111 ("MSI-X index too high\n"));
3112 KASSERT(msi->msi_handlers > 0,
3113 ("MSI rid %d is not setup\n", rid));
3115 msi->msi_handlers--;
3116 if (msi->msi_handlers == 0)
3117 pci_disable_msi(child);
3119 struct msix_vector *mv;
3121 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3122 ("No MSI or MSI-X rid %d allocated", rid));
3124 mv = pci_find_msix_vector(child, rid);
3126 ("MSI-X rid %d is not allocated\n", rid));
3127 KASSERT(mv->mv_address != 0,
3128 ("MSI-X rid %d has not been setup\n", rid));
3130 pci_mask_msix_vector(child, PCI_MSIX_RID2VEC(rid));
3135 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3138 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3143 pci_print_child(device_t dev, device_t child)
3145 struct pci_devinfo *dinfo;
3146 struct resource_list *rl;
3149 dinfo = device_get_ivars(child);
3150 rl = &dinfo->resources;
3152 retval += bus_print_child_header(dev, child);
3154 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3155 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3156 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3157 if (device_get_flags(dev))
3158 retval += kprintf(" flags %#x", device_get_flags(dev));
3160 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3161 pci_get_function(child));
3163 retval += bus_print_child_footer(dev, child);
3173 } pci_nomatch_tab[] = {
3174 {PCIC_OLD, -1, "old"},
3175 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3176 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3177 {PCIC_STORAGE, -1, "mass storage"},
3178 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3179 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3180 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3181 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3182 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3183 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3184 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3185 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3186 {PCIC_NETWORK, -1, "network"},
3187 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3188 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3189 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3190 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3191 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3192 {PCIC_DISPLAY, -1, "display"},
3193 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3194 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3195 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3196 {PCIC_MULTIMEDIA, -1, "multimedia"},
3197 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3198 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3199 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3200 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3201 {PCIC_MEMORY, -1, "memory"},
3202 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3203 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3204 {PCIC_BRIDGE, -1, "bridge"},
3205 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3206 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3207 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3208 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3209 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3210 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3211 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3212 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3213 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3214 {PCIC_SIMPLECOMM, -1, "simple comms"},
3215 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3216 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3217 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3218 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3219 {PCIC_BASEPERIPH, -1, "base peripheral"},
3220 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3221 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3222 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3223 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3224 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3225 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3226 {PCIC_INPUTDEV, -1, "input device"},
3227 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3228 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3229 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3230 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3231 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3232 {PCIC_DOCKING, -1, "docking station"},
3233 {PCIC_PROCESSOR, -1, "processor"},
3234 {PCIC_SERIALBUS, -1, "serial bus"},
3235 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3236 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3237 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3238 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3239 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3240 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3241 {PCIC_WIRELESS, -1, "wireless controller"},
3242 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3243 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3244 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3245 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3246 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3247 {PCIC_SATCOM, -1, "satellite communication"},
3248 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3249 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3250 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3251 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3252 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3253 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3254 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3255 {PCIC_DASP, -1, "dasp"},
3256 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3261 pci_probe_nomatch(device_t dev, device_t child)
3264 char *cp, *scp, *device;
3267 * Look for a listing for this device in a loaded device database.
3269 if ((device = pci_describe_device(child)) != NULL) {
3270 device_printf(dev, "<%s>", device);
3271 kfree(device, M_DEVBUF);
3274 * Scan the class/subclass descriptions for a general
3279 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3280 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3281 if (pci_nomatch_tab[i].subclass == -1) {
3282 cp = pci_nomatch_tab[i].desc;
3283 } else if (pci_nomatch_tab[i].subclass ==
3284 pci_get_subclass(child)) {
3285 scp = pci_nomatch_tab[i].desc;
3289 device_printf(dev, "<%s%s%s>",
3291 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3294 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3295 pci_get_vendor(child), pci_get_device(child),
3296 pci_get_slot(child), pci_get_function(child));
3297 if (pci_get_intpin(child) > 0) {
3300 irq = pci_get_irq(child);
3301 if (PCI_INTERRUPT_VALID(irq))
3302 kprintf(" irq %d", irq);
3306 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3310 * Parse the PCI device database, if loaded, and return a pointer to a
3311 * description of the device.
3313 * The database is flat text formatted as follows:
3315 * Any line not in a valid format is ignored.
3316 * Lines are terminated with newline '\n' characters.
3318 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3321 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3322 * - devices cannot be listed without a corresponding VENDOR line.
3323 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3324 * another TAB, then the device name.
3328 * Assuming (ptr) points to the beginning of a line in the database,
3329 * return the vendor or device and description of the next entry.
3330 * The value of (vendor) or (device) inappropriate for the entry type
3331 * is set to -1. Returns nonzero at the end of the database.
3333 * Note that this is slightly unrobust in the face of corrupt data;
3334 * we attempt to safeguard against this by spamming the end of the
3335 * database with a newline when we initialise.
3338 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3347 left = pci_vendordata_size - (cp - pci_vendordata);
3355 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3359 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3362 /* skip to next line */
3363 while (*cp != '\n' && left > 0) {
3372 /* skip to next line */
3373 while (*cp != '\n' && left > 0) {
3377 if (*cp == '\n' && left > 0)
3384 pci_describe_device(device_t dev)
3387 char *desc, *vp, *dp, *line;
3389 desc = vp = dp = NULL;
3392 * If we have no vendor data, we can't do anything.
3394 if (pci_vendordata == NULL)
3398 * Scan the vendor data looking for this device
3400 line = pci_vendordata;
3401 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3404 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3406 if (vendor == pci_get_vendor(dev))
3409 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3412 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3420 if (device == pci_get_device(dev))
3424 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3425 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3427 ksprintf(desc, "%s, %s", vp, dp);
3430 kfree(vp, M_DEVBUF);
3432 kfree(dp, M_DEVBUF);
3437 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3439 struct pci_devinfo *dinfo;
3442 dinfo = device_get_ivars(child);
3446 case PCI_IVAR_ETHADDR:
3448 * The generic accessor doesn't deal with failure, so
3449 * we set the return value, then return an error.
3451 *((uint8_t **) result) = NULL;
3453 case PCI_IVAR_SUBVENDOR:
3454 *result = cfg->subvendor;
3456 case PCI_IVAR_SUBDEVICE:
3457 *result = cfg->subdevice;
3459 case PCI_IVAR_VENDOR:
3460 *result = cfg->vendor;
3462 case PCI_IVAR_DEVICE:
3463 *result = cfg->device;
3465 case PCI_IVAR_DEVID:
3466 *result = (cfg->device << 16) | cfg->vendor;
3468 case PCI_IVAR_CLASS:
3469 *result = cfg->baseclass;
3471 case PCI_IVAR_SUBCLASS:
3472 *result = cfg->subclass;
3474 case PCI_IVAR_PROGIF:
3475 *result = cfg->progif;
3477 case PCI_IVAR_REVID:
3478 *result = cfg->revid;
3480 case PCI_IVAR_INTPIN:
3481 *result = cfg->intpin;
3484 *result = cfg->intline;
3486 case PCI_IVAR_DOMAIN:
3487 *result = cfg->domain;
3493 *result = cfg->slot;
3495 case PCI_IVAR_FUNCTION:
3496 *result = cfg->func;
3498 case PCI_IVAR_CMDREG:
3499 *result = cfg->cmdreg;
3501 case PCI_IVAR_CACHELNSZ:
3502 *result = cfg->cachelnsz;
3504 case PCI_IVAR_MINGNT:
3505 *result = cfg->mingnt;
3507 case PCI_IVAR_MAXLAT:
3508 *result = cfg->maxlat;
3510 case PCI_IVAR_LATTIMER:
3511 *result = cfg->lattimer;
3513 case PCI_IVAR_PCIXCAP_PTR:
3514 *result = cfg->pcix.pcix_ptr;
3516 case PCI_IVAR_PCIECAP_PTR:
3517 *result = cfg->expr.expr_ptr;
3519 case PCI_IVAR_VPDCAP_PTR:
3520 *result = cfg->vpd.vpd_reg;
3529 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3531 struct pci_devinfo *dinfo;
3533 dinfo = device_get_ivars(child);
3536 case PCI_IVAR_INTPIN:
3537 dinfo->cfg.intpin = value;
3539 case PCI_IVAR_ETHADDR:
3540 case PCI_IVAR_SUBVENDOR:
3541 case PCI_IVAR_SUBDEVICE:
3542 case PCI_IVAR_VENDOR:
3543 case PCI_IVAR_DEVICE:
3544 case PCI_IVAR_DEVID:
3545 case PCI_IVAR_CLASS:
3546 case PCI_IVAR_SUBCLASS:
3547 case PCI_IVAR_PROGIF:
3548 case PCI_IVAR_REVID:
3550 case PCI_IVAR_DOMAIN:
3553 case PCI_IVAR_FUNCTION:
3554 return (EINVAL); /* disallow for now */
3561 #include "opt_ddb.h"
3563 #include <ddb/ddb.h>
3564 #include <sys/cons.h>
3567 * List resources based on pci map registers, used for within ddb
3570 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3572 struct pci_devinfo *dinfo;
3573 struct devlist *devlist_head;
3576 int i, error, none_count;
3579 /* get the head of the device queue */
3580 devlist_head = &pci_devq;
3583 * Go through the list of devices and print out devices
3585 for (error = 0, i = 0,
3586 dinfo = STAILQ_FIRST(devlist_head);
3587 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3588 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3590 /* Populate pd_name and pd_unit */
3593 name = device_get_name(dinfo->cfg.dev);
3596 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3597 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3598 (name && *name) ? name : "none",
3599 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3601 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3602 p->pc_sel.pc_func, (p->pc_class << 16) |
3603 (p->pc_subclass << 8) | p->pc_progif,
3604 (p->pc_subdevice << 16) | p->pc_subvendor,
3605 (p->pc_device << 16) | p->pc_vendor,
3606 p->pc_revid, p->pc_hdr);
3612 static struct resource *
3613 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3614 u_long start, u_long end, u_long count, u_int flags)
3616 struct pci_devinfo *dinfo = device_get_ivars(child);
3617 struct resource_list *rl = &dinfo->resources;
3618 struct resource_list_entry *rle;
3619 struct resource *res;
3620 pci_addr_t map, testval;
3624 * Weed out the bogons, and figure out how large the BAR/map
3625 * is. Bars that read back 0 here are bogus and unimplemented.
3626 * Note: atapci in legacy mode are special and handled elsewhere
3627 * in the code. If you have a atapci device in legacy mode and
3628 * it fails here, that other code is broken.
3631 map = pci_read_config(child, *rid, 4);
3632 pci_write_config(child, *rid, 0xffffffff, 4);
3633 testval = pci_read_config(child, *rid, 4);
3634 if (pci_maprange(testval) == 64)
3635 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3636 if (pci_mapbase(testval) == 0)
3640 * Restore the original value of the BAR. We may have reprogrammed
3641 * the BAR of the low-level console device and when booting verbose,
3642 * we need the console device addressable.
3644 pci_write_config(child, *rid, map, 4);
3646 if (PCI_BAR_MEM(testval)) {
3647 if (type != SYS_RES_MEMORY) {
3650 "child %s requested type %d for rid %#x,"
3651 " but the BAR says it is an memio\n",
3652 device_get_nameunit(child), type, *rid);
3656 if (type != SYS_RES_IOPORT) {
3659 "child %s requested type %d for rid %#x,"
3660 " but the BAR says it is an ioport\n",
3661 device_get_nameunit(child), type, *rid);
3666 * For real BARs, we need to override the size that
3667 * the driver requests, because that's what the BAR
3668 * actually uses and we would otherwise have a
3669 * situation where we might allocate the excess to
3670 * another driver, which won't work.
3672 mapsize = pci_mapsize(testval);
3673 count = 1UL << mapsize;
3674 if (RF_ALIGNMENT(flags) < mapsize)
3675 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3676 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3677 flags |= RF_PREFETCHABLE;
3680 * Allocate enough resource, and then write back the
3681 * appropriate bar for that resource.
3683 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3684 start, end, count, flags, -1);
3686 device_printf(child,
3687 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3688 count, *rid, type, start, end);
3691 resource_list_add(rl, type, *rid, start, end, count, -1);
3692 rle = resource_list_find(rl, type, *rid);
3694 panic("pci_alloc_map: unexpectedly can't find resource.");
3696 rle->start = rman_get_start(res);
3697 rle->end = rman_get_end(res);
3700 device_printf(child,
3701 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3702 count, *rid, type, rman_get_start(res));
3703 map = rman_get_start(res);
3705 pci_write_config(child, *rid, map, 4);
3706 if (pci_maprange(testval) == 64)
3707 pci_write_config(child, *rid + 4, map >> 32, 4);
3713 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3714 u_long start, u_long end, u_long count, u_int flags, int cpuid)
3716 struct pci_devinfo *dinfo = device_get_ivars(child);
3717 struct resource_list *rl = &dinfo->resources;
3718 struct resource_list_entry *rle;
3719 pcicfgregs *cfg = &dinfo->cfg;
3722 * Perform lazy resource allocation
3724 if (device_get_parent(child) == dev) {
3728 * Can't alloc legacy interrupt once MSI messages
3729 * have been allocated.
3731 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3732 cfg->msix.msix_alloc > 0))
3735 * If the child device doesn't have an
3736 * interrupt routed and is deserving of an
3737 * interrupt, try to assign it one.
3739 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3741 pci_assign_interrupt(dev, child, 0);
3743 case SYS_RES_IOPORT:
3744 case SYS_RES_MEMORY:
3745 if (*rid < PCIR_BAR(cfg->nummaps)) {
3747 * Enable the I/O mode. We should
3748 * also be assigning resources too
3749 * when none are present. The
3750 * resource_list_alloc kind of sorta does
3753 if (PCI_ENABLE_IO(dev, child, type))
3756 rle = resource_list_find(rl, type, *rid);
3758 return (pci_alloc_map(dev, child, type, rid,
3759 start, end, count, flags));
3763 * If we've already allocated the resource, then
3764 * return it now. But first we may need to activate
3765 * it, since we don't allocate the resource as active
3766 * above. Normally this would be done down in the
3767 * nexus, but since we short-circuit that path we have
3768 * to do its job here. Not sure if we should kfree the
3769 * resource if it fails to activate.
3771 rle = resource_list_find(rl, type, *rid);
3772 if (rle != NULL && rle->res != NULL) {
3774 device_printf(child,
3775 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3776 rman_get_size(rle->res), *rid, type,
3777 rman_get_start(rle->res));
3778 if ((flags & RF_ACTIVE) &&
3779 bus_generic_activate_resource(dev, child, type,
3780 *rid, rle->res) != 0)
3785 return (resource_list_alloc(rl, dev, child, type, rid,
3786 start, end, count, flags, cpuid));
3790 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3792 struct pci_devinfo *dinfo;
3793 struct resource_list *rl;
3794 struct resource_list_entry *rle;
3796 if (device_get_parent(child) != dev)
3799 dinfo = device_get_ivars(child);
3800 rl = &dinfo->resources;
3801 rle = resource_list_find(rl, type, rid);
3804 if (rman_get_device(rle->res) != dev ||
3805 rman_get_flags(rle->res) & RF_ACTIVE) {
3806 device_printf(dev, "delete_resource: "
3807 "Resource still owned by child, oops. "
3808 "(type=%d, rid=%d, addr=%lx)\n",
3809 rle->type, rle->rid,
3810 rman_get_start(rle->res));
3813 bus_release_resource(dev, type, rid, rle->res);
3815 resource_list_delete(rl, type, rid);
3818 * Why do we turn off the PCI configuration BAR when we delete a
3821 pci_write_config(child, rid, 0, 4);
3822 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3825 struct resource_list *
3826 pci_get_resource_list (device_t dev, device_t child)
3828 struct pci_devinfo *dinfo = device_get_ivars(child);
3833 return (&dinfo->resources);
3837 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3839 struct pci_devinfo *dinfo = device_get_ivars(child);
3840 pcicfgregs *cfg = &dinfo->cfg;
3842 return (PCIB_READ_CONFIG(device_get_parent(dev),
3843 cfg->bus, cfg->slot, cfg->func, reg, width));
3847 pci_write_config_method(device_t dev, device_t child, int reg,
3848 uint32_t val, int width)
3850 struct pci_devinfo *dinfo = device_get_ivars(child);
3851 pcicfgregs *cfg = &dinfo->cfg;
3853 PCIB_WRITE_CONFIG(device_get_parent(dev),
3854 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3858 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3862 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3863 pci_get_function(child));
3868 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3871 struct pci_devinfo *dinfo;
3874 dinfo = device_get_ivars(child);
3876 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3877 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3878 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3884 pci_assign_interrupt_method(device_t dev, device_t child)
3886 struct pci_devinfo *dinfo = device_get_ivars(child);
3887 pcicfgregs *cfg = &dinfo->cfg;
3889 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3894 pci_modevent(module_t mod, int what, void *arg)
3896 static struct cdev *pci_cdev;
3900 STAILQ_INIT(&pci_devq);
3902 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3904 pci_load_vendor_data();
3908 destroy_dev(pci_cdev);
3916 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3921 * Only do header type 0 devices. Type 1 devices are bridges,
3922 * which we know need special treatment. Type 2 devices are
3923 * cardbus bridges which also require special treatment.
3924 * Other types are unknown, and we err on the side of safety
3927 if (dinfo->cfg.hdrtype != 0)
3931 * Restore the device to full power mode. We must do this
3932 * before we restore the registers because moving from D3 to
3933 * D0 will cause the chip's BARs and some other registers to
3934 * be reset to some unknown power on reset values. Cut down
3935 * the noise on boot by doing nothing if we are already in
3938 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3939 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3941 for (i = 0; i < dinfo->cfg.nummaps; i++)
3942 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3943 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3944 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3945 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3946 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3947 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3948 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3949 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3950 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3951 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3952 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3954 /* Restore MSI and MSI-X configurations if they are present. */
3955 if (dinfo->cfg.msi.msi_location != 0)
3956 pci_resume_msi(dev);
3957 if (dinfo->cfg.msix.msix_location != 0)
3958 pci_resume_msix(dev);
3962 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3969 * Only do header type 0 devices. Type 1 devices are bridges, which
3970 * we know need special treatment. Type 2 devices are cardbus bridges
3971 * which also require special treatment. Other types are unknown, and
3972 * we err on the side of safety by ignoring them. Powering down
3973 * bridges should not be undertaken lightly.
3975 if (dinfo->cfg.hdrtype != 0)
3977 for (i = 0; i < dinfo->cfg.nummaps; i++)
3978 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3979 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3982 * Some drivers apparently write to these registers w/o updating our
3983 * cached copy. No harm happens if we update the copy, so do so here
3984 * so we can restore them. The COMMAND register is modified by the
3985 * bus w/o updating the cache. This should represent the normally
3986 * writable portion of the 'defined' part of type 0 headers. In
3987 * theory we also need to save/restore the PCI capability structures
3988 * we know about, but apart from power we don't know any that are
3991 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3992 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3993 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3994 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3995 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3996 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3997 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3998 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3999 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4000 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4001 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4002 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4003 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4004 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4005 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4008 * don't set the state for display devices, base peripherals and
4009 * memory devices since bad things happen when they are powered down.
4010 * We should (a) have drivers that can easily detach and (b) use
4011 * generic drivers for these devices so that some device actually
4012 * attaches. We need to make sure that when we implement (a) we don't
4013 * power the device down on a reattach.
4015 cls = pci_get_class(dev);
4018 switch (pci_do_power_nodriver)
4020 case 0: /* NO powerdown at all */
4022 case 1: /* Conservative about what to power down */
4023 if (cls == PCIC_STORAGE)
4026 case 2: /* Agressive about what to power down */
4027 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4028 cls == PCIC_BASEPERIPH)
4031 case 3: /* Power down everything */
4035 * PCI spec says we can only go into D3 state from D0 state.
4036 * Transition from D[12] into D0 before going to D3 state.
4038 ps = pci_get_powerstate(dev);
4039 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4040 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4041 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4042 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4045 #ifdef COMPAT_OLDPCI
4048 * Locate the parent of a PCI device by scanning the PCI devlist
4049 * and return the entry for the parent.
4050 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4051 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4054 pci_devlist_get_parent(pcicfgregs *cfg)
4056 struct devlist *devlist_head;
4057 struct pci_devinfo *dinfo;
4058 pcicfgregs *bridge_cfg;
4061 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4063 /* If the device is on PCI bus 0, look for the host */
4064 if (cfg->bus == 0) {
4065 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4066 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4067 bridge_cfg = &dinfo->cfg;
4068 if (bridge_cfg->baseclass == PCIC_BRIDGE
4069 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4070 && bridge_cfg->bus == cfg->bus) {
4076 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4078 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4079 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4080 bridge_cfg = &dinfo->cfg;
4081 if (bridge_cfg->baseclass == PCIC_BRIDGE
4082 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4083 && bridge_cfg->secondarybus == cfg->bus) {
4092 #endif /* COMPAT_OLDPCI */
4095 pci_alloc_1intr(device_t dev, int msi_enable, int *rid0, u_int *flags0)
4102 type = PCI_INTR_TYPE_LEGACY;
4103 flags = RF_SHAREABLE | RF_ACTIVE;
4105 ksnprintf(env, sizeof(env), "hw.%s.msi.enable",
4106 device_get_nameunit(dev));
4107 kgetenv_int(env, &msi_enable);
4112 ksnprintf(env, sizeof(env), "hw.%s.msi.cpu",
4113 device_get_nameunit(dev));
4114 kgetenv_int(env, &cpu);
4118 if (pci_alloc_msi(dev, &rid, 1, cpu) == 0) {
4119 flags &= ~RF_SHAREABLE;
4120 type = PCI_INTR_TYPE_MSI;