2 * Copyright © 2012-2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
30 #include "intel_drv.h"
35 * The i915 driver supports dynamic enabling and disabling of entire hardware
36 * blocks at runtime. This is especially important on the display side where
37 * software is supposed to control many power gates manually on recent hardware,
38 * since on the GT side a lot of the power management is done by the hardware.
39 * But even there some manual control at the device level is required.
41 * Since i915 supports a diverse set of platforms with a unified codebase and
42 * hardware engineers just love to shuffle functionality around between power
43 * domains there's a sizeable amount of indirection required. This file provides
44 * generic functions to the driver for grabbing and releasing references for
45 * abstract power domains. It then maps those to the actual power wells
46 * present for a given platform.
49 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
51 i < (power_domains)->power_well_count && \
52 ((power_well) = &(power_domains)->power_wells[i]); \
54 if ((power_well)->domains & (domain_mask))
56 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
57 for (i = (power_domains)->power_well_count - 1; \
58 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
60 if ((power_well)->domains & (domain_mask))
63 * We should only use the power well if we explicitly asked the hardware to
64 * enable it, so check if it's enabled and also check if we've requested it to
67 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
68 struct i915_power_well *power_well)
70 return I915_READ(HSW_PWR_WELL_DRIVER) ==
71 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
75 * __intel_display_power_is_enabled - unlocked check for a power domain
76 * @dev_priv: i915 device instance
77 * @domain: power domain to check
79 * This is the unlocked version of intel_display_power_is_enabled() and should
80 * only be used from error capture and recovery code where deadlocks are
84 * True when the power domain is enabled, false otherwise.
86 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
87 enum intel_display_power_domain domain)
89 struct i915_power_domains *power_domains;
90 struct i915_power_well *power_well;
94 if (dev_priv->pm.suspended)
97 power_domains = &dev_priv->power_domains;
101 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
102 if (power_well->always_on)
105 if (!power_well->hw_enabled) {
115 * intel_display_power_is_enabled - check for a power domain
116 * @dev_priv: i915 device instance
117 * @domain: power domain to check
119 * This function can be used to check the hw power domain state. It is mostly
120 * used in hardware state readout functions. Everywhere else code should rely
121 * upon explicit power domain reference counting to ensure that the hardware
122 * block is powered up before accessing it.
124 * Callers must hold the relevant modesetting locks to ensure that concurrent
125 * threads can't disable the power well while the caller tries to read a few
129 * True when the power domain is enabled, false otherwise.
131 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
132 enum intel_display_power_domain domain)
134 struct i915_power_domains *power_domains;
137 power_domains = &dev_priv->power_domains;
139 mutex_lock(&power_domains->lock);
140 ret = __intel_display_power_is_enabled(dev_priv, domain);
141 mutex_unlock(&power_domains->lock);
147 * intel_display_set_init_power - set the initial power domain state
148 * @dev_priv: i915 device instance
149 * @enable: whether to enable or disable the initial power domain state
151 * For simplicity our driver load/unload and system suspend/resume code assumes
152 * that all power domains are always enabled. This functions controls the state
153 * of this little hack. While the initial power domain state is enabled runtime
154 * pm is effectively disabled.
156 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
159 if (dev_priv->power_domains.init_power_on == enable)
163 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
165 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
167 dev_priv->power_domains.init_power_on = enable;
171 * Starting with Haswell, we have a "Power Down Well" that can be turned off
172 * when not needed anymore. We have 4 registers that can request the power well
173 * to be enabled, and it will only be disabled if none of the registers is
174 * requesting it to be enabled.
176 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
178 struct drm_device *dev = dev_priv->dev;
181 * After we re-enable the power well, if we touch VGA register 0x3d5
182 * we'll get unclaimed register interrupts. This stops after we write
183 * anything to the VGA MSR register. The vgacon module uses this
184 * register all the time, so if we unbind our driver and, as a
185 * consequence, bind vgacon, we'll get stuck in an infinite loop at
186 * console_unlock(). So make here we touch the VGA MSR register, making
187 * sure vgacon can keep working normally without triggering interrupts
188 * and error messages.
191 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
192 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
193 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
196 if (IS_BROADWELL(dev))
197 gen8_irq_power_well_post_enable(dev_priv,
198 1 << PIPE_C | 1 << PIPE_B);
201 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
202 struct i915_power_well *power_well)
204 struct drm_device *dev = dev_priv->dev;
207 * After we re-enable the power well, if we touch VGA register 0x3d5
208 * we'll get unclaimed register interrupts. This stops after we write
209 * anything to the VGA MSR register. The vgacon module uses this
210 * register all the time, so if we unbind our driver and, as a
211 * consequence, bind vgacon, we'll get stuck in an infinite loop at
212 * console_unlock(). So make here we touch the VGA MSR register, making
213 * sure vgacon can keep working normally without triggering interrupts
214 * and error messages.
216 if (power_well->data == SKL_DISP_PW_2) {
218 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
219 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
220 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
223 gen8_irq_power_well_post_enable(dev_priv,
224 1 << PIPE_C | 1 << PIPE_B);
227 if (power_well->data == SKL_DISP_PW_1) {
228 intel_prepare_ddi(dev);
229 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
233 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
234 struct i915_power_well *power_well, bool enable)
236 bool is_enabled, enable_requested;
239 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
240 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
241 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
244 if (!enable_requested)
245 I915_WRITE(HSW_PWR_WELL_DRIVER,
246 HSW_PWR_WELL_ENABLE_REQUEST);
249 DRM_DEBUG_KMS("Enabling power well\n");
250 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
251 HSW_PWR_WELL_STATE_ENABLED), 20))
252 DRM_ERROR("Timeout enabling power well\n");
253 hsw_power_well_post_enable(dev_priv);
257 if (enable_requested) {
258 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
259 POSTING_READ(HSW_PWR_WELL_DRIVER);
260 DRM_DEBUG_KMS("Requesting to disable the power well\n");
265 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
266 BIT(POWER_DOMAIN_TRANSCODER_A) | \
267 BIT(POWER_DOMAIN_PIPE_B) | \
268 BIT(POWER_DOMAIN_TRANSCODER_B) | \
269 BIT(POWER_DOMAIN_PIPE_C) | \
270 BIT(POWER_DOMAIN_TRANSCODER_C) | \
271 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
272 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
273 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
274 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
275 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
276 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
277 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
278 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
279 BIT(POWER_DOMAIN_AUX_B) | \
280 BIT(POWER_DOMAIN_AUX_C) | \
281 BIT(POWER_DOMAIN_AUX_D) | \
282 BIT(POWER_DOMAIN_AUDIO) | \
283 BIT(POWER_DOMAIN_VGA) | \
284 BIT(POWER_DOMAIN_INIT))
285 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
286 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
287 BIT(POWER_DOMAIN_PLLS) | \
288 BIT(POWER_DOMAIN_PIPE_A) | \
289 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
290 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
291 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
292 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
293 BIT(POWER_DOMAIN_AUX_A) | \
294 BIT(POWER_DOMAIN_INIT))
295 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
296 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
297 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
298 BIT(POWER_DOMAIN_INIT))
299 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
300 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
301 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
302 BIT(POWER_DOMAIN_INIT))
303 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
304 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
305 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
306 BIT(POWER_DOMAIN_INIT))
307 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
308 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
309 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
310 BIT(POWER_DOMAIN_INIT))
311 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \
312 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS)
313 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
314 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
315 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
316 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
317 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
318 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
319 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \
320 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \
321 BIT(POWER_DOMAIN_INIT))
323 static void skl_set_power_well(struct drm_i915_private *dev_priv,
324 struct i915_power_well *power_well, bool enable)
326 uint32_t tmp, fuse_status;
327 uint32_t req_mask, state_mask;
328 bool is_enabled, enable_requested, check_fuse_status = false;
330 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
331 fuse_status = I915_READ(SKL_FUSE_STATUS);
333 switch (power_well->data) {
335 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
336 SKL_FUSE_PG0_DIST_STATUS), 1)) {
337 DRM_ERROR("PG0 not enabled\n");
342 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
343 DRM_ERROR("PG1 in disabled state\n");
347 case SKL_DISP_PW_DDI_A_E:
348 case SKL_DISP_PW_DDI_B:
349 case SKL_DISP_PW_DDI_C:
350 case SKL_DISP_PW_DDI_D:
351 case SKL_DISP_PW_MISC_IO:
354 WARN(1, "Unknown power well %lu\n", power_well->data);
358 req_mask = SKL_POWER_WELL_REQ(power_well->data);
359 enable_requested = tmp & req_mask;
360 state_mask = SKL_POWER_WELL_STATE(power_well->data);
361 is_enabled = tmp & state_mask;
364 if (!enable_requested) {
365 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
369 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
370 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
372 DRM_ERROR("%s enable timeout\n",
374 check_fuse_status = true;
377 if (enable_requested) {
378 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
379 POSTING_READ(HSW_PWR_WELL_DRIVER);
380 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
384 if (check_fuse_status) {
385 if (power_well->data == SKL_DISP_PW_1) {
386 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
387 SKL_FUSE_PG1_DIST_STATUS), 1))
388 DRM_ERROR("PG1 distributing status timeout\n");
389 } else if (power_well->data == SKL_DISP_PW_2) {
390 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
391 SKL_FUSE_PG2_DIST_STATUS), 1))
392 DRM_ERROR("PG2 distributing status timeout\n");
396 if (enable && !is_enabled)
397 skl_power_well_post_enable(dev_priv, power_well);
400 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
401 struct i915_power_well *power_well)
403 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
406 * We're taking over the BIOS, so clear any requests made by it since
407 * the driver is in charge now.
409 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
410 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
413 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
414 struct i915_power_well *power_well)
416 hsw_set_power_well(dev_priv, power_well, true);
419 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
420 struct i915_power_well *power_well)
422 hsw_set_power_well(dev_priv, power_well, false);
425 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
426 struct i915_power_well *power_well)
428 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
429 SKL_POWER_WELL_STATE(power_well->data);
431 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
434 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
435 struct i915_power_well *power_well)
437 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
439 /* Clear any request made by BIOS as driver is taking over */
440 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
443 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
444 struct i915_power_well *power_well)
446 skl_set_power_well(dev_priv, power_well, true);
449 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
450 struct i915_power_well *power_well)
452 skl_set_power_well(dev_priv, power_well, false);
455 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
456 struct i915_power_well *power_well)
460 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
461 struct i915_power_well *power_well)
466 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
467 struct i915_power_well *power_well, bool enable)
469 enum punit_power_well power_well_id = power_well->data;
474 mask = PUNIT_PWRGT_MASK(power_well_id);
475 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
476 PUNIT_PWRGT_PWR_GATE(power_well_id);
478 mutex_lock(&dev_priv->rps.hw_lock);
481 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
486 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
489 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
491 if (wait_for(COND, 100))
492 DRM_ERROR("timout setting power well state %08x (%08x)\n",
494 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
499 mutex_unlock(&dev_priv->rps.hw_lock);
502 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
503 struct i915_power_well *power_well)
505 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
508 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
509 struct i915_power_well *power_well)
511 vlv_set_power_well(dev_priv, power_well, true);
514 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
515 struct i915_power_well *power_well)
517 vlv_set_power_well(dev_priv, power_well, false);
520 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
521 struct i915_power_well *power_well)
523 int power_well_id = power_well->data;
524 bool enabled = false;
529 mask = PUNIT_PWRGT_MASK(power_well_id);
530 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
532 mutex_lock(&dev_priv->rps.hw_lock);
534 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
536 * We only ever set the power-on and power-gate states, anything
537 * else is unexpected.
539 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
540 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
545 * A transient state at this point would mean some unexpected party
546 * is poking at the power controls too.
548 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
549 WARN_ON(ctrl != state);
551 mutex_unlock(&dev_priv->rps.hw_lock);
556 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
557 struct i915_power_well *power_well)
559 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
561 vlv_set_power_well(dev_priv, power_well, true);
563 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
564 valleyview_enable_display_irqs(dev_priv);
565 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
568 * During driver initialization/resume we can avoid restoring the
569 * part of the HW/SW state that will be inited anyway explicitly.
571 if (dev_priv->power_domains.initializing)
574 intel_hpd_init(dev_priv);
576 i915_redisable_vga_power_on(dev_priv->dev);
579 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
580 struct i915_power_well *power_well)
582 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
584 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
585 valleyview_disable_display_irqs(dev_priv);
586 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
588 vlv_set_power_well(dev_priv, power_well, false);
590 vlv_power_sequencer_reset(dev_priv);
593 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
594 struct i915_power_well *power_well)
596 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
599 * Enable the CRI clock source so we can get at the
600 * display and the reference clock for VGA
601 * hotplug / manual detection.
603 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
604 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
605 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
607 vlv_set_power_well(dev_priv, power_well, true);
610 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
611 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
612 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
613 * b. The other bits such as sfr settings / modesel may all
616 * This should only be done on init and resume from S3 with
617 * both PLLs disabled, or we risk losing DPIO and PLL
620 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
623 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
624 struct i915_power_well *power_well)
628 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
630 for_each_pipe(dev_priv, pipe)
631 assert_pll_disabled(dev_priv, pipe);
633 /* Assert common reset */
634 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
636 vlv_set_power_well(dev_priv, power_well, false);
639 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
640 struct i915_power_well *power_well)
644 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
645 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
648 * Enable the CRI clock source so we can get at the
649 * display and the reference clock for VGA
650 * hotplug / manual detection.
652 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
654 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
655 DPLL_REFA_CLK_ENABLE_VLV);
656 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
657 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
660 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
661 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
663 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
664 vlv_set_power_well(dev_priv, power_well, true);
666 /* Poll for phypwrgood signal */
667 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
668 DRM_ERROR("Display PHY %d is not power up\n", phy);
670 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
671 PHY_COM_LANE_RESET_DEASSERT(phy));
674 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
675 struct i915_power_well *power_well)
679 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
680 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
682 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
684 assert_pll_disabled(dev_priv, PIPE_A);
685 assert_pll_disabled(dev_priv, PIPE_B);
688 assert_pll_disabled(dev_priv, PIPE_C);
691 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
692 ~PHY_COM_LANE_RESET_DEASSERT(phy));
694 vlv_set_power_well(dev_priv, power_well, false);
697 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
698 struct i915_power_well *power_well)
700 enum i915_pipe pipe = power_well->data;
704 mutex_lock(&dev_priv->rps.hw_lock);
706 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
708 * We only ever set the power-on and power-gate states, anything
709 * else is unexpected.
711 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
712 enabled = state == DP_SSS_PWR_ON(pipe);
715 * A transient state at this point would mean some unexpected party
716 * is poking at the power controls too.
718 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
719 WARN_ON(ctrl << 16 != state);
721 mutex_unlock(&dev_priv->rps.hw_lock);
726 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
727 struct i915_power_well *power_well,
730 enum i915_pipe pipe = power_well->data;
734 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
736 mutex_lock(&dev_priv->rps.hw_lock);
739 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
744 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
745 ctrl &= ~DP_SSC_MASK(pipe);
746 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
747 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
749 if (wait_for(COND, 100))
750 DRM_ERROR("timout setting power well state %08x (%08x)\n",
752 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
757 mutex_unlock(&dev_priv->rps.hw_lock);
760 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
761 struct i915_power_well *power_well)
763 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
766 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
767 struct i915_power_well *power_well)
769 WARN_ON_ONCE(power_well->data != PIPE_A &&
770 power_well->data != PIPE_B &&
771 power_well->data != PIPE_C);
773 chv_set_pipe_power_well(dev_priv, power_well, true);
775 if (power_well->data == PIPE_A) {
776 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
777 valleyview_enable_display_irqs(dev_priv);
778 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
781 * During driver initialization/resume we can avoid restoring the
782 * part of the HW/SW state that will be inited anyway explicitly.
784 if (dev_priv->power_domains.initializing)
787 intel_hpd_init(dev_priv);
789 i915_redisable_vga_power_on(dev_priv->dev);
793 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
794 struct i915_power_well *power_well)
796 WARN_ON_ONCE(power_well->data != PIPE_A &&
797 power_well->data != PIPE_B &&
798 power_well->data != PIPE_C);
800 if (power_well->data == PIPE_A) {
801 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
802 valleyview_disable_display_irqs(dev_priv);
803 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
806 chv_set_pipe_power_well(dev_priv, power_well, false);
808 if (power_well->data == PIPE_A)
809 vlv_power_sequencer_reset(dev_priv);
813 * intel_display_power_get - grab a power domain reference
814 * @dev_priv: i915 device instance
815 * @domain: power domain to reference
817 * This function grabs a power domain reference for @domain and ensures that the
818 * power domain and all its parents are powered up. Therefore users should only
819 * grab a reference to the innermost power domain they need.
821 * Any power domain reference obtained by this function must have a symmetric
822 * call to intel_display_power_put() to release the reference again.
824 void intel_display_power_get(struct drm_i915_private *dev_priv,
825 enum intel_display_power_domain domain)
827 struct i915_power_domains *power_domains;
828 struct i915_power_well *power_well;
831 intel_runtime_pm_get(dev_priv);
833 power_domains = &dev_priv->power_domains;
835 mutex_lock(&power_domains->lock);
837 for_each_power_well(i, power_well, BIT(domain), power_domains) {
838 if (!power_well->count++) {
839 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
840 power_well->ops->enable(dev_priv, power_well);
841 power_well->hw_enabled = true;
845 power_domains->domain_use_count[domain]++;
847 mutex_unlock(&power_domains->lock);
851 * intel_display_power_put - release a power domain reference
852 * @dev_priv: i915 device instance
853 * @domain: power domain to reference
855 * This function drops the power domain reference obtained by
856 * intel_display_power_get() and might power down the corresponding hardware
857 * block right away if this is the last reference.
859 void intel_display_power_put(struct drm_i915_private *dev_priv,
860 enum intel_display_power_domain domain)
862 struct i915_power_domains *power_domains;
863 struct i915_power_well *power_well;
866 power_domains = &dev_priv->power_domains;
868 mutex_lock(&power_domains->lock);
870 WARN_ON(!power_domains->domain_use_count[domain]);
871 power_domains->domain_use_count[domain]--;
873 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
874 WARN_ON(!power_well->count);
876 if (!--power_well->count && i915.disable_power_well) {
877 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
878 power_well->hw_enabled = false;
879 power_well->ops->disable(dev_priv, power_well);
883 mutex_unlock(&power_domains->lock);
885 intel_runtime_pm_put(dev_priv);
888 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
890 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
891 BIT(POWER_DOMAIN_PIPE_A) | \
892 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
893 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
894 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
895 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
896 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
897 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
898 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
899 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
900 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
901 BIT(POWER_DOMAIN_PORT_CRT) | \
902 BIT(POWER_DOMAIN_PLLS) | \
903 BIT(POWER_DOMAIN_AUX_A) | \
904 BIT(POWER_DOMAIN_AUX_B) | \
905 BIT(POWER_DOMAIN_AUX_C) | \
906 BIT(POWER_DOMAIN_AUX_D) | \
907 BIT(POWER_DOMAIN_INIT))
908 #define HSW_DISPLAY_POWER_DOMAINS ( \
909 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
910 BIT(POWER_DOMAIN_INIT))
912 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
913 HSW_ALWAYS_ON_POWER_DOMAINS | \
914 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
915 #define BDW_DISPLAY_POWER_DOMAINS ( \
916 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
917 BIT(POWER_DOMAIN_INIT))
919 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
920 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
922 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
923 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
924 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
925 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
926 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
927 BIT(POWER_DOMAIN_PORT_CRT) | \
928 BIT(POWER_DOMAIN_AUX_B) | \
929 BIT(POWER_DOMAIN_AUX_C) | \
930 BIT(POWER_DOMAIN_INIT))
932 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
933 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
934 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
935 BIT(POWER_DOMAIN_AUX_B) | \
936 BIT(POWER_DOMAIN_INIT))
938 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
939 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
940 BIT(POWER_DOMAIN_AUX_B) | \
941 BIT(POWER_DOMAIN_INIT))
943 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
944 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
945 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
946 BIT(POWER_DOMAIN_AUX_C) | \
947 BIT(POWER_DOMAIN_INIT))
949 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
950 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
951 BIT(POWER_DOMAIN_AUX_C) | \
952 BIT(POWER_DOMAIN_INIT))
954 #define CHV_PIPE_A_POWER_DOMAINS ( \
955 BIT(POWER_DOMAIN_PIPE_A) | \
956 BIT(POWER_DOMAIN_INIT))
958 #define CHV_PIPE_B_POWER_DOMAINS ( \
959 BIT(POWER_DOMAIN_PIPE_B) | \
960 BIT(POWER_DOMAIN_INIT))
962 #define CHV_PIPE_C_POWER_DOMAINS ( \
963 BIT(POWER_DOMAIN_PIPE_C) | \
964 BIT(POWER_DOMAIN_INIT))
966 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
967 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
968 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
969 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
970 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
971 BIT(POWER_DOMAIN_AUX_B) | \
972 BIT(POWER_DOMAIN_AUX_C) | \
973 BIT(POWER_DOMAIN_INIT))
975 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
976 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
977 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
978 BIT(POWER_DOMAIN_AUX_D) | \
979 BIT(POWER_DOMAIN_INIT))
981 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
982 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
983 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
984 BIT(POWER_DOMAIN_AUX_D) | \
985 BIT(POWER_DOMAIN_INIT))
987 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
988 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
989 BIT(POWER_DOMAIN_AUX_D) | \
990 BIT(POWER_DOMAIN_INIT))
992 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
993 .sync_hw = i9xx_always_on_power_well_noop,
994 .enable = i9xx_always_on_power_well_noop,
995 .disable = i9xx_always_on_power_well_noop,
996 .is_enabled = i9xx_always_on_power_well_enabled,
999 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1000 .sync_hw = chv_pipe_power_well_sync_hw,
1001 .enable = chv_pipe_power_well_enable,
1002 .disable = chv_pipe_power_well_disable,
1003 .is_enabled = chv_pipe_power_well_enabled,
1006 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1007 .sync_hw = vlv_power_well_sync_hw,
1008 .enable = chv_dpio_cmn_power_well_enable,
1009 .disable = chv_dpio_cmn_power_well_disable,
1010 .is_enabled = vlv_power_well_enabled,
1013 static struct i915_power_well i9xx_always_on_power_well[] = {
1015 .name = "always-on",
1017 .domains = POWER_DOMAIN_MASK,
1018 .ops = &i9xx_always_on_power_well_ops,
1022 static const struct i915_power_well_ops hsw_power_well_ops = {
1023 .sync_hw = hsw_power_well_sync_hw,
1024 .enable = hsw_power_well_enable,
1025 .disable = hsw_power_well_disable,
1026 .is_enabled = hsw_power_well_enabled,
1029 static const struct i915_power_well_ops skl_power_well_ops = {
1030 .sync_hw = skl_power_well_sync_hw,
1031 .enable = skl_power_well_enable,
1032 .disable = skl_power_well_disable,
1033 .is_enabled = skl_power_well_enabled,
1036 static struct i915_power_well hsw_power_wells[] = {
1038 .name = "always-on",
1040 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1041 .ops = &i9xx_always_on_power_well_ops,
1045 .domains = HSW_DISPLAY_POWER_DOMAINS,
1046 .ops = &hsw_power_well_ops,
1050 static struct i915_power_well bdw_power_wells[] = {
1052 .name = "always-on",
1054 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1055 .ops = &i9xx_always_on_power_well_ops,
1059 .domains = BDW_DISPLAY_POWER_DOMAINS,
1060 .ops = &hsw_power_well_ops,
1064 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1065 .sync_hw = vlv_power_well_sync_hw,
1066 .enable = vlv_display_power_well_enable,
1067 .disable = vlv_display_power_well_disable,
1068 .is_enabled = vlv_power_well_enabled,
1071 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1072 .sync_hw = vlv_power_well_sync_hw,
1073 .enable = vlv_dpio_cmn_power_well_enable,
1074 .disable = vlv_dpio_cmn_power_well_disable,
1075 .is_enabled = vlv_power_well_enabled,
1078 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1079 .sync_hw = vlv_power_well_sync_hw,
1080 .enable = vlv_power_well_enable,
1081 .disable = vlv_power_well_disable,
1082 .is_enabled = vlv_power_well_enabled,
1085 static struct i915_power_well vlv_power_wells[] = {
1087 .name = "always-on",
1089 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1090 .ops = &i9xx_always_on_power_well_ops,
1094 .domains = VLV_DISPLAY_POWER_DOMAINS,
1095 .data = PUNIT_POWER_WELL_DISP2D,
1096 .ops = &vlv_display_power_well_ops,
1099 .name = "dpio-tx-b-01",
1100 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1101 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1102 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1103 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1104 .ops = &vlv_dpio_power_well_ops,
1105 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1108 .name = "dpio-tx-b-23",
1109 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1110 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1111 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1112 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1113 .ops = &vlv_dpio_power_well_ops,
1114 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1117 .name = "dpio-tx-c-01",
1118 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1119 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1120 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1121 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1122 .ops = &vlv_dpio_power_well_ops,
1123 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1126 .name = "dpio-tx-c-23",
1127 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1128 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1129 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1130 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1131 .ops = &vlv_dpio_power_well_ops,
1132 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1135 .name = "dpio-common",
1136 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1137 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1138 .ops = &vlv_dpio_cmn_power_well_ops,
1142 static struct i915_power_well chv_power_wells[] = {
1144 .name = "always-on",
1146 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1147 .ops = &i9xx_always_on_power_well_ops,
1152 .domains = VLV_DISPLAY_POWER_DOMAINS,
1153 .data = PUNIT_POWER_WELL_DISP2D,
1154 .ops = &vlv_display_power_well_ops,
1160 * FIXME: pipe A power well seems to be the new disp2d well.
1161 * At least all registers seem to be housed there. Figure
1162 * out if this a a temporary situation in pre-production
1163 * hardware or a permanent state of affairs.
1165 .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS,
1167 .ops = &chv_pipe_power_well_ops,
1172 .domains = CHV_PIPE_B_POWER_DOMAINS,
1174 .ops = &chv_pipe_power_well_ops,
1178 .domains = CHV_PIPE_C_POWER_DOMAINS,
1180 .ops = &chv_pipe_power_well_ops,
1184 .name = "dpio-common-bc",
1186 * XXX: cmnreset for one PHY seems to disturb the other.
1187 * As a workaround keep both powered on at the same
1190 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
1191 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1192 .ops = &chv_dpio_cmn_power_well_ops,
1195 .name = "dpio-common-d",
1197 * XXX: cmnreset for one PHY seems to disturb the other.
1198 * As a workaround keep both powered on at the same
1201 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
1202 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1203 .ops = &chv_dpio_cmn_power_well_ops,
1207 .name = "dpio-tx-b-01",
1208 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1209 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1210 .ops = &vlv_dpio_power_well_ops,
1211 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1214 .name = "dpio-tx-b-23",
1215 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1216 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1217 .ops = &vlv_dpio_power_well_ops,
1218 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1221 .name = "dpio-tx-c-01",
1222 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1223 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1224 .ops = &vlv_dpio_power_well_ops,
1225 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1228 .name = "dpio-tx-c-23",
1229 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1230 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1231 .ops = &vlv_dpio_power_well_ops,
1232 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1235 .name = "dpio-tx-d-01",
1236 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1237 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1238 .ops = &vlv_dpio_power_well_ops,
1239 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
1242 .name = "dpio-tx-d-23",
1243 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1244 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1245 .ops = &vlv_dpio_power_well_ops,
1246 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
1251 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1252 enum punit_power_well power_well_id)
1254 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1255 struct i915_power_well *power_well;
1258 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1259 if (power_well->data == power_well_id)
1266 static struct i915_power_well skl_power_wells[] = {
1268 .name = "always-on",
1270 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1271 .ops = &i9xx_always_on_power_well_ops,
1274 .name = "power well 1",
1275 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1276 .ops = &skl_power_well_ops,
1277 .data = SKL_DISP_PW_1,
1280 .name = "MISC IO power well",
1281 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1282 .ops = &skl_power_well_ops,
1283 .data = SKL_DISP_PW_MISC_IO,
1286 .name = "power well 2",
1287 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1288 .ops = &skl_power_well_ops,
1289 .data = SKL_DISP_PW_2,
1292 .name = "DDI A/E power well",
1293 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1294 .ops = &skl_power_well_ops,
1295 .data = SKL_DISP_PW_DDI_A_E,
1298 .name = "DDI B power well",
1299 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1300 .ops = &skl_power_well_ops,
1301 .data = SKL_DISP_PW_DDI_B,
1304 .name = "DDI C power well",
1305 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1306 .ops = &skl_power_well_ops,
1307 .data = SKL_DISP_PW_DDI_C,
1310 .name = "DDI D power well",
1311 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1312 .ops = &skl_power_well_ops,
1313 .data = SKL_DISP_PW_DDI_D,
1317 #define set_power_wells(power_domains, __power_wells) ({ \
1318 (power_domains)->power_wells = (__power_wells); \
1319 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1323 * intel_power_domains_init - initializes the power domain structures
1324 * @dev_priv: i915 device instance
1326 * Initializes the power domain structures for @dev_priv depending upon the
1327 * supported platform.
1329 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1331 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1333 lockinit(&power_domains->lock, "i915pl", 0, LK_CANRECURSE);
1336 * The enabling order will be from lower to higher indexed wells,
1337 * the disabling order is reversed.
1339 if (IS_HASWELL(dev_priv->dev)) {
1340 set_power_wells(power_domains, hsw_power_wells);
1341 } else if (IS_BROADWELL(dev_priv->dev)) {
1342 set_power_wells(power_domains, bdw_power_wells);
1343 } else if (IS_SKYLAKE(dev_priv->dev)) {
1344 set_power_wells(power_domains, skl_power_wells);
1345 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1346 set_power_wells(power_domains, chv_power_wells);
1347 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1348 set_power_wells(power_domains, vlv_power_wells);
1350 set_power_wells(power_domains, i9xx_always_on_power_well);
1356 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1359 struct drm_device *dev = dev_priv->dev;
1360 struct device *device = &dev->pdev->dev;
1362 if (!HAS_RUNTIME_PM(dev))
1365 if (!intel_enable_rc6(dev))
1368 /* Make sure we're not suspended first. */
1369 pm_runtime_get_sync(device);
1370 pm_runtime_disable(device);
1375 * intel_power_domains_fini - finalizes the power domain structures
1376 * @dev_priv: i915 device instance
1378 * Finalizes the power domain structures for @dev_priv depending upon the
1379 * supported platform. This function also disables runtime pm and ensures that
1380 * the device stays powered up so that the driver can be reloaded.
1382 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1384 intel_runtime_pm_disable(dev_priv);
1386 /* The i915.ko module is still not prepared to be loaded when
1387 * the power well is not enabled, so just enable it in case
1388 * we're going to unload/reload. */
1389 intel_display_set_init_power(dev_priv, true);
1392 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1394 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1395 struct i915_power_well *power_well;
1398 mutex_lock(&power_domains->lock);
1399 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1400 power_well->ops->sync_hw(dev_priv, power_well);
1401 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1404 mutex_unlock(&power_domains->lock);
1407 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1409 struct i915_power_well *cmn =
1410 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1411 struct i915_power_well *disp2d =
1412 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1414 /* If the display might be already active skip this */
1415 if (cmn->ops->is_enabled(dev_priv, cmn) &&
1416 disp2d->ops->is_enabled(dev_priv, disp2d) &&
1417 I915_READ(DPIO_CTL) & DPIO_CMNRST)
1420 DRM_DEBUG_KMS("toggling display PHY side reset\n");
1422 /* cmnlane needs DPLL registers */
1423 disp2d->ops->enable(dev_priv, disp2d);
1426 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1427 * Need to assert and de-assert PHY SB reset by gating the
1428 * common lane power, then un-gating it.
1429 * Simply ungating isn't enough to reset the PHY enough to get
1430 * ports and lanes running.
1432 cmn->ops->disable(dev_priv, cmn);
1436 * intel_power_domains_init_hw - initialize hardware power domain state
1437 * @dev_priv: i915 device instance
1439 * This function initializes the hardware power domain state and enables all
1440 * power domains using intel_display_set_init_power().
1442 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1444 struct drm_device *dev = dev_priv->dev;
1445 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1447 power_domains->initializing = true;
1449 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
1450 mutex_lock(&power_domains->lock);
1451 vlv_cmnlane_wa(dev_priv);
1452 mutex_unlock(&power_domains->lock);
1455 /* For now, we need the power well to be always enabled. */
1456 intel_display_set_init_power(dev_priv, true);
1457 intel_power_domains_resume(dev_priv);
1458 power_domains->initializing = false;
1462 * intel_aux_display_runtime_get - grab an auxiliary power domain reference
1463 * @dev_priv: i915 device instance
1465 * This function grabs a power domain reference for the auxiliary power domain
1466 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
1467 * parents are powered up. Therefore users should only grab a reference to the
1468 * innermost power domain they need.
1470 * Any power domain reference obtained by this function must have a symmetric
1471 * call to intel_aux_display_runtime_put() to release the reference again.
1473 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
1475 intel_runtime_pm_get(dev_priv);
1479 * intel_aux_display_runtime_put - release an auxiliary power domain reference
1480 * @dev_priv: i915 device instance
1482 * This function drops the auxiliary power domain reference obtained by
1483 * intel_aux_display_runtime_get() and might power down the corresponding
1484 * hardware block right away if this is the last reference.
1486 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
1488 intel_runtime_pm_put(dev_priv);
1492 * intel_runtime_pm_get - grab a runtime pm reference
1493 * @dev_priv: i915 device instance
1495 * This function grabs a device-level runtime pm reference (mostly used for GEM
1496 * code to ensure the GTT or GT is on) and ensures that it is powered up.
1498 * Any runtime pm reference obtained by this function must have a symmetric
1499 * call to intel_runtime_pm_put() to release the reference again.
1501 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
1503 struct drm_device *dev = dev_priv->dev;
1505 struct device *device = &dev->pdev->dev;
1508 if (!HAS_RUNTIME_PM(dev))
1512 pm_runtime_get_sync(device);
1514 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
1518 * intel_runtime_pm_get_noresume - grab a runtime pm reference
1519 * @dev_priv: i915 device instance
1521 * This function grabs a device-level runtime pm reference (mostly used for GEM
1522 * code to ensure the GTT or GT is on).
1524 * It will _not_ power up the device but instead only check that it's powered
1525 * on. Therefore it is only valid to call this functions from contexts where
1526 * the device is known to be powered up and where trying to power it up would
1527 * result in hilarity and deadlocks. That pretty much means only the system
1528 * suspend/resume code where this is used to grab runtime pm references for
1529 * delayed setup down in work items.
1531 * Any runtime pm reference obtained by this function must have a symmetric
1532 * call to intel_runtime_pm_put() to release the reference again.
1534 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
1536 struct drm_device *dev = dev_priv->dev;
1538 struct device *device = &dev->pdev->dev;
1541 if (!HAS_RUNTIME_PM(dev))
1544 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
1546 pm_runtime_get_noresume(device);
1551 * intel_runtime_pm_put - release a runtime pm reference
1552 * @dev_priv: i915 device instance
1554 * This function drops the device-level runtime pm reference obtained by
1555 * intel_runtime_pm_get() and might power down the corresponding
1556 * hardware block right away if this is the last reference.
1558 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
1561 struct drm_device *dev = dev_priv->dev;
1562 struct device *device = &dev->pdev->dev;
1564 if (!HAS_RUNTIME_PM(dev))
1567 pm_runtime_mark_last_busy(device);
1568 pm_runtime_put_autosuspend(device);
1573 * intel_runtime_pm_enable - enable runtime pm
1574 * @dev_priv: i915 device instance
1576 * This function enables runtime pm at the end of the driver load sequence.
1578 * Note that this function does currently not enable runtime pm for the
1579 * subordinate display power domains. That is only done on the first modeset
1580 * using intel_display_set_init_power().
1582 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
1584 struct drm_device *dev = dev_priv->dev;
1586 struct device *device = &dev->pdev->dev;
1589 if (!HAS_RUNTIME_PM(dev))
1593 pm_runtime_set_active(device);
1597 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
1600 if (!intel_enable_rc6(dev)) {
1601 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
1606 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
1607 pm_runtime_mark_last_busy(device);
1608 pm_runtime_use_autosuspend(device);
1610 pm_runtime_put_autosuspend(device);