2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <sys/thread2.h>
35 #include <machine/pmap.h>
36 #include <machine_base/icu/icu_var.h>
37 #include <machine_base/apic/lapic.h>
38 #include <machine_base/apic/ioapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
41 #define IOAPIC_COUNT_MAX 16
42 #define IOAPIC_ID_MASK (IOAPIC_COUNT_MAX - 1)
51 TAILQ_ENTRY(ioapic_info) io_link;
53 TAILQ_HEAD(ioapic_info_list, ioapic_info);
55 struct ioapic_intsrc {
57 enum intr_trigger int_trig;
58 enum intr_polarity int_pola;
62 struct ioapic_info_list ioc_list;
63 struct ioapic_intsrc ioc_intsrc[16]; /* XXX magic number */
66 static void ioapic_setup(const struct ioapic_info *);
67 static int ioapic_alloc_apic_id(int);
68 static void ioapic_set_apic_id(const struct ioapic_info *);
69 static void ioapic_gsi_setup(int);
70 static const struct ioapic_info *
71 ioapic_gsi_search(int);
72 static void ioapic_pin_prog(void *, int, int,
73 enum intr_trigger, enum intr_polarity, uint32_t);
75 static struct ioapic_conf ioapic_conf;
77 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
78 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
80 int ioapic_enable = 1; /* I/O APIC is enabled by default */
85 struct ioapic_enumerator *e;
86 struct ioapic_info *info;
87 int start_apic_id = 0;
91 TAILQ_INIT(&ioapic_conf.ioc_list);
92 /* XXX magic number */
93 for (i = 0; i < 16; ++i)
94 ioapic_conf.ioc_intsrc[i].int_gsi = -1;
97 TUNABLE_INT_FETCH("hw.ioapic_probe", &probe);
99 kprintf("IOAPIC: warning I/O APIC will not be probed\n");
103 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
104 error = e->ioapic_probe(e);
109 kprintf("IOAPIC: can't find I/O APIC\n");
119 * Switch to I/O APIC MachIntrABI and reconfigure
120 * the default IDT entries.
122 MachIntrABI = MachIntrABI_IOAPIC;
123 MachIntrABI.setdefault();
125 e->ioapic_enumerate(e);
131 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
134 if (i > IOAPIC_COUNT_MAX) /* XXX magic number */
135 panic("ioapic_config: more than 16 I/O APIC\n");
140 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
143 apic_id = ioapic_alloc_apic_id(start_apic_id);
144 if (apic_id == NAPICID) {
145 kprintf("IOAPIC: can't alloc APIC ID for "
146 "%dth I/O APIC\n", info->io_idx);
149 info->io_apic_id = apic_id;
151 start_apic_id = apic_id + 1;
155 * xAPIC allows I/O APIC's APIC ID to be same
156 * as the LAPIC's APIC ID
158 kprintf("IOAPIC: use xAPIC model to alloc APIC ID "
161 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
162 info->io_apic_id = info->io_idx;
166 * Warning about any GSI holes
168 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
169 const struct ioapic_info *prev_info;
171 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
172 if (prev_info != NULL) {
173 if (info->io_gsi_base !=
174 prev_info->io_gsi_base + prev_info->io_npin) {
175 kprintf("IOAPIC: warning gsi hole "
177 prev_info->io_gsi_base +
179 info->io_gsi_base - 1);
185 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
186 kprintf("IOAPIC: idx %d, apic id %d, "
187 "gsi base %d, npin %d\n",
198 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
200 ioapic_abi_fixup_irqmap();
204 MachIntrABI.cleanup();
212 ioapic_enumerator_register(struct ioapic_enumerator *ne)
214 struct ioapic_enumerator *e;
216 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
217 if (e->ioapic_prio < ne->ioapic_prio) {
218 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
222 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
226 ioapic_add(void *addr, int gsi_base, int npin)
228 struct ioapic_info *info, *ninfo;
231 gsi_end = gsi_base + npin - 1;
232 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
233 if ((gsi_base >= info->io_gsi_base &&
234 gsi_base < info->io_gsi_base + info->io_npin) ||
235 (gsi_end >= info->io_gsi_base &&
236 gsi_end < info->io_gsi_base + info->io_npin)) {
237 panic("ioapic_add: overlapped gsi, base %d npin %d, "
238 "hit base %d, npin %d\n", gsi_base, npin,
239 info->io_gsi_base, info->io_npin);
241 if (info->io_addr == addr)
242 panic("ioapic_add: duplicated addr %p\n", addr);
245 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
246 ninfo->io_addr = addr;
247 ninfo->io_npin = npin;
248 ninfo->io_gsi_base = gsi_base;
249 ninfo->io_apic_id = -1;
252 * Create IOAPIC list in ascending order of GSI base
254 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
255 ioapic_info_list, io_link) {
256 if (ninfo->io_gsi_base > info->io_gsi_base) {
257 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
258 info, ninfo, io_link);
263 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
267 ioapic_intsrc(int irq, int gsi, enum intr_trigger trig, enum intr_polarity pola)
269 struct ioapic_intsrc *int_src;
272 int_src = &ioapic_conf.ioc_intsrc[irq];
275 /* Don't allow mixed mode */
276 kprintf("IOAPIC: warning intsrc irq %d -> gsi 0\n", irq);
280 if (int_src->int_gsi != -1) {
281 if (int_src->int_gsi != gsi) {
282 kprintf("IOAPIC: warning intsrc irq %d, gsi "
283 "%d -> %d\n", irq, int_src->int_gsi, gsi);
285 if (int_src->int_trig != trig) {
286 kprintf("IOAPIC: warning intsrc irq %d, trig "
288 intr_str_trigger(int_src->int_trig),
289 intr_str_trigger(trig));
291 if (int_src->int_pola != pola) {
292 kprintf("IOAPIC: warning intsrc irq %d, pola "
294 intr_str_polarity(int_src->int_pola),
295 intr_str_polarity(pola));
298 int_src->int_gsi = gsi;
299 int_src->int_trig = trig;
300 int_src->int_pola = pola;
304 ioapic_set_apic_id(const struct ioapic_info *info)
309 id = ioapic_read(info->io_addr, IOAPIC_ID);
312 id |= (info->io_apic_id << 24);
314 ioapic_write(info->io_addr, IOAPIC_ID, id);
319 id = ioapic_read(info->io_addr, IOAPIC_ID);
320 apic_id = (id & APIC_ID_MASK) >> 24;
323 * I/O APIC ID is a 4bits field
325 if ((apic_id & IOAPIC_ID_MASK) !=
326 (info->io_apic_id & IOAPIC_ID_MASK)) {
327 panic("ioapic_set_apic_id: can't set apic id to %d, "
328 "currently set to %d\n", info->io_apic_id, apic_id);
333 ioapic_gsi_setup(int gsi)
335 enum intr_trigger trig;
336 enum intr_polarity pola;
342 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
343 ioapic_gsi_pin(gsi), 0);
348 for (irq = 0; irq < 16; ++irq) {
349 const struct ioapic_intsrc *int_src =
350 &ioapic_conf.ioc_intsrc[irq];
352 if (gsi == int_src->int_gsi) {
353 trig = int_src->int_trig;
354 pola = int_src->int_pola;
361 trig = INTR_TRIGGER_EDGE;
362 pola = INTR_POLARITY_HIGH;
364 trig = INTR_TRIGGER_LEVEL;
365 pola = INTR_POLARITY_LOW;
370 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
374 ioapic_gsi_ioaddr(int gsi)
376 const struct ioapic_info *info;
378 info = ioapic_gsi_search(gsi);
379 return info->io_addr;
383 ioapic_gsi_pin(int gsi)
385 const struct ioapic_info *info;
387 info = ioapic_gsi_search(gsi);
388 return gsi - info->io_gsi_base;
391 static const struct ioapic_info *
392 ioapic_gsi_search(int gsi)
394 const struct ioapic_info *info;
396 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
397 if (gsi >= info->io_gsi_base &&
398 gsi < info->io_gsi_base + info->io_npin)
401 panic("ioapic_gsi_search: no I/O APIC\n");
405 ioapic_gsi(int idx, int pin)
407 const struct ioapic_info *info;
409 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
410 if (info->io_idx == idx)
415 if (pin >= info->io_npin)
417 return info->io_gsi_base + pin;
421 ioapic_extpin_setup(void *addr, int pin, int vec)
423 ioapic_pin_prog(addr, pin, vec,
424 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
428 ioapic_extpin_gsi(void)
434 ioapic_pin_setup(void *addr, int pin, int vec,
435 enum intr_trigger trig, enum intr_polarity pola)
438 * Always clear an I/O APIC pin before [re]programming it. This is
439 * particularly important if the pin is set up for a level interrupt
440 * as the IOART_REM_IRR bit might be set. When we reprogram the
441 * vector any EOI from pending ints on this pin could be lost and
442 * IRR might never get reset.
444 * To fix this problem, clear the vector and make sure it is
445 * programmed as an edge interrupt. This should theoretically
446 * clear IRR so we can later, safely program it as a level
449 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
451 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
455 ioapic_pin_prog(void *addr, int pin, int vec,
456 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
458 uint32_t flags, target;
461 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
463 select = IOAPIC_REDTBL0 + (2 * pin);
465 flags = ioapic_read(addr, select) & IOART_RESV;
466 flags |= IOART_INTMSET | IOART_DESTPHY;
471 * We only support limited I/O APIC mixed mode,
472 * so even for ExtINT, we still use "fixed"
475 flags |= IOART_DELFIXED;
478 if (del_mode == IOART_DELEXINT) {
479 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
480 pola == INTR_POLARITY_CONFORM);
481 flags |= IOART_TRGREDG | IOART_INTAHI;
484 case INTR_TRIGGER_EDGE:
485 flags |= IOART_TRGREDG;
488 case INTR_TRIGGER_LEVEL:
489 flags |= IOART_TRGRLVL;
492 case INTR_TRIGGER_CONFORM:
493 panic("ioapic_pin_prog: trig conform is not "
497 case INTR_POLARITY_HIGH:
498 flags |= IOART_INTAHI;
501 case INTR_POLARITY_LOW:
502 flags |= IOART_INTALO;
505 case INTR_POLARITY_CONFORM:
506 panic("ioapic_pin_prog: pola conform is not "
511 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
512 target |= (CPUID_TO_APICID(0) << IOART_HI_DEST_SHIFT) &
515 ioapic_write(addr, select, flags | vec);
516 ioapic_write(addr, select + 1, target);
520 ioapic_setup(const struct ioapic_info *info)
524 ioapic_set_apic_id(info);
526 for (i = 0; i < info->io_npin; ++i)
527 ioapic_gsi_setup(info->io_gsi_base + i);
531 ioapic_alloc_apic_id(int start)
534 const struct ioapic_info *info;
535 int apic_id, apic_id16;
537 apic_id = lapic_unused_apic_id(start);
538 if (apic_id == NAPICID) {
539 kprintf("IOAPIC: can't find unused APIC ID\n");
542 apic_id16 = apic_id & IOAPIC_ID_MASK;
545 * Check against other I/O APIC's APIC ID's lower 4bits.
547 * The new APIC ID will have to be different from others
548 * in the lower 4bits, no matter whether xAPIC is used
551 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
552 if (info->io_apic_id == -1) {
556 if ((info->io_apic_id & IOAPIC_ID_MASK) == apic_id16)
562 kprintf("IOAPIC: APIC ID %d has same lower 4bits as "
563 "%dth I/O APIC, keep searching...\n",
564 apic_id, info->io_idx);
568 panic("ioapic_unused_apic_id: never reached\n");
572 * Map a physical memory address representing I/O into KVA. The I/O
573 * block is assumed not to cross a page boundary.
576 ioapic_map(vm_paddr_t pa)
578 KKASSERT(pa < 0x100000000LL);
580 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
584 ioapic_sysinit(void *dummy __unused)
591 KASSERT(lapic_enable, ("I/O APIC is enabled, but LAPIC is disabled\n"));
592 error = ioapic_config();
595 icu_reinit_noioapic();
596 lapic_fixup_noioapic();
599 SYSINIT(ioapic, SI_BOOT2_IOAPIC, SI_ORDER_FIRST, ioapic_sysinit, NULL)