igb: Utilize mbuf's header length to setup TX context
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_polling.h"
33 #include "opt_igb.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/mbuf.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50
51 #include <net/bpf.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
63
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
69
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
72
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
76
77 #ifdef IGB_RSS_DEBUG
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79 do { \
80         if (sc->rss_debug >= lvl) \
81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82 } while (0)
83 #else   /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
85 #endif  /* IGB_RSS_DEBUG */
86
87 #define IGB_NAME        "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id)  \
89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
91
92 static struct igb_device {
93         uint16_t        vid;
94         uint16_t        did;
95         const char      *desc;
96 } igb_devices[] = {
97         IGB_DEVICE(82575EB_COPPER),
98         IGB_DEVICE(82575EB_FIBER_SERDES),
99         IGB_DEVICE(82575GB_QUAD_COPPER),
100         IGB_DEVICE(82576),
101         IGB_DEVICE(82576_NS),
102         IGB_DEVICE(82576_NS_SERDES),
103         IGB_DEVICE(82576_FIBER),
104         IGB_DEVICE(82576_SERDES),
105         IGB_DEVICE(82576_SERDES_QUAD),
106         IGB_DEVICE(82576_QUAD_COPPER),
107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
108         IGB_DEVICE(82576_VF),
109         IGB_DEVICE(82580_COPPER),
110         IGB_DEVICE(82580_FIBER),
111         IGB_DEVICE(82580_SERDES),
112         IGB_DEVICE(82580_SGMII),
113         IGB_DEVICE(82580_COPPER_DUAL),
114         IGB_DEVICE(82580_QUAD_FIBER),
115         IGB_DEVICE(DH89XXCC_SERDES),
116         IGB_DEVICE(DH89XXCC_SGMII),
117         IGB_DEVICE(DH89XXCC_SFP),
118         IGB_DEVICE(DH89XXCC_BACKPLANE),
119         IGB_DEVICE(I350_COPPER),
120         IGB_DEVICE(I350_FIBER),
121         IGB_DEVICE(I350_SERDES),
122         IGB_DEVICE(I350_SGMII),
123         IGB_DEVICE(I350_VF),
124
125         /* required last entry */
126         IGB_DEVICE_NULL
127 };
128
129 static int      igb_probe(device_t);
130 static int      igb_attach(device_t);
131 static int      igb_detach(device_t);
132 static int      igb_shutdown(device_t);
133 static int      igb_suspend(device_t);
134 static int      igb_resume(device_t);
135
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void     igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static void     igb_add_sysctl(struct igb_softc *);
140 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
141 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
142 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
143 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
144
145 static void     igb_vf_init_stats(struct igb_softc *);
146 static void     igb_reset(struct igb_softc *);
147 static void     igb_update_stats_counters(struct igb_softc *);
148 static void     igb_update_vf_stats_counters(struct igb_softc *);
149 static void     igb_update_link_status(struct igb_softc *);
150 static void     igb_init_tx_unit(struct igb_softc *);
151 static void     igb_init_rx_unit(struct igb_softc *);
152
153 static void     igb_set_vlan(struct igb_softc *);
154 static void     igb_set_multi(struct igb_softc *);
155 static void     igb_set_promisc(struct igb_softc *);
156 static void     igb_disable_promisc(struct igb_softc *);
157
158 static int      igb_alloc_rings(struct igb_softc *);
159 static void     igb_free_rings(struct igb_softc *);
160 static int      igb_create_tx_ring(struct igb_tx_ring *);
161 static int      igb_create_rx_ring(struct igb_rx_ring *);
162 static void     igb_free_tx_ring(struct igb_tx_ring *);
163 static void     igb_free_rx_ring(struct igb_rx_ring *);
164 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
165 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
166 static void     igb_init_tx_ring(struct igb_tx_ring *);
167 static int      igb_init_rx_ring(struct igb_rx_ring *);
168 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
169 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
170
171 static void     igb_stop(struct igb_softc *);
172 static void     igb_init(void *);
173 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
174 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
175 static int      igb_media_change(struct ifnet *);
176 static void     igb_timer(void *);
177 static void     igb_watchdog(struct ifnet *);
178 static void     igb_start(struct ifnet *);
179 #ifdef DEVICE_POLLING
180 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
181 #endif
182 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
183 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
184 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
185 #ifdef INVARIANTS
186 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
187                     boolean_t);
188 #endif
189
190 static void     igb_intr(void *);
191 static void     igb_intr_shared(void *);
192 static void     igb_rxeof(struct igb_rx_ring *, int);
193 static void     igb_txeof(struct igb_tx_ring *);
194 static void     igb_set_eitr(struct igb_softc *, int, int);
195 static void     igb_enable_intr(struct igb_softc *);
196 static void     igb_disable_intr(struct igb_softc *);
197 static void     igb_init_unshared_intr(struct igb_softc *);
198 static void     igb_init_intr(struct igb_softc *);
199 static int      igb_setup_intr(struct igb_softc *);
200 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
201 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
202 static void     igb_set_intr_mask(struct igb_softc *);
203 static int      igb_alloc_intr(struct igb_softc *);
204 static void     igb_free_intr(struct igb_softc *);
205 static void     igb_teardown_intr(struct igb_softc *);
206 static void     igb_msix_try_alloc(struct igb_softc *);
207 static void     igb_msix_free(struct igb_softc *, boolean_t);
208 static int      igb_msix_setup(struct igb_softc *);
209 static void     igb_msix_teardown(struct igb_softc *, int);
210 static void     igb_msix_rx(void *);
211 static void     igb_msix_tx(void *);
212 static void     igb_msix_status(void *);
213
214 /* Management and WOL Support */
215 static void     igb_get_mgmt(struct igb_softc *);
216 static void     igb_rel_mgmt(struct igb_softc *);
217 static void     igb_get_hw_control(struct igb_softc *);
218 static void     igb_rel_hw_control(struct igb_softc *);
219 static void     igb_enable_wol(device_t);
220
221 static device_method_t igb_methods[] = {
222         /* Device interface */
223         DEVMETHOD(device_probe,         igb_probe),
224         DEVMETHOD(device_attach,        igb_attach),
225         DEVMETHOD(device_detach,        igb_detach),
226         DEVMETHOD(device_shutdown,      igb_shutdown),
227         DEVMETHOD(device_suspend,       igb_suspend),
228         DEVMETHOD(device_resume,        igb_resume),
229         { 0, 0 }
230 };
231
232 static driver_t igb_driver = {
233         "igb",
234         igb_methods,
235         sizeof(struct igb_softc),
236 };
237
238 static devclass_t igb_devclass;
239
240 DECLARE_DUMMY_MODULE(if_igb);
241 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
242 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
243
244 static int      igb_rxd = IGB_DEFAULT_RXD;
245 static int      igb_txd = IGB_DEFAULT_TXD;
246 static int      igb_rxr = 0;
247 static int      igb_msi_enable = 1;
248 static int      igb_msix_enable = 1;
249 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
250 static int      igb_fc_setting = e1000_fc_full;
251
252 /*
253  * DMA Coalescing, only for i350 - default to off,
254  * this feature is for power savings
255  */
256 static int      igb_dma_coalesce = 0;
257
258 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
259 TUNABLE_INT("hw.igb.txd", &igb_txd);
260 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
261 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
262 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
263 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
264
265 /* i350 specific */
266 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
267 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
268
269 static __inline void
270 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
271 {
272         /* Ignore Checksum bit is set */
273         if (staterr & E1000_RXD_STAT_IXSM)
274                 return;
275
276         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
277             E1000_RXD_STAT_IPCS)
278                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
279
280         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
281                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
282                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
283                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
284                         mp->m_pkthdr.csum_data = htons(0xffff);
285                 }
286         }
287 }
288
289 static __inline struct pktinfo *
290 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
291     uint32_t hash, uint32_t hashtype, uint32_t staterr)
292 {
293         switch (hashtype) {
294         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
295                 pi->pi_netisr = NETISR_IP;
296                 pi->pi_flags = 0;
297                 pi->pi_l3proto = IPPROTO_TCP;
298                 break;
299
300         case E1000_RXDADV_RSSTYPE_IPV4:
301                 if (staterr & E1000_RXD_STAT_IXSM)
302                         return NULL;
303
304                 if ((staterr &
305                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
306                     E1000_RXD_STAT_TCPCS) {
307                         pi->pi_netisr = NETISR_IP;
308                         pi->pi_flags = 0;
309                         pi->pi_l3proto = IPPROTO_UDP;
310                         break;
311                 }
312                 /* FALL THROUGH */
313         default:
314                 return NULL;
315         }
316
317         m->m_flags |= M_HASH;
318         m->m_pkthdr.hash = toeplitz_hash(hash);
319         return pi;
320 }
321
322 static int
323 igb_probe(device_t dev)
324 {
325         const struct igb_device *d;
326         uint16_t vid, did;
327
328         vid = pci_get_vendor(dev);
329         did = pci_get_device(dev);
330
331         for (d = igb_devices; d->desc != NULL; ++d) {
332                 if (vid == d->vid && did == d->did) {
333                         device_set_desc(dev, d->desc);
334                         return 0;
335                 }
336         }
337         return ENXIO;
338 }
339
340 static int
341 igb_attach(device_t dev)
342 {
343         struct igb_softc *sc = device_get_softc(dev);
344         uint16_t eeprom_data;
345         int error = 0, i, j, ring_max;
346
347 #ifdef notyet
348         /* SYSCTL stuff */
349         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
350             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
351             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
352             igb_sysctl_nvm_info, "I", "NVM Information");
353
354         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
355             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
356             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
357             &igb_enable_aim, 1, "Interrupt Moderation");
358
359         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
360             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
361             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
362             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
363 #endif
364
365         callout_init_mp(&sc->timer);
366         lwkt_serialize_init(&sc->main_serialize);
367
368         sc->dev = sc->osdep.dev = dev;
369
370         /*
371          * Determine hardware and mac type
372          */
373         sc->hw.vendor_id = pci_get_vendor(dev);
374         sc->hw.device_id = pci_get_device(dev);
375         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
376         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
377         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
378
379         if (e1000_set_mac_type(&sc->hw))
380                 return ENXIO;
381
382         /* Are we a VF device? */
383         if (sc->hw.mac.type == e1000_vfadapt ||
384             sc->hw.mac.type == e1000_vfadapt_i350)
385                 sc->vf_ifp = 1;
386         else
387                 sc->vf_ifp = 0;
388
389         /*
390          * Configure total supported RX/TX ring count
391          */
392         switch (sc->hw.mac.type) {
393         case e1000_82575:
394                 ring_max = IGB_MAX_RING_82575;
395                 break;
396         case e1000_82580:
397                 ring_max = IGB_MAX_RING_82580;
398                 break;
399         case e1000_i350:
400                 ring_max = IGB_MAX_RING_I350;
401                 break;
402         case e1000_82576:
403                 ring_max = IGB_MAX_RING_82576;
404                 break;
405         default:
406                 ring_max = IGB_MIN_RING;
407                 break;
408         }
409         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
410         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
411 #ifdef IGB_RSS_DEBUG
412         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
413 #endif
414         sc->rx_ring_inuse = sc->rx_ring_cnt;
415         sc->tx_ring_cnt = 1; /* XXX */
416
417         /* Enable bus mastering */
418         pci_enable_busmaster(dev);
419
420         /*
421          * Allocate IO memory
422          */
423         sc->mem_rid = PCIR_BAR(0);
424         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
425             RF_ACTIVE);
426         if (sc->mem_res == NULL) {
427                 device_printf(dev, "Unable to allocate bus resource: memory\n");
428                 error = ENXIO;
429                 goto failed;
430         }
431         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
432         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
433
434         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
435
436         /* Save PCI command register for Shared Code */
437         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
438         sc->hw.back = &sc->osdep;
439
440         /* Do Shared Code initialization */
441         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
442                 device_printf(dev, "Setup of Shared code failed\n");
443                 error = ENXIO;
444                 goto failed;
445         }
446
447         e1000_get_bus_info(&sc->hw);
448
449         sc->hw.mac.autoneg = DO_AUTO_NEG;
450         sc->hw.phy.autoneg_wait_to_complete = FALSE;
451         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
452
453         /* Copper options */
454         if (sc->hw.phy.media_type == e1000_media_type_copper) {
455                 sc->hw.phy.mdix = AUTO_ALL_MODES;
456                 sc->hw.phy.disable_polarity_correction = FALSE;
457                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
458         }
459
460         /* Set the frame limits assuming  standard ethernet sized frames. */
461         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
462
463         /* Allocate RX/TX rings */
464         error = igb_alloc_rings(sc);
465         if (error)
466                 goto failed;
467
468         /* Allocate interrupt */
469         error = igb_alloc_intr(sc);
470         if (error)
471                 goto failed;
472
473         /*
474          * Setup serializers
475          */
476         i = 0;
477         sc->serializes[i++] = &sc->main_serialize;
478
479         sc->tx_serialize = i;
480         for (j = 0; j < sc->tx_ring_cnt; ++j)
481                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
482
483         sc->rx_serialize = i;
484         for (j = 0; j < sc->rx_ring_cnt; ++j)
485                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
486
487         sc->serialize_cnt = i;
488         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
489
490         /* Allocate the appropriate stats memory */
491         if (sc->vf_ifp) {
492                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
493                     M_WAITOK | M_ZERO);
494                 igb_vf_init_stats(sc);
495         } else {
496                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
497                     M_WAITOK | M_ZERO);
498         }
499
500         /* Allocate multicast array memory. */
501         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
502             M_DEVBUF, M_WAITOK);
503
504         /* Some adapter-specific advanced features */
505         if (sc->hw.mac.type >= e1000_i350) {
506 #ifdef notyet
507                 igb_set_sysctl_value(adapter, "dma_coalesce",
508                     "configure dma coalesce",
509                     &adapter->dma_coalesce, igb_dma_coalesce);
510                 igb_set_sysctl_value(adapter, "eee_disabled",
511                     "enable Energy Efficient Ethernet",
512                     &adapter->hw.dev_spec._82575.eee_disable,
513                     igb_eee_disabled);
514 #else
515                 sc->dma_coalesce = igb_dma_coalesce;
516                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
517 #endif
518                 e1000_set_eee_i350(&sc->hw);
519         }
520
521         /*
522          * Start from a known state, this is important in reading the nvm and
523          * mac from that.
524          */
525         e1000_reset_hw(&sc->hw);
526
527         /* Make sure we have a good EEPROM before we read from it */
528         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
529                 /*
530                  * Some PCI-E parts fail the first check due to
531                  * the link being in sleep state, call it again,
532                  * if it fails a second time its a real issue.
533                  */
534                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
535                         device_printf(dev,
536                             "The EEPROM Checksum Is Not Valid\n");
537                         error = EIO;
538                         goto failed;
539                 }
540         }
541
542         /* Copy the permanent MAC address out of the EEPROM */
543         if (e1000_read_mac_addr(&sc->hw) < 0) {
544                 device_printf(dev, "EEPROM read error while reading MAC"
545                     " address\n");
546                 error = EIO;
547                 goto failed;
548         }
549         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
550                 device_printf(dev, "Invalid MAC address\n");
551                 error = EIO;
552                 goto failed;
553         }
554
555 #ifdef notyet
556         /* 
557         ** Configure Interrupts
558         */
559         if ((adapter->msix > 1) && (igb_enable_msix))
560                 error = igb_allocate_msix(adapter);
561         else /* MSI or Legacy */
562                 error = igb_allocate_legacy(adapter);
563         if (error)
564                 goto err_late;
565 #endif
566
567         /* Setup OS specific network interface */
568         igb_setup_ifp(sc);
569
570         /* Add sysctl tree, must after igb_setup_ifp() */
571         igb_add_sysctl(sc);
572
573         /* Now get a good starting state */
574         igb_reset(sc);
575
576         /* Initialize statistics */
577         igb_update_stats_counters(sc);
578
579         sc->hw.mac.get_link_status = 1;
580         igb_update_link_status(sc);
581
582         /* Indicate SOL/IDER usage */
583         if (e1000_check_reset_block(&sc->hw)) {
584                 device_printf(dev,
585                     "PHY reset is blocked due to SOL/IDER session.\n");
586         }
587
588         /* Determine if we have to control management hardware */
589         if (e1000_enable_mng_pass_thru(&sc->hw))
590                 sc->flags |= IGB_FLAG_HAS_MGMT;
591
592         /*
593          * Setup Wake-on-Lan
594          */
595         /* APME bit in EEPROM is mapped to WUC.APME */
596         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
597         if (eeprom_data)
598                 sc->wol = E1000_WUFC_MAG;
599         /* XXX disable WOL */
600         sc->wol = 0; 
601
602 #ifdef notyet
603         /* Register for VLAN events */
604         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
605              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
606         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
607              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
608 #endif
609
610 #ifdef notyet
611         igb_add_hw_stats(adapter);
612 #endif
613
614         error = igb_setup_intr(sc);
615         if (error) {
616                 ether_ifdetach(&sc->arpcom.ac_if);
617                 goto failed;
618         }
619         return 0;
620
621 failed:
622         igb_detach(dev);
623         return error;
624 }
625
626 static int
627 igb_detach(device_t dev)
628 {
629         struct igb_softc *sc = device_get_softc(dev);
630
631         if (device_is_attached(dev)) {
632                 struct ifnet *ifp = &sc->arpcom.ac_if;
633
634                 ifnet_serialize_all(ifp);
635
636                 igb_stop(sc);
637
638                 e1000_phy_hw_reset(&sc->hw);
639
640                 /* Give control back to firmware */
641                 igb_rel_mgmt(sc);
642                 igb_rel_hw_control(sc);
643
644                 if (sc->wol) {
645                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
646                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
647                         igb_enable_wol(dev);
648                 }
649
650                 igb_teardown_intr(sc);
651
652                 ifnet_deserialize_all(ifp);
653
654                 ether_ifdetach(ifp);
655         } else if (sc->mem_res != NULL) {
656                 igb_rel_hw_control(sc);
657         }
658         bus_generic_detach(dev);
659
660         if (sc->sysctl_tree != NULL)
661                 sysctl_ctx_free(&sc->sysctl_ctx);
662
663         igb_free_intr(sc);
664
665         if (sc->msix_mem_res != NULL) {
666                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
667                     sc->msix_mem_res);
668         }
669         if (sc->mem_res != NULL) {
670                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
671                     sc->mem_res);
672         }
673
674         igb_free_rings(sc);
675
676         if (sc->mta != NULL)
677                 kfree(sc->mta, M_DEVBUF);
678         if (sc->stats != NULL)
679                 kfree(sc->stats, M_DEVBUF);
680
681         return 0;
682 }
683
684 static int
685 igb_shutdown(device_t dev)
686 {
687         return igb_suspend(dev);
688 }
689
690 static int
691 igb_suspend(device_t dev)
692 {
693         struct igb_softc *sc = device_get_softc(dev);
694         struct ifnet *ifp = &sc->arpcom.ac_if;
695
696         ifnet_serialize_all(ifp);
697
698         igb_stop(sc);
699
700         igb_rel_mgmt(sc);
701         igb_rel_hw_control(sc);
702
703         if (sc->wol) {
704                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
705                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
706                 igb_enable_wol(dev);
707         }
708
709         ifnet_deserialize_all(ifp);
710
711         return bus_generic_suspend(dev);
712 }
713
714 static int
715 igb_resume(device_t dev)
716 {
717         struct igb_softc *sc = device_get_softc(dev);
718         struct ifnet *ifp = &sc->arpcom.ac_if;
719
720         ifnet_serialize_all(ifp);
721
722         igb_init(sc);
723         igb_get_mgmt(sc);
724
725         if_devstart(ifp);
726
727         ifnet_deserialize_all(ifp);
728
729         return bus_generic_resume(dev);
730 }
731
732 static int
733 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
734 {
735         struct igb_softc *sc = ifp->if_softc;
736         struct ifreq *ifr = (struct ifreq *)data;
737         int max_frame_size, mask, reinit;
738         int error = 0;
739
740         ASSERT_IFNET_SERIALIZED_ALL(ifp);
741
742         switch (command) {
743         case SIOCSIFMTU:
744                 max_frame_size = 9234;
745                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
746                     ETHER_CRC_LEN) {
747                         error = EINVAL;
748                         break;
749                 }
750
751                 ifp->if_mtu = ifr->ifr_mtu;
752                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
753                     ETHER_CRC_LEN;
754
755                 if (ifp->if_flags & IFF_RUNNING)
756                         igb_init(sc);
757                 break;
758
759         case SIOCSIFFLAGS:
760                 if (ifp->if_flags & IFF_UP) {
761                         if (ifp->if_flags & IFF_RUNNING) {
762                                 if ((ifp->if_flags ^ sc->if_flags) &
763                                     (IFF_PROMISC | IFF_ALLMULTI)) {
764                                         igb_disable_promisc(sc);
765                                         igb_set_promisc(sc);
766                                 }
767                         } else {
768                                 igb_init(sc);
769                         }
770                 } else if (ifp->if_flags & IFF_RUNNING) {
771                         igb_stop(sc);
772                 }
773                 sc->if_flags = ifp->if_flags;
774                 break;
775
776         case SIOCADDMULTI:
777         case SIOCDELMULTI:
778                 if (ifp->if_flags & IFF_RUNNING) {
779                         igb_disable_intr(sc);
780                         igb_set_multi(sc);
781 #ifdef DEVICE_POLLING
782                         if (!(ifp->if_flags & IFF_POLLING))
783 #endif
784                                 igb_enable_intr(sc);
785                 }
786                 break;
787
788         case SIOCSIFMEDIA:
789                 /*
790                  * As the speed/duplex settings are being
791                  * changed, we need toreset the PHY.
792                  */
793                 sc->hw.phy.reset_disable = FALSE;
794
795                 /* Check SOL/IDER usage */
796                 if (e1000_check_reset_block(&sc->hw)) {
797                         if_printf(ifp, "Media change is "
798                             "blocked due to SOL/IDER session.\n");
799                         break;
800                 }
801                 /* FALL THROUGH */
802
803         case SIOCGIFMEDIA:
804                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
805                 break;
806
807         case SIOCSIFCAP:
808                 reinit = 0;
809                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
810                 if (mask & IFCAP_HWCSUM) {
811                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
812                         reinit = 1;
813                 }
814                 if (mask & IFCAP_VLAN_HWTAGGING) {
815                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
816                         reinit = 1;
817                 }
818                 if (mask & IFCAP_RSS)
819                         ifp->if_capenable ^= IFCAP_RSS;
820                 if (reinit && (ifp->if_flags & IFF_RUNNING))
821                         igb_init(sc);
822                 break;
823
824         default:
825                 error = ether_ioctl(ifp, command, data);
826                 break;
827         }
828         return error;
829 }
830
831 static void
832 igb_init(void *xsc)
833 {
834         struct igb_softc *sc = xsc;
835         struct ifnet *ifp = &sc->arpcom.ac_if;
836         boolean_t polling;
837         int i;
838
839         ASSERT_IFNET_SERIALIZED_ALL(ifp);
840
841         igb_stop(sc);
842
843         /* Get the latest mac address, User can use a LAA */
844         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
845
846         /* Put the address into the Receive Address Array */
847         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
848
849         igb_reset(sc);
850         igb_update_link_status(sc);
851
852         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
853
854         /* Set hardware offload abilities */
855         if (ifp->if_capenable & IFCAP_TXCSUM)
856                 ifp->if_hwassist = IGB_CSUM_FEATURES;
857         else
858                 ifp->if_hwassist = 0;
859
860         /* Configure for OS presence */
861         igb_get_mgmt(sc);
862
863         polling = FALSE;
864 #ifdef DEVICE_POLLING
865         if (ifp->if_flags & IFF_POLLING)
866                 polling = TRUE;
867 #endif
868
869         /* Configured used RX/TX rings */
870         igb_set_ring_inuse(sc, polling);
871
872         /* Initialize interrupt */
873         igb_init_intr(sc);
874
875         /* Prepare transmit descriptors and buffers */
876         for (i = 0; i < sc->tx_ring_cnt; ++i)
877                 igb_init_tx_ring(&sc->tx_rings[i]);
878         igb_init_tx_unit(sc);
879
880         /* Setup Multicast table */
881         igb_set_multi(sc);
882
883 #if 0
884         /*
885          * Figure out the desired mbuf pool
886          * for doing jumbo/packetsplit
887          */
888         if (adapter->max_frame_size <= 2048)
889                 adapter->rx_mbuf_sz = MCLBYTES;
890         else if (adapter->max_frame_size <= 4096)
891                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
892         else
893                 adapter->rx_mbuf_sz = MJUM9BYTES;
894 #endif
895
896         /* Prepare receive descriptors and buffers */
897         for (i = 0; i < sc->rx_ring_inuse; ++i) {
898                 int error;
899
900                 error = igb_init_rx_ring(&sc->rx_rings[i]);
901                 if (error) {
902                         if_printf(ifp, "Could not setup receive structures\n");
903                         igb_stop(sc);
904                         return;
905                 }
906         }
907         igb_init_rx_unit(sc);
908
909         /* Enable VLAN support */
910         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
911                 igb_set_vlan(sc);
912
913         /* Don't lose promiscuous settings */
914         igb_set_promisc(sc);
915
916         ifp->if_flags |= IFF_RUNNING;
917         ifp->if_flags &= ~IFF_OACTIVE;
918
919         callout_reset(&sc->timer, hz, igb_timer, sc);
920         e1000_clear_hw_cntrs_base_generic(&sc->hw);
921
922 #if 0
923         if (adapter->msix > 1) /* Set up queue routing */
924                 igb_configure_queues(adapter);
925 #endif
926
927         /* This clears any pending interrupts */
928         E1000_READ_REG(&sc->hw, E1000_ICR);
929
930         /*
931          * Only enable interrupts if we are not polling, make sure
932          * they are off otherwise.
933          */
934         if (polling) {
935                 igb_disable_intr(sc);
936         } else {
937                 igb_enable_intr(sc);
938                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
939         }
940
941         /* Set Energy Efficient Ethernet */
942         e1000_set_eee_i350(&sc->hw);
943
944         /* Don't reset the phy next time init gets called */
945         sc->hw.phy.reset_disable = TRUE;
946 }
947
948 static void
949 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
950 {
951         struct igb_softc *sc = ifp->if_softc;
952         u_char fiber_type = IFM_1000_SX;
953
954         ASSERT_IFNET_SERIALIZED_ALL(ifp);
955
956         igb_update_link_status(sc);
957
958         ifmr->ifm_status = IFM_AVALID;
959         ifmr->ifm_active = IFM_ETHER;
960
961         if (!sc->link_active)
962                 return;
963
964         ifmr->ifm_status |= IFM_ACTIVE;
965
966         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
967             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
968                 ifmr->ifm_active |= fiber_type | IFM_FDX;
969         } else {
970                 switch (sc->link_speed) {
971                 case 10:
972                         ifmr->ifm_active |= IFM_10_T;
973                         break;
974
975                 case 100:
976                         ifmr->ifm_active |= IFM_100_TX;
977                         break;
978
979                 case 1000:
980                         ifmr->ifm_active |= IFM_1000_T;
981                         break;
982                 }
983                 if (sc->link_duplex == FULL_DUPLEX)
984                         ifmr->ifm_active |= IFM_FDX;
985                 else
986                         ifmr->ifm_active |= IFM_HDX;
987         }
988 }
989
990 static int
991 igb_media_change(struct ifnet *ifp)
992 {
993         struct igb_softc *sc = ifp->if_softc;
994         struct ifmedia *ifm = &sc->media;
995
996         ASSERT_IFNET_SERIALIZED_ALL(ifp);
997
998         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
999                 return EINVAL;
1000
1001         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1002         case IFM_AUTO:
1003                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1004                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1005                 break;
1006
1007         case IFM_1000_LX:
1008         case IFM_1000_SX:
1009         case IFM_1000_T:
1010                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1011                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1012                 break;
1013
1014         case IFM_100_TX:
1015                 sc->hw.mac.autoneg = FALSE;
1016                 sc->hw.phy.autoneg_advertised = 0;
1017                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1018                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1019                 else
1020                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1021                 break;
1022
1023         case IFM_10_T:
1024                 sc->hw.mac.autoneg = FALSE;
1025                 sc->hw.phy.autoneg_advertised = 0;
1026                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1027                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1028                 else
1029                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1030                 break;
1031
1032         default:
1033                 if_printf(ifp, "Unsupported media type\n");
1034                 break;
1035         }
1036
1037         igb_init(sc);
1038
1039         return 0;
1040 }
1041
1042 static void
1043 igb_set_promisc(struct igb_softc *sc)
1044 {
1045         struct ifnet *ifp = &sc->arpcom.ac_if;
1046         struct e1000_hw *hw = &sc->hw;
1047         uint32_t reg;
1048
1049         if (sc->vf_ifp) {
1050                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1051                 return;
1052         }
1053
1054         reg = E1000_READ_REG(hw, E1000_RCTL);
1055         if (ifp->if_flags & IFF_PROMISC) {
1056                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1057                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1058         } else if (ifp->if_flags & IFF_ALLMULTI) {
1059                 reg |= E1000_RCTL_MPE;
1060                 reg &= ~E1000_RCTL_UPE;
1061                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1062         }
1063 }
1064
1065 static void
1066 igb_disable_promisc(struct igb_softc *sc)
1067 {
1068         struct e1000_hw *hw = &sc->hw;
1069         uint32_t reg;
1070
1071         if (sc->vf_ifp) {
1072                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1073                 return;
1074         }
1075         reg = E1000_READ_REG(hw, E1000_RCTL);
1076         reg &= ~E1000_RCTL_UPE;
1077         reg &= ~E1000_RCTL_MPE;
1078         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1079 }
1080
1081 static void
1082 igb_set_multi(struct igb_softc *sc)
1083 {
1084         struct ifnet *ifp = &sc->arpcom.ac_if;
1085         struct ifmultiaddr *ifma;
1086         uint32_t reg_rctl = 0;
1087         uint8_t *mta;
1088         int mcnt = 0;
1089
1090         mta = sc->mta;
1091         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1092
1093         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1094                 if (ifma->ifma_addr->sa_family != AF_LINK)
1095                         continue;
1096
1097                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1098                         break;
1099
1100                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1101                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1102                 mcnt++;
1103         }
1104
1105         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1106                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1107                 reg_rctl |= E1000_RCTL_MPE;
1108                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1109         } else {
1110                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1111         }
1112 }
1113
1114 static void
1115 igb_timer(void *xsc)
1116 {
1117         struct igb_softc *sc = xsc;
1118
1119         lwkt_serialize_enter(&sc->main_serialize);
1120
1121         igb_update_link_status(sc);
1122         igb_update_stats_counters(sc);
1123
1124         callout_reset(&sc->timer, hz, igb_timer, sc);
1125
1126         lwkt_serialize_exit(&sc->main_serialize);
1127 }
1128
1129 static void
1130 igb_update_link_status(struct igb_softc *sc)
1131 {
1132         struct ifnet *ifp = &sc->arpcom.ac_if;
1133         struct e1000_hw *hw = &sc->hw;
1134         uint32_t link_check, thstat, ctrl;
1135
1136         link_check = thstat = ctrl = 0;
1137
1138         /* Get the cached link value or read for real */
1139         switch (hw->phy.media_type) {
1140         case e1000_media_type_copper:
1141                 if (hw->mac.get_link_status) {
1142                         /* Do the work to read phy */
1143                         e1000_check_for_link(hw);
1144                         link_check = !hw->mac.get_link_status;
1145                 } else {
1146                         link_check = TRUE;
1147                 }
1148                 break;
1149
1150         case e1000_media_type_fiber:
1151                 e1000_check_for_link(hw);
1152                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1153                 break;
1154
1155         case e1000_media_type_internal_serdes:
1156                 e1000_check_for_link(hw);
1157                 link_check = hw->mac.serdes_has_link;
1158                 break;
1159
1160         /* VF device is type_unknown */
1161         case e1000_media_type_unknown:
1162                 e1000_check_for_link(hw);
1163                 link_check = !hw->mac.get_link_status;
1164                 /* Fall thru */
1165         default:
1166                 break;
1167         }
1168
1169         /* Check for thermal downshift or shutdown */
1170         if (hw->mac.type == e1000_i350) {
1171                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1172                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1173         }
1174
1175         /* Now we check if a transition has happened */
1176         if (link_check && sc->link_active == 0) {
1177                 e1000_get_speed_and_duplex(hw, 
1178                     &sc->link_speed, &sc->link_duplex);
1179                 if (bootverbose) {
1180                         if_printf(ifp, "Link is up %d Mbps %s\n",
1181                             sc->link_speed,
1182                             sc->link_duplex == FULL_DUPLEX ?
1183                             "Full Duplex" : "Half Duplex");
1184                 }
1185                 sc->link_active = 1;
1186
1187                 ifp->if_baudrate = sc->link_speed * 1000000;
1188                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1189                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1190                         if_printf(ifp, "Link: thermal downshift\n");
1191                 /* This can sleep */
1192                 ifp->if_link_state = LINK_STATE_UP;
1193                 if_link_state_change(ifp);
1194         } else if (!link_check && sc->link_active == 1) {
1195                 ifp->if_baudrate = sc->link_speed = 0;
1196                 sc->link_duplex = 0;
1197                 if (bootverbose)
1198                         if_printf(ifp, "Link is Down\n");
1199                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1200                     (thstat & E1000_THSTAT_PWR_DOWN))
1201                         if_printf(ifp, "Link: thermal shutdown\n");
1202                 sc->link_active = 0;
1203                 /* This can sleep */
1204                 ifp->if_link_state = LINK_STATE_DOWN;
1205                 if_link_state_change(ifp);
1206         }
1207 }
1208
1209 static void
1210 igb_stop(struct igb_softc *sc)
1211 {
1212         struct ifnet *ifp = &sc->arpcom.ac_if;
1213         int i;
1214
1215         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1216
1217         igb_disable_intr(sc);
1218
1219         callout_stop(&sc->timer);
1220
1221         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1222         ifp->if_timer = 0;
1223
1224         e1000_reset_hw(&sc->hw);
1225         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1226
1227         e1000_led_off(&sc->hw);
1228         e1000_cleanup_led(&sc->hw);
1229
1230         for (i = 0; i < sc->tx_ring_cnt; ++i)
1231                 igb_free_tx_ring(&sc->tx_rings[i]);
1232         for (i = 0; i < sc->rx_ring_cnt; ++i)
1233                 igb_free_rx_ring(&sc->rx_rings[i]);
1234 }
1235
1236 static void
1237 igb_reset(struct igb_softc *sc)
1238 {
1239         struct ifnet *ifp = &sc->arpcom.ac_if;
1240         struct e1000_hw *hw = &sc->hw;
1241         struct e1000_fc_info *fc = &hw->fc;
1242         uint32_t pba = 0;
1243         uint16_t hwm;
1244
1245         /* Let the firmware know the OS is in control */
1246         igb_get_hw_control(sc);
1247
1248         /*
1249          * Packet Buffer Allocation (PBA)
1250          * Writing PBA sets the receive portion of the buffer
1251          * the remainder is used for the transmit buffer.
1252          */
1253         switch (hw->mac.type) {
1254         case e1000_82575:
1255                 pba = E1000_PBA_32K;
1256                 break;
1257
1258         case e1000_82576:
1259         case e1000_vfadapt:
1260                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1261                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1262                 break;
1263
1264         case e1000_82580:
1265         case e1000_i350:
1266         case e1000_vfadapt_i350:
1267                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1268                 pba = e1000_rxpbs_adjust_82580(pba);
1269                 break;
1270                 /* XXX pba = E1000_PBA_35K; */
1271
1272         default:
1273                 break;
1274         }
1275
1276         /* Special needs in case of Jumbo frames */
1277         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1278                 uint32_t tx_space, min_tx, min_rx;
1279
1280                 pba = E1000_READ_REG(hw, E1000_PBA);
1281                 tx_space = pba >> 16;
1282                 pba &= 0xffff;
1283
1284                 min_tx = (sc->max_frame_size +
1285                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1286                 min_tx = roundup2(min_tx, 1024);
1287                 min_tx >>= 10;
1288                 min_rx = sc->max_frame_size;
1289                 min_rx = roundup2(min_rx, 1024);
1290                 min_rx >>= 10;
1291                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1292                         pba = pba - (min_tx - tx_space);
1293                         /*
1294                          * if short on rx space, rx wins
1295                          * and must trump tx adjustment
1296                          */
1297                         if (pba < min_rx)
1298                                 pba = min_rx;
1299                 }
1300                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1301         }
1302
1303         /*
1304          * These parameters control the automatic generation (Tx) and
1305          * response (Rx) to Ethernet PAUSE frames.
1306          * - High water mark should allow for at least two frames to be
1307          *   received after sending an XOFF.
1308          * - Low water mark works best when it is very near the high water mark.
1309          *   This allows the receiver to restart by sending XON when it has
1310          *   drained a bit.
1311          */
1312         hwm = min(((pba << 10) * 9 / 10),
1313             ((pba << 10) - 2 * sc->max_frame_size));
1314
1315         if (hw->mac.type < e1000_82576) {
1316                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1317                 fc->low_water = fc->high_water - 8;
1318         } else {
1319                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1320                 fc->low_water = fc->high_water - 16;
1321         }
1322         fc->pause_time = IGB_FC_PAUSE_TIME;
1323         fc->send_xon = TRUE;
1324
1325         /* Issue a global reset */
1326         e1000_reset_hw(hw);
1327         E1000_WRITE_REG(hw, E1000_WUC, 0);
1328
1329         if (e1000_init_hw(hw) < 0)
1330                 if_printf(ifp, "Hardware Initialization Failed\n");
1331
1332         /* Setup DMA Coalescing */
1333         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1334                 uint32_t reg;
1335
1336                 hwm = (pba - 4) << 10;
1337                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1338                     & E1000_DMACR_DMACTHR_MASK;
1339
1340                 /* transition to L0x or L1 if available..*/
1341                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1342
1343                 /* timer = +-1000 usec in 32usec intervals */
1344                 reg |= (1000 >> 5);
1345                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1346
1347                 /* No lower threshold */
1348                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1349
1350                 /* set hwm to PBA -  2 * max frame size */
1351                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1352
1353                 /* Set the interval before transition */
1354                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1355                 reg |= 0x800000FF; /* 255 usec */
1356                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1357
1358                 /* free space in tx packet buffer to wake from DMA coal */
1359                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1360                     (20480 - (2 * sc->max_frame_size)) >> 6);
1361
1362                 /* make low power state decision controlled by DMA coal */
1363                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1364                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1365                     reg | E1000_PCIEMISC_LX_DECISION);
1366                 if_printf(ifp, "DMA Coalescing enabled\n");
1367         }
1368
1369         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1370         e1000_get_phy_info(hw);
1371         e1000_check_for_link(hw);
1372 }
1373
1374 static void
1375 igb_setup_ifp(struct igb_softc *sc)
1376 {
1377         struct ifnet *ifp = &sc->arpcom.ac_if;
1378
1379         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1380         ifp->if_softc = sc;
1381         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1382         ifp->if_init = igb_init;
1383         ifp->if_ioctl = igb_ioctl;
1384         ifp->if_start = igb_start;
1385         ifp->if_serialize = igb_serialize;
1386         ifp->if_deserialize = igb_deserialize;
1387         ifp->if_tryserialize = igb_tryserialize;
1388 #ifdef INVARIANTS
1389         ifp->if_serialize_assert = igb_serialize_assert;
1390 #endif
1391 #ifdef DEVICE_POLLING
1392         ifp->if_poll = igb_poll;
1393 #endif
1394         ifp->if_watchdog = igb_watchdog;
1395
1396         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1397         ifq_set_ready(&ifp->if_snd);
1398
1399         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1400
1401         ifp->if_capabilities =
1402             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1403         if (IGB_ENABLE_HWRSS(sc))
1404                 ifp->if_capabilities |= IFCAP_RSS;
1405         ifp->if_capenable = ifp->if_capabilities;
1406         ifp->if_hwassist = IGB_CSUM_FEATURES;
1407
1408         /*
1409          * Tell the upper layer(s) we support long frames
1410          */
1411         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1412
1413         /*
1414          * Specify the media types supported by this adapter and register
1415          * callbacks to update media and link information
1416          */
1417         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1418         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1419             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1420                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1421                     0, NULL);
1422                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1423         } else {
1424                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1425                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1426                     0, NULL);
1427                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1428                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1429                     0, NULL);
1430                 if (sc->hw.phy.type != e1000_phy_ife) {
1431                         ifmedia_add(&sc->media,
1432                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1433                         ifmedia_add(&sc->media,
1434                             IFM_ETHER | IFM_1000_T, 0, NULL);
1435                 }
1436         }
1437         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1438         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1439 }
1440
1441 static void
1442 igb_add_sysctl(struct igb_softc *sc)
1443 {
1444         char node[32];
1445         int i;
1446
1447         sysctl_ctx_init(&sc->sysctl_ctx);
1448         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1449             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1450             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1451         if (sc->sysctl_tree == NULL) {
1452                 device_printf(sc->dev, "can't add sysctl node\n");
1453                 return;
1454         }
1455
1456         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1457             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1458         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1459             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1460             "# of RX rings used");
1461         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1462             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1463             "# of RX descs");
1464         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1465             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1466             "# of TX descs");
1467
1468         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1469                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1470                     SYSCTL_CHILDREN(sc->sysctl_tree),
1471                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1472                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1473         } else {
1474                 for (i = 0; i < sc->msix_cnt; ++i) {
1475                         struct igb_msix_data *msix = &sc->msix_data[i];
1476
1477                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1478                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1479                             SYSCTL_CHILDREN(sc->sysctl_tree),
1480                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1481                             msix, 0, igb_sysctl_msix_rate, "I",
1482                             msix->msix_rate_desc);
1483                 }
1484         }
1485
1486         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1487             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1488             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1489             "# of segments per TX interrupt");
1490
1491 #ifdef IGB_RSS_DEBUG
1492         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1493             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1494             "RSS debug level");
1495         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1496                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1497                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1498                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1499                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1500         }
1501 #endif
1502 }
1503
1504 static int
1505 igb_alloc_rings(struct igb_softc *sc)
1506 {
1507         int error, i;
1508
1509         /*
1510          * Create top level busdma tag
1511          */
1512         error = bus_dma_tag_create(NULL, 1, 0,
1513             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1514             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1515             &sc->parent_tag);
1516         if (error) {
1517                 device_printf(sc->dev, "could not create top level DMA tag\n");
1518                 return error;
1519         }
1520
1521         /*
1522          * Allocate TX descriptor rings and buffers
1523          */
1524         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1525             M_DEVBUF, M_WAITOK | M_ZERO);
1526         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1527                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1528
1529                 /* Set up some basics */
1530                 txr->sc = sc;
1531                 txr->me = i;
1532                 lwkt_serialize_init(&txr->tx_serialize);
1533
1534                 error = igb_create_tx_ring(txr);
1535                 if (error)
1536                         return error;
1537         }
1538
1539         /*
1540          * Allocate RX descriptor rings and buffers
1541          */ 
1542         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1543             M_DEVBUF, M_WAITOK | M_ZERO);
1544         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1545                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1546
1547                 /* Set up some basics */
1548                 rxr->sc = sc;
1549                 rxr->me = i;
1550                 lwkt_serialize_init(&rxr->rx_serialize);
1551
1552                 error = igb_create_rx_ring(rxr);
1553                 if (error)
1554                         return error;
1555         }
1556
1557         return 0;
1558 }
1559
1560 static void
1561 igb_free_rings(struct igb_softc *sc)
1562 {
1563         int i;
1564
1565         if (sc->tx_rings != NULL) {
1566                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1567                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1568
1569                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1570                 }
1571                 kfree(sc->tx_rings, M_DEVBUF);
1572         }
1573
1574         if (sc->rx_rings != NULL) {
1575                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1576                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1577
1578                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1579                 }
1580                 kfree(sc->rx_rings, M_DEVBUF);
1581         }
1582 }
1583
1584 static int
1585 igb_create_tx_ring(struct igb_tx_ring *txr)
1586 {
1587         int tsize, error, i;
1588
1589         /*
1590          * Validate number of transmit descriptors. It must not exceed
1591          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1592          */
1593         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1594             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1595                 device_printf(txr->sc->dev,
1596                     "Using %d TX descriptors instead of %d!\n",
1597                     IGB_DEFAULT_TXD, igb_txd);
1598                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1599         } else {
1600                 txr->num_tx_desc = igb_txd;
1601         }
1602
1603         /*
1604          * Allocate TX descriptor ring
1605          */
1606         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1607             IGB_DBA_ALIGN);
1608         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1609             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1610             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1611         if (txr->txdma.dma_vaddr == NULL) {
1612                 device_printf(txr->sc->dev,
1613                     "Unable to allocate TX Descriptor memory\n");
1614                 return ENOMEM;
1615         }
1616         txr->tx_base = txr->txdma.dma_vaddr;
1617         bzero(txr->tx_base, tsize);
1618
1619         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1620             M_DEVBUF, M_WAITOK | M_ZERO);
1621
1622         /*
1623          * Allocate TX head write-back buffer
1624          */
1625         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1626             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1627             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1628         if (txr->tx_hdr == NULL) {
1629                 device_printf(txr->sc->dev,
1630                     "Unable to allocate TX head write-back buffer\n");
1631                 return ENOMEM;
1632         }
1633
1634         /*
1635          * Create DMA tag for TX buffers
1636          */
1637         error = bus_dma_tag_create(txr->sc->parent_tag,
1638             1, 0,               /* alignment, bounds */
1639             BUS_SPACE_MAXADDR,  /* lowaddr */
1640             BUS_SPACE_MAXADDR,  /* highaddr */
1641             NULL, NULL,         /* filter, filterarg */
1642             IGB_TSO_SIZE,       /* maxsize */
1643             IGB_MAX_SCATTER,    /* nsegments */
1644             PAGE_SIZE,          /* maxsegsize */
1645             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1646             BUS_DMA_ONEBPAGE,   /* flags */
1647             &txr->tx_tag);
1648         if (error) {
1649                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1650                 kfree(txr->tx_buf, M_DEVBUF);
1651                 txr->tx_buf = NULL;
1652                 return error;
1653         }
1654
1655         /*
1656          * Create DMA maps for TX buffers
1657          */
1658         for (i = 0; i < txr->num_tx_desc; ++i) {
1659                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1660
1661                 error = bus_dmamap_create(txr->tx_tag,
1662                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1663                 if (error) {
1664                         device_printf(txr->sc->dev,
1665                             "Unable to create TX DMA map\n");
1666                         igb_destroy_tx_ring(txr, i);
1667                         return error;
1668                 }
1669         }
1670
1671         /*
1672          * Initialize various watermark
1673          */
1674         txr->spare_desc = IGB_TX_SPARE;
1675         txr->intr_nsegs = txr->num_tx_desc / 16;
1676         txr->oact_hi_desc = txr->num_tx_desc / 2;
1677         txr->oact_lo_desc = txr->num_tx_desc / 8;
1678         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1679                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1680         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1681                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1682
1683         return 0;
1684 }
1685
1686 static void
1687 igb_free_tx_ring(struct igb_tx_ring *txr)
1688 {
1689         int i;
1690
1691         for (i = 0; i < txr->num_tx_desc; ++i) {
1692                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1693
1694                 if (txbuf->m_head != NULL) {
1695                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1696                         m_freem(txbuf->m_head);
1697                         txbuf->m_head = NULL;
1698                 }
1699         }
1700 }
1701
1702 static void
1703 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1704 {
1705         int i;
1706
1707         if (txr->txdma.dma_vaddr != NULL) {
1708                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1709                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1710                     txr->txdma.dma_map);
1711                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1712                 txr->txdma.dma_vaddr = NULL;
1713         }
1714
1715         if (txr->tx_hdr != NULL) {
1716                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1717                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1718                     txr->tx_hdr_dmap);
1719                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1720                 txr->tx_hdr = NULL;
1721         }
1722
1723         if (txr->tx_buf == NULL)
1724                 return;
1725
1726         for (i = 0; i < ndesc; ++i) {
1727                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1728
1729                 KKASSERT(txbuf->m_head == NULL);
1730                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1731         }
1732         bus_dma_tag_destroy(txr->tx_tag);
1733
1734         kfree(txr->tx_buf, M_DEVBUF);
1735         txr->tx_buf = NULL;
1736 }
1737
1738 static void
1739 igb_init_tx_ring(struct igb_tx_ring *txr)
1740 {
1741         /* Clear the old descriptor contents */
1742         bzero(txr->tx_base,
1743             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1744
1745         /* Clear TX head write-back buffer */
1746         *(txr->tx_hdr) = 0;
1747
1748         /* Reset indices */
1749         txr->next_avail_desc = 0;
1750         txr->next_to_clean = 0;
1751         txr->tx_nsegs = 0;
1752
1753         /* Set number of descriptors available */
1754         txr->tx_avail = txr->num_tx_desc;
1755 }
1756
1757 static void
1758 igb_init_tx_unit(struct igb_softc *sc)
1759 {
1760         struct e1000_hw *hw = &sc->hw;
1761         uint32_t tctl;
1762         int i;
1763
1764         /* Setup the Tx Descriptor Rings */
1765         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1766                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1767                 uint64_t bus_addr = txr->txdma.dma_paddr;
1768                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1769                 uint32_t txdctl = 0;
1770                 uint32_t dca_txctrl;
1771
1772                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1773                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1774                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1775                     (uint32_t)(bus_addr >> 32));
1776                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1777                     (uint32_t)bus_addr);
1778
1779                 /* Setup the HW Tx Head and Tail descriptor pointers */
1780                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1781                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1782
1783                 /*
1784                  * WTHRESH is ignored by the hardware, since header
1785                  * write back mode is used.
1786                  */
1787                 txdctl |= IGB_TX_PTHRESH;
1788                 txdctl |= IGB_TX_HTHRESH << 8;
1789                 txdctl |= IGB_TX_WTHRESH << 16;
1790                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1791                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1792
1793                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1794                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1795                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1796
1797                 /*
1798                  * Don't set WB_on_EITR:
1799                  * - 82575 does not have it
1800                  * - It almost has no effect on 82576, see:
1801                  *   82576 specification update errata #26
1802                  * - It causes unnecessary bus traffic
1803                  */
1804                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1805                     (uint32_t)(hdr_paddr >> 32));
1806                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1807                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1808         }
1809
1810         if (sc->vf_ifp)
1811                 return;
1812
1813         e1000_config_collision_dist(hw);
1814
1815         /* Program the Transmit Control Register */
1816         tctl = E1000_READ_REG(hw, E1000_TCTL);
1817         tctl &= ~E1000_TCTL_CT;
1818         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1819             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1820
1821         /* This write will effectively turn on the transmit unit. */
1822         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1823 }
1824
1825 static boolean_t
1826 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1827 {
1828         struct e1000_adv_tx_context_desc *TXD;
1829         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1830         int ehdrlen, ctxd, ip_hlen = 0;
1831         uint16_t vlantag = 0;
1832         boolean_t offload = TRUE;
1833
1834         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1835                 offload = FALSE;
1836
1837         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1838
1839         ctxd = txr->next_avail_desc;
1840         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1841
1842         /*
1843          * In advanced descriptors the vlan tag must 
1844          * be placed into the context descriptor, thus
1845          * we need to be here just for that setup.
1846          */
1847         if (mp->m_flags & M_VLANTAG) {
1848                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1849                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1850         } else if (!offload) {
1851                 return FALSE;
1852         }
1853
1854         ehdrlen = mp->m_pkthdr.csum_lhlen;
1855         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1856
1857         /* Set the ether header length */
1858         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1859
1860         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1861                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1862                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1863                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1864         }
1865
1866         vlan_macip_lens |= ip_hlen;
1867         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1868
1869         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1870                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1871         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1872                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1873
1874         /* 82575 needs the queue index added */
1875         if (txr->sc->hw.mac.type == e1000_82575)
1876                 mss_l4len_idx = txr->me << 4;
1877
1878         /* Now copy bits into descriptor */
1879         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1880         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1881         TXD->seqnum_seed = htole32(0);
1882         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1883
1884         /* We've consumed the first desc, adjust counters */
1885         if (++ctxd == txr->num_tx_desc)
1886                 ctxd = 0;
1887         txr->next_avail_desc = ctxd;
1888         --txr->tx_avail;
1889
1890         return offload;
1891 }
1892
1893 static void
1894 igb_txeof(struct igb_tx_ring *txr)
1895 {
1896         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1897         int first, hdr, avail;
1898
1899         if (txr->tx_avail == txr->num_tx_desc)
1900                 return;
1901
1902         first = txr->next_to_clean;
1903         hdr = *(txr->tx_hdr);
1904
1905         if (first == hdr)
1906                 return;
1907
1908         avail = txr->tx_avail;
1909         while (first != hdr) {
1910                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1911
1912                 ++avail;
1913                 if (txbuf->m_head) {
1914                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1915                         m_freem(txbuf->m_head);
1916                         txbuf->m_head = NULL;
1917                         ++ifp->if_opackets;
1918                 }
1919                 if (++first == txr->num_tx_desc)
1920                         first = 0;
1921         }
1922         txr->next_to_clean = first;
1923         txr->tx_avail = avail;
1924
1925         /*
1926          * If we have a minimum free, clear IFF_OACTIVE
1927          * to tell the stack that it is OK to send packets.
1928          */
1929         if (IGB_IS_NOT_OACTIVE(txr)) {
1930                 ifp->if_flags &= ~IFF_OACTIVE;
1931
1932                 /*
1933                  * We have enough TX descriptors, turn off
1934                  * the watchdog.  We allow small amount of
1935                  * packets (roughly intr_nsegs) pending on
1936                  * the transmit ring.
1937                  */
1938                 ifp->if_timer = 0;
1939         }
1940 }
1941
1942 static int
1943 igb_create_rx_ring(struct igb_rx_ring *rxr)
1944 {
1945         int rsize, i, error;
1946
1947         /*
1948          * Validate number of receive descriptors. It must not exceed
1949          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1950          */
1951         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1952             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1953                 device_printf(rxr->sc->dev,
1954                     "Using %d RX descriptors instead of %d!\n",
1955                     IGB_DEFAULT_RXD, igb_rxd);
1956                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1957         } else {
1958                 rxr->num_rx_desc = igb_rxd;
1959         }
1960
1961         /*
1962          * Allocate RX descriptor ring
1963          */
1964         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1965             IGB_DBA_ALIGN);
1966         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1967             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1968             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1969             &rxr->rxdma.dma_paddr);
1970         if (rxr->rxdma.dma_vaddr == NULL) {
1971                 device_printf(rxr->sc->dev,
1972                     "Unable to allocate RxDescriptor memory\n");
1973                 return ENOMEM;
1974         }
1975         rxr->rx_base = rxr->rxdma.dma_vaddr;
1976         bzero(rxr->rx_base, rsize);
1977
1978         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
1979             M_DEVBUF, M_WAITOK | M_ZERO);
1980
1981         /*
1982          * Create DMA tag for RX buffers
1983          */
1984         error = bus_dma_tag_create(rxr->sc->parent_tag,
1985             1, 0,               /* alignment, bounds */
1986             BUS_SPACE_MAXADDR,  /* lowaddr */
1987             BUS_SPACE_MAXADDR,  /* highaddr */
1988             NULL, NULL,         /* filter, filterarg */
1989             MCLBYTES,           /* maxsize */
1990             1,                  /* nsegments */
1991             MCLBYTES,           /* maxsegsize */
1992             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1993             &rxr->rx_tag);
1994         if (error) {
1995                 device_printf(rxr->sc->dev,
1996                     "Unable to create RX payload DMA tag\n");
1997                 kfree(rxr->rx_buf, M_DEVBUF);
1998                 rxr->rx_buf = NULL;
1999                 return error;
2000         }
2001
2002         /*
2003          * Create spare DMA map for RX buffers
2004          */
2005         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2006             &rxr->rx_sparemap);
2007         if (error) {
2008                 device_printf(rxr->sc->dev,
2009                     "Unable to create spare RX DMA maps\n");
2010                 bus_dma_tag_destroy(rxr->rx_tag);
2011                 kfree(rxr->rx_buf, M_DEVBUF);
2012                 rxr->rx_buf = NULL;
2013                 return error;
2014         }
2015
2016         /*
2017          * Create DMA maps for RX buffers
2018          */
2019         for (i = 0; i < rxr->num_rx_desc; i++) {
2020                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2021
2022                 error = bus_dmamap_create(rxr->rx_tag,
2023                     BUS_DMA_WAITOK, &rxbuf->map);
2024                 if (error) {
2025                         device_printf(rxr->sc->dev,
2026                             "Unable to create RX DMA maps\n");
2027                         igb_destroy_rx_ring(rxr, i);
2028                         return error;
2029                 }
2030         }
2031         return 0;
2032 }
2033
2034 static void
2035 igb_free_rx_ring(struct igb_rx_ring *rxr)
2036 {
2037         int i;
2038
2039         for (i = 0; i < rxr->num_rx_desc; ++i) {
2040                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2041
2042                 if (rxbuf->m_head != NULL) {
2043                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2044                         m_freem(rxbuf->m_head);
2045                         rxbuf->m_head = NULL;
2046                 }
2047         }
2048
2049         if (rxr->fmp != NULL)
2050                 m_freem(rxr->fmp);
2051         rxr->fmp = NULL;
2052         rxr->lmp = NULL;
2053 }
2054
2055 static void
2056 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2057 {
2058         int i;
2059
2060         if (rxr->rxdma.dma_vaddr != NULL) {
2061                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2062                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2063                     rxr->rxdma.dma_map);
2064                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2065                 rxr->rxdma.dma_vaddr = NULL;
2066         }
2067
2068         if (rxr->rx_buf == NULL)
2069                 return;
2070
2071         for (i = 0; i < ndesc; ++i) {
2072                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2073
2074                 KKASSERT(rxbuf->m_head == NULL);
2075                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2076         }
2077         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2078         bus_dma_tag_destroy(rxr->rx_tag);
2079
2080         kfree(rxr->rx_buf, M_DEVBUF);
2081         rxr->rx_buf = NULL;
2082 }
2083
2084 static void
2085 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2086 {
2087         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2088         rxd->wb.upper.status_error = 0;
2089 }
2090
2091 static int
2092 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2093 {
2094         struct mbuf *m;
2095         bus_dma_segment_t seg;
2096         bus_dmamap_t map;
2097         struct igb_rx_buf *rxbuf;
2098         int error, nseg;
2099
2100         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2101         if (m == NULL) {
2102                 if (wait) {
2103                         if_printf(&rxr->sc->arpcom.ac_if,
2104                             "Unable to allocate RX mbuf\n");
2105                 }
2106                 return ENOBUFS;
2107         }
2108         m->m_len = m->m_pkthdr.len = MCLBYTES;
2109
2110         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2111                 m_adj(m, ETHER_ALIGN);
2112
2113         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2114             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2115         if (error) {
2116                 m_freem(m);
2117                 if (wait) {
2118                         if_printf(&rxr->sc->arpcom.ac_if,
2119                             "Unable to load RX mbuf\n");
2120                 }
2121                 return error;
2122         }
2123
2124         rxbuf = &rxr->rx_buf[i];
2125         if (rxbuf->m_head != NULL)
2126                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2127
2128         map = rxbuf->map;
2129         rxbuf->map = rxr->rx_sparemap;
2130         rxr->rx_sparemap = map;
2131
2132         rxbuf->m_head = m;
2133         rxbuf->paddr = seg.ds_addr;
2134
2135         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2136         return 0;
2137 }
2138
2139 static int
2140 igb_init_rx_ring(struct igb_rx_ring *rxr)
2141 {
2142         int i;
2143
2144         /* Clear the ring contents */
2145         bzero(rxr->rx_base,
2146             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2147
2148         /* Now replenish the ring mbufs */
2149         for (i = 0; i < rxr->num_rx_desc; ++i) {
2150                 int error;
2151
2152                 error = igb_newbuf(rxr, i, TRUE);
2153                 if (error)
2154                         return error;
2155         }
2156
2157         /* Setup our descriptor indices */
2158         rxr->next_to_check = 0;
2159
2160         rxr->fmp = NULL;
2161         rxr->lmp = NULL;
2162         rxr->discard = FALSE;
2163
2164         return 0;
2165 }
2166
2167 static void
2168 igb_init_rx_unit(struct igb_softc *sc)
2169 {
2170         struct ifnet *ifp = &sc->arpcom.ac_if;
2171         struct e1000_hw *hw = &sc->hw;
2172         uint32_t rctl, rxcsum, srrctl = 0;
2173         int i;
2174
2175         /*
2176          * Make sure receives are disabled while setting
2177          * up the descriptor ring
2178          */
2179         rctl = E1000_READ_REG(hw, E1000_RCTL);
2180         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2181
2182 #if 0
2183         /*
2184         ** Set up for header split
2185         */
2186         if (igb_header_split) {
2187                 /* Use a standard mbuf for the header */
2188                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2189                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2190         } else
2191 #endif
2192                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2193
2194         /*
2195         ** Set up for jumbo frames
2196         */
2197         if (ifp->if_mtu > ETHERMTU) {
2198                 rctl |= E1000_RCTL_LPE;
2199 #if 0
2200                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2201                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2202                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2203                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2204                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2205                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2206                 }
2207                 /* Set maximum packet len */
2208                 psize = adapter->max_frame_size;
2209                 /* are we on a vlan? */
2210                 if (adapter->ifp->if_vlantrunk != NULL)
2211                         psize += VLAN_TAG_SIZE;
2212                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2213 #else
2214                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2215                 rctl |= E1000_RCTL_SZ_2048;
2216 #endif
2217         } else {
2218                 rctl &= ~E1000_RCTL_LPE;
2219                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2220                 rctl |= E1000_RCTL_SZ_2048;
2221         }
2222
2223         /* Setup the Base and Length of the Rx Descriptor Rings */
2224         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2225                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2226                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2227                 uint32_t rxdctl;
2228
2229                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2230                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2231                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2232                     (uint32_t)(bus_addr >> 32));
2233                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2234                     (uint32_t)bus_addr);
2235                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2236                 /* Enable this Queue */
2237                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2238                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2239                 rxdctl &= 0xFFF00000;
2240                 rxdctl |= IGB_RX_PTHRESH;
2241                 rxdctl |= IGB_RX_HTHRESH << 8;
2242                 /*
2243                  * Don't set WTHRESH to a value above 1 on 82576, see:
2244                  * 82576 specification update errata #26
2245                  */
2246                 rxdctl |= IGB_RX_WTHRESH << 16;
2247                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2248         }
2249
2250         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2251         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2252
2253         /*
2254          * Receive Checksum Offload for TCP and UDP
2255          *
2256          * Checksum offloading is also enabled if multiple receive
2257          * queue is to be supported, since we need it to figure out
2258          * fragments.
2259          */
2260         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2261                 /*
2262                  * NOTE:
2263                  * PCSD must be enabled to enable multiple
2264                  * receive queues.
2265                  */
2266                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2267                     E1000_RXCSUM_PCSD;
2268         } else {
2269                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2270                     E1000_RXCSUM_PCSD);
2271         }
2272         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2273
2274         if (IGB_ENABLE_HWRSS(sc)) {
2275                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2276                 uint32_t reta_shift;
2277                 int j, r;
2278
2279                 /*
2280                  * NOTE:
2281                  * When we reach here, RSS has already been disabled
2282                  * in igb_stop(), so we could safely configure RSS key
2283                  * and redirect table.
2284                  */
2285
2286                 /*
2287                  * Configure RSS key
2288                  */
2289                 toeplitz_get_key(key, sizeof(key));
2290                 for (i = 0; i < IGB_NRSSRK; ++i) {
2291                         uint32_t rssrk;
2292
2293                         rssrk = IGB_RSSRK_VAL(key, i);
2294                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2295
2296                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2297                 }
2298
2299                 /*
2300                  * Configure RSS redirect table in following fashion:
2301                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2302                  */
2303                 reta_shift = IGB_RETA_SHIFT;
2304                 if (hw->mac.type == e1000_82575)
2305                         reta_shift = IGB_RETA_SHIFT_82575;
2306
2307                 r = 0;
2308                 for (j = 0; j < IGB_NRETA; ++j) {
2309                         uint32_t reta = 0;
2310
2311                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2312                                 uint32_t q;
2313
2314                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2315                                 reta |= q << (8 * i);
2316                                 ++r;
2317                         }
2318                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2319                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2320                 }
2321
2322                 /*
2323                  * Enable multiple receive queues.
2324                  * Enable IPv4 RSS standard hash functions.
2325                  * Disable RSS interrupt on 82575
2326                  */
2327                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2328                                 E1000_MRQC_ENABLE_RSS_4Q |
2329                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2330                                 E1000_MRQC_RSS_FIELD_IPV4);
2331         }
2332
2333         /* Setup the Receive Control Register */
2334         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2335         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2336             E1000_RCTL_RDMTS_HALF |
2337             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2338         /* Strip CRC bytes. */
2339         rctl |= E1000_RCTL_SECRC;
2340         /* Make sure VLAN Filters are off */
2341         rctl &= ~E1000_RCTL_VFE;
2342         /* Don't store bad packets */
2343         rctl &= ~E1000_RCTL_SBP;
2344
2345         /* Enable Receives */
2346         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2347
2348         /*
2349          * Setup the HW Rx Head and Tail Descriptor Pointers
2350          *   - needs to be after enable
2351          */
2352         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2353                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2354
2355                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2356                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2357         }
2358 }
2359
2360 static void
2361 igb_rxeof(struct igb_rx_ring *rxr, int count)
2362 {
2363         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2364         union e1000_adv_rx_desc *cur;
2365         uint32_t staterr;
2366         int i;
2367
2368         i = rxr->next_to_check;
2369         cur = &rxr->rx_base[i];
2370         staterr = le32toh(cur->wb.upper.status_error);
2371
2372         if ((staterr & E1000_RXD_STAT_DD) == 0)
2373                 return;
2374
2375         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2376                 struct pktinfo *pi = NULL, pi0;
2377                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2378                 struct mbuf *m = NULL;
2379                 boolean_t eop;
2380
2381                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2382                 if (eop)
2383                         --count;
2384
2385                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2386                     !rxr->discard) {
2387                         struct mbuf *mp = rxbuf->m_head;
2388                         uint32_t hash, hashtype;
2389                         uint16_t vlan;
2390                         int len;
2391
2392                         len = le16toh(cur->wb.upper.length);
2393                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2394                             (staterr & E1000_RXDEXT_STATERR_LB))
2395                                 vlan = be16toh(cur->wb.upper.vlan);
2396                         else
2397                                 vlan = le16toh(cur->wb.upper.vlan);
2398
2399                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2400                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2401                             E1000_RXDADV_RSSTYPE_MASK;
2402
2403                         IGB_RSS_DPRINTF(rxr->sc, 10,
2404                             "ring%d, hash 0x%08x, hashtype %u\n",
2405                             rxr->me, hash, hashtype);
2406
2407                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2408                             BUS_DMASYNC_POSTREAD);
2409
2410                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2411                                 ifp->if_iqdrops++;
2412                                 goto discard;
2413                         }
2414
2415                         mp->m_len = len;
2416                         if (rxr->fmp == NULL) {
2417                                 mp->m_pkthdr.len = len;
2418                                 rxr->fmp = mp;
2419                                 rxr->lmp = mp;
2420                         } else {
2421                                 rxr->lmp->m_next = mp;
2422                                 rxr->lmp = rxr->lmp->m_next;
2423                                 rxr->fmp->m_pkthdr.len += len;
2424                         }
2425
2426                         if (eop) {
2427                                 m = rxr->fmp;
2428                                 rxr->fmp = NULL;
2429                                 rxr->lmp = NULL;
2430
2431                                 m->m_pkthdr.rcvif = ifp;
2432                                 ifp->if_ipackets++;
2433
2434                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2435                                         igb_rxcsum(staterr, m);
2436
2437                                 if (staterr & E1000_RXD_STAT_VP) {
2438                                         m->m_pkthdr.ether_vlantag = vlan;
2439                                         m->m_flags |= M_VLANTAG;
2440                                 }
2441
2442                                 if (ifp->if_capenable & IFCAP_RSS) {
2443                                         pi = igb_rssinfo(m, &pi0,
2444                                             hash, hashtype, staterr);
2445                                 }
2446 #ifdef IGB_RSS_DEBUG
2447                                 rxr->rx_packets++;
2448 #endif
2449                         }
2450                 } else {
2451                         ifp->if_ierrors++;
2452 discard:
2453                         igb_setup_rxdesc(cur, rxbuf);
2454                         if (!eop)
2455                                 rxr->discard = TRUE;
2456                         else
2457                                 rxr->discard = FALSE;
2458                         if (rxr->fmp != NULL) {
2459                                 m_freem(rxr->fmp);
2460                                 rxr->fmp = NULL;
2461                                 rxr->lmp = NULL;
2462                         }
2463                         m = NULL;
2464                 }
2465
2466                 if (m != NULL)
2467                         ether_input_pkt(ifp, m, pi);
2468
2469                 /* Advance our pointers to the next descriptor. */
2470                 if (++i == rxr->num_rx_desc)
2471                         i = 0;
2472
2473                 cur = &rxr->rx_base[i];
2474                 staterr = le32toh(cur->wb.upper.status_error);
2475         }
2476         rxr->next_to_check = i;
2477
2478         if (--i < 0)
2479                 i = rxr->num_rx_desc - 1;
2480         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2481 }
2482
2483
2484 static void
2485 igb_set_vlan(struct igb_softc *sc)
2486 {
2487         struct e1000_hw *hw = &sc->hw;
2488         uint32_t reg;
2489 #if 0
2490         struct ifnet *ifp = sc->arpcom.ac_if;
2491 #endif
2492
2493         if (sc->vf_ifp) {
2494                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2495                 return;
2496         }
2497
2498         reg = E1000_READ_REG(hw, E1000_CTRL);
2499         reg |= E1000_CTRL_VME;
2500         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2501
2502 #if 0
2503         /* Enable the Filter Table */
2504         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2505                 reg = E1000_READ_REG(hw, E1000_RCTL);
2506                 reg &= ~E1000_RCTL_CFIEN;
2507                 reg |= E1000_RCTL_VFE;
2508                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2509         }
2510 #endif
2511
2512         /* Update the frame size */
2513         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2514             sc->max_frame_size + VLAN_TAG_SIZE);
2515
2516 #if 0
2517         /* Don't bother with table if no vlans */
2518         if ((adapter->num_vlans == 0) ||
2519             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2520                 return;
2521         /*
2522         ** A soft reset zero's out the VFTA, so
2523         ** we need to repopulate it now.
2524         */
2525         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2526                 if (adapter->shadow_vfta[i] != 0) {
2527                         if (adapter->vf_ifp)
2528                                 e1000_vfta_set_vf(hw,
2529                                     adapter->shadow_vfta[i], TRUE);
2530                         else
2531                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2532                                  i, adapter->shadow_vfta[i]);
2533                 }
2534 #endif
2535 }
2536
2537 static void
2538 igb_enable_intr(struct igb_softc *sc)
2539 {
2540         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2541                 lwkt_serialize_handler_enable(&sc->main_serialize);
2542         } else {
2543                 int i;
2544
2545                 for (i = 0; i < sc->msix_cnt; ++i) {
2546                         lwkt_serialize_handler_enable(
2547                             sc->msix_data[i].msix_serialize);
2548                 }
2549         }
2550
2551         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2552                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2553                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2554                 else
2555                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2556                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2557                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2558                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2559         } else {
2560                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2561         }
2562         E1000_WRITE_FLUSH(&sc->hw);
2563 }
2564
2565 static void
2566 igb_disable_intr(struct igb_softc *sc)
2567 {
2568         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2569                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2570                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2571         }
2572         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2573         E1000_WRITE_FLUSH(&sc->hw);
2574
2575         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2576                 lwkt_serialize_handler_disable(&sc->main_serialize);
2577         } else {
2578                 int i;
2579
2580                 for (i = 0; i < sc->msix_cnt; ++i) {
2581                         lwkt_serialize_handler_disable(
2582                             sc->msix_data[i].msix_serialize);
2583                 }
2584         }
2585 }
2586
2587 /*
2588  * Bit of a misnomer, what this really means is
2589  * to enable OS management of the system... aka
2590  * to disable special hardware management features 
2591  */
2592 static void
2593 igb_get_mgmt(struct igb_softc *sc)
2594 {
2595         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2596                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2597                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2598
2599                 /* disable hardware interception of ARP */
2600                 manc &= ~E1000_MANC_ARP_EN;
2601
2602                 /* enable receiving management packets to the host */
2603                 manc |= E1000_MANC_EN_MNG2HOST;
2604                 manc2h |= 1 << 5; /* Mng Port 623 */
2605                 manc2h |= 1 << 6; /* Mng Port 664 */
2606                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2607                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2608         }
2609 }
2610
2611 /*
2612  * Give control back to hardware management controller
2613  * if there is one.
2614  */
2615 static void
2616 igb_rel_mgmt(struct igb_softc *sc)
2617 {
2618         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2619                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2620
2621                 /* Re-enable hardware interception of ARP */
2622                 manc |= E1000_MANC_ARP_EN;
2623                 manc &= ~E1000_MANC_EN_MNG2HOST;
2624
2625                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2626         }
2627 }
2628
2629 /*
2630  * Sets CTRL_EXT:DRV_LOAD bit.
2631  *
2632  * For ASF and Pass Through versions of f/w this means that
2633  * the driver is loaded. 
2634  */
2635 static void
2636 igb_get_hw_control(struct igb_softc *sc)
2637 {
2638         uint32_t ctrl_ext;
2639
2640         if (sc->vf_ifp)
2641                 return;
2642
2643         /* Let firmware know the driver has taken over */
2644         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2645         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2646             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2647 }
2648
2649 /*
2650  * Resets CTRL_EXT:DRV_LOAD bit.
2651  *
2652  * For ASF and Pass Through versions of f/w this means that the
2653  * driver is no longer loaded.
2654  */
2655 static void
2656 igb_rel_hw_control(struct igb_softc *sc)
2657 {
2658         uint32_t ctrl_ext;
2659
2660         if (sc->vf_ifp)
2661                 return;
2662
2663         /* Let firmware taken over control of h/w */
2664         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2665         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2666             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2667 }
2668
2669 static int
2670 igb_is_valid_ether_addr(const uint8_t *addr)
2671 {
2672         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2673
2674         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2675                 return FALSE;
2676         return TRUE;
2677 }
2678
2679 /*
2680  * Enable PCI Wake On Lan capability
2681  */
2682 static void
2683 igb_enable_wol(device_t dev)
2684 {
2685         uint16_t cap, status;
2686         uint8_t id;
2687
2688         /* First find the capabilities pointer*/
2689         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2690
2691         /* Read the PM Capabilities */
2692         id = pci_read_config(dev, cap, 1);
2693         if (id != PCIY_PMG)     /* Something wrong */
2694                 return;
2695
2696         /*
2697          * OK, we have the power capabilities,
2698          * so now get the status register
2699          */
2700         cap += PCIR_POWER_STATUS;
2701         status = pci_read_config(dev, cap, 2);
2702         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2703         pci_write_config(dev, cap, status, 2);
2704 }
2705
2706 static void
2707 igb_update_stats_counters(struct igb_softc *sc)
2708 {
2709         struct e1000_hw *hw = &sc->hw;
2710         struct e1000_hw_stats *stats;
2711         struct ifnet *ifp = &sc->arpcom.ac_if;
2712
2713         /* 
2714          * The virtual function adapter has only a
2715          * small controlled set of stats, do only 
2716          * those and return.
2717          */
2718         if (sc->vf_ifp) {
2719                 igb_update_vf_stats_counters(sc);
2720                 return;
2721         }
2722         stats = sc->stats;
2723
2724         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2725             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2726                 stats->symerrs +=
2727                     E1000_READ_REG(hw,E1000_SYMERRS);
2728                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2729         }
2730
2731         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2732         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2733         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2734         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2735
2736         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2737         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2738         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2739         stats->dc += E1000_READ_REG(hw, E1000_DC);
2740         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2741         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2742         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2743
2744         /*
2745          * For watchdog management we need to know if we have been
2746          * paused during the last interval, so capture that here.
2747          */ 
2748         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2749         stats->xoffrxc += sc->pause_frames;
2750         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2751         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2752         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2753         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2754         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2755         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2756         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2757         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2758         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2759         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2760         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2761         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2762
2763         /* For the 64-bit byte counters the low dword must be read first. */
2764         /* Both registers clear on the read of the high dword */
2765
2766         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2767             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2768         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2769             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2770
2771         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2772         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2773         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2774         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2775         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2776
2777         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2778         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2779
2780         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2781         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2782         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2783         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2784         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2785         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2786         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2787         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2788         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2789         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2790
2791         /* Interrupt Counts */
2792
2793         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2794         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2795         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2796         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2797         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2798         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2799         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2800         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2801         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2802
2803         /* Host to Card Statistics */
2804
2805         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2806         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2807         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2808         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2809         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2810         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2811         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2812         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2813             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2814         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2815             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2816         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2817         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2818         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2819
2820         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2821         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2822         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2823         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2824         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2825         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2826
2827         ifp->if_collisions = stats->colc;
2828
2829         /* Rx Errors */
2830         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2831             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2832
2833         /* Tx Errors */
2834         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2835
2836         /* Driver specific counters */
2837         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2838         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2839         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2840         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2841         sc->packet_buf_alloc_tx =
2842             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2843         sc->packet_buf_alloc_rx =
2844             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2845 }
2846
2847 static void
2848 igb_vf_init_stats(struct igb_softc *sc)
2849 {
2850         struct e1000_hw *hw = &sc->hw;
2851         struct e1000_vf_stats *stats;
2852
2853         stats = sc->stats;
2854         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2855         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2856         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2857         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2858         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2859 }
2860  
2861 static void
2862 igb_update_vf_stats_counters(struct igb_softc *sc)
2863 {
2864         struct e1000_hw *hw = &sc->hw;
2865         struct e1000_vf_stats *stats;
2866
2867         if (sc->link_speed == 0)
2868                 return;
2869
2870         stats = sc->stats;
2871         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2872         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2873         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2874         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2875         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2876 }
2877
2878 #ifdef DEVICE_POLLING
2879
2880 static void
2881 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2882 {
2883         struct igb_softc *sc = ifp->if_softc;
2884         uint32_t reg_icr;
2885
2886         switch (cmd) {
2887         case POLL_REGISTER:
2888         case POLL_DEREGISTER:
2889                 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2890                 igb_init(sc);
2891                 break;
2892
2893         case POLL_AND_CHECK_STATUS:
2894                 ASSERT_SERIALIZED(&sc->main_serialize);
2895                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2896                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2897                         sc->hw.mac.get_link_status = 1;
2898                         igb_update_link_status(sc);
2899                 }
2900                 /* FALL THROUGH */
2901         case POLL_ONLY:
2902                 ASSERT_SERIALIZED(&sc->main_serialize);
2903                 if (ifp->if_flags & IFF_RUNNING) {
2904                         struct igb_tx_ring *txr;
2905                         int i;
2906
2907                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2908                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2909
2910                                 lwkt_serialize_enter(&rxr->rx_serialize);
2911                                 igb_rxeof(rxr, count);
2912                                 lwkt_serialize_exit(&rxr->rx_serialize);
2913                         }
2914
2915                         txr = &sc->tx_rings[0];
2916                         lwkt_serialize_enter(&txr->tx_serialize);
2917                         igb_txeof(txr);
2918                         if (!ifq_is_empty(&ifp->if_snd))
2919                                 if_devstart(ifp);
2920                         lwkt_serialize_exit(&txr->tx_serialize);
2921                 }
2922                 break;
2923         }
2924 }
2925
2926 #endif /* DEVICE_POLLING */
2927
2928 static void
2929 igb_intr(void *xsc)
2930 {
2931         struct igb_softc *sc = xsc;
2932         struct ifnet *ifp = &sc->arpcom.ac_if;
2933         uint32_t eicr;
2934
2935         ASSERT_SERIALIZED(&sc->main_serialize);
2936
2937         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2938
2939         if (eicr == 0)
2940                 return;
2941
2942         if (ifp->if_flags & IFF_RUNNING) {
2943                 struct igb_tx_ring *txr;
2944                 int i;
2945
2946                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2947                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2948
2949                         if (eicr & rxr->rx_intr_mask) {
2950                                 lwkt_serialize_enter(&rxr->rx_serialize);
2951                                 igb_rxeof(rxr, -1);
2952                                 lwkt_serialize_exit(&rxr->rx_serialize);
2953                         }
2954                 }
2955
2956                 txr = &sc->tx_rings[0];
2957                 if (eicr & txr->tx_intr_mask) {
2958                         lwkt_serialize_enter(&txr->tx_serialize);
2959                         igb_txeof(txr);
2960                         if (!ifq_is_empty(&ifp->if_snd))
2961                                 if_devstart(ifp);
2962                         lwkt_serialize_exit(&txr->tx_serialize);
2963                 }
2964         }
2965
2966         if (eicr & E1000_EICR_OTHER) {
2967                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2968
2969                 /* Link status change */
2970                 if (icr & E1000_ICR_LSC) {
2971                         sc->hw.mac.get_link_status = 1;
2972                         igb_update_link_status(sc);
2973                 }
2974         }
2975
2976         /*
2977          * Reading EICR has the side effect to clear interrupt mask,
2978          * so all interrupts need to be enabled here.
2979          */
2980         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2981 }
2982
2983 static void
2984 igb_intr_shared(void *xsc)
2985 {
2986         struct igb_softc *sc = xsc;
2987         struct ifnet *ifp = &sc->arpcom.ac_if;
2988         uint32_t reg_icr;
2989
2990         ASSERT_SERIALIZED(&sc->main_serialize);
2991
2992         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2993
2994         /* Hot eject?  */
2995         if (reg_icr == 0xffffffff)
2996                 return;
2997
2998         /* Definitely not our interrupt.  */
2999         if (reg_icr == 0x0)
3000                 return;
3001
3002         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3003                 return;
3004
3005         if (ifp->if_flags & IFF_RUNNING) {
3006                 if (reg_icr &
3007                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3008                         int i;
3009
3010                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3011                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3012
3013                                 lwkt_serialize_enter(&rxr->rx_serialize);
3014                                 igb_rxeof(rxr, -1);
3015                                 lwkt_serialize_exit(&rxr->rx_serialize);
3016                         }
3017                 }
3018
3019                 if (reg_icr & E1000_ICR_TXDW) {
3020                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3021
3022                         lwkt_serialize_enter(&txr->tx_serialize);
3023                         igb_txeof(txr);
3024                         if (!ifq_is_empty(&ifp->if_snd))
3025                                 if_devstart(ifp);
3026                         lwkt_serialize_exit(&txr->tx_serialize);
3027                 }
3028         }
3029
3030         /* Link status change */
3031         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3032                 sc->hw.mac.get_link_status = 1;
3033                 igb_update_link_status(sc);
3034         }
3035
3036         if (reg_icr & E1000_ICR_RXO)
3037                 sc->rx_overruns++;
3038 }
3039
3040 static int
3041 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3042 {
3043         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3044         bus_dmamap_t map;
3045         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3046         union e1000_adv_tx_desc *txd = NULL;
3047         struct mbuf *m_head = *m_headp;
3048         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3049         int maxsegs, nsegs, i, j, error, last = 0;
3050         uint32_t hdrlen = 0;
3051
3052         /* Set basic descriptor constants */
3053         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3054         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3055         if (m_head->m_flags & M_VLANTAG)
3056                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3057
3058         /*
3059          * Map the packet for DMA.
3060          */
3061         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3062         tx_buf_mapped = tx_buf;
3063         map = tx_buf->map;
3064
3065         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3066         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3067         if (maxsegs > IGB_MAX_SCATTER)
3068                 maxsegs = IGB_MAX_SCATTER;
3069
3070         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3071             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3072         if (error) {
3073                 if (error == ENOBUFS)
3074                         txr->sc->mbuf_defrag_failed++;
3075                 else
3076                         txr->sc->no_tx_dma_setup++;
3077
3078                 m_freem(*m_headp);
3079                 *m_headp = NULL;
3080                 return error;
3081         }
3082         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3083
3084         m_head = *m_headp;
3085
3086 #if 0
3087         /*
3088          * Set up the context descriptor:
3089          * used when any hardware offload is done.
3090          * This includes CSUM, VLAN, and TSO. It
3091          * will use the first descriptor.
3092          */
3093         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3094                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3095                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3096                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3097                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3098                 } else
3099                         return (ENXIO); 
3100         } else if (igb_tx_ctx_setup(txr, m_head))
3101                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3102 #else
3103         if (igb_txcsum_ctx(txr, m_head)) {
3104                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3105                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3106                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3107                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3108                 txr->tx_nsegs++;
3109         }
3110 #endif
3111
3112         txr->tx_nsegs += nsegs;
3113         if (txr->tx_nsegs >= txr->intr_nsegs) {
3114                 /*
3115                  * Report Status (RS) is turned on every intr_nsegs
3116                  * descriptors (roughly).
3117                  */
3118                 txr->tx_nsegs = 0;
3119                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3120         }
3121
3122         /* Calculate payload length */
3123         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3124             << E1000_ADVTXD_PAYLEN_SHIFT);
3125
3126         /* 82575 needs the queue index added */
3127         if (txr->sc->hw.mac.type == e1000_82575)
3128                 olinfo_status |= txr->me << 4;
3129
3130         /* Set up our transmit descriptors */
3131         i = txr->next_avail_desc;
3132         for (j = 0; j < nsegs; j++) {
3133                 bus_size_t seg_len;
3134                 bus_addr_t seg_addr;
3135
3136                 tx_buf = &txr->tx_buf[i];
3137                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3138                 seg_addr = segs[j].ds_addr;
3139                 seg_len = segs[j].ds_len;
3140
3141                 txd->read.buffer_addr = htole64(seg_addr);
3142                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3143                 txd->read.olinfo_status = htole32(olinfo_status);
3144                 last = i;
3145                 if (++i == txr->num_tx_desc)
3146                         i = 0;
3147                 tx_buf->m_head = NULL;
3148         }
3149
3150         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3151         txr->next_avail_desc = i;
3152         txr->tx_avail -= nsegs;
3153
3154         tx_buf->m_head = m_head;
3155         tx_buf_mapped->map = tx_buf->map;
3156         tx_buf->map = map;
3157
3158         /*
3159          * Last Descriptor of Packet needs End Of Packet (EOP)
3160          */
3161         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3162
3163         /*
3164          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3165          * that this frame is available to transmit.
3166          */
3167         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3168         ++txr->tx_packets;
3169
3170         return 0;
3171 }
3172
3173 static void
3174 igb_start(struct ifnet *ifp)
3175 {
3176         struct igb_softc *sc = ifp->if_softc;
3177         struct igb_tx_ring *txr = &sc->tx_rings[0];
3178         struct mbuf *m_head;
3179
3180         ASSERT_SERIALIZED(&txr->tx_serialize);
3181
3182         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3183                 return;
3184
3185         if (!sc->link_active) {
3186                 ifq_purge(&ifp->if_snd);
3187                 return;
3188         }
3189
3190         if (!IGB_IS_NOT_OACTIVE(txr))
3191                 igb_txeof(txr);
3192
3193         while (!ifq_is_empty(&ifp->if_snd)) {
3194                 if (IGB_IS_OACTIVE(txr)) {
3195                         ifp->if_flags |= IFF_OACTIVE;
3196                         /* Set watchdog on */
3197                         ifp->if_timer = 5;
3198                         break;
3199                 }
3200
3201                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3202                 if (m_head == NULL)
3203                         break;
3204
3205                 if (igb_encap(txr, &m_head)) {
3206                         ifp->if_oerrors++;
3207                         continue;
3208                 }
3209
3210                 /* Send a copy of the frame to the BPF listener */
3211                 ETHER_BPF_MTAP(ifp, m_head);
3212         }
3213 }
3214
3215 static void
3216 igb_watchdog(struct ifnet *ifp)
3217 {
3218         struct igb_softc *sc = ifp->if_softc;
3219         struct igb_tx_ring *txr = &sc->tx_rings[0];
3220
3221         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3222
3223         /* 
3224          * If flow control has paused us since last checking
3225          * it invalidates the watchdog timing, so dont run it.
3226          */
3227         if (sc->pause_frames) {
3228                 sc->pause_frames = 0;
3229                 ifp->if_timer = 5;
3230                 return;
3231         }
3232
3233         if_printf(ifp, "Watchdog timeout -- resetting\n");
3234         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3235             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3236             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3237         if_printf(ifp, "TX(%d) desc avail = %d, "
3238             "Next TX to Clean = %d\n",
3239             txr->me, txr->tx_avail, txr->next_to_clean);
3240
3241         ifp->if_oerrors++;
3242         sc->watchdog_events++;
3243
3244         igb_init(sc);
3245         if (!ifq_is_empty(&ifp->if_snd))
3246                 if_devstart(ifp);
3247 }
3248
3249 static void
3250 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3251 {
3252         uint32_t eitr = 0;
3253
3254         if (rate > 0) {
3255                 if (sc->hw.mac.type == e1000_82575) {
3256                         eitr = 1000000000 / 256 / rate;
3257                         /*
3258                          * NOTE:
3259                          * Document is wrong on the 2 bits left shift
3260                          */
3261                 } else {
3262                         eitr = 1000000 / rate;
3263                         eitr <<= IGB_EITR_INTVL_SHIFT;
3264                 }
3265
3266                 if (eitr == 0) {
3267                         /* Don't disable it */
3268                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3269                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3270                         /* Don't allow it to be too large */
3271                         eitr = IGB_EITR_INTVL_MASK;
3272                 }
3273         }
3274         if (sc->hw.mac.type == e1000_82575)
3275                 eitr |= eitr << 16;
3276         else
3277                 eitr |= E1000_EITR_CNT_IGNR;
3278         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3279 }
3280
3281 static int
3282 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3283 {
3284         struct igb_softc *sc = (void *)arg1;
3285         struct ifnet *ifp = &sc->arpcom.ac_if;
3286         int error, intr_rate;
3287
3288         intr_rate = sc->intr_rate;
3289         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3290         if (error || req->newptr == NULL)
3291                 return error;
3292         if (intr_rate < 0)
3293                 return EINVAL;
3294
3295         ifnet_serialize_all(ifp);
3296
3297         sc->intr_rate = intr_rate;
3298         if (ifp->if_flags & IFF_RUNNING)
3299                 igb_set_eitr(sc, 0, sc->intr_rate);
3300
3301         if (bootverbose)
3302                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3303
3304         ifnet_deserialize_all(ifp);
3305
3306         return 0;
3307 }
3308
3309 static int
3310 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3311 {
3312         struct igb_msix_data *msix = (void *)arg1;
3313         struct igb_softc *sc = msix->msix_sc;
3314         struct ifnet *ifp = &sc->arpcom.ac_if;
3315         int error, msix_rate;
3316
3317         msix_rate = msix->msix_rate;
3318         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3319         if (error || req->newptr == NULL)
3320                 return error;
3321         if (msix_rate < 0)
3322                 return EINVAL;
3323
3324         lwkt_serialize_enter(msix->msix_serialize);
3325
3326         msix->msix_rate = msix_rate;
3327         if (ifp->if_flags & IFF_RUNNING)
3328                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3329
3330         if (bootverbose) {
3331                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3332                     msix->msix_rate);
3333         }
3334
3335         lwkt_serialize_exit(msix->msix_serialize);
3336
3337         return 0;
3338 }
3339
3340 static int
3341 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3342 {
3343         struct igb_softc *sc = (void *)arg1;
3344         struct ifnet *ifp = &sc->arpcom.ac_if;
3345         struct igb_tx_ring *txr = &sc->tx_rings[0];
3346         int error, nsegs;
3347
3348         nsegs = txr->intr_nsegs;
3349         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3350         if (error || req->newptr == NULL)
3351                 return error;
3352         if (nsegs <= 0)
3353                 return EINVAL;
3354
3355         ifnet_serialize_all(ifp);
3356
3357         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3358             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3359                 error = EINVAL;
3360         } else {
3361                 error = 0;
3362                 txr->intr_nsegs = nsegs;
3363         }
3364
3365         ifnet_deserialize_all(ifp);
3366
3367         return error;
3368 }
3369
3370 static void
3371 igb_init_intr(struct igb_softc *sc)
3372 {
3373         igb_set_intr_mask(sc);
3374
3375         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3376                 igb_init_unshared_intr(sc);
3377
3378         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3379                 igb_set_eitr(sc, 0, sc->intr_rate);
3380         } else {
3381                 int i;
3382
3383                 for (i = 0; i < sc->msix_cnt; ++i)
3384                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3385         }
3386 }
3387
3388 static void
3389 igb_init_unshared_intr(struct igb_softc *sc)
3390 {
3391         struct e1000_hw *hw = &sc->hw;
3392         const struct igb_rx_ring *rxr;
3393         const struct igb_tx_ring *txr;
3394         uint32_t ivar, index;
3395         int i;
3396
3397         /*
3398          * Enable extended mode
3399          */
3400         if (sc->hw.mac.type != e1000_82575) {
3401                 uint32_t gpie;
3402                 int ivar_max;
3403
3404                 gpie = E1000_GPIE_NSICR;
3405                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3406                         gpie |= E1000_GPIE_MSIX_MODE |
3407                             E1000_GPIE_EIAME |
3408                             E1000_GPIE_PBA;
3409                 }
3410                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3411
3412                 /*
3413                  * Clear IVARs
3414                  */
3415                 switch (sc->hw.mac.type) {
3416                 case e1000_82580:
3417                         ivar_max = IGB_MAX_IVAR_82580;
3418                         break;
3419
3420                 case e1000_i350:
3421                         ivar_max = IGB_MAX_IVAR_I350;
3422                         break;
3423
3424                 case e1000_vfadapt:
3425                 case e1000_vfadapt_i350:
3426                         ivar_max = IGB_MAX_IVAR_VF;
3427                         break;
3428
3429                 case e1000_82576:
3430                         ivar_max = IGB_MAX_IVAR_82576;
3431                         break;
3432
3433                 default:
3434                         panic("unknown mac type %d\n", sc->hw.mac.type);
3435                 }
3436                 for (i = 0; i < ivar_max; ++i)
3437                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3438                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3439         } else {
3440                 uint32_t tmp;
3441
3442                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3443                     ("82575 w/ MSI-X"));
3444                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3445                 tmp |= E1000_CTRL_EXT_IRCA;
3446                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3447         }
3448
3449         /*
3450          * Map TX/RX interrupts to EICR
3451          */
3452         switch (sc->hw.mac.type) {
3453         case e1000_82580:
3454         case e1000_i350:
3455         case e1000_vfadapt:
3456         case e1000_vfadapt_i350:
3457                 /* RX entries */
3458                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3459                         rxr = &sc->rx_rings[i];
3460
3461                         index = i >> 1;
3462                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3463
3464                         if (i & 1) {
3465                                 ivar &= 0xff00ffff;
3466                                 ivar |=
3467                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3468                         } else {
3469                                 ivar &= 0xffffff00;
3470                                 ivar |=
3471                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3472                         }
3473                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3474                 }
3475                 /* TX entries */
3476                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3477                         txr = &sc->tx_rings[i];
3478
3479                         index = i >> 1;
3480                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3481
3482                         if (i & 1) {
3483                                 ivar &= 0x00ffffff;
3484                                 ivar |=
3485                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3486                         } else {
3487                                 ivar &= 0xffff00ff;
3488                                 ivar |=
3489                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3490                         }
3491                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3492                 }
3493                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3494                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3495                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3496                 }
3497                 break;
3498
3499         case e1000_82576:
3500                 /* RX entries */
3501                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3502                         rxr = &sc->rx_rings[i];
3503
3504                         index = i & 0x7; /* Each IVAR has two entries */
3505                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3506
3507                         if (i < 8) {
3508                                 ivar &= 0xffffff00;
3509                                 ivar |=
3510                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3511                         } else {
3512                                 ivar &= 0xff00ffff;
3513                                 ivar |=
3514                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3515                         }
3516                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3517                 }
3518                 /* TX entries */
3519                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3520                         txr = &sc->tx_rings[i];
3521
3522                         index = i & 0x7; /* Each IVAR has two entries */
3523                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3524
3525                         if (i < 8) {
3526                                 ivar &= 0xffff00ff;
3527                                 ivar |=
3528                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3529                         } else {
3530                                 ivar &= 0x00ffffff;
3531                                 ivar |=
3532                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3533                         }
3534                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3535                 }
3536                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3537                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3538                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3539                 }
3540                 break;
3541
3542         case e1000_82575:
3543                 /*
3544                  * Enable necessary interrupt bits.
3545                  *
3546                  * The name of the register is confusing; in addition to
3547                  * configuring the first vector of MSI-X, it also configures
3548                  * which bits of EICR could be set by the hardware even when
3549                  * MSI or line interrupt is used; it thus controls interrupt
3550                  * generation.  It MUST be configured explicitly; the default
3551                  * value mentioned in the datasheet is wrong: RX queue0 and
3552                  * TX queue0 are NOT enabled by default.
3553                  */
3554                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3555                 break;
3556
3557         default:
3558                 panic("unknown mac type %d\n", sc->hw.mac.type);
3559         }
3560 }
3561
3562 static int
3563 igb_setup_intr(struct igb_softc *sc)
3564 {
3565         struct ifnet *ifp = &sc->arpcom.ac_if;
3566         int error;
3567
3568         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3569                 return igb_msix_setup(sc);
3570
3571         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3572             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3573             sc, &sc->intr_tag, &sc->main_serialize);
3574         if (error) {
3575                 device_printf(sc->dev, "Failed to register interrupt handler");
3576                 return error;
3577         }
3578
3579         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3580         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3581
3582         return 0;
3583 }
3584
3585 static void
3586 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3587 {
3588         if (txr->sc->hw.mac.type == e1000_82575) {
3589                 txr->tx_intr_bit = 0;   /* unused */
3590                 switch (txr->me) {
3591                 case 0:
3592                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3593                         break;
3594                 case 1:
3595                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3596                         break;
3597                 case 2:
3598                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3599                         break;
3600                 case 3:
3601                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3602                         break;
3603                 default:
3604                         panic("unsupported # of TX ring, %d\n", txr->me);
3605                 }
3606         } else {
3607                 int intr_bit = *intr_bit0;
3608
3609                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3610                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3611
3612                 *intr_bit0 = intr_bit + 1;
3613         }
3614 }
3615
3616 static void
3617 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3618 {
3619         if (rxr->sc->hw.mac.type == e1000_82575) {
3620                 rxr->rx_intr_bit = 0;   /* unused */
3621                 switch (rxr->me) {
3622                 case 0:
3623                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3624                         break;
3625                 case 1:
3626                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3627                         break;
3628                 case 2:
3629                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3630                         break;
3631                 case 3:
3632                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3633                         break;
3634                 default:
3635                         panic("unsupported # of RX ring, %d\n", rxr->me);
3636                 }
3637         } else {
3638                 int intr_bit = *intr_bit0;
3639
3640                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3641                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3642
3643                 *intr_bit0 = intr_bit + 1;
3644         }
3645 }
3646
3647 static void
3648 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3649 {
3650         struct igb_softc *sc = ifp->if_softc;
3651
3652         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3653             sc->tx_serialize, sc->rx_serialize, slz);
3654 }
3655
3656 static void
3657 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3658 {
3659         struct igb_softc *sc = ifp->if_softc;
3660
3661         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3662             sc->tx_serialize, sc->rx_serialize, slz);
3663 }
3664
3665 static int
3666 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3667 {
3668         struct igb_softc *sc = ifp->if_softc;
3669
3670         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3671             sc->tx_serialize, sc->rx_serialize, slz);
3672 }
3673
3674 #ifdef INVARIANTS
3675
3676 static void
3677 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3678     boolean_t serialized)
3679 {
3680         struct igb_softc *sc = ifp->if_softc;
3681
3682         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3683             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3684 }
3685
3686 #endif  /* INVARIANTS */
3687
3688 static void
3689 igb_set_intr_mask(struct igb_softc *sc)
3690 {
3691         int i;
3692
3693         sc->intr_mask = sc->sts_intr_mask;
3694         for (i = 0; i < sc->rx_ring_inuse; ++i)
3695                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3696         for (i = 0; i < sc->tx_ring_cnt; ++i)
3697                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3698         if (bootverbose)
3699                 device_printf(sc->dev, "intr mask 0x%08x\n", sc->intr_mask);
3700 }
3701
3702 static int
3703 igb_alloc_intr(struct igb_softc *sc)
3704 {
3705         int i, intr_bit, intr_bitmax;
3706         u_int intr_flags;
3707
3708         igb_msix_try_alloc(sc);
3709         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3710                 goto done;
3711
3712         /*
3713          * Allocate MSI/legacy interrupt resource
3714          */
3715         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3716             &sc->intr_rid, &intr_flags);
3717
3718         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3719                 int unshared;
3720
3721                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3722                 if (!unshared) {
3723                         sc->flags |= IGB_FLAG_SHARED_INTR;
3724                         if (bootverbose)
3725                                 device_printf(sc->dev, "IRQ shared\n");
3726                 } else {
3727                         intr_flags &= ~RF_SHAREABLE;
3728                         if (bootverbose)
3729                                 device_printf(sc->dev, "IRQ unshared\n");
3730                 }
3731         }
3732
3733         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3734             &sc->intr_rid, intr_flags);
3735         if (sc->intr_res == NULL) {
3736                 device_printf(sc->dev, "Unable to allocate bus resource: "
3737                     "interrupt\n");
3738                 return ENXIO;
3739         }
3740
3741         /*
3742          * Setup MSI/legacy interrupt mask
3743          */
3744         switch (sc->hw.mac.type) {
3745         case e1000_82575:
3746                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3747                 break;
3748         case e1000_82580:
3749                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3750                 break;
3751         case e1000_i350:
3752                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3753                 break;
3754         case e1000_82576:
3755                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3756                 break;
3757         default:
3758                 intr_bitmax = IGB_MIN_TXRXINT;
3759                 break;
3760         }
3761         intr_bit = 0;
3762         for (i = 0; i < sc->tx_ring_cnt; ++i)
3763                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3764         for (i = 0; i < sc->rx_ring_cnt; ++i)
3765                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3766         sc->sts_intr_bit = 0;
3767         sc->sts_intr_mask = E1000_EICR_OTHER;
3768
3769         /* Initialize interrupt rate */
3770         sc->intr_rate = IGB_INTR_RATE;
3771 done:
3772         igb_set_ring_inuse(sc, FALSE);
3773         igb_set_intr_mask(sc);
3774         return 0;
3775 }
3776
3777 static void
3778 igb_free_intr(struct igb_softc *sc)
3779 {
3780         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3781                 if (sc->intr_res != NULL) {
3782                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3783                             sc->intr_res);
3784                 }
3785                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3786                         pci_release_msi(sc->dev);
3787         } else {
3788                 igb_msix_free(sc, TRUE);
3789         }
3790 }
3791
3792 static void
3793 igb_teardown_intr(struct igb_softc *sc)
3794 {
3795         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3796                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3797         else
3798                 igb_msix_teardown(sc, sc->msix_cnt);
3799 }
3800
3801 static void
3802 igb_msix_try_alloc(struct igb_softc *sc)
3803 {
3804         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3805         int i, x, error;
3806         struct igb_msix_data *msix;
3807         boolean_t aggregate, setup = FALSE;
3808
3809         /*
3810          * Don't enable MSI-X on 82575, see:
3811          * 82575 specification update errata #25
3812          */
3813         if (sc->hw.mac.type == e1000_82575)
3814                 return;
3815
3816         /* Don't enable MSI-X on VF */
3817         if (sc->vf_ifp)
3818                 return;
3819
3820         msix_enable = device_getenv_int(sc->dev, "msix.enable",
3821             igb_msix_enable);
3822         if (!msix_enable)
3823                 return;
3824
3825         msix_cnt = pci_msix_count(sc->dev);
3826 #ifdef IGB_MSIX_DEBUG
3827         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3828 #endif
3829         if (msix_cnt <= 1) {
3830                 /* One MSI-X model does not make sense */
3831                 return;
3832         }
3833
3834         i = 0;
3835         while ((1 << (i + 1)) <= msix_cnt)
3836                 ++i;
3837         msix_cnt2 = 1 << i;
3838
3839         if (bootverbose) {
3840                 device_printf(sc->dev, "MSI-X count %d/%d\n",
3841                     msix_cnt2, msix_cnt);
3842         }
3843
3844         KKASSERT(msix_cnt2 <= msix_cnt);
3845         if (msix_cnt == msix_cnt2) {
3846                 /* We need at least one MSI-X for link status */
3847                 msix_cnt2 >>= 1;
3848                 if (msix_cnt2 <= 1) {
3849                         /* One MSI-X for RX/TX does not make sense */
3850                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
3851                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
3852                         return;
3853                 }
3854                 KKASSERT(msix_cnt > msix_cnt2);
3855
3856                 if (bootverbose) {
3857                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
3858                             msix_cnt2, msix_cnt);
3859                 }
3860         }
3861
3862         sc->rx_ring_msix = sc->rx_ring_cnt;
3863         if (sc->rx_ring_msix > msix_cnt2)
3864                 sc->rx_ring_msix = msix_cnt2;
3865
3866         if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
3867                 /*
3868                  * Independent TX/RX MSI-X
3869                  */
3870                 aggregate = FALSE;
3871                 if (bootverbose)
3872                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
3873                 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
3874         } else {
3875                 /*
3876                  * Aggregate TX/RX MSI-X
3877                  */
3878                 aggregate = TRUE;
3879                 if (bootverbose)
3880                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
3881                 alloc_cnt = msix_cnt2;
3882                 if (alloc_cnt > ncpus2)
3883                         alloc_cnt = ncpus2;
3884                 if (sc->rx_ring_msix > alloc_cnt)
3885                         sc->rx_ring_msix = alloc_cnt;
3886         }
3887         ++alloc_cnt;    /* For link status */
3888
3889         if (bootverbose) {
3890                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
3891                     alloc_cnt, sc->rx_ring_msix);
3892         }
3893
3894         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
3895         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3896             &sc->msix_mem_rid, RF_ACTIVE);
3897         if (sc->msix_mem_res == NULL) {
3898                 device_printf(sc->dev, "Unable to map MSI-X table\n");
3899                 return;
3900         }
3901
3902         sc->msix_cnt = alloc_cnt;
3903         sc->msix_data = kmalloc(sizeof(struct igb_msix_data) * sc->msix_cnt,
3904             M_DEVBUF, M_WAITOK | M_ZERO);
3905         for (x = 0; x < sc->msix_cnt; ++x) {
3906                 msix = &sc->msix_data[x];
3907
3908                 lwkt_serialize_init(&msix->msix_serialize0);
3909                 msix->msix_sc = sc;
3910                 msix->msix_rid = -1;
3911                 msix->msix_vector = x;
3912                 msix->msix_mask = 1 << msix->msix_vector;
3913                 msix->msix_rate = IGB_INTR_RATE;
3914         }
3915
3916         x = 0;
3917         if (!aggregate) {
3918                 int offset, offset_def;
3919
3920                 if (sc->rx_ring_msix == ncpus2) {
3921                         offset = 0;
3922                 } else {
3923                         offset_def = (sc->rx_ring_msix *
3924                             device_get_unit(sc->dev)) % ncpus2;
3925
3926                         offset = device_getenv_int(sc->dev,
3927                             "msix.rxoff", offset_def);
3928                         if (offset >= ncpus2 ||
3929                             offset % sc->rx_ring_msix != 0) {
3930                                 device_printf(sc->dev,
3931                                     "invalid msix.rxoff %d, use %d\n",
3932                                     offset, offset_def);
3933                                 offset = offset_def;
3934                         }
3935                 }
3936
3937                 /* RX rings */
3938                 for (i = 0; i < sc->rx_ring_msix; ++i) {
3939                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3940
3941                         KKASSERT(x < sc->msix_cnt);
3942                         msix = &sc->msix_data[x++];
3943                         rxr->rx_intr_bit = msix->msix_vector;
3944                         rxr->rx_intr_mask = msix->msix_mask;
3945
3946                         msix->msix_serialize = &rxr->rx_serialize;
3947                         msix->msix_func = igb_msix_rx;
3948                         msix->msix_arg = rxr;
3949                         msix->msix_cpuid = i + offset;
3950                         KKASSERT(msix->msix_cpuid < ncpus2);
3951                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
3952                             "%s rx%d", device_get_nameunit(sc->dev), i);
3953                         msix->msix_rate = IGB_MSIX_RX_RATE;
3954                         ksnprintf(msix->msix_rate_desc,
3955                             sizeof(msix->msix_rate_desc),
3956                             "RX%d interrupt rate", i);
3957                 }
3958
3959                 offset_def = device_get_unit(sc->dev) % ncpus2;
3960                 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
3961                 if (offset >= ncpus2) {
3962                         device_printf(sc->dev, "invalid msix.txoff %d, "
3963                             "use %d\n", offset, offset_def);
3964                         offset = offset_def;
3965                 }
3966
3967                 /* TX rings */
3968                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3969                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3970
3971                         KKASSERT(x < sc->msix_cnt);
3972                         msix = &sc->msix_data[x++];
3973                         txr->tx_intr_bit = msix->msix_vector;
3974                         txr->tx_intr_mask = msix->msix_mask;
3975
3976                         msix->msix_serialize = &txr->tx_serialize;
3977                         msix->msix_func = igb_msix_tx;
3978                         msix->msix_arg = txr;
3979                         msix->msix_cpuid = i + offset;
3980                         sc->msix_tx_cpuid = msix->msix_cpuid; /* XXX */
3981                         KKASSERT(msix->msix_cpuid < ncpus2);
3982                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
3983                             "%s tx%d", device_get_nameunit(sc->dev), i);
3984                         msix->msix_rate = IGB_MSIX_TX_RATE;
3985                         ksnprintf(msix->msix_rate_desc,
3986                             sizeof(msix->msix_rate_desc),
3987                             "TX%d interrupt rate", i);
3988                 }
3989         } else {
3990                 /* TODO */
3991                 error = EOPNOTSUPP;
3992                 goto back;
3993         }
3994
3995         /*
3996          * Link status
3997          */
3998         KKASSERT(x < sc->msix_cnt);
3999         msix = &sc->msix_data[x++];
4000         sc->sts_intr_bit = msix->msix_vector;
4001         sc->sts_intr_mask = msix->msix_mask;
4002
4003         msix->msix_serialize = &sc->main_serialize;
4004         msix->msix_func = igb_msix_status;
4005         msix->msix_arg = sc;
4006         msix->msix_cpuid = 0; /* TODO tunable */
4007         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4008             device_get_nameunit(sc->dev));
4009         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4010             "status interrupt rate");
4011
4012         KKASSERT(x == sc->msix_cnt);
4013
4014         error = pci_setup_msix(sc->dev);
4015         if (error) {
4016                 device_printf(sc->dev, "Setup MSI-X failed\n");
4017                 goto back;
4018         }
4019         setup = TRUE;
4020
4021         for (i = 0; i < sc->msix_cnt; ++i) {
4022                 msix = &sc->msix_data[i];
4023
4024                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4025                     &msix->msix_rid, msix->msix_cpuid);
4026                 if (error) {
4027                         device_printf(sc->dev,
4028                             "Unable to allocate MSI-X %d on cpu%d\n",
4029                             msix->msix_vector, msix->msix_cpuid);
4030                         goto back;
4031                 }
4032
4033                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4034                     &msix->msix_rid, RF_ACTIVE);
4035                 if (msix->msix_res == NULL) {
4036                         device_printf(sc->dev,
4037                             "Unable to allocate MSI-X %d resource\n",
4038                             msix->msix_vector);
4039                         error = ENOMEM;
4040                         goto back;
4041                 }
4042         }
4043
4044         pci_enable_msix(sc->dev);
4045         sc->intr_type = PCI_INTR_TYPE_MSIX;
4046 back:
4047         if (error)
4048                 igb_msix_free(sc, setup);
4049 }
4050
4051 static void
4052 igb_msix_free(struct igb_softc *sc, boolean_t setup)
<