2 * Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 *---------------------------------------------------------------------------
27 * i4b_ifpnp_isac.c - i4b Fritz PnP ISAC handler
28 * ---------------------------------------------
30 * $Id: i4b_ifpnp_isac.c,v 1.3 2000/05/29 15:41:41 hm Exp $
31 * $Ust: src/i4b/layer1-nb/ifpnp/i4b_ifpnp_isac.c,v 1.4 2000/04/18 08:03:05 ust Exp $
33 * $FreeBSD: src/sys/i4b/layer1/ifpnp/i4b_ifpnp_isac.c,v 1.4.2.1 2001/08/10 14:08:37 obrien Exp $
34 * $DragonFly: src/sys/net/i4b/layer1/ifpnp/i4b_ifpnp_isac.c,v 1.6 2006/12/22 23:44:56 swildner Exp $
36 * last edit-date: [Mon May 29 15:24:49 2000]
38 *---------------------------------------------------------------------------*/
40 #include "use_ifpnp.h"
46 #include <sys/param.h>
47 #include <sys/systm.h>
49 #include <sys/socket.h>
54 #include <net/i4b/include/machine/i4b_debug.h>
55 #include <net/i4b/include/machine/i4b_ioctl.h>
56 #include <net/i4b/include/machine/i4b_trace.h>
58 #include "../i4b_l1.h"
59 #include "../isic/i4b_isic.h"
60 #include "../isic/i4b_isac.h"
61 #include "../isic/i4b_hscx.h"
63 #include "i4b_ifpnp_ext.h"
65 #include "../../include/i4b_global.h"
66 #include "../../include/i4b_mbuf.h"
68 static u_char ifpnp_isac_exir_hdlr(struct l1_softc *sc, u_char exir);
69 static void ifpnp_isac_ind_hdlr(struct l1_softc *sc, int ind);
71 /*---------------------------------------------------------------------------*
72 * ISAC interrupt service routine
73 *---------------------------------------------------------------------------*/
75 ifpnp_isac_irq(struct l1_softc *sc, int ista)
78 NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
80 if(ista & ISAC_ISTA_EXI) /* extended interrupt */
82 c |= ifpnp_isac_exir_hdlr(sc, ISAC_READ(I_EXIR));
85 if(ista & ISAC_ISTA_RME) /* receive message end */
90 /* get rx status register */
92 rsta = ISAC_READ(I_RSTA);
94 if((rsta & ISAC_RSTA_MASK) != 0x20)
98 if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */
101 NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
104 if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */
107 NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
110 if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */
113 NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
117 NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTA = 0x%02x!", sc->sc_unit, rsta);
119 i4b_Dfreembuf(sc->sc_ibuf);
121 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
127 ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
133 rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
136 rest = ISAC_FIFO_LEN;
138 if(sc->sc_ibuf == NULL)
140 if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
141 sc->sc_ib = sc->sc_ibuf->m_data;
143 panic("ifpnp_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n");
147 if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
149 ISAC_RDFIFO(sc->sc_ib, rest);
152 sc->sc_ibuf->m_pkthdr.len =
153 sc->sc_ibuf->m_len = sc->sc_ilen;
155 if(sc->sc_trace & TRACE_D_RX)
158 hdr.unit = L0IFPNPUNIT(sc->sc_unit);
161 hdr.count = ++sc->sc_trace_dcount;
163 i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
169 (ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
171 i4b_l1_ph_data_ind(L0IFPNPUNIT(sc->sc_unit), sc->sc_ibuf);
175 i4b_Dfreembuf(sc->sc_ibuf);
180 NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
181 i4b_Dfreembuf(sc->sc_ibuf);
182 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
190 if(ista & ISAC_ISTA_RPF) /* receive fifo full */
192 if(sc->sc_ibuf == NULL)
194 if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
195 sc->sc_ib= sc->sc_ibuf->m_data;
197 panic("ifpnp_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
201 if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
203 ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
204 sc->sc_ilen += ISAC_FIFO_LEN;
205 sc->sc_ib += ISAC_FIFO_LEN;
210 NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
211 i4b_Dfreembuf(sc->sc_ibuf);
215 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
219 if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */
221 if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
223 sc->sc_freeflag = sc->sc_freeflag2;
224 sc->sc_obuf = sc->sc_obuf2;
225 sc->sc_op = sc->sc_obuf->m_data;
226 sc->sc_ol = sc->sc_obuf->m_len;
229 kprintf("ob2=%x, op=%x, ol=%d, f=%d #",
239 kprintf("ob=%x, op=%x, ol=%d, f=%d #",
249 ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
251 if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */
253 sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
254 sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
255 c |= ISAC_CMDR_XTF; /* set XTF bit */
261 i4b_Dfreembuf(sc->sc_obuf);
268 c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
273 sc->sc_state &= ~ISAC_TX_ACTIVE;
277 if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */
281 /* get command/indication rx register*/
283 ci = ISAC_READ(I_CIRR);
285 /* if S/Q IRQ, read SQC reg to clr SQC IRQ */
287 if(ci & ISAC_CIRR_SQC)
290 /* C/I code change IRQ (flag already cleared by CIRR read) */
292 if(ci & ISAC_CIRR_CIC0)
293 ifpnp_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
298 ISAC_WRITE(I_CMDR, c);
303 /*---------------------------------------------------------------------------*
304 * ISAC L1 Extended IRQ handler
305 *---------------------------------------------------------------------------*/
307 ifpnp_isac_exir_hdlr(struct l1_softc *sc, u_char exir)
311 if(exir & ISAC_EXIR_XMR)
313 NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
318 if(exir & ISAC_EXIR_XDU)
320 NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
325 if(exir & ISAC_EXIR_PCE)
327 NDBGL1(L1_I_ERR, "EXIRQ Protocol Error");
330 if(exir & ISAC_EXIR_RFO)
332 NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
334 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
337 if(exir & ISAC_EXIR_SOV)
339 NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
342 if(exir & ISAC_EXIR_MOS)
344 NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
347 if(exir & ISAC_EXIR_SAW)
349 /* cannot happen, STCR:TSF is set to 0 */
351 NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
354 if(exir & ISAC_EXIR_WOV)
356 /* cannot happen, STCR:TSF is set to 0 */
358 NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
364 /*---------------------------------------------------------------------------*
365 * ISAC L1 Indication handler
366 *---------------------------------------------------------------------------*/
368 ifpnp_isac_ind_hdlr(struct l1_softc *sc, int ind)
375 NDBGL1(L1_I_CICO, "rx AI8 in state %s", ifpnp_printstate(sc));
376 if(sc->sc_bustyp == BUS_TYPE_IOM2)
377 ifpnp_isac_l1_cmd(sc, CMD_AR8);
379 i4b_l1_mph_status_ind(L0IFPNPUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
382 case ISAC_CIRR_IAI10:
383 NDBGL1(L1_I_CICO, "rx AI10 in state %s", ifpnp_printstate(sc));
384 if(sc->sc_bustyp == BUS_TYPE_IOM2)
385 ifpnp_isac_l1_cmd(sc, CMD_AR10);
387 i4b_l1_mph_status_ind(L0IFPNPUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
391 NDBGL1(L1_I_CICO, "rx RSY in state %s", ifpnp_printstate(sc));
396 NDBGL1(L1_I_CICO, "rx PU in state %s", ifpnp_printstate(sc));
401 NDBGL1(L1_I_CICO, "rx DR in state %s", ifpnp_printstate(sc));
402 ifpnp_isac_l1_cmd(sc, CMD_DIU);
407 NDBGL1(L1_I_CICO, "rx DID in state %s", ifpnp_printstate(sc));
409 i4b_l1_mph_status_ind(L0IFPNPUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
413 NDBGL1(L1_I_CICO, "rx DIS in state %s", ifpnp_printstate(sc));
418 NDBGL1(L1_I_CICO, "rx EI in state %s", ifpnp_printstate(sc));
419 ifpnp_isac_l1_cmd(sc, CMD_DIU);
424 NDBGL1(L1_I_CICO, "rx ARD in state %s", ifpnp_printstate(sc));
429 NDBGL1(L1_I_CICO, "rx TI in state %s", ifpnp_printstate(sc));
434 NDBGL1(L1_I_CICO, "rx ATI in state %s", ifpnp_printstate(sc));
439 NDBGL1(L1_I_CICO, "rx SD in state %s", ifpnp_printstate(sc));
444 NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, ifpnp_printstate(sc));
448 ifpnp_next_state(sc, event);
451 /*---------------------------------------------------------------------------*
452 * execute a layer 1 command
453 *---------------------------------------------------------------------------*/
455 ifpnp_isac_l1_cmd(struct l1_softc *sc, int command)
459 #ifdef I4B_SMP_WORKAROUND
461 /* XXXXXXXXXXXXXXXXXXX */
464 * patch from Wolfgang Helbig:
466 * Here is a patch that makes i4b work on an SMP:
467 * The card (TELES 16.3) didn't interrupt on an SMP machine.
468 * This is a gross workaround, but anyway it works *and* provides
469 * some information as how to finally fix this problem.
472 HSCX_WRITE(0, H_MASK, 0xff);
473 HSCX_WRITE(1, H_MASK, 0xff);
474 ISAC_WRITE(I_MASK, 0xff);
476 HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
477 HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
478 ISAC_WRITE(I_MASK, ISAC_IMASK);
480 /* XXXXXXXXXXXXXXXXXXX */
482 #endif /* I4B_SMP_WORKAROUND */
484 if(command < 0 || command > CMD_ILL)
486 NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, ifpnp_printstate(sc));
490 if(sc->sc_bustyp == BUS_TYPE_IOM2)
498 NDBGL1(L1_I_CICO, "tx TIM in state %s", ifpnp_printstate(sc));
499 cmd |= (ISAC_CIXR_CTIM << 2);
503 NDBGL1(L1_I_CICO, "tx RS in state %s", ifpnp_printstate(sc));
504 cmd |= (ISAC_CIXR_CRS << 2);
508 NDBGL1(L1_I_CICO, "tx AR8 in state %s", ifpnp_printstate(sc));
509 cmd |= (ISAC_CIXR_CAR8 << 2);
513 NDBGL1(L1_I_CICO, "tx AR10 in state %s", ifpnp_printstate(sc));
514 cmd |= (ISAC_CIXR_CAR10 << 2);
518 NDBGL1(L1_I_CICO, "tx DIU in state %s", ifpnp_printstate(sc));
519 cmd |= (ISAC_CIXR_CDIU << 2);
522 ISAC_WRITE(I_CIXR, cmd);
525 /*---------------------------------------------------------------------------*
526 * L1 ISAC initialization
527 *---------------------------------------------------------------------------*/
529 ifpnp_isac_init(struct l1_softc *sc)
531 ISAC_IMASK = 0xff; /* disable all irqs */
533 ISAC_WRITE(I_MASK, ISAC_IMASK);
535 if(sc->sc_bustyp != BUS_TYPE_IOM2)
537 NDBGL1(L1_I_SETUP, "configuring for IOM-1 mode");
539 /* ADF2: Select mode IOM-1 */
540 ISAC_WRITE(I_ADF2, 0x00);
542 /* SPCR: serial port control register:
543 * SPU - software power up = 0
544 * SAC - SIP port high Z
545 * SPM - timing mode 0
546 * TLP - test loop = 0
547 * C1C, C2C - B1 and B2 switched to/from SPa
549 ISAC_WRITE(I_SPCR, ISAC_SPCR_C1C1|ISAC_SPCR_C2C1);
551 /* SQXR: S/Q channel xmit register:
552 * SQIE - S/Q IRQ enable = 0
553 * SQX1-4 - Fa bits = 1
555 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
557 /* ADF1: additional feature reg 1:
559 * TEM - test mode = 0
560 * PFS - pre-filter = 0
561 * CFS - IOM clock/frame always active
562 * FSC1/2 - polarity of 8kHz strobe
563 * ITF - interframe fill = idle
565 ISAC_WRITE(I_ADF1, ISAC_ADF1_FC2); /* ADF1 */
567 /* STCR: sync transfer control reg:
568 * TSF - terminal secific functions = 0
569 * TBA - TIC bus address = 7
572 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
574 /* MODE: Mode Register:
575 * MDSx - transparent mode 2
576 * TMD - timer mode = external
577 * RAC - Receiver enabled
578 * DIMx - digital i/f mode
580 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
584 NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
586 /* ADF2: Select mode IOM-2 */
587 ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
589 /* SPCR: serial port control register:
590 * SPU - software power up = 0
591 * SPM - timing mode 0
592 * TLP - test loop = 0
593 * C1C, C2C - B1 + C1 and B2 + IC2 monitoring
595 ISAC_WRITE(I_SPCR, 0x00);
597 /* SQXR: S/Q channel xmit register:
598 * IDC - IOM direction = 0 (master)
599 * CFS - Config Select = 0 (clock always active)
600 * CI1E - C/I channel 1 IRQ enable = 0
601 * SQIE - S/Q IRQ enable = 0
602 * SQX1-4 - Fa bits = 1
604 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
606 /* ADF1: additional feature reg 1:
608 * TEM - test mode = 0
609 * PFS - pre-filter = 0
610 * IOF - IOM i/f off = 0
611 * ITF - interframe fill = idle
613 ISAC_WRITE(I_ADF1, 0x00);
615 /* STCR: sync transfer control reg:
616 * TSF - terminal secific functions = 0
617 * TBA - TIC bus address = 7
620 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
622 /* MODE: Mode Register:
623 * MDSx - transparent mode 2
624 * TMD - timer mode = external
625 * RAC - Receiver enabled
626 * DIMx - digital i/f mode
628 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
633 * XXX a transmitter reset causes an ISAC tx IRQ which will not
634 * be serviced at attach time under some circumstances leaving
635 * the associated IRQ line on the ISA bus active. This prevents
636 * any further interrupts to be serviced because no low -> high
637 * transition can take place anymore. (-hm)
641 * RRES - HDLC receiver reset
642 * XRES - transmitter reset
644 ISAC_WRITE(I_CMDR, ISAC_CMDR_RRES|ISAC_CMDR_XRES);
648 /* enabled interrupts:
649 * ===================
650 * RME - receive message end
651 * RPF - receive pool full
652 * XPR - transmit pool ready
653 * CISQ - CI or S/Q channel change
654 * EXI - extended interrupt
657 ISAC_IMASK = ISAC_MASK_RSC | /* auto mode only */
658 ISAC_MASK_TIN | /* timer irq */
659 ISAC_MASK_SIN; /* sync xfer irq */
661 ISAC_WRITE(I_MASK, ISAC_IMASK);
666 #endif /* NIFPNP > 0 */