igb: Properly set RX ring in use upon enter/exit polling mode
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_ifpoll.h"
33 #include "opt_igb.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/mbuf.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50
51 #include <net/bpf.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
63
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
69
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
72
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
76
77 #ifdef IGB_RSS_DEBUG
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79 do { \
80         if (sc->rss_debug >= lvl) \
81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82 } while (0)
83 #else   /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
85 #endif  /* IGB_RSS_DEBUG */
86
87 #define IGB_NAME        "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id)  \
89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
91
92 static struct igb_device {
93         uint16_t        vid;
94         uint16_t        did;
95         const char      *desc;
96 } igb_devices[] = {
97         IGB_DEVICE(82575EB_COPPER),
98         IGB_DEVICE(82575EB_FIBER_SERDES),
99         IGB_DEVICE(82575GB_QUAD_COPPER),
100         IGB_DEVICE(82576),
101         IGB_DEVICE(82576_NS),
102         IGB_DEVICE(82576_NS_SERDES),
103         IGB_DEVICE(82576_FIBER),
104         IGB_DEVICE(82576_SERDES),
105         IGB_DEVICE(82576_SERDES_QUAD),
106         IGB_DEVICE(82576_QUAD_COPPER),
107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
108         IGB_DEVICE(82576_VF),
109         IGB_DEVICE(82580_COPPER),
110         IGB_DEVICE(82580_FIBER),
111         IGB_DEVICE(82580_SERDES),
112         IGB_DEVICE(82580_SGMII),
113         IGB_DEVICE(82580_COPPER_DUAL),
114         IGB_DEVICE(82580_QUAD_FIBER),
115         IGB_DEVICE(DH89XXCC_SERDES),
116         IGB_DEVICE(DH89XXCC_SGMII),
117         IGB_DEVICE(DH89XXCC_SFP),
118         IGB_DEVICE(DH89XXCC_BACKPLANE),
119         IGB_DEVICE(I350_COPPER),
120         IGB_DEVICE(I350_FIBER),
121         IGB_DEVICE(I350_SERDES),
122         IGB_DEVICE(I350_SGMII),
123         IGB_DEVICE(I350_VF),
124
125         /* required last entry */
126         IGB_DEVICE_NULL
127 };
128
129 static int      igb_probe(device_t);
130 static int      igb_attach(device_t);
131 static int      igb_detach(device_t);
132 static int      igb_shutdown(device_t);
133 static int      igb_suspend(device_t);
134 static int      igb_resume(device_t);
135
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void     igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
141 static void     igb_add_sysctl(struct igb_softc *);
142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
145 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
146 static int      igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
147 #ifdef IFPOLL_ENABLE
148 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
149 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
150 #endif
151
152 static void     igb_vf_init_stats(struct igb_softc *);
153 static void     igb_reset(struct igb_softc *);
154 static void     igb_update_stats_counters(struct igb_softc *);
155 static void     igb_update_vf_stats_counters(struct igb_softc *);
156 static void     igb_update_link_status(struct igb_softc *);
157 static void     igb_init_tx_unit(struct igb_softc *);
158 static void     igb_init_rx_unit(struct igb_softc *);
159
160 static void     igb_set_vlan(struct igb_softc *);
161 static void     igb_set_multi(struct igb_softc *);
162 static void     igb_set_promisc(struct igb_softc *);
163 static void     igb_disable_promisc(struct igb_softc *);
164
165 static int      igb_alloc_rings(struct igb_softc *);
166 static void     igb_free_rings(struct igb_softc *);
167 static int      igb_create_tx_ring(struct igb_tx_ring *);
168 static int      igb_create_rx_ring(struct igb_rx_ring *);
169 static void     igb_free_tx_ring(struct igb_tx_ring *);
170 static void     igb_free_rx_ring(struct igb_rx_ring *);
171 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
172 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
173 static void     igb_init_tx_ring(struct igb_tx_ring *);
174 static int      igb_init_rx_ring(struct igb_rx_ring *);
175 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
176 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
177 static void     igb_rx_refresh(struct igb_rx_ring *, int);
178
179 static void     igb_stop(struct igb_softc *);
180 static void     igb_init(void *);
181 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
182 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
183 static int      igb_media_change(struct ifnet *);
184 static void     igb_timer(void *);
185 static void     igb_watchdog(struct ifnet *);
186 static void     igb_start(struct ifnet *, struct ifaltq_subque *);
187 #ifdef IFPOLL_ENABLE
188 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
189 static void     igb_npoll_rx(struct ifnet *, void *, int);
190 static void     igb_npoll_tx(struct ifnet *, void *, int);
191 static void     igb_npoll_status(struct ifnet *);
192 #endif
193 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
194 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
195 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
196 #ifdef INVARIANTS
197 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
198                     boolean_t);
199 #endif
200
201 static void     igb_intr(void *);
202 static void     igb_intr_shared(void *);
203 static void     igb_rxeof(struct igb_rx_ring *, int);
204 static void     igb_txeof(struct igb_tx_ring *);
205 static void     igb_set_eitr(struct igb_softc *, int, int);
206 static void     igb_enable_intr(struct igb_softc *);
207 static void     igb_disable_intr(struct igb_softc *);
208 static void     igb_init_unshared_intr(struct igb_softc *);
209 static void     igb_init_intr(struct igb_softc *);
210 static int      igb_setup_intr(struct igb_softc *);
211 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
212 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
213 static void     igb_set_intr_mask(struct igb_softc *);
214 static int      igb_alloc_intr(struct igb_softc *);
215 static void     igb_free_intr(struct igb_softc *);
216 static void     igb_teardown_intr(struct igb_softc *);
217 static void     igb_msix_try_alloc(struct igb_softc *);
218 static void     igb_msix_free(struct igb_softc *, boolean_t);
219 static int      igb_msix_setup(struct igb_softc *);
220 static void     igb_msix_teardown(struct igb_softc *, int);
221 static void     igb_msix_rx(void *);
222 static void     igb_msix_tx(void *);
223 static void     igb_msix_status(void *);
224
225 /* Management and WOL Support */
226 static void     igb_get_mgmt(struct igb_softc *);
227 static void     igb_rel_mgmt(struct igb_softc *);
228 static void     igb_get_hw_control(struct igb_softc *);
229 static void     igb_rel_hw_control(struct igb_softc *);
230 static void     igb_enable_wol(device_t);
231
232 static device_method_t igb_methods[] = {
233         /* Device interface */
234         DEVMETHOD(device_probe,         igb_probe),
235         DEVMETHOD(device_attach,        igb_attach),
236         DEVMETHOD(device_detach,        igb_detach),
237         DEVMETHOD(device_shutdown,      igb_shutdown),
238         DEVMETHOD(device_suspend,       igb_suspend),
239         DEVMETHOD(device_resume,        igb_resume),
240         { 0, 0 }
241 };
242
243 static driver_t igb_driver = {
244         "igb",
245         igb_methods,
246         sizeof(struct igb_softc),
247 };
248
249 static devclass_t igb_devclass;
250
251 DECLARE_DUMMY_MODULE(if_igb);
252 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
253 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
254
255 static int      igb_rxd = IGB_DEFAULT_RXD;
256 static int      igb_txd = IGB_DEFAULT_TXD;
257 static int      igb_rxr = 0;
258 static int      igb_msi_enable = 1;
259 static int      igb_msix_enable = 1;
260 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
261 static int      igb_fc_setting = e1000_fc_full;
262
263 /*
264  * DMA Coalescing, only for i350 - default to off,
265  * this feature is for power savings
266  */
267 static int      igb_dma_coalesce = 0;
268
269 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
270 TUNABLE_INT("hw.igb.txd", &igb_txd);
271 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
272 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
273 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
274 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
275
276 /* i350 specific */
277 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
278 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
279
280 static __inline void
281 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
282 {
283         /* Ignore Checksum bit is set */
284         if (staterr & E1000_RXD_STAT_IXSM)
285                 return;
286
287         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
288             E1000_RXD_STAT_IPCS)
289                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
290
291         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
292                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
293                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
294                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
295                         mp->m_pkthdr.csum_data = htons(0xffff);
296                 }
297         }
298 }
299
300 static __inline struct pktinfo *
301 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
302     uint32_t hash, uint32_t hashtype, uint32_t staterr)
303 {
304         switch (hashtype) {
305         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
306                 pi->pi_netisr = NETISR_IP;
307                 pi->pi_flags = 0;
308                 pi->pi_l3proto = IPPROTO_TCP;
309                 break;
310
311         case E1000_RXDADV_RSSTYPE_IPV4:
312                 if (staterr & E1000_RXD_STAT_IXSM)
313                         return NULL;
314
315                 if ((staterr &
316                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
317                     E1000_RXD_STAT_TCPCS) {
318                         pi->pi_netisr = NETISR_IP;
319                         pi->pi_flags = 0;
320                         pi->pi_l3proto = IPPROTO_UDP;
321                         break;
322                 }
323                 /* FALL THROUGH */
324         default:
325                 return NULL;
326         }
327
328         m->m_flags |= M_HASH;
329         m->m_pkthdr.hash = toeplitz_hash(hash);
330         return pi;
331 }
332
333 static int
334 igb_probe(device_t dev)
335 {
336         const struct igb_device *d;
337         uint16_t vid, did;
338
339         vid = pci_get_vendor(dev);
340         did = pci_get_device(dev);
341
342         for (d = igb_devices; d->desc != NULL; ++d) {
343                 if (vid == d->vid && did == d->did) {
344                         device_set_desc(dev, d->desc);
345                         return 0;
346                 }
347         }
348         return ENXIO;
349 }
350
351 static int
352 igb_attach(device_t dev)
353 {
354         struct igb_softc *sc = device_get_softc(dev);
355         uint16_t eeprom_data;
356         int error = 0, i, j, ring_max;
357 #ifdef IFPOLL_ENABLE
358         int offset, offset_def;
359 #endif
360
361 #ifdef notyet
362         /* SYSCTL stuff */
363         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
364             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
365             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
366             igb_sysctl_nvm_info, "I", "NVM Information");
367         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
368             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
369             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
370             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
371 #endif
372
373         callout_init_mp(&sc->timer);
374         lwkt_serialize_init(&sc->main_serialize);
375
376         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
377             device_get_unit(dev));
378         sc->dev = sc->osdep.dev = dev;
379
380         /*
381          * Determine hardware and mac type
382          */
383         sc->hw.vendor_id = pci_get_vendor(dev);
384         sc->hw.device_id = pci_get_device(dev);
385         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
386         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
387         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
388
389         if (e1000_set_mac_type(&sc->hw))
390                 return ENXIO;
391
392         /* Are we a VF device? */
393         if (sc->hw.mac.type == e1000_vfadapt ||
394             sc->hw.mac.type == e1000_vfadapt_i350)
395                 sc->vf_ifp = 1;
396         else
397                 sc->vf_ifp = 0;
398
399         /*
400          * Configure total supported RX/TX ring count
401          */
402         switch (sc->hw.mac.type) {
403         case e1000_82575:
404                 ring_max = IGB_MAX_RING_82575;
405                 break;
406         case e1000_82580:
407                 ring_max = IGB_MAX_RING_82580;
408                 break;
409         case e1000_i350:
410                 ring_max = IGB_MAX_RING_I350;
411                 break;
412         case e1000_82576:
413                 ring_max = IGB_MAX_RING_82576;
414                 break;
415         default:
416                 ring_max = IGB_MIN_RING;
417                 break;
418         }
419         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
420         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
421 #ifdef IGB_RSS_DEBUG
422         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
423 #endif
424         sc->rx_ring_inuse = sc->rx_ring_cnt;
425         sc->tx_ring_cnt = 1; /* XXX */
426
427         if (sc->hw.mac.type == e1000_82575)
428                 sc->flags |= IGB_FLAG_TSO_IPLEN0;
429
430         /* Enable bus mastering */
431         pci_enable_busmaster(dev);
432
433         /*
434          * Allocate IO memory
435          */
436         sc->mem_rid = PCIR_BAR(0);
437         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
438             RF_ACTIVE);
439         if (sc->mem_res == NULL) {
440                 device_printf(dev, "Unable to allocate bus resource: memory\n");
441                 error = ENXIO;
442                 goto failed;
443         }
444         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
445         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
446
447         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
448
449         /* Save PCI command register for Shared Code */
450         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
451         sc->hw.back = &sc->osdep;
452
453         /* Do Shared Code initialization */
454         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
455                 device_printf(dev, "Setup of Shared code failed\n");
456                 error = ENXIO;
457                 goto failed;
458         }
459
460         e1000_get_bus_info(&sc->hw);
461
462         sc->hw.mac.autoneg = DO_AUTO_NEG;
463         sc->hw.phy.autoneg_wait_to_complete = FALSE;
464         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
465
466         /* Copper options */
467         if (sc->hw.phy.media_type == e1000_media_type_copper) {
468                 sc->hw.phy.mdix = AUTO_ALL_MODES;
469                 sc->hw.phy.disable_polarity_correction = FALSE;
470                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
471         }
472
473         /* Set the frame limits assuming  standard ethernet sized frames. */
474         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
475
476         /* Allocate RX/TX rings */
477         error = igb_alloc_rings(sc);
478         if (error)
479                 goto failed;
480
481 #ifdef IFPOLL_ENABLE
482         /*
483          * NPOLLING RX CPU offset
484          */
485         if (sc->rx_ring_cnt == ncpus2) {
486                 offset = 0;
487         } else {
488                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
489                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
490                 if (offset >= ncpus2 ||
491                     offset % sc->rx_ring_cnt != 0) {
492                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
493                             offset, offset_def);
494                         offset = offset_def;
495                 }
496         }
497         sc->rx_npoll_off = offset;
498
499         /*
500          * NPOLLING TX CPU offset
501          */
502         offset_def = sc->rx_npoll_off;
503         offset = device_getenv_int(dev, "npoll.txoff", offset_def);
504         if (offset >= ncpus2) {
505                 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
506                     offset, offset_def);
507                 offset = offset_def;
508         }
509         sc->tx_npoll_off = offset;
510 #endif
511
512         /* Allocate interrupt */
513         error = igb_alloc_intr(sc);
514         if (error)
515                 goto failed;
516
517         /*
518          * Setup serializers
519          */
520         i = 0;
521         sc->serializes[i++] = &sc->main_serialize;
522
523         sc->tx_serialize = i;
524         for (j = 0; j < sc->tx_ring_cnt; ++j)
525                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
526
527         sc->rx_serialize = i;
528         for (j = 0; j < sc->rx_ring_cnt; ++j)
529                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
530
531         sc->serialize_cnt = i;
532         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
533
534         /* Allocate the appropriate stats memory */
535         if (sc->vf_ifp) {
536                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
537                     M_WAITOK | M_ZERO);
538                 igb_vf_init_stats(sc);
539         } else {
540                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
541                     M_WAITOK | M_ZERO);
542         }
543
544         /* Allocate multicast array memory. */
545         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
546             M_DEVBUF, M_WAITOK);
547
548         /* Some adapter-specific advanced features */
549         if (sc->hw.mac.type >= e1000_i350) {
550 #ifdef notyet
551                 igb_set_sysctl_value(adapter, "dma_coalesce",
552                     "configure dma coalesce",
553                     &adapter->dma_coalesce, igb_dma_coalesce);
554                 igb_set_sysctl_value(adapter, "eee_disabled",
555                     "enable Energy Efficient Ethernet",
556                     &adapter->hw.dev_spec._82575.eee_disable,
557                     igb_eee_disabled);
558 #else
559                 sc->dma_coalesce = igb_dma_coalesce;
560                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
561 #endif
562                 e1000_set_eee_i350(&sc->hw);
563         }
564
565         /*
566          * Start from a known state, this is important in reading the nvm and
567          * mac from that.
568          */
569         e1000_reset_hw(&sc->hw);
570
571         /* Make sure we have a good EEPROM before we read from it */
572         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
573                 /*
574                  * Some PCI-E parts fail the first check due to
575                  * the link being in sleep state, call it again,
576                  * if it fails a second time its a real issue.
577                  */
578                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
579                         device_printf(dev,
580                             "The EEPROM Checksum Is Not Valid\n");
581                         error = EIO;
582                         goto failed;
583                 }
584         }
585
586         /* Copy the permanent MAC address out of the EEPROM */
587         if (e1000_read_mac_addr(&sc->hw) < 0) {
588                 device_printf(dev, "EEPROM read error while reading MAC"
589                     " address\n");
590                 error = EIO;
591                 goto failed;
592         }
593         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
594                 device_printf(dev, "Invalid MAC address\n");
595                 error = EIO;
596                 goto failed;
597         }
598
599         /* Setup OS specific network interface */
600         igb_setup_ifp(sc);
601
602         /* Add sysctl tree, must after igb_setup_ifp() */
603         igb_add_sysctl(sc);
604
605         /* Now get a good starting state */
606         igb_reset(sc);
607
608         /* Initialize statistics */
609         igb_update_stats_counters(sc);
610
611         sc->hw.mac.get_link_status = 1;
612         igb_update_link_status(sc);
613
614         /* Indicate SOL/IDER usage */
615         if (e1000_check_reset_block(&sc->hw)) {
616                 device_printf(dev,
617                     "PHY reset is blocked due to SOL/IDER session.\n");
618         }
619
620         /* Determine if we have to control management hardware */
621         if (e1000_enable_mng_pass_thru(&sc->hw))
622                 sc->flags |= IGB_FLAG_HAS_MGMT;
623
624         /*
625          * Setup Wake-on-Lan
626          */
627         /* APME bit in EEPROM is mapped to WUC.APME */
628         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
629         if (eeprom_data)
630                 sc->wol = E1000_WUFC_MAG;
631         /* XXX disable WOL */
632         sc->wol = 0; 
633
634 #ifdef notyet
635         /* Register for VLAN events */
636         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
637              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
638         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
639              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
640 #endif
641
642 #ifdef notyet
643         igb_add_hw_stats(adapter);
644 #endif
645
646         error = igb_setup_intr(sc);
647         if (error) {
648                 ether_ifdetach(&sc->arpcom.ac_if);
649                 goto failed;
650         }
651
652         for (i = 0; i < sc->tx_ring_cnt; ++i) {
653                 struct ifaltq_subque *ifsq =
654                     ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
655                 struct igb_tx_ring *txr = &sc->tx_rings[i];
656
657                 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
658                 ifsq_set_priv(ifsq, txr);
659                 txr->ifsq = ifsq;
660         }
661
662         return 0;
663
664 failed:
665         igb_detach(dev);
666         return error;
667 }
668
669 static int
670 igb_detach(device_t dev)
671 {
672         struct igb_softc *sc = device_get_softc(dev);
673
674         if (device_is_attached(dev)) {
675                 struct ifnet *ifp = &sc->arpcom.ac_if;
676
677                 ifnet_serialize_all(ifp);
678
679                 igb_stop(sc);
680
681                 e1000_phy_hw_reset(&sc->hw);
682
683                 /* Give control back to firmware */
684                 igb_rel_mgmt(sc);
685                 igb_rel_hw_control(sc);
686
687                 if (sc->wol) {
688                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
689                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
690                         igb_enable_wol(dev);
691                 }
692
693                 igb_teardown_intr(sc);
694
695                 ifnet_deserialize_all(ifp);
696
697                 ether_ifdetach(ifp);
698         } else if (sc->mem_res != NULL) {
699                 igb_rel_hw_control(sc);
700         }
701         bus_generic_detach(dev);
702
703         if (sc->sysctl_tree != NULL)
704                 sysctl_ctx_free(&sc->sysctl_ctx);
705
706         igb_free_intr(sc);
707
708         if (sc->msix_mem_res != NULL) {
709                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
710                     sc->msix_mem_res);
711         }
712         if (sc->mem_res != NULL) {
713                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
714                     sc->mem_res);
715         }
716
717         igb_free_rings(sc);
718
719         if (sc->mta != NULL)
720                 kfree(sc->mta, M_DEVBUF);
721         if (sc->stats != NULL)
722                 kfree(sc->stats, M_DEVBUF);
723
724         return 0;
725 }
726
727 static int
728 igb_shutdown(device_t dev)
729 {
730         return igb_suspend(dev);
731 }
732
733 static int
734 igb_suspend(device_t dev)
735 {
736         struct igb_softc *sc = device_get_softc(dev);
737         struct ifnet *ifp = &sc->arpcom.ac_if;
738
739         ifnet_serialize_all(ifp);
740
741         igb_stop(sc);
742
743         igb_rel_mgmt(sc);
744         igb_rel_hw_control(sc);
745
746         if (sc->wol) {
747                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
748                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
749                 igb_enable_wol(dev);
750         }
751
752         ifnet_deserialize_all(ifp);
753
754         return bus_generic_suspend(dev);
755 }
756
757 static int
758 igb_resume(device_t dev)
759 {
760         struct igb_softc *sc = device_get_softc(dev);
761         struct ifnet *ifp = &sc->arpcom.ac_if;
762         int i;
763
764         ifnet_serialize_all(ifp);
765
766         igb_init(sc);
767         igb_get_mgmt(sc);
768
769         for (i = 0; i < sc->tx_ring_cnt; ++i)
770                 ifsq_devstart(sc->tx_rings[i].ifsq);
771
772         ifnet_deserialize_all(ifp);
773
774         return bus_generic_resume(dev);
775 }
776
777 static int
778 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
779 {
780         struct igb_softc *sc = ifp->if_softc;
781         struct ifreq *ifr = (struct ifreq *)data;
782         int max_frame_size, mask, reinit;
783         int error = 0;
784
785         ASSERT_IFNET_SERIALIZED_ALL(ifp);
786
787         switch (command) {
788         case SIOCSIFMTU:
789                 max_frame_size = 9234;
790                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
791                     ETHER_CRC_LEN) {
792                         error = EINVAL;
793                         break;
794                 }
795
796                 ifp->if_mtu = ifr->ifr_mtu;
797                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
798                     ETHER_CRC_LEN;
799
800                 if (ifp->if_flags & IFF_RUNNING)
801                         igb_init(sc);
802                 break;
803
804         case SIOCSIFFLAGS:
805                 if (ifp->if_flags & IFF_UP) {
806                         if (ifp->if_flags & IFF_RUNNING) {
807                                 if ((ifp->if_flags ^ sc->if_flags) &
808                                     (IFF_PROMISC | IFF_ALLMULTI)) {
809                                         igb_disable_promisc(sc);
810                                         igb_set_promisc(sc);
811                                 }
812                         } else {
813                                 igb_init(sc);
814                         }
815                 } else if (ifp->if_flags & IFF_RUNNING) {
816                         igb_stop(sc);
817                 }
818                 sc->if_flags = ifp->if_flags;
819                 break;
820
821         case SIOCADDMULTI:
822         case SIOCDELMULTI:
823                 if (ifp->if_flags & IFF_RUNNING) {
824                         igb_disable_intr(sc);
825                         igb_set_multi(sc);
826 #ifdef IFPOLL_ENABLE
827                         if (!(ifp->if_flags & IFF_NPOLLING))
828 #endif
829                                 igb_enable_intr(sc);
830                 }
831                 break;
832
833         case SIOCSIFMEDIA:
834                 /*
835                  * As the speed/duplex settings are being
836                  * changed, we need toreset the PHY.
837                  */
838                 sc->hw.phy.reset_disable = FALSE;
839
840                 /* Check SOL/IDER usage */
841                 if (e1000_check_reset_block(&sc->hw)) {
842                         if_printf(ifp, "Media change is "
843                             "blocked due to SOL/IDER session.\n");
844                         break;
845                 }
846                 /* FALL THROUGH */
847
848         case SIOCGIFMEDIA:
849                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
850                 break;
851
852         case SIOCSIFCAP:
853                 reinit = 0;
854                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
855                 if (mask & IFCAP_RXCSUM) {
856                         ifp->if_capenable ^= IFCAP_RXCSUM;
857                         reinit = 1;
858                 }
859                 if (mask & IFCAP_VLAN_HWTAGGING) {
860                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
861                         reinit = 1;
862                 }
863                 if (mask & IFCAP_TXCSUM) {
864                         ifp->if_capenable ^= IFCAP_TXCSUM;
865                         if (ifp->if_capenable & IFCAP_TXCSUM)
866                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
867                         else
868                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
869                 }
870                 if (mask & IFCAP_TSO) {
871                         ifp->if_capenable ^= IFCAP_TSO;
872                         if (ifp->if_capenable & IFCAP_TSO)
873                                 ifp->if_hwassist |= CSUM_TSO;
874                         else
875                                 ifp->if_hwassist &= ~CSUM_TSO;
876                 }
877                 if (mask & IFCAP_RSS)
878                         ifp->if_capenable ^= IFCAP_RSS;
879                 if (reinit && (ifp->if_flags & IFF_RUNNING))
880                         igb_init(sc);
881                 break;
882
883         default:
884                 error = ether_ioctl(ifp, command, data);
885                 break;
886         }
887         return error;
888 }
889
890 static void
891 igb_init(void *xsc)
892 {
893         struct igb_softc *sc = xsc;
894         struct ifnet *ifp = &sc->arpcom.ac_if;
895         boolean_t polling;
896         int i;
897
898         ASSERT_IFNET_SERIALIZED_ALL(ifp);
899
900         igb_stop(sc);
901
902         /* Get the latest mac address, User can use a LAA */
903         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
904
905         /* Put the address into the Receive Address Array */
906         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
907
908         igb_reset(sc);
909         igb_update_link_status(sc);
910
911         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
912
913         /* Configure for OS presence */
914         igb_get_mgmt(sc);
915
916         polling = FALSE;
917 #ifdef IFPOLL_ENABLE
918         if (ifp->if_flags & IFF_NPOLLING)
919                 polling = TRUE;
920 #endif
921
922         /* Configured used RX/TX rings */
923         igb_set_ring_inuse(sc, polling);
924
925         /* Initialize interrupt */
926         igb_init_intr(sc);
927
928         /* Prepare transmit descriptors and buffers */
929         for (i = 0; i < sc->tx_ring_cnt; ++i)
930                 igb_init_tx_ring(&sc->tx_rings[i]);
931         igb_init_tx_unit(sc);
932
933         /* Setup Multicast table */
934         igb_set_multi(sc);
935
936 #if 0
937         /*
938          * Figure out the desired mbuf pool
939          * for doing jumbo/packetsplit
940          */
941         if (adapter->max_frame_size <= 2048)
942                 adapter->rx_mbuf_sz = MCLBYTES;
943         else if (adapter->max_frame_size <= 4096)
944                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
945         else
946                 adapter->rx_mbuf_sz = MJUM9BYTES;
947 #endif
948
949         /* Prepare receive descriptors and buffers */
950         for (i = 0; i < sc->rx_ring_inuse; ++i) {
951                 int error;
952
953                 error = igb_init_rx_ring(&sc->rx_rings[i]);
954                 if (error) {
955                         if_printf(ifp, "Could not setup receive structures\n");
956                         igb_stop(sc);
957                         return;
958                 }
959         }
960         igb_init_rx_unit(sc);
961
962         /* Enable VLAN support */
963         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
964                 igb_set_vlan(sc);
965
966         /* Don't lose promiscuous settings */
967         igb_set_promisc(sc);
968
969         ifp->if_flags |= IFF_RUNNING;
970         for (i = 0; i < sc->tx_ring_cnt; ++i)
971                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
972
973         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
974                 sc->timer_cpuid = 0; /* XXX fixed */
975         else
976                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
977         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
978         e1000_clear_hw_cntrs_base_generic(&sc->hw);
979
980         /* This clears any pending interrupts */
981         E1000_READ_REG(&sc->hw, E1000_ICR);
982
983         /*
984          * Only enable interrupts if we are not polling, make sure
985          * they are off otherwise.
986          */
987         if (polling) {
988                 igb_disable_intr(sc);
989         } else {
990                 igb_enable_intr(sc);
991                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
992         }
993
994         /* Set Energy Efficient Ethernet */
995         e1000_set_eee_i350(&sc->hw);
996
997         /* Don't reset the phy next time init gets called */
998         sc->hw.phy.reset_disable = TRUE;
999 }
1000
1001 static void
1002 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1003 {
1004         struct igb_softc *sc = ifp->if_softc;
1005         u_char fiber_type = IFM_1000_SX;
1006
1007         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1008
1009         igb_update_link_status(sc);
1010
1011         ifmr->ifm_status = IFM_AVALID;
1012         ifmr->ifm_active = IFM_ETHER;
1013
1014         if (!sc->link_active)
1015                 return;
1016
1017         ifmr->ifm_status |= IFM_ACTIVE;
1018
1019         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1020             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1021                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1022         } else {
1023                 switch (sc->link_speed) {
1024                 case 10:
1025                         ifmr->ifm_active |= IFM_10_T;
1026                         break;
1027
1028                 case 100:
1029                         ifmr->ifm_active |= IFM_100_TX;
1030                         break;
1031
1032                 case 1000:
1033                         ifmr->ifm_active |= IFM_1000_T;
1034                         break;
1035                 }
1036                 if (sc->link_duplex == FULL_DUPLEX)
1037                         ifmr->ifm_active |= IFM_FDX;
1038                 else
1039                         ifmr->ifm_active |= IFM_HDX;
1040         }
1041 }
1042
1043 static int
1044 igb_media_change(struct ifnet *ifp)
1045 {
1046         struct igb_softc *sc = ifp->if_softc;
1047         struct ifmedia *ifm = &sc->media;
1048
1049         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1050
1051         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1052                 return EINVAL;
1053
1054         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1055         case IFM_AUTO:
1056                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1057                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1058                 break;
1059
1060         case IFM_1000_LX:
1061         case IFM_1000_SX:
1062         case IFM_1000_T:
1063                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1064                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1065                 break;
1066
1067         case IFM_100_TX:
1068                 sc->hw.mac.autoneg = FALSE;
1069                 sc->hw.phy.autoneg_advertised = 0;
1070                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1071                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1072                 else
1073                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1074                 break;
1075
1076         case IFM_10_T:
1077                 sc->hw.mac.autoneg = FALSE;
1078                 sc->hw.phy.autoneg_advertised = 0;
1079                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1080                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1081                 else
1082                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1083                 break;
1084
1085         default:
1086                 if_printf(ifp, "Unsupported media type\n");
1087                 break;
1088         }
1089
1090         igb_init(sc);
1091
1092         return 0;
1093 }
1094
1095 static void
1096 igb_set_promisc(struct igb_softc *sc)
1097 {
1098         struct ifnet *ifp = &sc->arpcom.ac_if;
1099         struct e1000_hw *hw = &sc->hw;
1100         uint32_t reg;
1101
1102         if (sc->vf_ifp) {
1103                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1104                 return;
1105         }
1106
1107         reg = E1000_READ_REG(hw, E1000_RCTL);
1108         if (ifp->if_flags & IFF_PROMISC) {
1109                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1110                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1111         } else if (ifp->if_flags & IFF_ALLMULTI) {
1112                 reg |= E1000_RCTL_MPE;
1113                 reg &= ~E1000_RCTL_UPE;
1114                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1115         }
1116 }
1117
1118 static void
1119 igb_disable_promisc(struct igb_softc *sc)
1120 {
1121         struct e1000_hw *hw = &sc->hw;
1122         uint32_t reg;
1123
1124         if (sc->vf_ifp) {
1125                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1126                 return;
1127         }
1128         reg = E1000_READ_REG(hw, E1000_RCTL);
1129         reg &= ~E1000_RCTL_UPE;
1130         reg &= ~E1000_RCTL_MPE;
1131         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1132 }
1133
1134 static void
1135 igb_set_multi(struct igb_softc *sc)
1136 {
1137         struct ifnet *ifp = &sc->arpcom.ac_if;
1138         struct ifmultiaddr *ifma;
1139         uint32_t reg_rctl = 0;
1140         uint8_t *mta;
1141         int mcnt = 0;
1142
1143         mta = sc->mta;
1144         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1145
1146         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1147                 if (ifma->ifma_addr->sa_family != AF_LINK)
1148                         continue;
1149
1150                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1151                         break;
1152
1153                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1154                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1155                 mcnt++;
1156         }
1157
1158         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1159                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1160                 reg_rctl |= E1000_RCTL_MPE;
1161                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1162         } else {
1163                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1164         }
1165 }
1166
1167 static void
1168 igb_timer(void *xsc)
1169 {
1170         struct igb_softc *sc = xsc;
1171
1172         lwkt_serialize_enter(&sc->main_serialize);
1173
1174         igb_update_link_status(sc);
1175         igb_update_stats_counters(sc);
1176
1177         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1178
1179         lwkt_serialize_exit(&sc->main_serialize);
1180 }
1181
1182 static void
1183 igb_update_link_status(struct igb_softc *sc)
1184 {
1185         struct ifnet *ifp = &sc->arpcom.ac_if;
1186         struct e1000_hw *hw = &sc->hw;
1187         uint32_t link_check, thstat, ctrl;
1188
1189         link_check = thstat = ctrl = 0;
1190
1191         /* Get the cached link value or read for real */
1192         switch (hw->phy.media_type) {
1193         case e1000_media_type_copper:
1194                 if (hw->mac.get_link_status) {
1195                         /* Do the work to read phy */
1196                         e1000_check_for_link(hw);
1197                         link_check = !hw->mac.get_link_status;
1198                 } else {
1199                         link_check = TRUE;
1200                 }
1201                 break;
1202
1203         case e1000_media_type_fiber:
1204                 e1000_check_for_link(hw);
1205                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1206                 break;
1207
1208         case e1000_media_type_internal_serdes:
1209                 e1000_check_for_link(hw);
1210                 link_check = hw->mac.serdes_has_link;
1211                 break;
1212
1213         /* VF device is type_unknown */
1214         case e1000_media_type_unknown:
1215                 e1000_check_for_link(hw);
1216                 link_check = !hw->mac.get_link_status;
1217                 /* Fall thru */
1218         default:
1219                 break;
1220         }
1221
1222         /* Check for thermal downshift or shutdown */
1223         if (hw->mac.type == e1000_i350) {
1224                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1225                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1226         }
1227
1228         /* Now we check if a transition has happened */
1229         if (link_check && sc->link_active == 0) {
1230                 e1000_get_speed_and_duplex(hw, 
1231                     &sc->link_speed, &sc->link_duplex);
1232                 if (bootverbose) {
1233                         if_printf(ifp, "Link is up %d Mbps %s\n",
1234                             sc->link_speed,
1235                             sc->link_duplex == FULL_DUPLEX ?
1236                             "Full Duplex" : "Half Duplex");
1237                 }
1238                 sc->link_active = 1;
1239
1240                 ifp->if_baudrate = sc->link_speed * 1000000;
1241                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1242                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1243                         if_printf(ifp, "Link: thermal downshift\n");
1244                 /* This can sleep */
1245                 ifp->if_link_state = LINK_STATE_UP;
1246                 if_link_state_change(ifp);
1247         } else if (!link_check && sc->link_active == 1) {
1248                 ifp->if_baudrate = sc->link_speed = 0;
1249                 sc->link_duplex = 0;
1250                 if (bootverbose)
1251                         if_printf(ifp, "Link is Down\n");
1252                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1253                     (thstat & E1000_THSTAT_PWR_DOWN))
1254                         if_printf(ifp, "Link: thermal shutdown\n");
1255                 sc->link_active = 0;
1256                 /* This can sleep */
1257                 ifp->if_link_state = LINK_STATE_DOWN;
1258                 if_link_state_change(ifp);
1259         }
1260 }
1261
1262 static void
1263 igb_stop(struct igb_softc *sc)
1264 {
1265         struct ifnet *ifp = &sc->arpcom.ac_if;
1266         int i;
1267
1268         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1269
1270         igb_disable_intr(sc);
1271
1272         callout_stop(&sc->timer);
1273
1274         ifp->if_flags &= ~IFF_RUNNING;
1275         for (i = 0; i < sc->tx_ring_cnt; ++i)
1276                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1277         ifp->if_timer = 0;
1278
1279         e1000_reset_hw(&sc->hw);
1280         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1281
1282         e1000_led_off(&sc->hw);
1283         e1000_cleanup_led(&sc->hw);
1284
1285         for (i = 0; i < sc->tx_ring_cnt; ++i)
1286                 igb_free_tx_ring(&sc->tx_rings[i]);
1287         for (i = 0; i < sc->rx_ring_cnt; ++i)
1288                 igb_free_rx_ring(&sc->rx_rings[i]);
1289 }
1290
1291 static void
1292 igb_reset(struct igb_softc *sc)
1293 {
1294         struct ifnet *ifp = &sc->arpcom.ac_if;
1295         struct e1000_hw *hw = &sc->hw;
1296         struct e1000_fc_info *fc = &hw->fc;
1297         uint32_t pba = 0;
1298         uint16_t hwm;
1299
1300         /* Let the firmware know the OS is in control */
1301         igb_get_hw_control(sc);
1302
1303         /*
1304          * Packet Buffer Allocation (PBA)
1305          * Writing PBA sets the receive portion of the buffer
1306          * the remainder is used for the transmit buffer.
1307          */
1308         switch (hw->mac.type) {
1309         case e1000_82575:
1310                 pba = E1000_PBA_32K;
1311                 break;
1312
1313         case e1000_82576:
1314         case e1000_vfadapt:
1315                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1316                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1317                 break;
1318
1319         case e1000_82580:
1320         case e1000_i350:
1321         case e1000_vfadapt_i350:
1322                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1323                 pba = e1000_rxpbs_adjust_82580(pba);
1324                 break;
1325                 /* XXX pba = E1000_PBA_35K; */
1326
1327         default:
1328                 break;
1329         }
1330
1331         /* Special needs in case of Jumbo frames */
1332         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1333                 uint32_t tx_space, min_tx, min_rx;
1334
1335                 pba = E1000_READ_REG(hw, E1000_PBA);
1336                 tx_space = pba >> 16;
1337                 pba &= 0xffff;
1338
1339                 min_tx = (sc->max_frame_size +
1340                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1341                 min_tx = roundup2(min_tx, 1024);
1342                 min_tx >>= 10;
1343                 min_rx = sc->max_frame_size;
1344                 min_rx = roundup2(min_rx, 1024);
1345                 min_rx >>= 10;
1346                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1347                         pba = pba - (min_tx - tx_space);
1348                         /*
1349                          * if short on rx space, rx wins
1350                          * and must trump tx adjustment
1351                          */
1352                         if (pba < min_rx)
1353                                 pba = min_rx;
1354                 }
1355                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1356         }
1357
1358         /*
1359          * These parameters control the automatic generation (Tx) and
1360          * response (Rx) to Ethernet PAUSE frames.
1361          * - High water mark should allow for at least two frames to be
1362          *   received after sending an XOFF.
1363          * - Low water mark works best when it is very near the high water mark.
1364          *   This allows the receiver to restart by sending XON when it has
1365          *   drained a bit.
1366          */
1367         hwm = min(((pba << 10) * 9 / 10),
1368             ((pba << 10) - 2 * sc->max_frame_size));
1369
1370         if (hw->mac.type < e1000_82576) {
1371                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1372                 fc->low_water = fc->high_water - 8;
1373         } else {
1374                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1375                 fc->low_water = fc->high_water - 16;
1376         }
1377         fc->pause_time = IGB_FC_PAUSE_TIME;
1378         fc->send_xon = TRUE;
1379
1380         /* Issue a global reset */
1381         e1000_reset_hw(hw);
1382         E1000_WRITE_REG(hw, E1000_WUC, 0);
1383
1384         if (e1000_init_hw(hw) < 0)
1385                 if_printf(ifp, "Hardware Initialization Failed\n");
1386
1387         /* Setup DMA Coalescing */
1388         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1389                 uint32_t reg;
1390
1391                 hwm = (pba - 4) << 10;
1392                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1393                     & E1000_DMACR_DMACTHR_MASK;
1394
1395                 /* transition to L0x or L1 if available..*/
1396                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1397
1398                 /* timer = +-1000 usec in 32usec intervals */
1399                 reg |= (1000 >> 5);
1400                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1401
1402                 /* No lower threshold */
1403                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1404
1405                 /* set hwm to PBA -  2 * max frame size */
1406                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1407
1408                 /* Set the interval before transition */
1409                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1410                 reg |= 0x800000FF; /* 255 usec */
1411                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1412
1413                 /* free space in tx packet buffer to wake from DMA coal */
1414                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1415                     (20480 - (2 * sc->max_frame_size)) >> 6);
1416
1417                 /* make low power state decision controlled by DMA coal */
1418                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1419                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1420                     reg | E1000_PCIEMISC_LX_DECISION);
1421                 if_printf(ifp, "DMA Coalescing enabled\n");
1422         }
1423
1424         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1425         e1000_get_phy_info(hw);
1426         e1000_check_for_link(hw);
1427 }
1428
1429 static void
1430 igb_setup_ifp(struct igb_softc *sc)
1431 {
1432         struct ifnet *ifp = &sc->arpcom.ac_if;
1433
1434         ifp->if_softc = sc;
1435         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1436         ifp->if_init = igb_init;
1437         ifp->if_ioctl = igb_ioctl;
1438         ifp->if_start = igb_start;
1439         ifp->if_serialize = igb_serialize;
1440         ifp->if_deserialize = igb_deserialize;
1441         ifp->if_tryserialize = igb_tryserialize;
1442 #ifdef INVARIANTS
1443         ifp->if_serialize_assert = igb_serialize_assert;
1444 #endif
1445 #ifdef IFPOLL_ENABLE
1446         ifp->if_npoll = igb_npoll;
1447 #endif
1448         ifp->if_watchdog = igb_watchdog;
1449
1450         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1451         ifq_set_ready(&ifp->if_snd);
1452
1453         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1454
1455         ifp->if_capabilities =
1456             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1457         if (IGB_ENABLE_HWRSS(sc))
1458                 ifp->if_capabilities |= IFCAP_RSS;
1459         ifp->if_capenable = ifp->if_capabilities;
1460         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1461
1462         /*
1463          * Tell the upper layer(s) we support long frames
1464          */
1465         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1466
1467         /*
1468          * Specify the media types supported by this adapter and register
1469          * callbacks to update media and link information
1470          */
1471         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1472         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1473             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1474                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1475                     0, NULL);
1476                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1477         } else {
1478                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1479                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1480                     0, NULL);
1481                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1482                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1483                     0, NULL);
1484                 if (sc->hw.phy.type != e1000_phy_ife) {
1485                         ifmedia_add(&sc->media,
1486                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1487                         ifmedia_add(&sc->media,
1488                             IFM_ETHER | IFM_1000_T, 0, NULL);
1489                 }
1490         }
1491         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1492         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1493 }
1494
1495 static void
1496 igb_add_sysctl(struct igb_softc *sc)
1497 {
1498         char node[32];
1499         int i;
1500
1501         sysctl_ctx_init(&sc->sysctl_ctx);
1502         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1503             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1504             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1505         if (sc->sysctl_tree == NULL) {
1506                 device_printf(sc->dev, "can't add sysctl node\n");
1507                 return;
1508         }
1509
1510         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1511             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1512         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1513             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1514             "# of RX rings used");
1515         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1516             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1517             "# of RX descs");
1518         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1519             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1520             "# of TX descs");
1521
1522         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1523                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1524                     SYSCTL_CHILDREN(sc->sysctl_tree),
1525                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1526                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1527         } else {
1528                 for (i = 0; i < sc->msix_cnt; ++i) {
1529                         struct igb_msix_data *msix = &sc->msix_data[i];
1530
1531                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1532                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1533                             SYSCTL_CHILDREN(sc->sysctl_tree),
1534                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1535                             msix, 0, igb_sysctl_msix_rate, "I",
1536                             msix->msix_rate_desc);
1537                 }
1538         }
1539
1540         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1541             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1542             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1543             "# of segments per TX interrupt");
1544
1545         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1546             OID_AUTO, "tx_wreg_nsegs", CTLFLAG_RW,
1547             &sc->tx_rings[0].wreg_nsegs, 0,
1548             "# of segments before write to hardare register");
1549
1550 #ifdef IFPOLL_ENABLE
1551         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1552             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1553             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1554         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1555             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1556             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1557 #endif
1558
1559 #ifdef IGB_RSS_DEBUG
1560         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1561             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1562             "RSS debug level");
1563 #endif
1564         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1565 #ifdef IGB_RSS_DEBUG
1566                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1567                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1568                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1569                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1570 #endif
1571                 ksnprintf(node, sizeof(node), "rx%d_wreg", i);
1572                 SYSCTL_ADD_INT(&sc->sysctl_ctx,
1573                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1574                     CTLFLAG_RW, &sc->rx_rings[i].rx_wreg, 0,
1575                     "# of segments before write to hardare register");
1576         }
1577 }
1578
1579 static int
1580 igb_alloc_rings(struct igb_softc *sc)
1581 {
1582         int error, i;
1583
1584         /*
1585          * Create top level busdma tag
1586          */
1587         error = bus_dma_tag_create(NULL, 1, 0,
1588             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1589             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1590             &sc->parent_tag);
1591         if (error) {
1592                 device_printf(sc->dev, "could not create top level DMA tag\n");
1593                 return error;
1594         }
1595
1596         /*
1597          * Allocate TX descriptor rings and buffers
1598          */
1599         sc->tx_rings = kmalloc_cachealign(
1600             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1601             M_DEVBUF, M_WAITOK | M_ZERO);
1602         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1603                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1604
1605                 /* Set up some basics */
1606                 txr->sc = sc;
1607                 txr->me = i;
1608                 lwkt_serialize_init(&txr->tx_serialize);
1609
1610                 error = igb_create_tx_ring(txr);
1611                 if (error)
1612                         return error;
1613         }
1614
1615         /*
1616          * Allocate RX descriptor rings and buffers
1617          */ 
1618         sc->rx_rings = kmalloc_cachealign(
1619             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1620             M_DEVBUF, M_WAITOK | M_ZERO);
1621         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1622                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1623
1624                 /* Set up some basics */
1625                 rxr->sc = sc;
1626                 rxr->me = i;
1627                 lwkt_serialize_init(&rxr->rx_serialize);
1628
1629                 error = igb_create_rx_ring(rxr);
1630                 if (error)
1631                         return error;
1632         }
1633
1634         return 0;
1635 }
1636
1637 static void
1638 igb_free_rings(struct igb_softc *sc)
1639 {
1640         int i;
1641
1642         if (sc->tx_rings != NULL) {
1643                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1644                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1645
1646                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1647                 }
1648                 kfree(sc->tx_rings, M_DEVBUF);
1649         }
1650
1651         if (sc->rx_rings != NULL) {
1652                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1653                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1654
1655                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1656                 }
1657                 kfree(sc->rx_rings, M_DEVBUF);
1658         }
1659 }
1660
1661 static int
1662 igb_create_tx_ring(struct igb_tx_ring *txr)
1663 {
1664         int tsize, error, i, ntxd;
1665
1666         /*
1667          * Validate number of transmit descriptors. It must not exceed
1668          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1669          */
1670         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1671         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1672             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1673                 device_printf(txr->sc->dev,
1674                     "Using %d TX descriptors instead of %d!\n",
1675                     IGB_DEFAULT_TXD, ntxd);
1676                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1677         } else {
1678                 txr->num_tx_desc = ntxd;
1679         }
1680
1681         /*
1682          * Allocate TX descriptor ring
1683          */
1684         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1685             IGB_DBA_ALIGN);
1686         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1687             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1688             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1689         if (txr->txdma.dma_vaddr == NULL) {
1690                 device_printf(txr->sc->dev,
1691                     "Unable to allocate TX Descriptor memory\n");
1692                 return ENOMEM;
1693         }
1694         txr->tx_base = txr->txdma.dma_vaddr;
1695         bzero(txr->tx_base, tsize);
1696
1697         tsize = __VM_CACHELINE_ALIGN(
1698             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1699         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1700
1701         /*
1702          * Allocate TX head write-back buffer
1703          */
1704         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1705             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1706             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1707         if (txr->tx_hdr == NULL) {
1708                 device_printf(txr->sc->dev,
1709                     "Unable to allocate TX head write-back buffer\n");
1710                 return ENOMEM;
1711         }
1712
1713         /*
1714          * Create DMA tag for TX buffers
1715          */
1716         error = bus_dma_tag_create(txr->sc->parent_tag,
1717             1, 0,               /* alignment, bounds */
1718             BUS_SPACE_MAXADDR,  /* lowaddr */
1719             BUS_SPACE_MAXADDR,  /* highaddr */
1720             NULL, NULL,         /* filter, filterarg */
1721             IGB_TSO_SIZE,       /* maxsize */
1722             IGB_MAX_SCATTER,    /* nsegments */
1723             PAGE_SIZE,          /* maxsegsize */
1724             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1725             BUS_DMA_ONEBPAGE,   /* flags */
1726             &txr->tx_tag);
1727         if (error) {
1728                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1729                 kfree(txr->tx_buf, M_DEVBUF);
1730                 txr->tx_buf = NULL;
1731                 return error;
1732         }
1733
1734         /*
1735          * Create DMA maps for TX buffers
1736          */
1737         for (i = 0; i < txr->num_tx_desc; ++i) {
1738                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1739
1740                 error = bus_dmamap_create(txr->tx_tag,
1741                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1742                 if (error) {
1743                         device_printf(txr->sc->dev,
1744                             "Unable to create TX DMA map\n");
1745                         igb_destroy_tx_ring(txr, i);
1746                         return error;
1747                 }
1748         }
1749
1750         /*
1751          * Initialize various watermark
1752          */
1753         txr->spare_desc = IGB_TX_SPARE;
1754         txr->intr_nsegs = txr->num_tx_desc / 16;
1755         txr->wreg_nsegs = 8;
1756         txr->oact_hi_desc = txr->num_tx_desc / 2;
1757         txr->oact_lo_desc = txr->num_tx_desc / 8;
1758         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1759                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1760         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1761                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1762
1763         return 0;
1764 }
1765
1766 static void
1767 igb_free_tx_ring(struct igb_tx_ring *txr)
1768 {
1769         int i;
1770
1771         for (i = 0; i < txr->num_tx_desc; ++i) {
1772                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1773
1774                 if (txbuf->m_head != NULL) {
1775                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1776                         m_freem(txbuf->m_head);
1777                         txbuf->m_head = NULL;
1778                 }
1779         }
1780 }
1781
1782 static void
1783 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1784 {
1785         int i;
1786
1787         if (txr->txdma.dma_vaddr != NULL) {
1788                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1789                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1790                     txr->txdma.dma_map);
1791                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1792                 txr->txdma.dma_vaddr = NULL;
1793         }
1794
1795         if (txr->tx_hdr != NULL) {
1796                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1797                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1798                     txr->tx_hdr_dmap);
1799                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1800                 txr->tx_hdr = NULL;
1801         }
1802
1803         if (txr->tx_buf == NULL)
1804                 return;
1805
1806         for (i = 0; i < ndesc; ++i) {
1807                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1808
1809                 KKASSERT(txbuf->m_head == NULL);
1810                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1811         }
1812         bus_dma_tag_destroy(txr->tx_tag);
1813
1814         kfree(txr->tx_buf, M_DEVBUF);
1815         txr->tx_buf = NULL;
1816 }
1817
1818 static void
1819 igb_init_tx_ring(struct igb_tx_ring *txr)
1820 {
1821         /* Clear the old descriptor contents */
1822         bzero(txr->tx_base,
1823             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1824
1825         /* Clear TX head write-back buffer */
1826         *(txr->tx_hdr) = 0;
1827
1828         /* Reset indices */
1829         txr->next_avail_desc = 0;
1830         txr->next_to_clean = 0;
1831         txr->tx_nsegs = 0;
1832
1833         /* Set number of descriptors available */
1834         txr->tx_avail = txr->num_tx_desc;
1835 }
1836
1837 static void
1838 igb_init_tx_unit(struct igb_softc *sc)
1839 {
1840         struct e1000_hw *hw = &sc->hw;
1841         uint32_t tctl;
1842         int i;
1843
1844         /* Setup the Tx Descriptor Rings */
1845         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1846                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1847                 uint64_t bus_addr = txr->txdma.dma_paddr;
1848                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1849                 uint32_t txdctl = 0;
1850                 uint32_t dca_txctrl;
1851
1852                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1853                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1854                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1855                     (uint32_t)(bus_addr >> 32));
1856                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1857                     (uint32_t)bus_addr);
1858
1859                 /* Setup the HW Tx Head and Tail descriptor pointers */
1860                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1861                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1862
1863                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1864                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1865                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1866
1867                 /*
1868                  * Don't set WB_on_EITR:
1869                  * - 82575 does not have it
1870                  * - It almost has no effect on 82576, see:
1871                  *   82576 specification update errata #26
1872                  * - It causes unnecessary bus traffic
1873                  */
1874                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1875                     (uint32_t)(hdr_paddr >> 32));
1876                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1877                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1878
1879                 /*
1880                  * WTHRESH is ignored by the hardware, since header
1881                  * write back mode is used.
1882                  */
1883                 txdctl |= IGB_TX_PTHRESH;
1884                 txdctl |= IGB_TX_HTHRESH << 8;
1885                 txdctl |= IGB_TX_WTHRESH << 16;
1886                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1887                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1888         }
1889
1890         if (sc->vf_ifp)
1891                 return;
1892
1893         e1000_config_collision_dist(hw);
1894
1895         /* Program the Transmit Control Register */
1896         tctl = E1000_READ_REG(hw, E1000_TCTL);
1897         tctl &= ~E1000_TCTL_CT;
1898         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1899             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1900
1901         /* This write will effectively turn on the transmit unit. */
1902         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1903 }
1904
1905 static boolean_t
1906 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1907 {
1908         struct e1000_adv_tx_context_desc *TXD;
1909         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1910         int ehdrlen, ctxd, ip_hlen = 0;
1911         boolean_t offload = TRUE;
1912
1913         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1914                 offload = FALSE;
1915
1916         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1917
1918         ctxd = txr->next_avail_desc;
1919         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1920
1921         /*
1922          * In advanced descriptors the vlan tag must 
1923          * be placed into the context descriptor, thus
1924          * we need to be here just for that setup.
1925          */
1926         if (mp->m_flags & M_VLANTAG) {
1927                 uint16_t vlantag;
1928
1929                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1930                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1931         } else if (!offload) {
1932                 return FALSE;
1933         }
1934
1935         ehdrlen = mp->m_pkthdr.csum_lhlen;
1936         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1937
1938         /* Set the ether header length */
1939         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1940         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1941                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1942                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1943                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1944         }
1945         vlan_macip_lens |= ip_hlen;
1946
1947         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1948         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1949                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1950         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1951                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1952
1953         /* 82575 needs the queue index added */
1954         if (txr->sc->hw.mac.type == e1000_82575)
1955                 mss_l4len_idx = txr->me << 4;
1956
1957         /* Now copy bits into descriptor */
1958         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1959         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1960         TXD->seqnum_seed = htole32(0);
1961         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1962
1963         /* We've consumed the first desc, adjust counters */
1964         if (++ctxd == txr->num_tx_desc)
1965                 ctxd = 0;
1966         txr->next_avail_desc = ctxd;
1967         --txr->tx_avail;
1968
1969         return offload;
1970 }
1971
1972 static void
1973 igb_txeof(struct igb_tx_ring *txr)
1974 {
1975         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1976         int first, hdr, avail;
1977
1978         if (txr->tx_avail == txr->num_tx_desc)
1979                 return;
1980
1981         first = txr->next_to_clean;
1982         hdr = *(txr->tx_hdr);
1983
1984         if (first == hdr)
1985                 return;
1986
1987         avail = txr->tx_avail;
1988         while (first != hdr) {
1989                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1990
1991                 ++avail;
1992                 if (txbuf->m_head) {
1993                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1994                         m_freem(txbuf->m_head);
1995                         txbuf->m_head = NULL;
1996                         ++ifp->if_opackets;
1997                 }
1998                 if (++first == txr->num_tx_desc)
1999                         first = 0;
2000         }
2001         txr->next_to_clean = first;
2002         txr->tx_avail = avail;
2003
2004         /*
2005          * If we have a minimum free, clear OACTIVE
2006          * to tell the stack that it is OK to send packets.
2007          */
2008         if (IGB_IS_NOT_OACTIVE(txr)) {
2009                 ifsq_clr_oactive(txr->ifsq);
2010
2011                 /*
2012                  * We have enough TX descriptors, turn off
2013                  * the watchdog.  We allow small amount of
2014                  * packets (roughly intr_nsegs) pending on
2015                  * the transmit ring.
2016                  */
2017                 ifp->if_timer = 0;
2018         }
2019 }
2020
2021 static int
2022 igb_create_rx_ring(struct igb_rx_ring *rxr)
2023 {
2024         int rsize, i, error, nrxd;
2025
2026         /*
2027          * Validate number of receive descriptors. It must not exceed
2028          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2029          */
2030         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2031         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2032             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2033                 device_printf(rxr->sc->dev,
2034                     "Using %d RX descriptors instead of %d!\n",
2035                     IGB_DEFAULT_RXD, nrxd);
2036                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2037         } else {
2038                 rxr->num_rx_desc = nrxd;
2039         }
2040
2041         /*
2042          * Allocate RX descriptor ring
2043          */
2044         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2045             IGB_DBA_ALIGN);
2046         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2047             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2048             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2049             &rxr->rxdma.dma_paddr);
2050         if (rxr->rxdma.dma_vaddr == NULL) {
2051                 device_printf(rxr->sc->dev,
2052                     "Unable to allocate RxDescriptor memory\n");
2053                 return ENOMEM;
2054         }
2055         rxr->rx_base = rxr->rxdma.dma_vaddr;
2056         bzero(rxr->rx_base, rsize);
2057
2058         rsize = __VM_CACHELINE_ALIGN(
2059             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2060         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2061
2062         /*
2063          * Create DMA tag for RX buffers
2064          */
2065         error = bus_dma_tag_create(rxr->sc->parent_tag,
2066             1, 0,               /* alignment, bounds */
2067             BUS_SPACE_MAXADDR,  /* lowaddr */
2068             BUS_SPACE_MAXADDR,  /* highaddr */
2069             NULL, NULL,         /* filter, filterarg */
2070             MCLBYTES,           /* maxsize */
2071             1,                  /* nsegments */
2072             MCLBYTES,           /* maxsegsize */
2073             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2074             &rxr->rx_tag);
2075         if (error) {
2076                 device_printf(rxr->sc->dev,
2077                     "Unable to create RX payload DMA tag\n");
2078                 kfree(rxr->rx_buf, M_DEVBUF);
2079                 rxr->rx_buf = NULL;
2080                 return error;
2081         }
2082
2083         /*
2084          * Create spare DMA map for RX buffers
2085          */
2086         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2087             &rxr->rx_sparemap);
2088         if (error) {
2089                 device_printf(rxr->sc->dev,
2090                     "Unable to create spare RX DMA maps\n");
2091                 bus_dma_tag_destroy(rxr->rx_tag);
2092                 kfree(rxr->rx_buf, M_DEVBUF);
2093                 rxr->rx_buf = NULL;
2094                 return error;
2095         }
2096
2097         /*
2098          * Create DMA maps for RX buffers
2099          */
2100         for (i = 0; i < rxr->num_rx_desc; i++) {
2101                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2102
2103                 error = bus_dmamap_create(rxr->rx_tag,
2104                     BUS_DMA_WAITOK, &rxbuf->map);
2105                 if (error) {
2106                         device_printf(rxr->sc->dev,
2107                             "Unable to create RX DMA maps\n");
2108                         igb_destroy_rx_ring(rxr, i);
2109                         return error;
2110                 }
2111         }
2112
2113         /*
2114          * Initialize various watermark
2115          */
2116         rxr->rx_wreg = 32;
2117
2118         return 0;
2119 }
2120
2121 static void
2122 igb_free_rx_ring(struct igb_rx_ring *rxr)
2123 {
2124         int i;
2125
2126         for (i = 0; i < rxr->num_rx_desc; ++i) {
2127                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2128
2129                 if (rxbuf->m_head != NULL) {
2130                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2131                         m_freem(rxbuf->m_head);
2132                         rxbuf->m_head = NULL;
2133                 }
2134         }
2135
2136         if (rxr->fmp != NULL)
2137                 m_freem(rxr->fmp);
2138         rxr->fmp = NULL;
2139         rxr->lmp = NULL;
2140 }
2141
2142 static void
2143 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2144 {
2145         int i;
2146
2147         if (rxr->rxdma.dma_vaddr != NULL) {
2148                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2149                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2150                     rxr->rxdma.dma_map);
2151                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2152                 rxr->rxdma.dma_vaddr = NULL;
2153         }
2154
2155         if (rxr->rx_buf == NULL)
2156                 return;
2157
2158         for (i = 0; i < ndesc; ++i) {
2159                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2160
2161                 KKASSERT(rxbuf->m_head == NULL);
2162                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2163         }
2164         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2165         bus_dma_tag_destroy(rxr->rx_tag);
2166
2167         kfree(rxr->rx_buf, M_DEVBUF);
2168         rxr->rx_buf = NULL;
2169 }
2170
2171 static void
2172 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2173 {
2174         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2175         rxd->wb.upper.status_error = 0;
2176 }
2177
2178 static int
2179 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2180 {
2181         struct mbuf *m;
2182         bus_dma_segment_t seg;
2183         bus_dmamap_t map;
2184         struct igb_rx_buf *rxbuf;
2185         int error, nseg;
2186
2187         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2188         if (m == NULL) {
2189                 if (wait) {
2190                         if_printf(&rxr->sc->arpcom.ac_if,
2191                             "Unable to allocate RX mbuf\n");
2192                 }
2193                 return ENOBUFS;
2194         }
2195         m->m_len = m->m_pkthdr.len = MCLBYTES;
2196
2197         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2198                 m_adj(m, ETHER_ALIGN);
2199
2200         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2201             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2202         if (error) {
2203                 m_freem(m);
2204                 if (wait) {
2205                         if_printf(&rxr->sc->arpcom.ac_if,
2206                             "Unable to load RX mbuf\n");
2207                 }
2208                 return error;
2209         }
2210
2211         rxbuf = &rxr->rx_buf[i];
2212         if (rxbuf->m_head != NULL)
2213                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2214
2215         map = rxbuf->map;
2216         rxbuf->map = rxr->rx_sparemap;
2217         rxr->rx_sparemap = map;
2218
2219         rxbuf->m_head = m;
2220         rxbuf->paddr = seg.ds_addr;
2221
2222         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2223         return 0;
2224 }
2225
2226 static int
2227 igb_init_rx_ring(struct igb_rx_ring *rxr)
2228 {
2229         int i;
2230
2231         /* Clear the ring contents */
2232         bzero(rxr->rx_base,
2233             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2234
2235         /* Now replenish the ring mbufs */
2236         for (i = 0; i < rxr->num_rx_desc; ++i) {
2237                 int error;
2238
2239                 error = igb_newbuf(rxr, i, TRUE);
2240                 if (error)
2241                         return error;
2242         }
2243
2244         /* Setup our descriptor indices */
2245         rxr->next_to_check = 0;
2246
2247         rxr->fmp = NULL;
2248         rxr->lmp = NULL;
2249         rxr->discard = FALSE;
2250
2251         return 0;
2252 }
2253
2254 static void
2255 igb_init_rx_unit(struct igb_softc *sc)
2256 {
2257         struct ifnet *ifp = &sc->arpcom.ac_if;
2258         struct e1000_hw *hw = &sc->hw;
2259         uint32_t rctl, rxcsum, srrctl = 0;
2260         int i;
2261
2262         /*
2263          * Make sure receives are disabled while setting
2264          * up the descriptor ring
2265          */
2266         rctl = E1000_READ_REG(hw, E1000_RCTL);
2267         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2268
2269 #if 0
2270         /*
2271         ** Set up for header split
2272         */
2273         if (igb_header_split) {
2274                 /* Use a standard mbuf for the header */
2275                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2276                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2277         } else
2278 #endif
2279                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2280
2281         /*
2282         ** Set up for jumbo frames
2283         */
2284         if (ifp->if_mtu > ETHERMTU) {
2285                 rctl |= E1000_RCTL_LPE;
2286 #if 0
2287                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2288                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2289                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2290                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2291                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2292                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2293                 }
2294                 /* Set maximum packet len */
2295                 psize = adapter->max_frame_size;
2296                 /* are we on a vlan? */
2297                 if (adapter->ifp->if_vlantrunk != NULL)
2298                         psize += VLAN_TAG_SIZE;
2299                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2300 #else
2301                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2302                 rctl |= E1000_RCTL_SZ_2048;
2303 #endif
2304         } else {
2305                 rctl &= ~E1000_RCTL_LPE;
2306                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2307                 rctl |= E1000_RCTL_SZ_2048;
2308         }
2309
2310         /* Setup the Base and Length of the Rx Descriptor Rings */
2311         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2312                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2313                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2314                 uint32_t rxdctl;
2315
2316                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2317                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2318                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2319                     (uint32_t)(bus_addr >> 32));
2320                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2321                     (uint32_t)bus_addr);
2322                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2323                 /* Enable this Queue */
2324                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2325                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2326                 rxdctl &= 0xFFF00000;
2327                 rxdctl |= IGB_RX_PTHRESH;
2328                 rxdctl |= IGB_RX_HTHRESH << 8;
2329                 /*
2330                  * Don't set WTHRESH to a value above 1 on 82576, see:
2331                  * 82576 specification update errata #26
2332                  */
2333                 rxdctl |= IGB_RX_WTHRESH << 16;
2334                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2335         }
2336
2337         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2338         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2339
2340         /*
2341          * Receive Checksum Offload for TCP and UDP
2342          *
2343          * Checksum offloading is also enabled if multiple receive
2344          * queue is to be supported, since we need it to figure out
2345          * fragments.
2346          */
2347         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2348                 /*
2349                  * NOTE:
2350                  * PCSD must be enabled to enable multiple
2351                  * receive queues.
2352                  */
2353                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2354                     E1000_RXCSUM_PCSD;
2355         } else {
2356                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2357                     E1000_RXCSUM_PCSD);
2358         }
2359         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2360
2361         if (IGB_ENABLE_HWRSS(sc)) {
2362                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2363                 uint32_t reta_shift;
2364                 int j, r;
2365
2366                 /*
2367                  * NOTE:
2368                  * When we reach here, RSS has already been disabled
2369                  * in igb_stop(), so we could safely configure RSS key
2370                  * and redirect table.
2371                  */
2372
2373                 /*
2374                  * Configure RSS key
2375                  */
2376                 toeplitz_get_key(key, sizeof(key));
2377                 for (i = 0; i < IGB_NRSSRK; ++i) {
2378                         uint32_t rssrk;
2379
2380                         rssrk = IGB_RSSRK_VAL(key, i);
2381                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2382
2383                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2384                 }
2385
2386                 /*
2387                  * Configure RSS redirect table in following fashion:
2388                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2389                  */
2390                 reta_shift = IGB_RETA_SHIFT;
2391                 if (hw->mac.type == e1000_82575)
2392                         reta_shift = IGB_RETA_SHIFT_82575;
2393
2394                 r = 0;
2395                 for (j = 0; j < IGB_NRETA; ++j) {
2396                         uint32_t reta = 0;
2397
2398                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2399                                 uint32_t q;
2400
2401                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2402                                 reta |= q << (8 * i);
2403                                 ++r;
2404                         }
2405                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2406                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2407                 }
2408
2409                 /*
2410                  * Enable multiple receive queues.
2411                  * Enable IPv4 RSS standard hash functions.
2412                  * Disable RSS interrupt on 82575
2413                  */
2414                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2415                                 E1000_MRQC_ENABLE_RSS_4Q |
2416                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2417                                 E1000_MRQC_RSS_FIELD_IPV4);
2418         }
2419
2420         /* Setup the Receive Control Register */
2421         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2422         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2423             E1000_RCTL_RDMTS_HALF |
2424             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2425         /* Strip CRC bytes. */
2426         rctl |= E1000_RCTL_SECRC;
2427         /* Make sure VLAN Filters are off */
2428         rctl &= ~E1000_RCTL_VFE;
2429         /* Don't store bad packets */
2430         rctl &= ~E1000_RCTL_SBP;
2431
2432         /* Enable Receives */
2433         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2434
2435         /*
2436          * Setup the HW Rx Head and Tail Descriptor Pointers
2437          *   - needs to be after enable
2438          */
2439         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2440                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2441
2442                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2443                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2444         }
2445 }
2446
2447 static void
2448 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2449 {
2450         if (--i < 0)
2451                 i = rxr->num_rx_desc - 1;
2452         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2453 }
2454
2455 static void
2456 igb_rxeof(struct igb_rx_ring *rxr, int count)
2457 {
2458         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2459         union e1000_adv_rx_desc *cur;
2460         uint32_t staterr;
2461         int i, ncoll = 0;
2462
2463         i = rxr->next_to_check;
2464         cur = &rxr->rx_base[i];
2465         staterr = le32toh(cur->wb.upper.status_error);
2466
2467         if ((staterr & E1000_RXD_STAT_DD) == 0)
2468                 return;
2469
2470         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2471                 struct pktinfo *pi = NULL, pi0;
2472                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2473                 struct mbuf *m = NULL;
2474                 boolean_t eop;
2475
2476                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2477                 if (eop)
2478                         --count;
2479
2480                 ++ncoll;
2481                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2482                     !rxr->discard) {
2483                         struct mbuf *mp = rxbuf->m_head;
2484                         uint32_t hash, hashtype;
2485                         uint16_t vlan;
2486                         int len;
2487
2488                         len = le16toh(cur->wb.upper.length);
2489                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2490                             (staterr & E1000_RXDEXT_STATERR_LB))
2491                                 vlan = be16toh(cur->wb.upper.vlan);
2492                         else
2493                                 vlan = le16toh(cur->wb.upper.vlan);
2494
2495                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2496                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2497                             E1000_RXDADV_RSSTYPE_MASK;
2498
2499                         IGB_RSS_DPRINTF(rxr->sc, 10,
2500                             "ring%d, hash 0x%08x, hashtype %u\n",
2501                             rxr->me, hash, hashtype);
2502
2503                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2504                             BUS_DMASYNC_POSTREAD);
2505
2506                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2507                                 ifp->if_iqdrops++;
2508                                 goto discard;
2509                         }
2510
2511                         mp->m_len = len;
2512                         if (rxr->fmp == NULL) {
2513                                 mp->m_pkthdr.len = len;
2514                                 rxr->fmp = mp;
2515                                 rxr->lmp = mp;
2516                         } else {
2517                                 rxr->lmp->m_next = mp;
2518                                 rxr->lmp = rxr->lmp->m_next;
2519                                 rxr->fmp->m_pkthdr.len += len;
2520                         }
2521
2522                         if (eop) {
2523                                 m = rxr->fmp;
2524                                 rxr->fmp = NULL;
2525                                 rxr->lmp = NULL;
2526
2527                                 m->m_pkthdr.rcvif = ifp;
2528                                 ifp->if_ipackets++;
2529
2530                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2531                                         igb_rxcsum(staterr, m);
2532
2533                                 if (staterr & E1000_RXD_STAT_VP) {
2534                                         m->m_pkthdr.ether_vlantag = vlan;
2535                                         m->m_flags |= M_VLANTAG;
2536                                 }
2537
2538                                 if (ifp->if_capenable & IFCAP_RSS) {
2539                                         pi = igb_rssinfo(m, &pi0,
2540                                             hash, hashtype, staterr);
2541                                 }
2542 #ifdef IGB_RSS_DEBUG
2543                                 rxr->rx_packets++;
2544 #endif
2545                         }
2546                 } else {
2547                         ifp->if_ierrors++;
2548 discard:
2549                         igb_setup_rxdesc(cur, rxbuf);
2550                         if (!eop)
2551                                 rxr->discard = TRUE;
2552                         else
2553                                 rxr->discard = FALSE;
2554                         if (rxr->fmp != NULL) {
2555                                 m_freem(rxr->fmp);
2556                                 rxr->fmp = NULL;
2557                                 rxr->lmp = NULL;
2558                         }
2559                         m = NULL;
2560                 }
2561
2562                 if (m != NULL)
2563                         ether_input_pkt(ifp, m, pi);
2564
2565                 /* Advance our pointers to the next descriptor. */
2566                 if (++i == rxr->num_rx_desc)
2567                         i = 0;
2568
2569                 if (ncoll >= rxr->rx_wreg) {
2570                         igb_rx_refresh(rxr, i);
2571                         ncoll = 0;
2572                 }
2573
2574                 cur = &rxr->rx_base[i];
2575                 staterr = le32toh(cur->wb.upper.status_error);
2576         }
2577         rxr->next_to_check = i;
2578
2579         if (ncoll > 0)
2580                 igb_rx_refresh(rxr, i);
2581 }
2582
2583
2584 static void
2585 igb_set_vlan(struct igb_softc *sc)
2586 {
2587         struct e1000_hw *hw = &sc->hw;
2588         uint32_t reg;
2589 #if 0
2590         struct ifnet *ifp = sc->arpcom.ac_if;
2591 #endif
2592
2593         if (sc->vf_ifp) {
2594                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2595                 return;
2596         }
2597
2598         reg = E1000_READ_REG(hw, E1000_CTRL);
2599         reg |= E1000_CTRL_VME;
2600         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2601
2602 #if 0
2603         /* Enable the Filter Table */
2604         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2605                 reg = E1000_READ_REG(hw, E1000_RCTL);
2606                 reg &= ~E1000_RCTL_CFIEN;
2607                 reg |= E1000_RCTL_VFE;
2608                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2609         }
2610 #endif
2611
2612         /* Update the frame size */
2613         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2614             sc->max_frame_size + VLAN_TAG_SIZE);
2615
2616 #if 0
2617         /* Don't bother with table if no vlans */
2618         if ((adapter->num_vlans == 0) ||
2619             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2620                 return;
2621         /*
2622         ** A soft reset zero's out the VFTA, so
2623         ** we need to repopulate it now.
2624         */
2625         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2626                 if (adapter->shadow_vfta[i] != 0) {
2627                         if (adapter->vf_ifp)
2628                                 e1000_vfta_set_vf(hw,
2629                                     adapter->shadow_vfta[i], TRUE);
2630                         else
2631                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2632                                  i, adapter->shadow_vfta[i]);
2633                 }
2634 #endif
2635 }
2636
2637 static void
2638 igb_enable_intr(struct igb_softc *sc)
2639 {
2640         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2641                 lwkt_serialize_handler_enable(&sc->main_serialize);
2642         } else {
2643                 int i;
2644
2645                 for (i = 0; i < sc->msix_cnt; ++i) {
2646                         lwkt_serialize_handler_enable(
2647                             sc->msix_data[i].msix_serialize);
2648                 }
2649         }
2650
2651         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2652                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2653                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2654                 else
2655                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2656                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2657                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2658                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2659         } else {
2660                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2661         }
2662         E1000_WRITE_FLUSH(&sc->hw);
2663 }
2664
2665 static void
2666 igb_disable_intr(struct igb_softc *sc)
2667 {
2668         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2669                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2670                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2671         }
2672         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2673         E1000_WRITE_FLUSH(&sc->hw);
2674
2675         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2676                 lwkt_serialize_handler_disable(&sc->main_serialize);
2677         } else {
2678                 int i;
2679
2680                 for (i = 0; i < sc->msix_cnt; ++i) {
2681                         lwkt_serialize_handler_disable(
2682                             sc->msix_data[i].msix_serialize);
2683                 }
2684         }
2685 }
2686
2687 /*
2688  * Bit of a misnomer, what this really means is
2689  * to enable OS management of the system... aka
2690  * to disable special hardware management features 
2691  */
2692 static void
2693 igb_get_mgmt(struct igb_softc *sc)
2694 {
2695         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2696                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2697                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2698
2699                 /* disable hardware interception of ARP */
2700                 manc &= ~E1000_MANC_ARP_EN;
2701
2702                 /* enable receiving management packets to the host */
2703                 manc |= E1000_MANC_EN_MNG2HOST;
2704                 manc2h |= 1 << 5; /* Mng Port 623 */
2705                 manc2h |= 1 << 6; /* Mng Port 664 */
2706                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2707                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2708         }
2709 }
2710
2711 /*
2712  * Give control back to hardware management controller
2713  * if there is one.
2714  */
2715 static void
2716 igb_rel_mgmt(struct igb_softc *sc)
2717 {
2718         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2719                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2720
2721                 /* Re-enable hardware interception of ARP */
2722                 manc |= E1000_MANC_ARP_EN;
2723                 manc &= ~E1000_MANC_EN_MNG2HOST;
2724
2725                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2726         }
2727 }
2728
2729 /*
2730  * Sets CTRL_EXT:DRV_LOAD bit.
2731  *
2732  * For ASF and Pass Through versions of f/w this means that
2733  * the driver is loaded. 
2734  */
2735 static void
2736 igb_get_hw_control(struct igb_softc *sc)
2737 {
2738         uint32_t ctrl_ext;
2739
2740         if (sc->vf_ifp)
2741                 return;
2742
2743         /* Let firmware know the driver has taken over */
2744         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2745         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2746             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2747 }
2748
2749 /*
2750  * Resets CTRL_EXT:DRV_LOAD bit.
2751  *
2752  * For ASF and Pass Through versions of f/w this means that the
2753  * driver is no longer loaded.
2754  */
2755 static void
2756 igb_rel_hw_control(struct igb_softc *sc)
2757 {
2758         uint32_t ctrl_ext;
2759
2760         if (sc->vf_ifp)
2761                 return;
2762
2763         /* Let firmware taken over control of h/w */
2764         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2765         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2766             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2767 }
2768
2769 static int
2770 igb_is_valid_ether_addr(const uint8_t *addr)
2771 {
2772         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2773
2774         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2775                 return FALSE;
2776         return TRUE;
2777 }
2778
2779 /*
2780  * Enable PCI Wake On Lan capability
2781  */
2782 static void
2783 igb_enable_wol(device_t dev)
2784 {
2785         uint16_t cap, status;
2786         uint8_t id;
2787
2788         /* First find the capabilities pointer*/
2789         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2790
2791         /* Read the PM Capabilities */
2792         id = pci_read_config(dev, cap, 1);
2793         if (id != PCIY_PMG)     /* Something wrong */
2794                 return;
2795
2796         /*
2797          * OK, we have the power capabilities,
2798          * so now get the status register
2799          */
2800         cap += PCIR_POWER_STATUS;
2801         status = pci_read_config(dev, cap, 2);
2802         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2803         pci_write_config(dev, cap, status, 2);
2804 }
2805
2806 static void
2807 igb_update_stats_counters(struct igb_softc *sc)
2808 {
2809         struct e1000_hw *hw = &sc->hw;
2810         struct e1000_hw_stats *stats;
2811         struct ifnet *ifp = &sc->arpcom.ac_if;
2812
2813         /* 
2814          * The virtual function adapter has only a
2815          * small controlled set of stats, do only 
2816          * those and return.
2817          */
2818         if (sc->vf_ifp) {
2819                 igb_update_vf_stats_counters(sc);
2820                 return;
2821         }
2822         stats = sc->stats;
2823
2824         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2825             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2826                 stats->symerrs +=
2827                     E1000_READ_REG(hw,E1000_SYMERRS);
2828                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2829         }
2830
2831         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2832         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2833         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2834         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2835
2836         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2837         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2838         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2839         stats->dc += E1000_READ_REG(hw, E1000_DC);
2840         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2841         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2842         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2843
2844         /*
2845          * For watchdog management we need to know if we have been
2846          * paused during the last interval, so capture that here.
2847          */ 
2848         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2849         stats->xoffrxc += sc->pause_frames;
2850         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2851         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2852         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2853         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2854         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2855         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2856         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2857         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2858         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2859         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2860         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2861         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2862
2863         /* For the 64-bit byte counters the low dword must be read first. */
2864         /* Both registers clear on the read of the high dword */
2865
2866         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2867             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2868         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2869             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2870
2871         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2872         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2873         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2874         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2875         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2876
2877         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2878         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2879
2880         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2881         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2882         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2883         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2884         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2885         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2886         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2887         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2888         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2889         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2890
2891         /* Interrupt Counts */
2892
2893         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2894         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2895         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2896         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2897         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2898         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2899         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2900         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2901         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2902
2903         /* Host to Card Statistics */
2904
2905         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2906         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2907         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2908         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2909         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2910         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2911         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2912         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2913             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2914         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2915             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2916         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2917         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2918         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2919
2920         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2921         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2922         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2923         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2924         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2925         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2926
2927         ifp->if_collisions = stats->colc;
2928
2929         /* Rx Errors */
2930         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2931             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2932
2933         /* Tx Errors */
2934         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2935
2936         /* Driver specific counters */
2937         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2938         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2939         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2940         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2941         sc->packet_buf_alloc_tx =
2942             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2943         sc->packet_buf_alloc_rx =
2944             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2945 }
2946
2947 static void
2948 igb_vf_init_stats(struct igb_softc *sc)
2949 {
2950         struct e1000_hw *hw = &sc->hw;
2951         struct e1000_vf_stats *stats;
2952
2953         stats = sc->stats;
2954         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2955         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2956         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2957         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2958         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2959 }
2960  
2961 static void
2962 igb_update_vf_stats_counters(struct igb_softc *sc)
2963 {
2964         struct e1000_hw *hw = &sc->hw;
2965         struct e1000_vf_stats *stats;
2966
2967         if (sc->link_speed == 0)
2968                 return;
2969
2970         stats = sc->stats;
2971         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2972         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2973         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2974         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2975         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2976 }
2977
2978 #ifdef IFPOLL_ENABLE
2979
2980 static void
2981 igb_npoll_status(struct ifnet *ifp)
2982 {
2983         struct igb_softc *sc = ifp->if_softc;
2984         uint32_t reg_icr;
2985
2986         ASSERT_SERIALIZED(&sc->main_serialize);
2987
2988         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2989         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2990                 sc->hw.mac.get_link_status = 1;
2991                 igb_update_link_status(sc);
2992         }
2993 }
2994
2995 static void
2996 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
2997 {
2998         struct igb_tx_ring *txr = arg;
2999
3000         ASSERT_SERIALIZED(&txr->tx_serialize);
3001
3002         igb_txeof(txr);
3003         if (!ifsq_is_empty(txr->ifsq))
3004                 ifsq_devstart(txr->ifsq);
3005 }
3006
3007 static void
3008 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3009 {
3010         struct igb_rx_ring *rxr = arg;
3011
3012         ASSERT_SERIALIZED(&rxr->rx_serialize);
3013
3014         igb_rxeof(rxr, cycle);
3015 }
3016
3017 static void
3018 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3019 {
3020         struct igb_softc *sc = ifp->if_softc;
3021         int i;
3022
3023         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3024
3025         if (info) {
3026                 int off;
3027
3028                 info->ifpi_status.status_func = igb_npoll_status;
3029                 info->ifpi_status.serializer = &sc->main_serialize;
3030
3031                 off = sc->tx_npoll_off;
3032                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3033                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3034                         int idx = i + off;
3035
3036                         KKASSERT(idx < ncpus2);
3037                         info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3038                         info->ifpi_tx[idx].arg = txr;
3039                         info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3040                         ifsq_set_cpuid(txr->ifsq, idx);
3041                 }
3042
3043                 off = sc->rx_npoll_off;
3044                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3045                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3046                         int idx = i + off;
3047
3048                         KKASSERT(idx < ncpus2);
3049                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3050                         info->ifpi_rx[idx].arg = rxr;
3051                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3052                 }
3053
3054                 if (ifp->if_flags & IFF_RUNNING) {
3055                         if (igb_get_rxring_inuse(sc, TRUE) ==
3056                             sc->rx_ring_inuse)
3057                                 igb_disable_intr(sc);
3058                         else
3059                                 igb_init(sc);
3060                 }
3061         } else {
3062                 if (ifp->if_flags & IFF_RUNNING) {
3063                         if (igb_get_rxring_inuse(sc, FALSE) ==
3064                             sc->rx_ring_inuse)
3065                                 igb_enable_intr(sc);
3066                         else
3067                                 igb_init(sc);
3068                 }
3069
3070                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3071                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3072
3073                         ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3074                 }
3075         }
3076 }
3077
3078 #endif /* IFPOLL_ENABLE */
3079
3080 static void
3081 igb_intr(void *xsc)
3082 {
3083         struct igb_softc *sc = xsc;
3084         struct ifnet *ifp = &sc->arpcom.ac_if;
3085         uint32_t eicr;
3086
3087         ASSERT_SERIALIZED(&sc->main_serialize);
3088
3089         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3090
3091         if (eicr == 0)
3092                 return;
3093
3094         if (ifp->if_flags & IFF_RUNNING) {
3095                 struct igb_tx_ring *txr = &sc->tx_rings[0];
3096                 int i;
3097
3098                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3099                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3100
3101                         if (eicr & rxr->rx_intr_mask) {
3102                                 lwkt_serialize_enter(&rxr->rx_serialize);
3103                                 igb_rxeof(rxr, -1);
3104                                 lwkt_serialize_exit(&rxr->rx_serialize);
3105                         }
3106                 }
3107
3108                 if (eicr & txr->tx_intr_mask) {
3109                         lwkt_serialize_enter(&txr->tx_serialize);
3110                         igb_txeof(txr);
3111                         if (!ifsq_is_empty(txr->ifsq))
3112                                 ifsq_devstart(txr->ifsq);
3113                         lwkt_serialize_exit(&txr->tx_serialize);
3114                 }
3115         }
3116
3117         if (eicr & E1000_EICR_OTHER) {
3118                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3119
3120                 /* Link status change */
3121                 if (icr & E1000_ICR_LSC) {
3122                         sc->hw.mac.get_link_status = 1;
3123                         igb_update_link_status(sc);
3124                 }
3125         }
3126
3127         /*
3128          * Reading EICR has the side effect to clear interrupt mask,
3129          * so all interrupts need to be enabled here.
3130          */
3131         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3132 }
3133
3134 static void
3135 igb_intr_shared(void *xsc)
3136 {
3137         struct igb_softc *sc = xsc;
3138         struct ifnet *ifp = &sc->arpcom.ac_if;
3139         uint32_t reg_icr;
3140
3141         ASSERT_SERIALIZED(&sc->main_serialize);
3142
3143         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3144
3145         /* Hot eject?  */
3146         if (reg_icr == 0xffffffff)
3147                 return;
3148
3149         /* Definitely not our interrupt.  */
3150         if (reg_icr == 0x0)
3151                 return;
3152
3153         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3154                 return;
3155
3156         if (ifp->if_flags & IFF_RUNNING) {
3157                 if (reg_icr &
3158                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3159                         int i;
3160
3161                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3162                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3163
3164                                 lwkt_serialize_enter(&rxr->rx_serialize);
3165                                 igb_rxeof(rxr, -1);
3166                                 lwkt_serialize_exit(&rxr->rx_serialize);
3167                         }
3168                 }
3169
3170                 if (reg_icr & E1000_ICR_TXDW) {
3171                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3172
3173                         lwkt_serialize_enter(&txr->tx_serialize);
3174                         igb_txeof(txr);
3175                         if (!ifsq_is_empty(txr->ifsq))
3176                                 ifsq_devstart(txr->ifsq);
3177                         lwkt_serialize_exit(&txr->tx_serialize);
3178                 }
3179         }
3180
3181         /* Link status change */
3182         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3183                 sc->hw.mac.get_link_status = 1;
3184                 igb_update_link_status(sc);
3185         }
3186
3187         if (reg_icr & E1000_ICR_RXO)
3188                 sc->rx_overruns++;
3189 }
3190
3191 static int
3192 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3193     int *segs_used, int *idx)
3194 {
3195         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3196         bus_dmamap_t map;
3197         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3198         union e1000_adv_tx_desc *txd = NULL;
3199         struct mbuf *m_head = *m_headp;
3200         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3201         int maxsegs, nsegs, i, j, error;
3202         uint32_t hdrlen = 0;
3203
3204         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3205                 error = igb_tso_pullup(txr, m_headp);
3206                 if (error)
3207                         return error;
3208                 m_head = *m_headp;
3209         }
3210
3211         /* Set basic descriptor constants */
3212         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3213         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3214         if (m_head->m_flags & M_VLANTAG)
3215                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3216
3217         /*
3218          * Map the packet for DMA.
3219          */
3220         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3221         tx_buf_mapped = tx_buf;
3222         map = tx_buf->map;
3223
3224         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3225         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3226         if (maxsegs > IGB_MAX_SCATTER)
3227                 maxsegs = IGB_MAX_SCATTER;
3228
3229         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3230             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3231         if (error) {
3232                 if (error == ENOBUFS)
3233                         txr->sc->mbuf_defrag_failed++;
3234                 else
3235                         txr->sc->no_tx_dma_setup++;
3236
3237                 m_freem(*m_headp);
3238                 *m_headp = NULL;
3239                 return error;
3240         }
3241         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3242
3243         m_head = *m_headp;
3244
3245         /*
3246          * Set up the TX context descriptor, if any hardware offloading is
3247          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3248          * TX descriptor.
3249          *
3250          * Unlike these chips' predecessors (em/emx), TX context descriptor
3251          * will _not_ interfere TX data fetching pipelining.
3252          */
3253         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3254                 igb_tso_ctx(txr, m_head, &hdrlen);
3255                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3256                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3257                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3258                 txr->tx_nsegs++;
3259                 (*segs_used)++;
3260         } else if (igb_txcsum_ctx(txr, m_head)) {
3261                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3262                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3263                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3264                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3265                 txr->tx_nsegs++;
3266                 (*segs_used)++;
3267         }
3268
3269         *segs_used += nsegs;
3270         txr->tx_nsegs += nsegs;
3271         if (txr->tx_nsegs >= txr->intr_nsegs) {
3272                 /*
3273                  * Report Status (RS) is turned on every intr_nsegs
3274                  * descriptors (roughly).
3275                  */
3276                 txr->tx_nsegs = 0;
3277                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3278         }
3279
3280         /* Calculate payload length */
3281         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3282             << E1000_ADVTXD_PAYLEN_SHIFT);
3283
3284         /* 82575 needs the queue index added */
3285         if (txr->sc->hw.mac.type == e1000_82575)
3286                 olinfo_status |= txr->me << 4;
3287
3288         /* Set up our transmit descriptors */
3289         i = txr->next_avail_desc;
3290         for (j = 0; j < nsegs; j++) {
3291                 bus_size_t seg_len;
3292                 bus_addr_t seg_addr;
3293
3294                 tx_buf = &txr->tx_buf[i];
3295                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3296                 seg_addr = segs[j].ds_addr;
3297                 seg_len = segs[j].ds_len;
3298
3299                 txd->read.buffer_addr = htole64(seg_addr);
3300                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3301                 txd->read.olinfo_status = htole32(olinfo_status);
3302                 if (++i == txr->num_tx_desc)
3303                         i = 0;
3304                 tx_buf->m_head = NULL;
3305         }
3306
3307         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3308         txr->next_avail_desc = i;
3309         txr->tx_avail -= nsegs;
3310
3311         tx_buf->m_head = m_head;
3312         tx_buf_mapped->map = tx_buf->map;
3313         tx_buf->map = map;
3314
3315         /*
3316          * Last Descriptor of Packet needs End Of Packet (EOP)
3317          */
3318         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3319
3320         /*
3321          * Defer TDT updating, until enough descrptors are setup
3322          */
3323         *idx = i;
3324         ++txr->tx_packets;
3325
3326         return 0;
3327 }
3328
3329 static void
3330 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3331 {
3332         struct igb_softc *sc = ifp->if_softc;
3333         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3334         struct mbuf *m_head;
3335         int idx = -1, nsegs = 0;
3336
3337         KKASSERT(txr->ifsq == ifsq);
3338         ASSERT_SERIALIZED(&txr->tx_serialize);
3339
3340         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3341                 return;
3342
3343         if (!sc->link_active) {
3344                 ifsq_purge(ifsq);
3345                 return;
3346         }
3347
3348         if (!IGB_IS_NOT_OACTIVE(txr))
3349                 igb_txeof(txr);
3350
3351         while (!ifsq_is_empty(ifsq)) {
3352                 if (IGB_IS_OACTIVE(txr)) {
3353                         ifsq_set_oactive(ifsq);
3354                         /* Set watchdog on */
3355                         ifp->if_timer = 5;
3356                         break;
3357                 }
3358
3359                 m_head = ifsq_dequeue(ifsq, NULL);
3360                 if (m_head == NULL)
3361                         break;
3362
3363                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3364                         ifp->if_oerrors++;
3365                         continue;
3366                 }
3367
3368                 if (nsegs >= txr->wreg_nsegs) {
3369                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3370                         idx = -1;
3371                         nsegs = 0;
3372                 }
3373
3374                 /* Send a copy of the frame to the BPF listener */
3375                 ETHER_BPF_MTAP(ifp, m_head);
3376         }
3377         if (idx >= 0)
3378                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3379 }
3380
3381 static void
3382 igb_watchdog(struct ifnet *ifp)
3383 {
3384         struct igb_softc *sc = ifp->if_softc;
3385         struct igb_tx_ring *txr = &sc->tx_rings[0];
3386
3387         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3388
3389         /* 
3390          * If flow control has paused us since last checking
3391          * it invalidates the watchdog timing, so dont run it.
3392          */
3393         if (sc->pause_frames) {
3394                 sc->pause_frames = 0;
3395                 ifp->if_timer = 5;
3396                 return;
3397         }
3398
3399         if_printf(ifp, "Watchdog timeout -- resetting\n");
3400         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3401             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3402             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3403         if_printf(ifp, "TX(%d) desc avail = %d, "
3404             "Next TX to Clean = %d\n",
3405             txr->me, txr->tx_avail, txr->next_to_clean);
3406
3407         ifp->if_oerrors++;
3408         sc->watchdog_events++;
3409
3410         igb_init(sc);
3411         if (!ifsq_is_empty(txr->ifsq))
3412                 ifsq_devstart(txr->ifsq);
3413 }
3414
3415 static void
3416 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3417 {
3418         uint32_t eitr = 0;
3419
3420         if (rate > 0) {
3421                 if (sc->hw.mac.type == e1000_82575) {
3422                         eitr = 1000000000 / 256 / rate;
3423                         /*
3424                          * NOTE:
3425                          * Document is wrong on the 2 bits left shift
3426                          */
3427                 } else {
3428                         eitr = 1000000 / rate;
3429                         eitr <<= IGB_EITR_INTVL_SHIFT;
3430                 }
3431
3432                 if (eitr == 0) {
3433                         /* Don't disable it */
3434                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3435                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3436                         /* Don't allow it to be too large */
3437                         eitr = IGB_EITR_INTVL_MASK;
3438                 }
3439         }
3440         if (sc->hw.mac.type == e1000_82575)
3441                 eitr |= eitr << 16;
3442         else
3443                 eitr |= E1000_EITR_CNT_IGNR;
3444         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3445 }
3446
3447 static int
3448 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3449 {
3450         struct igb_softc *sc = (void *)arg1;
3451         struct ifnet *ifp = &sc->arpcom.ac_if;
3452         int error, intr_rate;
3453
3454         intr_rate = sc->intr_rate;
3455         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3456         if (error || req->newptr == NULL)
3457                 return error;
3458         if (intr_rate < 0)
3459                 return EINVAL;
3460
3461         ifnet_serialize_all(ifp);
3462
3463         sc->intr_rate = intr_rate;
3464         if (ifp->if_flags & IFF_RUNNING)
3465                 igb_set_eitr(sc, 0, sc->intr_rate);
3466
3467         if (bootverbose)
3468                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3469
3470         ifnet_deserialize_all(ifp);
3471
3472         return 0;
3473 }
3474
3475 static int
3476 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3477 {
3478         struct igb_msix_data *msix = (void *)arg1;
3479         struct igb_softc *sc = msix->msix_sc;
3480         struct ifnet *ifp = &sc->arpcom.ac_if;
3481         int error, msix_rate;
3482
3483         msix_rate = msix->msix_rate;
3484         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3485         if (error || req->newptr == NULL)
3486                 return error;
3487         if (msix_rate < 0)
3488                 return EINVAL;
3489
3490         lwkt_serialize_enter(msix->msix_serialize);
3491
3492         msix->msix_rate = msix_rate;
3493         if (ifp->if_flags & IFF_RUNNING)
3494                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3495
3496         if (bootverbose) {
3497                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3498                     msix->msix_rate);
3499         }
3500
3501         lwkt_serialize_exit(msix->msix_serialize);
3502
3503         return 0;
3504 }
3505
3506 static int
3507 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3508 {
3509         struct igb_softc *sc = (void *)arg1;
3510         struct ifnet *ifp = &sc->arpcom.ac_if;
3511         struct igb_tx_ring *txr = &sc->tx_rings[0];
3512         int error, nsegs;
3513
3514         nsegs = txr->intr_nsegs;
3515         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3516         if (error || req->newptr == NULL)
3517                 return error;
3518         if (nsegs <= 0)
3519                 return EINVAL;
3520
3521         ifnet_serialize_all(ifp);
3522
3523         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3524             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3525                 error = EINVAL;
3526         } else {
3527                 error = 0;
3528                 txr->intr_nsegs = nsegs;
3529         }
3530
3531         ifnet_deserialize_all(ifp);
3532
3533         return error;
3534 }
3535
3536 #ifdef IFPOLL_ENABLE
3537
3538 static int
3539 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3540 {
3541         struct igb_softc *sc = (void *)arg1;
3542         struct ifnet *ifp = &sc->arpcom.ac_if;
3543         int error, off;
3544
3545         off = sc->rx_npoll_off;
3546         error = sysctl_handle_int(oidp, &off, 0, req);
3547         if (error || req->newptr == NULL)
3548                 return error;
3549         if (off < 0)
3550                 return EINVAL;
3551
3552         ifnet_serialize_all(ifp);
3553         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3554                 error = EINVAL;
3555         } else {
3556                 error = 0;
3557                 sc->rx_npoll_off = off;
3558         }
3559         ifnet_deserialize_all(ifp);
3560
3561         return error;
3562 }
3563
3564 static int
3565 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3566 {
3567         struct igb_softc *sc = (void *)arg1;
3568         struct ifnet *ifp = &sc->arpcom.ac_if;
3569         int error, off;
3570
3571         off = sc->tx_npoll_off;
3572         error = sysctl_handle_int(oidp, &off, 0, req);
3573         if (error || req->newptr == NULL)
3574                 return error;
3575         if (off < 0)
3576                 return EINVAL;
3577
3578         ifnet_serialize_all(ifp);
3579         if (off >= ncpus2) {
3580                 error = EINVAL;
3581         } else {
3582                 error = 0;
3583                 sc->tx_npoll_off = off;
3584         }
3585         ifnet_deserialize_all(ifp);
3586
3587         return error;
3588 }
3589
3590 #endif  /* IFPOLL_ENABLE */
3591
3592 static void
3593 igb_init_intr(struct igb_softc *sc)
3594 {
3595         igb_set_intr_mask(sc);
3596
3597         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3598                 igb_init_unshared_intr(sc);
3599
3600         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3601                 igb_set_eitr(sc, 0, sc->intr_rate);
3602         } else {
3603                 int i;
3604
3605                 for (i = 0; i < sc->msix_cnt; ++i)
3606                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3607         }
3608 }
3609
3610 static void
3611 igb_init_unshared_intr(struct igb_softc *sc)
3612 {
3613         struct e1000_hw *hw = &sc->hw;
3614         const struct igb_rx_ring *rxr;
3615         const struct igb_tx_ring *txr;
3616         uint32_t ivar, index;
3617         int i;
3618
3619         /*
3620          * Enable extended mode
3621          */
3622         if (sc->hw.mac.type != e1000_82575) {
3623                 uint32_t gpie;
3624                 int ivar_max;
3625
3626                 gpie = E1000_GPIE_NSICR;
3627                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3628                         gpie |= E1000_GPIE_MSIX_MODE |
3629                             E1000_GPIE_EIAME |
3630                             E1000_GPIE_PBA;
3631                 }
3632                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3633
3634                 /*
3635                  * Clear IVARs
3636                  */
3637                 switch (sc->hw.mac.type) {
3638                 case e1000_82580:
3639                         ivar_max = IGB_MAX_IVAR_82580;
3640                         break;
3641
3642                 case e1000_i350:
3643                         ivar_max = IGB_MAX_IVAR_I350;
3644                         break;
3645
3646                 case e1000_vfadapt:
3647                 case e1000_vfadapt_i350:
3648                         ivar_max = IGB_MAX_IVAR_VF;
3649                         break;
3650
3651                 case e1000_82576:
3652                         ivar_max = IGB_MAX_IVAR_82576;
3653                         break;
3654
3655                 default:
3656                         panic("unknown mac type %d\n", sc->hw.mac.type);
3657                 }
3658                 for (i = 0; i < ivar_max; ++i)
3659                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3660                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3661         } else {
3662                 uint32_t tmp;
3663
3664                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3665                     ("82575 w/ MSI-X"));
3666                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3667                 tmp |= E1000_CTRL_EXT_IRCA;
3668                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3669         }
3670
3671         /*
3672          * Map TX/RX interrupts to EICR
3673          */
3674         switch (sc->hw.mac.type) {
3675         case e1000_82580:
3676         case e1000_i350:
3677         case e1000_vfadapt:
3678         case e1000_vfadapt_i350:
3679                 /* RX entries */
3680                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3681                         rxr = &sc->rx_rings[i];
3682
3683                         index = i >> 1;
3684                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3685
3686                         if (i & 1) {
3687                                 ivar &= 0xff00ffff;
3688                                 ivar |=
3689                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3690                         } else {
3691                                 ivar &= 0xffffff00;
3692                                 ivar |=
3693                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3694                         }
3695                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3696                 }
3697                 /* TX entries */
3698                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3699                         txr = &sc->tx_rings[i];
3700
3701                         index = i >> 1;
3702                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3703
3704                         if (i & 1) {
3705                                 ivar &= 0x00ffffff;
3706                                 ivar |=
3707                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3708                         } else {
3709                                 ivar &= 0xffff00ff;
3710                                 ivar |=
3711                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3712                         }
3713                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3714                 }
3715                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3716                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3717                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3718                 }
3719                 break;
3720
3721         case e1000_82576:
3722                 /* RX entries */
3723                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3724                         rxr = &sc->rx_rings[i];
3725
3726                         index = i & 0x7; /* Each IVAR has two entries */
3727                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3728
3729                         if (i < 8) {
3730                                 ivar &= 0xffffff00;
3731                                 ivar |=
3732                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3733                         } else {
3734                                 ivar &= 0xff00ffff;
3735                                 ivar |=
3736                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3737                         }
3738                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3739                 }
3740                 /* TX entries */
3741                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3742                         txr = &sc->tx_rings[i];
3743
3744                         index = i & 0x7; /* Each IVAR has two entries */
3745                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3746
3747                         if (i < 8) {
3748                                 ivar &= 0xffff00ff;
3749                                 ivar |=
3750                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3751                         } else {
3752                                 ivar &= 0x00ffffff;
3753                                 ivar |=
3754                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3755                         }
3756                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3757                 }
3758                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3759                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3760                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3761                 }
3762                 break;
3763
3764         case e1000_82575:
3765                 /*
3766                  * Enable necessary interrupt bits.
3767                  *
3768                  * The name of the register is confusing; in addition to
3769                  * configuring the first vector of MSI-X, it also configures
3770                  * which bits of EICR could be set by the hardware even when
3771                  * MSI or line interrupt is used; it thus controls interrupt
3772                  * generation.  It MUST be configured explicitly; the default
3773                  * value mentioned in the datasheet is wrong: RX queue0 and
3774                  * TX queue0 are NOT enabled by default.
3775                  */
3776                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3777                 break;
3778
3779         default:
3780                 panic("unknown mac type %d\n", sc->hw.mac.type);
3781         }
3782 }
3783
3784 static int
3785 igb_setup_intr(struct igb_softc *sc)
3786 {
3787         int error;
3788
3789         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3790                 return igb_msix_setup(sc);
3791
3792         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3793             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3794             sc, &sc->intr_tag, &sc->main_serialize);
3795         if (error) {
3796                 device_printf(sc->dev, "Failed to register interrupt handler");
3797                 return error;
3798         }
3799         sc->tx_rings[0].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
3800
3801         return 0;
3802 }
3803
3804 static void
3805 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3806 {
3807         if (txr->sc->hw.mac.type == e1000_82575) {
3808                 txr->tx_intr_bit = 0;   /* unused */
3809                 switch (txr->me) {
3810                 case 0:
3811                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3812                         break;
3813                 case 1:
3814                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3815                         break;
3816                 case 2:
3817                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3818                         break;
3819                 case 3:
3820                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3821                         break;
3822                 default:
3823                         panic("unsupported # of TX ring, %d\n", txr->me);
3824                 }
3825         } else {
3826                 int intr_bit = *intr_bit0;
3827
3828                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3829                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3830
3831                 *intr_bit0 = intr_bit + 1;
3832         }
3833 }
3834
3835 static void
3836 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3837 {
3838         if (rxr->sc->hw.mac.type == e1000_82575) {
3839                 rxr->rx_intr_bit = 0;   /* unused */
3840                 switch (rxr->me) {
3841                 case 0:
3842                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3843                         break;
3844                 case 1:
3845                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3846                         break;
3847                 case 2:
3848                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3849                         break;
3850                 case 3:
3851                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3852                         break;
3853                 default:
3854                         panic("unsupported # of RX ring, %d\n", rxr->me);
3855                 }
3856         } else {
3857                 int intr_bit = *intr_bit0;
3858
3859                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3860                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3861
3862                 *intr_bit0 = intr_bit + 1;
3863         }
3864 }
3865
3866 static void
3867 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3868 {
3869         struct igb_softc *sc = ifp->if_softc;
3870
3871         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3872             sc->tx_serialize, sc->rx_serialize, slz);
3873 }
3874
3875 static void
3876 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3877 {
3878         struct igb_softc *sc = ifp->if_softc;
3879
3880         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3881             sc->tx_serialize, sc->rx_serialize, slz);
3882 }
3883
3884 static int
3885 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3886 {
3887         struct igb_softc *sc = ifp->if_softc;
3888
3889         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3890             sc->tx_serialize, sc->rx_serialize, slz);
3891 }
3892
3893 #ifdef INVARIANTS
3894
3895 static void
3896 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3897     boolean_t serialized)
3898 {
3899         struct igb_softc *sc = ifp->if_softc;
3900
3901         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3902             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3903 }
3904
3905 #endif  /* INVARIANTS */
3906
3907 static void
3908 igb_set_intr_mask(struct igb_softc *sc)
3909 {
3910         int i;
3911
3912         sc->intr_mask = sc->sts_intr_mask;
3913         for (i = 0; i < sc->rx_ring_inuse; ++i)
3914                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3915         for (i = 0; i < sc->tx_ring_cnt; ++i)
3916                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3917         if (bootverbose) {
3918                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3919                     sc->intr_mask);
3920         }
3921 }
3922
3923 static int
3924 igb_alloc_intr(struct igb_softc *sc)
3925 {
3926         int i, intr_bit, intr_bitmax;
3927         u_int intr_flags;
3928
3929         igb_msix_try_alloc(sc);
3930         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3931                 goto done;
3932
3933         /*
3934          * Allocate MSI/legacy interrupt resource
3935          */
3936         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3937             &sc->intr_rid, &intr_flags);
3938
3939         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3940                 int unshared;
3941
3942                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3943                 if (!unshared) {
3944                         sc->flags |= IGB_FLAG_SHARED_INTR;
3945                         if (bootverbose)
3946                                 device_printf(sc->dev, "IRQ shared\n");
3947                 } else {
3948                         intr_flags &= ~RF_SHAREABLE;
3949                         if (bootverbose)
3950                                 device_printf(sc->dev, "IRQ unshared\n");
3951                 }
3952         }
3953
3954         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3955             &sc->intr_rid, intr_flags);
3956         if (sc->intr_res == NULL) {
3957                 device_printf(sc->dev, "Unable to allocate bus resource: "
3958                     "interrupt\n");
3959                 return ENXIO;
3960         }
3961
3962         /*
3963          * Setup MSI/legacy interrupt mask
3964          */
3965         switch (sc->hw.mac.type) {
3966         case e1000_82575:
3967                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3968                 break;
3969         case e1000_82580:
3970                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3971                 break;
3972         case e1000_i350:
3973                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3974                 break;
3975         case e1000_82576:
3976                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3977                 break;
3978         default:
3979                 intr_bitmax = IGB_MIN_TXRXINT;
3980                 break;
3981         }
3982         intr_bit = 0;
3983         for (i = 0; i < sc->tx_ring_cnt; ++i)
3984                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3985         for (i = 0; i < sc->rx_ring_cnt; ++i)
3986                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3987         sc->sts_intr_bit = 0;
3988         sc->sts_intr_mask = E1000_EICR_OTHER;
3989
3990         /* Initialize interrupt rate */
3991         sc->intr_rate = IGB_INTR_RATE;
3992 done:
3993         igb_set_ring_inuse(sc, FALSE);
3994         igb_set_intr_mask(sc);
3995         return 0;
3996 }
3997
3998 static void
3999 igb_free_intr(struct igb_softc *sc)
4000 {
4001         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4002                 if (sc->intr_res != NULL) {
4003                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4004                             sc->intr_res);
4005                 }
4006                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4007                         pci_release_msi(sc->dev);
4008         } else {
4009                 igb_msix_free(sc, TRUE);
4010         }
4011 }
4012
4013 static void
4014 igb_teardown_intr(struct igb_softc *sc)
4015 {
4016         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4017                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4018         else
4019                 igb_msix_teardown(sc, sc->msix_cnt);
4020 }
4021
4022 static void
4023 igb_msix_try_alloc(struct igb_softc *sc)
4024 {
4025         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4026         int i, x, error;
4027         struct igb_msix_data *msix;
4028         boolean_t aggregate, setup = FALSE;
4029
4030         /*
4031          * Don't enable MSI-X on 82575, see:
4032          * 82575 specification update errata #25
4033          */
4034         if (sc->hw.mac.type == e1000_82575)
4035                 return;
4036
4037         /* Don't enable MSI-X on VF */
4038         if (sc->vf_ifp)
4039                 return;
4040
4041         msix_enable = device_getenv_int(sc->dev, "msix.enable",
4042             igb_msix_enable);
4043         if (!msix_enable)
4044                 return;
4045
4046         msix_cnt = pci_msix_count(sc->dev);
4047 #ifdef IGB_MSIX_DEBUG
4048         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4049 #endif
4050         if (msix_cnt <= 1) {
4051                 /* One MSI-X model does not make sense */
4052                 return;
4053         }
4054
4055         i = 0;
4056         while ((1 << (i + 1)) <= msix_cnt)
4057                 ++i;
4058         msix_cnt2 = 1 << i;
4059
4060         if (bootverbose) {
4061                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4062                     msix_cnt2, msix_cnt);
4063         }
4064
4065         KKASSERT(msix_cnt2 <= msix_cnt);
4066         if (msix_cnt == msix_cnt2) {
4067                 /* We need at least one MSI-X for link status */
4068                 msix_cnt2 >>= 1;
4069                 if (msix_cnt2 <= 1) {
4070                         /* One MSI-X for RX/TX does not make sense */
4071                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4072                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4073                         return;
4074                 }
4075                 KKASSERT(msix_cnt > msix_cnt2);