2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 #define MPTABLE_POS_USE_DEFAULT(mpt) \
173 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
177 int mb_type; /* MPTABLE_BUS_ */
178 TAILQ_ENTRY(mptable_bus) mb_link;
181 #define MPTABLE_BUS_ISA 0
182 #define MPTABLE_BUS_PCI 1
184 struct mptable_bus_info {
185 TAILQ_HEAD(, mptable_bus) mbi_list;
188 struct mptable_pci_int {
195 TAILQ_ENTRY(mptable_pci_int) mpci_link;
198 struct mptable_ioapic {
204 TAILQ_ENTRY(mptable_ioapic) mio_link;
207 typedef int (*mptable_iter_func)(void *, const void *, int);
210 * this code MUST be enabled here and in mpboot.s.
211 * it follows the very early stages of AP boot by placing values in CMOS ram.
212 * it NORMALLY will never be needed and thus the primitive method for enabling.
215 #if defined(CHECK_POINTS)
216 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
217 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
219 #define CHECK_INIT(D); \
220 CHECK_WRITE(0x34, (D)); \
221 CHECK_WRITE(0x35, (D)); \
222 CHECK_WRITE(0x36, (D)); \
223 CHECK_WRITE(0x37, (D)); \
224 CHECK_WRITE(0x38, (D)); \
225 CHECK_WRITE(0x39, (D));
227 #define CHECK_PRINT(S); \
228 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
237 #else /* CHECK_POINTS */
239 #define CHECK_INIT(D)
240 #define CHECK_PRINT(S)
242 #endif /* CHECK_POINTS */
245 * Values to send to the POST hardware.
247 #define MP_BOOTADDRESS_POST 0x10
248 #define MP_PROBE_POST 0x11
249 #define MPTABLE_PASS1_POST 0x12
251 #define MP_START_POST 0x13
252 #define MP_ENABLE_POST 0x14
253 #define MPTABLE_PASS2_POST 0x15
255 #define START_ALL_APS_POST 0x16
256 #define INSTALL_AP_TRAMP_POST 0x17
257 #define START_AP_POST 0x18
259 #define MP_ANNOUNCE_POST 0x19
261 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
262 int current_postcode;
264 /** XXX FIXME: what system files declare these??? */
265 extern struct region_descriptor r_gdt, r_idt;
267 int mp_naps; /* # of Applications processors */
268 #ifdef SMP /* APIC-IO */
269 static int mp_nbusses; /* # of busses */
270 int mp_napics; /* # of IO APICs */
271 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
272 u_int32_t *io_apic_versions;
276 u_int32_t cpu_apic_versions[MAXCPU];
278 extern int64_t tsc_offsets[];
280 extern u_long ebda_addr;
282 #ifdef SMP /* APIC-IO */
283 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
287 * APIC ID logical/physical mapping structures.
288 * We oversize these to simplify boot-time config.
290 int cpu_num_to_apic_id[NAPICID];
291 #ifdef SMP /* APIC-IO */
292 int io_num_to_apic_id[NAPICID];
294 int apic_id_to_logical[NAPICID];
296 /* AP uses this during bootstrap. Do not staticize. */
300 /* Hotwire a 0->4MB V==P mapping */
301 extern pt_entry_t *KPTphys;
304 * SMP page table page. Setup by locore to point to a page table
305 * page from which we allocate per-cpu privatespace areas io_apics,
309 #define IO_MAPPING_START_INDEX \
310 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
312 extern pt_entry_t *SMPpt;
313 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
315 struct pcb stoppcbs[MAXCPU];
317 static basetable_entry basetable_entry_types[] =
319 {0, 20, "Processor"},
327 * Local data and functions.
330 static u_int boot_address;
331 static u_int base_memory;
332 static int mp_finish;
334 static void mp_enable(u_int boot_addr);
336 static int mptable_iterate_entries(const mpcth_t,
337 mptable_iter_func, void *);
338 static int mptable_search(void);
339 static int mptable_search_sig(u_int32_t target, int count);
340 static int mptable_hyperthread_fixup(cpumask_t, int);
341 #ifdef SMP /* APIC-IO */
342 static void mptable_pass1(struct mptable_pos *);
343 static void mptable_pass2(struct mptable_pos *);
344 static void mptable_default(int type);
345 static void mptable_fix(void);
347 static int mptable_map(struct mptable_pos *);
348 static void mptable_unmap(struct mptable_pos *);
349 static void mptable_bus_info_alloc(const mpcth_t,
350 struct mptable_bus_info *);
351 static void mptable_bus_info_free(struct mptable_bus_info *);
353 static int mptable_lapic_probe(struct lapic_enumerator *);
354 static void mptable_lapic_enumerate(struct lapic_enumerator *);
355 static void mptable_lapic_default(void);
357 static int mptable_ioapic_probe(struct ioapic_enumerator *);
358 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
360 #ifdef SMP /* APIC-IO */
361 static void setup_apic_irq_mapping(void);
362 static int apic_int_is_bus_type(int intr, int bus_type);
364 static int start_all_aps(u_int boot_addr);
365 static void install_ap_tramp(u_int boot_addr);
366 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
367 static int smitest(void);
369 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
370 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
371 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
375 static vm_paddr_t mptable_fps_phyaddr;
376 static int mptable_use_default;
377 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
378 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
379 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
380 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
383 * Calculate usable address in base memory for AP trampoline code.
386 mp_bootaddress(u_int basemem)
388 POSTCODE(MP_BOOTADDRESS_POST);
390 base_memory = basemem;
392 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
393 if ((base_memory - boot_address) < bootMP_size)
394 boot_address -= 4096; /* not enough, lower by 4k */
403 struct mptable_pos mpt;
406 KKASSERT(mptable_fps_phyaddr == 0);
408 mptable_fps_phyaddr = mptable_search();
409 if (mptable_fps_phyaddr == 0)
412 error = mptable_map(&mpt);
414 mptable_fps_phyaddr = 0;
418 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
419 kprintf("MPTABLE: use default configuration\n");
420 mptable_use_default = 1;
422 if (mpt.mp_fps->mpfb2 & 0x80)
427 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
430 * Look for an Intel MP spec table (ie, SMP capable hardware).
439 * Make sure our SMPpt[] page table is big enough to hold all the
442 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
444 POSTCODE(MP_PROBE_POST);
446 /* see if EBDA exists */
447 if (ebda_addr != 0) {
448 /* search first 1K of EBDA */
449 target = (u_int32_t)ebda_addr;
450 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
453 /* last 1K of base memory, effective 'top of base' passed in */
454 target = (u_int32_t)(base_memory - 0x400);
455 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
459 /* search the BIOS */
460 target = (u_int32_t)BIOS_BASE;
461 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
464 /* search the extended BIOS */
465 target = (u_int32_t)BIOS_BASE2;
466 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
474 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
476 int count, total_size;
477 const void *position;
479 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
480 total_size = cth->base_table_length - sizeof(struct MPCTH);
481 position = (const uint8_t *)cth + sizeof(struct MPCTH);
482 count = cth->entry_count;
487 KKASSERT(total_size >= 0);
488 if (total_size == 0) {
489 kprintf("invalid base MP table, "
490 "entry count and length mismatch\n");
494 type = *(const uint8_t *)position;
496 case 0: /* processor_entry */
497 case 1: /* bus_entry */
498 case 2: /* io_apic_entry */
499 case 3: /* int_entry */
500 case 4: /* int_entry */
503 kprintf("unknown base MP table entry type %d\n", type);
507 if (total_size < basetable_entry_types[type].length) {
508 kprintf("invalid base MP table length, "
509 "does not contain all entries\n");
512 total_size -= basetable_entry_types[type].length;
514 error = func(arg, position, type);
518 position = (const uint8_t *)position +
519 basetable_entry_types[type].length;
526 * Startup the SMP processors.
531 POSTCODE(MP_START_POST);
532 mp_enable(boot_address);
537 * Print various information about the SMP system hardware and setup.
544 POSTCODE(MP_ANNOUNCE_POST);
546 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
547 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
548 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
549 for (x = 1; x <= mp_naps; ++x) {
550 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
551 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
554 if (apic_io_enable) {
555 if (ioapic_use_old) {
556 for (x = 0; x < mp_napics; ++x) {
557 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
558 kprintf(", version: 0x%08x", io_apic_versions[x]);
559 kprintf(", at 0x%08lx\n", io_apic_address[x]);
563 kprintf(" Warning: APIC I/O disabled\n");
568 * AP cpu's call this to sync up protected mode.
570 * WARNING! We must ensure that the cpu is sufficiently initialized to
571 * be able to use to the FP for our optimized bzero/bcopy code before
572 * we enter more mainstream C code.
574 * WARNING! %fs is not set up on entry. This routine sets up %fs.
580 int x, myid = bootAP;
582 struct mdglobaldata *md;
583 struct privatespace *ps;
585 ps = &CPU_prvspace[myid];
587 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
588 gdt_segs[GPROC0_SEL].ssd_base =
589 (int) &ps->mdglobaldata.gd_common_tss;
590 ps->mdglobaldata.mi.gd_prvspace = ps;
592 for (x = 0; x < NGDT; x++) {
593 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
596 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
597 r_gdt.rd_base = (int) &gdt[myid * NGDT];
598 lgdt(&r_gdt); /* does magic intra-segment return */
603 mdcpu->gd_currentldt = _default_ldt;
605 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
606 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
608 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
610 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
611 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
612 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
613 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
614 md->gd_common_tssd = *md->gd_tss_gdt;
618 * Set to a known state:
619 * Set by mpboot.s: CR0_PG, CR0_PE
620 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
623 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
625 pmap_set_opt(); /* PSE/4MB pages, etc */
627 /* set up CPU registers and state */
630 /* set up FPU state on the AP */
631 npxinit(__INITIAL_NPXCW__);
633 /* set up SSE registers */
637 /*******************************************************************
638 * local functions and data
642 * start the SMP system
645 mp_enable(u_int boot_addr)
649 struct mptable_pos mpt;
651 POSTCODE(MP_ENABLE_POST);
658 if (apic_io_enable && ioapic_use_old) {
660 if (!mptable_fps_phyaddr)
661 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
666 * Examine the MP table for needed info
673 /* Post scan cleanup */
676 setup_apic_irq_mapping();
678 /* fill the LOGICAL io_apic_versions table */
679 for (apic = 0; apic < mp_napics; ++apic) {
680 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
681 io_apic_versions[apic] = ux;
682 io_apic_set_id(apic, IO_TO_ID(apic));
685 /* program each IO APIC in the system */
686 for (apic = 0; apic < mp_napics; ++apic)
687 if (io_apic_setup(apic) < 0)
688 panic("IO APIC setup failure");
693 * These are required for SMP operation
696 /* install a 'Spurious INTerrupt' vector */
697 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
698 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
700 /* install an inter-CPU IPI for TLB invalidation */
701 setidt(XINVLTLB_OFFSET, Xinvltlb,
702 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
704 /* install an inter-CPU IPI for IPIQ messaging */
705 setidt(XIPIQ_OFFSET, Xipiq,
706 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
708 /* install a timer vector */
709 setidt(XTIMER_OFFSET, Xtimer,
710 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
712 /* install an inter-CPU IPI for CPU stop/restart */
713 setidt(XCPUSTOP_OFFSET, Xcpustop,
714 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
716 /* start each Application Processor */
717 start_all_aps(boot_addr);
722 * look for the MP spec signature
725 /* string defined by the Intel MP Spec as identifying the MP table */
726 #define MP_SIG 0x5f504d5f /* _MP_ */
727 #define NEXT(X) ((X) += 4)
729 mptable_search_sig(u_int32_t target, int count)
735 KKASSERT(target != 0);
737 map_size = count * sizeof(u_int32_t);
738 addr = pmap_mapdev((vm_paddr_t)target, map_size);
741 for (x = 0; x < count; NEXT(x)) {
742 if (addr[x] == MP_SIG) {
743 /* make array index a byte index */
744 ret = target + (x * sizeof(u_int32_t));
749 pmap_unmapdev((vm_offset_t)addr, map_size);
754 typedef struct BUSDATA {
756 enum busTypes bus_type;
759 typedef struct INTDATA {
769 typedef struct BUSTYPENAME {
774 static bus_type_name bus_type_table[] =
780 {UNKNOWN_BUSTYPE, "---"},
783 {UNKNOWN_BUSTYPE, "---"},
784 {UNKNOWN_BUSTYPE, "---"},
785 {UNKNOWN_BUSTYPE, "---"},
786 {UNKNOWN_BUSTYPE, "---"},
787 {UNKNOWN_BUSTYPE, "---"},
789 {UNKNOWN_BUSTYPE, "---"},
790 {UNKNOWN_BUSTYPE, "---"},
791 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
794 {UNKNOWN_BUSTYPE, "---"}
796 /* from MP spec v1.4, table 5-1 */
797 static int default_data[7][5] =
799 /* nbus, id0, type0, id1, type1 */
800 {1, 0, ISA, 255, 255},
801 {1, 0, EISA, 255, 255},
802 {1, 0, EISA, 255, 255},
803 {1, 0, MCA, 255, 255},
805 {2, 0, EISA, 1, PCI},
811 static bus_datum *bus_data;
813 /* the IO INT data, one entry per possible APIC INTerrupt */
814 static io_int *io_apic_ints;
817 static int processor_entry (const struct PROCENTRY *entry, int cpu);
818 static int bus_entry (const struct BUSENTRY *entry, int bus);
819 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
820 static int int_entry (const struct INTENTRY *entry, int intr);
821 static int lookup_bus_type (char *name);
824 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
826 const struct IOAPICENTRY *ioapic_ent;
829 case 1: /* bus_entry */
833 case 2: /* io_apic_entry */
835 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
836 io_apic_address[mp_napics++] =
837 (vm_offset_t)ioapic_ent->apic_address;
841 case 3: /* int_entry */
849 * 1st pass on motherboard's Intel MP specification table.
858 mptable_pass1(struct mptable_pos *mpt)
863 POSTCODE(MPTABLE_PASS1_POST);
866 KKASSERT(fps != NULL);
868 /* clear various tables */
869 for (x = 0; x < NAPICID; ++x)
870 io_apic_address[x] = ~0; /* IO APIC address table */
876 /* check for use of 'default' configuration */
877 if (fps->mpfb1 != 0) {
878 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
879 mp_nbusses = default_data[fps->mpfb1 - 1][0];
885 error = mptable_iterate_entries(mpt->mp_cth,
886 mptable_ioapic_pass1_callback, NULL);
888 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
892 struct mptable_ioapic2_cbarg {
899 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
901 struct mptable_ioapic2_cbarg *arg = xarg;
905 if (bus_entry(pos, arg->bus))
910 if (io_apic_entry(pos, arg->apic))
915 if (int_entry(pos, arg->intr))
923 * 2nd pass on motherboard's Intel MP specification table.
926 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
927 * IO_TO_ID(N), logical IO to APIC ID table
932 mptable_pass2(struct mptable_pos *mpt)
934 struct mptable_ioapic2_cbarg arg;
938 POSTCODE(MPTABLE_PASS2_POST);
941 KKASSERT(fps != NULL);
943 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
945 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
946 M_DEVBUF, M_WAITOK | M_ZERO);
947 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
949 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
952 for (x = 0; x < mp_napics; x++)
953 ioapic[x] = ioapic_map(io_apic_address[x]);
955 /* clear various tables */
956 for (x = 0; x < NAPICID; ++x) {
957 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
958 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
961 /* clear bus data table */
962 for (x = 0; x < mp_nbusses; ++x)
963 bus_data[x].bus_id = 0xff;
965 /* clear IO APIC INT table */
966 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
967 io_apic_ints[x].int_type = 0xff;
968 io_apic_ints[x].int_vector = 0xff;
971 /* check for use of 'default' configuration */
972 if (fps->mpfb1 != 0) {
973 mptable_default(fps->mpfb1);
977 bzero(&arg, sizeof(arg));
978 error = mptable_iterate_entries(mpt->mp_cth,
979 mptable_ioapic_pass2_callback, &arg);
981 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
985 * Check if we should perform a hyperthreading "fix-up" to
986 * enumerate any logical CPU's that aren't already listed
989 * XXX: We assume that all of the physical CPUs in the
990 * system have the same number of logical CPUs.
992 * XXX: We assume that APIC ID's are allocated such that
993 * the APIC ID's for a physical processor are aligned
994 * with the number of logical CPU's in the processor.
997 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
999 int i, id, lcpus_max, logical_cpus;
1001 if ((cpu_feature & CPUID_HTT) == 0)
1004 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1008 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1010 * INSTRUCTION SET REFERENCE, A-M (#253666)
1011 * Page 3-181, Table 3-20
1012 * "The nearest power-of-2 integer that is not smaller
1013 * than EBX[23:16] is the number of unique initial APIC
1014 * IDs reserved for addressing different logical
1015 * processors in a physical package."
1017 for (i = 0; ; ++i) {
1018 if ((1 << i) >= lcpus_max) {
1025 KKASSERT(cpu_count != 0);
1026 if (cpu_count == lcpus_max) {
1027 /* We have nothing to fix */
1029 } else if (cpu_count == 1) {
1030 /* XXX this may be incorrect */
1031 logical_cpus = lcpus_max;
1033 int cur, prev, dist;
1036 * Calculate the distances between two nearest
1037 * APIC IDs. If all such distances are same,
1038 * then it is the number of missing cpus that
1039 * we are going to fill later.
1041 dist = cur = prev = -1;
1042 for (id = 0; id < MAXCPU; ++id) {
1043 if ((id_mask & CPUMASK(id)) == 0)
1048 int new_dist = cur - prev;
1054 * Make sure that all distances
1055 * between two nearest APIC IDs
1058 if (dist != new_dist)
1066 /* Must be power of 2 */
1067 if (dist & (dist - 1))
1070 /* Can't exceed CPU package capacity */
1071 if (dist > lcpus_max)
1072 logical_cpus = lcpus_max;
1074 logical_cpus = dist;
1078 * For each APIC ID of a CPU that is set in the mask,
1079 * scan the other candidate APIC ID's for this
1080 * physical processor. If any of those ID's are
1081 * already in the table, then kill the fixup.
1083 for (id = 0; id < MAXCPU; id++) {
1084 if ((id_mask & CPUMASK(id)) == 0)
1086 /* First, make sure we are on a logical_cpus boundary. */
1087 if (id % logical_cpus != 0)
1089 for (i = id + 1; i < id + logical_cpus; i++)
1090 if ((id_mask & CPUMASK(i)) != 0)
1093 return logical_cpus;
1097 mptable_map(struct mptable_pos *mpt)
1101 vm_size_t cth_mapsz = 0;
1103 KKASSERT(mptable_fps_phyaddr != 0);
1105 bzero(mpt, sizeof(*mpt));
1107 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1108 if (fps->pap != 0) {
1110 * Map configuration table header to get
1111 * the base table size
1113 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1114 cth_mapsz = cth->base_table_length;
1115 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1117 if (cth_mapsz < sizeof(*cth)) {
1118 kprintf("invalid base MP table length %d\n",
1120 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1125 * Map the base table
1127 cth = pmap_mapdev(fps->pap, cth_mapsz);
1132 mpt->mp_cth_mapsz = cth_mapsz;
1138 mptable_unmap(struct mptable_pos *mpt)
1140 if (mpt->mp_cth != NULL) {
1141 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1143 mpt->mp_cth_mapsz = 0;
1145 if (mpt->mp_fps != NULL) {
1146 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1152 assign_apic_irq(int apic, int intpin, int irq)
1156 if (int_to_apicintpin[irq].ioapic != -1)
1157 panic("assign_apic_irq: inconsistent table");
1159 int_to_apicintpin[irq].ioapic = apic;
1160 int_to_apicintpin[irq].int_pin = intpin;
1161 int_to_apicintpin[irq].apic_address = ioapic[apic];
1162 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1164 for (x = 0; x < nintrs; x++) {
1165 if ((io_apic_ints[x].int_type == 0 ||
1166 io_apic_ints[x].int_type == 3) &&
1167 io_apic_ints[x].int_vector == 0xff &&
1168 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1169 io_apic_ints[x].dst_apic_int == intpin)
1170 io_apic_ints[x].int_vector = irq;
1175 revoke_apic_irq(int irq)
1181 if (int_to_apicintpin[irq].ioapic == -1)
1182 panic("revoke_apic_irq: inconsistent table");
1184 oldapic = int_to_apicintpin[irq].ioapic;
1185 oldintpin = int_to_apicintpin[irq].int_pin;
1187 int_to_apicintpin[irq].ioapic = -1;
1188 int_to_apicintpin[irq].int_pin = 0;
1189 int_to_apicintpin[irq].apic_address = NULL;
1190 int_to_apicintpin[irq].redirindex = 0;
1192 for (x = 0; x < nintrs; x++) {
1193 if ((io_apic_ints[x].int_type == 0 ||
1194 io_apic_ints[x].int_type == 3) &&
1195 io_apic_ints[x].int_vector != 0xff &&
1196 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1197 io_apic_ints[x].dst_apic_int == oldintpin)
1198 io_apic_ints[x].int_vector = 0xff;
1206 allocate_apic_irq(int intr)
1212 if (io_apic_ints[intr].int_vector != 0xff)
1213 return; /* Interrupt handler already assigned */
1215 if (io_apic_ints[intr].int_type != 0 &&
1216 (io_apic_ints[intr].int_type != 3 ||
1217 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1218 io_apic_ints[intr].dst_apic_int == 0)))
1219 return; /* Not INT or ExtInt on != (0, 0) */
1222 while (irq < APIC_INTMAPSIZE &&
1223 int_to_apicintpin[irq].ioapic != -1)
1226 if (irq >= APIC_INTMAPSIZE)
1227 return; /* No free interrupt handlers */
1229 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1230 intpin = io_apic_ints[intr].dst_apic_int;
1232 assign_apic_irq(apic, intpin, irq);
1237 swap_apic_id(int apic, int oldid, int newid)
1244 return; /* Nothing to do */
1246 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1247 apic, oldid, newid);
1249 /* Swap physical APIC IDs in interrupt entries */
1250 for (x = 0; x < nintrs; x++) {
1251 if (io_apic_ints[x].dst_apic_id == oldid)
1252 io_apic_ints[x].dst_apic_id = newid;
1253 else if (io_apic_ints[x].dst_apic_id == newid)
1254 io_apic_ints[x].dst_apic_id = oldid;
1257 /* Swap physical APIC IDs in IO_TO_ID mappings */
1258 for (oapic = 0; oapic < mp_napics; oapic++)
1259 if (IO_TO_ID(oapic) == newid)
1262 if (oapic < mp_napics) {
1263 kprintf("Changing APIC ID for IO APIC #%d from "
1264 "%d to %d in MP table\n",
1265 oapic, newid, oldid);
1266 IO_TO_ID(oapic) = oldid;
1268 IO_TO_ID(apic) = newid;
1273 fix_id_to_io_mapping(void)
1277 for (x = 0; x < NAPICID; x++)
1280 for (x = 0; x <= mp_naps; x++)
1281 if (CPU_TO_ID(x) < NAPICID)
1282 ID_TO_IO(CPU_TO_ID(x)) = x;
1284 for (x = 0; x < mp_napics; x++)
1285 if (IO_TO_ID(x) < NAPICID)
1286 ID_TO_IO(IO_TO_ID(x)) = x;
1291 first_free_apic_id(void)
1295 for (freeid = 0; freeid < NAPICID; freeid++) {
1296 for (x = 0; x <= mp_naps; x++)
1297 if (CPU_TO_ID(x) == freeid)
1301 for (x = 0; x < mp_napics; x++)
1302 if (IO_TO_ID(x) == freeid)
1313 io_apic_id_acceptable(int apic, int id)
1315 int cpu; /* Logical CPU number */
1316 int oapic; /* Logical IO APIC number for other IO APIC */
1319 return 0; /* Out of range */
1321 for (cpu = 0; cpu <= mp_naps; cpu++)
1322 if (CPU_TO_ID(cpu) == id)
1323 return 0; /* Conflict with CPU */
1325 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1326 if (IO_TO_ID(oapic) == id)
1327 return 0; /* Conflict with other APIC */
1329 return 1; /* ID is acceptable for IO APIC */
1334 io_apic_find_int_entry(int apic, int pin)
1338 /* search each of the possible INTerrupt sources */
1339 for (x = 0; x < nintrs; ++x) {
1340 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1341 (pin == io_apic_ints[x].dst_apic_int))
1342 return (&io_apic_ints[x]);
1348 * parse an Intel MP specification table
1355 int apic; /* IO APIC unit number */
1356 int freeid; /* Free physical APIC ID */
1357 int physid; /* Current physical IO APIC ID */
1359 int bus_0 = 0; /* Stop GCC warning */
1360 int bus_pci = 0; /* Stop GCC warning */
1364 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1365 * did it wrong. The MP spec says that when more than 1 PCI bus
1366 * exists the BIOS must begin with bus entries for the PCI bus and use
1367 * actual PCI bus numbering. This implies that when only 1 PCI bus
1368 * exists the BIOS can choose to ignore this ordering, and indeed many
1369 * MP motherboards do ignore it. This causes a problem when the PCI
1370 * sub-system makes requests of the MP sub-system based on PCI bus
1371 * numbers. So here we look for the situation and renumber the
1372 * busses and associated INTs in an effort to "make it right".
1375 /* find bus 0, PCI bus, count the number of PCI busses */
1376 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1377 if (bus_data[x].bus_id == 0) {
1380 if (bus_data[x].bus_type == PCI) {
1386 * bus_0 == slot of bus with ID of 0
1387 * bus_pci == slot of last PCI bus encountered
1390 /* check the 1 PCI bus case for sanity */
1391 /* if it is number 0 all is well */
1392 if (num_pci_bus == 1 &&
1393 bus_data[bus_pci].bus_id != 0) {
1395 /* mis-numbered, swap with whichever bus uses slot 0 */
1397 /* swap the bus entry types */
1398 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1399 bus_data[bus_0].bus_type = PCI;
1401 /* swap each relavant INTerrupt entry */
1402 id = bus_data[bus_pci].bus_id;
1403 for (x = 0; x < nintrs; ++x) {
1404 if (io_apic_ints[x].src_bus_id == id) {
1405 io_apic_ints[x].src_bus_id = 0;
1407 else if (io_apic_ints[x].src_bus_id == 0) {
1408 io_apic_ints[x].src_bus_id = id;
1413 /* Assign IO APIC IDs.
1415 * First try the existing ID. If a conflict is detected, try
1416 * the ID in the MP table. If a conflict is still detected, find
1419 * We cannot use the ID_TO_IO table before all conflicts has been
1420 * resolved and the table has been corrected.
1422 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1424 /* First try to use the value set by the BIOS */
1425 physid = io_apic_get_id(apic);
1426 if (io_apic_id_acceptable(apic, physid)) {
1427 if (IO_TO_ID(apic) != physid)
1428 swap_apic_id(apic, IO_TO_ID(apic), physid);
1432 /* Then check if the value in the MP table is acceptable */
1433 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1436 /* Last resort, find a free APIC ID and use it */
1437 freeid = first_free_apic_id();
1438 if (freeid >= NAPICID)
1439 panic("No free physical APIC IDs found");
1441 if (io_apic_id_acceptable(apic, freeid)) {
1442 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1445 panic("Free physical APIC ID not usable");
1447 fix_id_to_io_mapping();
1449 /* detect and fix broken Compaq MP table */
1450 if (apic_int_type(0, 0) == -1) {
1451 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1452 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1453 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1454 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1455 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1456 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1458 } else if (apic_int_type(0, 0) == 0) {
1459 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1460 for (x = 0; x < nintrs; ++x)
1461 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1462 (0 == io_apic_ints[x].dst_apic_int)) {
1463 io_apic_ints[x].int_type = 3;
1464 io_apic_ints[x].int_vector = 0xff;
1470 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1471 * controllers universally come in pairs. If IRQ 14 is specified
1472 * as an ISA interrupt, then IRQ 15 had better be too.
1474 * [ Shuttle XPC / AMD Athlon X2 ]
1475 * The MPTable is missing an entry for IRQ 15. Note that the
1476 * ACPI table has an entry for both 14 and 15.
1478 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1479 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1480 io14 = io_apic_find_int_entry(0, 14);
1481 io_apic_ints[nintrs] = *io14;
1482 io_apic_ints[nintrs].src_bus_irq = 15;
1483 io_apic_ints[nintrs].dst_apic_int = 15;
1488 /* Assign low level interrupt handlers */
1490 setup_apic_irq_mapping(void)
1496 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1497 int_to_apicintpin[x].ioapic = -1;
1498 int_to_apicintpin[x].int_pin = 0;
1499 int_to_apicintpin[x].apic_address = NULL;
1500 int_to_apicintpin[x].redirindex = 0;
1502 /* Default to masked */
1503 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1506 /* First assign ISA/EISA interrupts */
1507 for (x = 0; x < nintrs; x++) {
1508 int_vector = io_apic_ints[x].src_bus_irq;
1509 if (int_vector < APIC_INTMAPSIZE &&
1510 io_apic_ints[x].int_vector == 0xff &&
1511 int_to_apicintpin[int_vector].ioapic == -1 &&
1512 (apic_int_is_bus_type(x, ISA) ||
1513 apic_int_is_bus_type(x, EISA)) &&
1514 io_apic_ints[x].int_type == 0) {
1515 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1516 io_apic_ints[x].dst_apic_int,
1521 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1522 for (x = 0; x < nintrs; x++) {
1523 if (io_apic_ints[x].dst_apic_int == 0 &&
1524 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1525 io_apic_ints[x].int_vector == 0xff &&
1526 int_to_apicintpin[0].ioapic == -1 &&
1527 io_apic_ints[x].int_type == 3) {
1528 assign_apic_irq(0, 0, 0);
1533 /* Assign PCI interrupts */
1534 for (x = 0; x < nintrs; ++x) {
1535 if (io_apic_ints[x].int_type == 0 &&
1536 io_apic_ints[x].int_vector == 0xff &&
1537 apic_int_is_bus_type(x, PCI))
1538 allocate_apic_irq(x);
1543 mp_set_cpuids(int cpu_id, int apic_id)
1545 CPU_TO_ID(cpu_id) = apic_id;
1546 ID_TO_CPU(apic_id) = cpu_id;
1548 if (apic_id > lapic_id_max)
1549 lapic_id_max = apic_id;
1553 processor_entry(const struct PROCENTRY *entry, int cpu)
1557 /* check for usability */
1558 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1561 /* check for BSP flag */
1562 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1563 mp_set_cpuids(0, entry->apic_id);
1564 return 0; /* its already been counted */
1567 /* add another AP to list, if less than max number of CPUs */
1568 else if (cpu < MAXCPU) {
1569 mp_set_cpuids(cpu, entry->apic_id);
1577 bus_entry(const struct BUSENTRY *entry, int bus)
1582 /* encode the name into an index */
1583 for (x = 0; x < 6; ++x) {
1584 if ((c = entry->bus_type[x]) == ' ')
1590 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1591 panic("unknown bus type: '%s'", name);
1593 bus_data[bus].bus_id = entry->bus_id;
1594 bus_data[bus].bus_type = x;
1600 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1602 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1605 IO_TO_ID(apic) = entry->apic_id;
1606 ID_TO_IO(entry->apic_id) = apic;
1612 lookup_bus_type(char *name)
1616 for (x = 0; x < MAX_BUSTYPE; ++x)
1617 if (strcmp(bus_type_table[x].name, name) == 0)
1618 return bus_type_table[x].type;
1620 return UNKNOWN_BUSTYPE;
1624 int_entry(const struct INTENTRY *entry, int intr)
1628 io_apic_ints[intr].int_type = entry->int_type;
1629 io_apic_ints[intr].int_flags = entry->int_flags;
1630 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1631 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1632 if (entry->dst_apic_id == 255) {
1633 /* This signal goes to all IO APICS. Select an IO APIC
1634 with sufficient number of interrupt pins */
1635 for (apic = 0; apic < mp_napics; apic++)
1636 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1637 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1638 entry->dst_apic_int)
1640 if (apic < mp_napics)
1641 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1643 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1645 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1646 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1652 apic_int_is_bus_type(int intr, int bus_type)
1656 for (bus = 0; bus < mp_nbusses; ++bus)
1657 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1658 && ((int) bus_data[bus].bus_type == bus_type))
1665 * Given a traditional ISA INT mask, return an APIC mask.
1668 isa_apic_mask(u_int isa_mask)
1673 #if defined(SKIP_IRQ15_REDIRECT)
1674 if (isa_mask == (1 << 15)) {
1675 kprintf("skipping ISA IRQ15 redirect\n");
1678 #endif /* SKIP_IRQ15_REDIRECT */
1680 isa_irq = ffs(isa_mask); /* find its bit position */
1681 if (isa_irq == 0) /* doesn't exist */
1683 --isa_irq; /* make it zero based */
1685 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1689 return (1 << apic_pin); /* convert pin# to a mask */
1693 * Determine which APIC pin an ISA/EISA INT is attached to.
1695 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1696 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1697 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1698 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1700 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1702 isa_apic_irq(int isa_irq)
1706 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1707 if (INTTYPE(intr) == 0) { /* standard INT */
1708 if (SRCBUSIRQ(intr) == isa_irq) {
1709 if (apic_int_is_bus_type(intr, ISA) ||
1710 apic_int_is_bus_type(intr, EISA)) {
1711 if (INTIRQ(intr) == 0xff)
1712 return -1; /* unassigned */
1713 return INTIRQ(intr); /* found */
1718 return -1; /* NOT found */
1723 * Determine which APIC pin a PCI INT is attached to.
1725 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1726 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1727 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1729 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1733 --pciInt; /* zero based */
1735 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1736 if ((INTTYPE(intr) == 0) /* standard INT */
1737 && (SRCBUSID(intr) == pciBus)
1738 && (SRCBUSDEVICE(intr) == pciDevice)
1739 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1740 if (apic_int_is_bus_type(intr, PCI)) {
1741 if (INTIRQ(intr) == 0xff) {
1742 kprintf("IOAPIC: pci_apic_irq() "
1744 return -1; /* unassigned */
1746 return INTIRQ(intr); /* exact match */
1751 return -1; /* NOT found */
1755 next_apic_irq(int irq)
1762 for (intr = 0; intr < nintrs; intr++) {
1763 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1765 bus = SRCBUSID(intr);
1766 bustype = apic_bus_type(bus);
1767 if (bustype != ISA &&
1773 if (intr >= nintrs) {
1776 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1777 if (INTTYPE(ointr) != 0)
1779 if (bus != SRCBUSID(ointr))
1781 if (bustype == PCI) {
1782 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1784 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1787 if (bustype == ISA || bustype == EISA) {
1788 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1791 if (INTPIN(intr) == INTPIN(ointr))
1795 if (ointr >= nintrs) {
1798 return INTIRQ(ointr);
1811 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1814 * Exactly what this means is unclear at this point. It is a solution
1815 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1816 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1817 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1821 undirect_isa_irq(int rirq)
1825 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1826 /** FIXME: tickle the MB redirector chip */
1830 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1837 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1840 undirect_pci_irq(int rirq)
1844 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1846 /** FIXME: tickle the MB redirector chip */
1850 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1858 * given a bus ID, return:
1859 * the bus type if found
1863 apic_bus_type(int id)
1867 for (x = 0; x < mp_nbusses; ++x)
1868 if (bus_data[x].bus_id == id)
1869 return bus_data[x].bus_type;
1875 * given a LOGICAL APIC# and pin#, return:
1876 * the associated src bus ID if found
1880 apic_src_bus_id(int apic, int pin)
1884 /* search each of the possible INTerrupt sources */
1885 for (x = 0; x < nintrs; ++x)
1886 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1887 (pin == io_apic_ints[x].dst_apic_int))
1888 return (io_apic_ints[x].src_bus_id);
1890 return -1; /* NOT found */
1894 * given a LOGICAL APIC# and pin#, return:
1895 * the associated src bus IRQ if found
1899 apic_src_bus_irq(int apic, int pin)
1903 for (x = 0; x < nintrs; x++)
1904 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1905 (pin == io_apic_ints[x].dst_apic_int))
1906 return (io_apic_ints[x].src_bus_irq);
1908 return -1; /* NOT found */
1913 * given a LOGICAL APIC# and pin#, return:
1914 * the associated INTerrupt type if found
1918 apic_int_type(int apic, int pin)
1922 /* search each of the possible INTerrupt sources */
1923 for (x = 0; x < nintrs; ++x) {
1924 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1925 (pin == io_apic_ints[x].dst_apic_int))
1926 return (io_apic_ints[x].int_type);
1928 return -1; /* NOT found */
1932 * Return the IRQ associated with an APIC pin
1935 apic_irq(int apic, int pin)
1940 for (x = 0; x < nintrs; ++x) {
1941 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1942 (pin == io_apic_ints[x].dst_apic_int)) {
1943 res = io_apic_ints[x].int_vector;
1946 if (apic != int_to_apicintpin[res].ioapic)
1947 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1948 if (pin != int_to_apicintpin[res].int_pin)
1949 panic("apic_irq inconsistent table (2)");
1958 * given a LOGICAL APIC# and pin#, return:
1959 * the associated trigger mode if found
1963 apic_trigger(int apic, int pin)
1967 /* search each of the possible INTerrupt sources */
1968 for (x = 0; x < nintrs; ++x)
1969 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1970 (pin == io_apic_ints[x].dst_apic_int))
1971 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1973 return -1; /* NOT found */
1978 * given a LOGICAL APIC# and pin#, return:
1979 * the associated 'active' level if found
1983 apic_polarity(int apic, int pin)
1987 /* search each of the possible INTerrupt sources */
1988 for (x = 0; x < nintrs; ++x)
1989 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1990 (pin == io_apic_ints[x].dst_apic_int))
1991 return (io_apic_ints[x].int_flags & 0x03);
1993 return -1; /* NOT found */
1997 * set data according to MP defaults
1998 * FIXME: probably not complete yet...
2001 mptable_default(int type)
2007 kprintf(" MP default config type: %d\n", type);
2010 kprintf(" bus: ISA, APIC: 82489DX\n");
2013 kprintf(" bus: EISA, APIC: 82489DX\n");
2016 kprintf(" bus: EISA, APIC: 82489DX\n");
2019 kprintf(" bus: MCA, APIC: 82489DX\n");
2022 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2025 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2028 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2031 kprintf(" future type\n");
2037 /* one and only IO APIC */
2038 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2041 * sanity check, refer to MP spec section 3.6.6, last paragraph
2042 * necessary as some hardware isn't properly setting up the IO APIC
2044 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2045 if (io_apic_id != 2) {
2047 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2048 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2049 io_apic_set_id(0, 2);
2052 IO_TO_ID(0) = io_apic_id;
2053 ID_TO_IO(io_apic_id) = 0;
2055 /* fill out bus entries */
2064 bus_data[0].bus_id = default_data[type - 1][1];
2065 bus_data[0].bus_type = default_data[type - 1][2];
2066 bus_data[1].bus_id = default_data[type - 1][3];
2067 bus_data[1].bus_type = default_data[type - 1][4];
2070 /* case 4: case 7: MCA NOT supported */
2071 default: /* illegal/reserved */
2072 panic("BAD default MP config: %d", type);
2076 /* general cases from MP v1.4, table 5-2 */
2077 for (pin = 0; pin < 16; ++pin) {
2078 io_apic_ints[pin].int_type = 0;
2079 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2080 io_apic_ints[pin].src_bus_id = 0;
2081 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2082 io_apic_ints[pin].dst_apic_id = io_apic_id;
2083 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2086 /* special cases from MP v1.4, table 5-2 */
2088 io_apic_ints[2].int_type = 0xff; /* N/C */
2089 io_apic_ints[13].int_type = 0xff; /* N/C */
2090 #if !defined(APIC_MIXED_MODE)
2092 panic("sorry, can't support type 2 default yet");
2093 #endif /* APIC_MIXED_MODE */
2096 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2099 io_apic_ints[0].int_type = 0xff; /* N/C */
2101 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2105 * Map a physical memory address representing I/O into KVA. The I/O
2106 * block is assumed not to cross a page boundary.
2109 ioapic_map(vm_paddr_t pa)
2115 KKASSERT(pa < 0x100000000LL);
2117 pgeflag = 0; /* not used for SMP yet */
2120 * If the requested physical address has already been incidently
2121 * mapped, just use the existing mapping. Otherwise create a new
2124 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2125 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2126 ((vm_offset_t)pa & PG_FRAME)) {
2130 if (i == SMPpt_alloc_index) {
2131 if (i == NPTEPG - 2) {
2132 panic("permanent_io_mapping: We ran out of space"
2135 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2136 ((vm_offset_t)pa & PG_FRAME));
2137 ++SMPpt_alloc_index;
2139 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2140 ((vm_offset_t)pa & PAGE_MASK);
2141 return ((void *)vaddr);
2145 * start each AP in our list
2148 start_all_aps(u_int boot_addr)
2155 u_char mpbiosreason;
2156 u_long mpbioswarmvec;
2157 struct mdglobaldata *gd;
2158 struct privatespace *ps;
2162 POSTCODE(START_ALL_APS_POST);
2164 /* Initialize BSP's local APIC */
2168 MachIntrABI.finalize();
2170 /* install the AP 1st level boot code */
2171 install_ap_tramp(boot_addr);
2174 /* save the current value of the warm-start vector */
2175 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2176 outb(CMOS_REG, BIOS_RESET);
2177 mpbiosreason = inb(CMOS_DATA);
2179 /* setup a vector to our boot code */
2180 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2181 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2182 outb(CMOS_REG, BIOS_RESET);
2183 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2186 * If we have a TSC we can figure out the SMI interrupt rate.
2187 * The SMI does not necessarily use a constant rate. Spend
2188 * up to 250ms trying to figure it out.
2191 if (cpu_feature & CPUID_TSC) {
2192 set_apic_timer(275000);
2193 smilast = read_apic_timer();
2194 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2195 smicount = smitest();
2196 if (smibest == 0 || smilast - smicount < smibest)
2197 smibest = smilast - smicount;
2200 if (smibest > 250000)
2203 smibest = smibest * (int64_t)1000000 /
2204 get_apic_timer_frequency();
2208 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2209 1000000 / smibest, smibest);
2212 /* set up temporary P==V mapping for AP boot */
2213 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2214 kptbase = (uintptr_t)(void *)KPTphys;
2215 for (x = 0; x < NKPT; x++) {
2216 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2217 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2222 for (x = 1; x <= mp_naps; ++x) {
2224 /* This is a bit verbose, it will go away soon. */
2226 /* first page of AP's private space */
2227 pg = x * i386_btop(sizeof(struct privatespace));
2229 /* allocate new private data page(s) */
2230 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2231 MDGLOBALDATA_BASEALLOC_SIZE);
2232 /* wire it into the private page table page */
2233 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2234 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2235 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2237 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2239 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2240 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2241 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2242 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2244 /* allocate and set up an idle stack data page */
2245 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2246 for (i = 0; i < UPAGES; i++) {
2247 SMPpt[pg + 4 + i] = (pt_entry_t)
2248 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2251 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2252 bzero(gd, sizeof(*gd));
2253 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2255 /* prime data page for it to use */
2256 mi_gdinit(&gd->mi, x);
2258 gd->gd_CMAP1 = &SMPpt[pg + 0];
2259 gd->gd_CMAP2 = &SMPpt[pg + 1];
2260 gd->gd_CMAP3 = &SMPpt[pg + 2];
2261 gd->gd_PMAP1 = &SMPpt[pg + 3];
2262 gd->gd_CADDR1 = ps->CPAGE1;
2263 gd->gd_CADDR2 = ps->CPAGE2;
2264 gd->gd_CADDR3 = ps->CPAGE3;
2265 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2268 * Per-cpu pmap for get_ptbase().
2270 gd->gd_GDADDR1= (unsigned *)
2271 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2272 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2274 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2275 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2278 * Setup the AP boot stack
2280 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2283 /* attempt to start the Application Processor */
2284 CHECK_INIT(99); /* setup checkpoints */
2285 if (!start_ap(gd, boot_addr, smibest)) {
2286 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2287 CHECK_PRINT("trace"); /* show checkpoints */
2288 /* better panic as the AP may be running loose */
2289 kprintf("panic y/n? [y] ");
2290 if (cngetc() != 'n')
2293 CHECK_PRINT("trace"); /* show checkpoints */
2295 /* record its version info */
2296 cpu_apic_versions[x] = cpu_apic_versions[0];
2299 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2302 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2303 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2306 ncpus2_shift = shift;
2307 ncpus2 = 1 << shift;
2308 ncpus2_mask = ncpus2 - 1;
2310 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2311 if ((1 << shift) < ncpus)
2313 ncpus_fit = 1 << shift;
2314 ncpus_fit_mask = ncpus_fit - 1;
2316 /* build our map of 'other' CPUs */
2317 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2318 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2319 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2321 /* fill in our (BSP) APIC version */
2322 cpu_apic_versions[0] = lapic.version;
2324 /* restore the warmstart vector */
2325 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2326 outb(CMOS_REG, BIOS_RESET);
2327 outb(CMOS_DATA, mpbiosreason);
2330 * NOTE! The idlestack for the BSP was setup by locore. Finish
2331 * up, clean out the P==V mapping we did earlier.
2333 for (x = 0; x < NKPT; x++)
2337 /* number of APs actually started */
2342 * load the 1st level AP boot code into base memory.
2345 /* targets for relocation */
2346 extern void bigJump(void);
2347 extern void bootCodeSeg(void);
2348 extern void bootDataSeg(void);
2349 extern void MPentry(void);
2350 extern u_int MP_GDT;
2351 extern u_int mp_gdtbase;
2354 install_ap_tramp(u_int boot_addr)
2357 int size = *(int *) ((u_long) & bootMP_size);
2358 u_char *src = (u_char *) ((u_long) bootMP);
2359 u_char *dst = (u_char *) boot_addr + KERNBASE;
2360 u_int boot_base = (u_int) bootMP;
2365 POSTCODE(INSTALL_AP_TRAMP_POST);
2367 for (x = 0; x < size; ++x)
2371 * modify addresses in code we just moved to basemem. unfortunately we
2372 * need fairly detailed info about mpboot.s for this to work. changes
2373 * to mpboot.s might require changes here.
2376 /* boot code is located in KERNEL space */
2377 dst = (u_char *) boot_addr + KERNBASE;
2379 /* modify the lgdt arg */
2380 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2381 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2383 /* modify the ljmp target for MPentry() */
2384 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2385 *dst32 = ((u_int) MPentry - KERNBASE);
2387 /* modify the target for boot code segment */
2388 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2389 dst8 = (u_int8_t *) (dst16 + 1);
2390 *dst16 = (u_int) boot_addr & 0xffff;
2391 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2393 /* modify the target for boot data segment */
2394 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2395 dst8 = (u_int8_t *) (dst16 + 1);
2396 *dst16 = (u_int) boot_addr & 0xffff;
2397 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2402 * This function starts the AP (application processor) identified
2403 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2404 * to accomplish this. This is necessary because of the nuances
2405 * of the different hardware we might encounter. It ain't pretty,
2406 * but it seems to work.
2408 * NOTE: eventually an AP gets to ap_init(), which is called just
2409 * before the AP goes into the LWKT scheduler's idle loop.
2412 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2416 u_long icr_lo, icr_hi;
2418 POSTCODE(START_AP_POST);
2420 /* get the PHYSICAL APIC ID# */
2421 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2423 /* calculate the vector */
2424 vector = (boot_addr >> 12) & 0xff;
2426 /* We don't want anything interfering */
2429 /* Make sure the target cpu sees everything */
2433 * Try to detect when a SMI has occurred, wait up to 200ms.
2435 * If a SMI occurs during an AP reset but before we issue
2436 * the STARTUP command, the AP may brick. To work around
2437 * this problem we hold off doing the AP startup until
2438 * after we have detected the SMI. Hopefully another SMI
2439 * will not occur before we finish the AP startup.
2441 * Retries don't seem to help. SMIs have a window of opportunity
2442 * and if USB->legacy keyboard emulation is enabled in the BIOS
2443 * the interrupt rate can be quite high.
2445 * NOTE: Don't worry about the L1 cache load, it might bloat
2446 * ldelta a little but ndelta will be so huge when the SMI
2447 * occurs the detection logic will still work fine.
2450 set_apic_timer(200000);
2455 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2456 * and running the target CPU. OR this INIT IPI might be latched (P5
2457 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2460 * see apic/apicreg.h for icr bit definitions.
2462 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2466 * Setup the address for the target AP. We can setup
2467 * icr_hi once and then just trigger operations with
2470 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2471 icr_hi |= (physical_cpu << 24);
2472 icr_lo = lapic.icr_lo & 0xfff00000;
2473 lapic.icr_hi = icr_hi;
2476 * Do an INIT IPI: assert RESET
2478 * Use edge triggered mode to assert INIT
2480 lapic.icr_lo = icr_lo | 0x0000c500;
2481 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2485 * The spec calls for a 10ms delay but we may have to use a
2486 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2487 * interrupt. We have other loops here too and dividing by 2
2488 * doesn't seem to be enough even after subtracting 350us,
2489 * so we divide by 4.
2491 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2492 * interrupt was detected we use the full 10ms.
2496 else if (smibest < 150 * 4 + 350)
2498 else if ((smibest - 350) / 4 < 10000)
2499 u_sleep((smibest - 350) / 4);
2504 * Do an INIT IPI: deassert RESET
2506 * Use level triggered mode to deassert. It is unclear
2507 * why we need to do this.
2509 lapic.icr_lo = icr_lo | 0x00008500;
2510 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2512 u_sleep(150); /* wait 150us */
2515 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2516 * latched, (P5 bug) this 1st STARTUP would then terminate
2517 * immediately, and the previously started INIT IPI would continue. OR
2518 * the previous INIT IPI has already run. and this STARTUP IPI will
2519 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2522 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2523 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2525 u_sleep(200); /* wait ~200uS */
2528 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2529 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2530 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2531 * recognized after hardware RESET or INIT IPI.
2533 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2534 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2537 /* Resume normal operation */
2540 /* wait for it to start, see ap_init() */
2541 set_apic_timer(5000000);/* == 5 seconds */
2542 while (read_apic_timer()) {
2543 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2544 return 1; /* return SUCCESS */
2547 return 0; /* return FAILURE */
2562 while (read_apic_timer()) {
2564 for (count = 0; count < 100; ++count)
2565 ntsc = rdtsc(); /* force loop to occur */
2567 ndelta = ntsc - ltsc;
2568 if (ldelta > ndelta)
2570 if (ndelta > ldelta * 2)
2573 ldelta = ntsc - ltsc;
2576 return(read_apic_timer());
2580 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2582 * If for some reason we were unable to start all cpus we cannot safely
2583 * use broadcast IPIs.
2586 static cpumask_t smp_invltlb_req;
2587 #define SMP_INVLTLB_DEBUG
2593 struct mdglobaldata *md = mdcpu;
2594 #ifdef SMP_INVLTLB_DEBUG
2599 crit_enter_gd(&md->mi);
2600 md->gd_invltlb_ret = 0;
2601 ++md->mi.gd_cnt.v_smpinvltlb;
2602 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2603 #ifdef SMP_INVLTLB_DEBUG
2606 if (smp_startup_mask == smp_active_mask) {
2607 all_but_self_ipi(XINVLTLB_OFFSET);
2609 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2610 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2613 #ifdef SMP_INVLTLB_DEBUG
2615 kprintf("smp_invltlb: ipi sent\n");
2617 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2618 (smp_active_mask & ~md->mi.gd_cpumask)) {
2621 #ifdef SMP_INVLTLB_DEBUG
2623 if (++count == 400000000) {
2624 print_backtrace(-1);
2625 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2626 "rflags %016lx retry",
2627 (long)md->gd_invltlb_ret,
2628 (long)smp_invltlb_req,
2629 (long)read_eflags());
2630 __asm __volatile ("sti");
2633 lwkt_process_ipiq();
2635 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2636 ~md->mi.gd_cpumask &
2639 kprintf("bcpu %d\n", bcpu);
2640 xgd = globaldata_find(bcpu);
2641 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2650 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2651 crit_exit_gd(&md->mi);
2658 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2659 * bother to bump the critical section count or nested interrupt count
2660 * so only do very low level operations here.
2663 smp_invltlb_intr(void)
2665 struct mdglobaldata *md = mdcpu;
2666 struct mdglobaldata *omd;
2670 mask = smp_invltlb_req;
2674 cpu = BSFCPUMASK(mask);
2675 mask &= ~CPUMASK(cpu);
2676 omd = (struct mdglobaldata *)globaldata_find(cpu);
2677 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2684 * When called the executing CPU will send an IPI to all other CPUs
2685 * requesting that they halt execution.
2687 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2689 * - Signals all CPUs in map to stop.
2690 * - Waits for each to stop.
2697 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2698 * from executing at same time.
2701 stop_cpus(cpumask_t map)
2703 map &= smp_active_mask;
2705 /* send the Xcpustop IPI to all CPUs in map */
2706 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2708 while ((stopped_cpus & map) != map)
2716 * Called by a CPU to restart stopped CPUs.
2718 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2720 * - Signals all CPUs in map to restart.
2721 * - Waits for each to restart.
2729 restart_cpus(cpumask_t map)
2731 /* signal other cpus to restart */
2732 started_cpus = map & smp_active_mask;
2734 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2741 * This is called once the mpboot code has gotten us properly relocated
2742 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2743 * and when it returns the scheduler will call the real cpu_idle() main
2744 * loop for the idlethread. Interrupts are disabled on entry and should
2745 * remain disabled at return.
2753 * Adjust smp_startup_mask to signal the BSP that we have started
2754 * up successfully. Note that we do not yet hold the BGL. The BSP
2755 * is waiting for our signal.
2757 * We can't set our bit in smp_active_mask yet because we are holding
2758 * interrupts physically disabled and remote cpus could deadlock
2759 * trying to send us an IPI.
2761 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2765 * Interlock for finalization. Wait until mp_finish is non-zero,
2766 * then get the MP lock.
2768 * Note: We are in a critical section.
2770 * Note: we are the idle thread, we can only spin.
2772 * Note: The load fence is memory volatile and prevents the compiler
2773 * from improperly caching mp_finish, and the cpu from improperly
2776 while (mp_finish == 0)
2778 while (try_mplock() == 0)
2781 if (cpu_feature & CPUID_TSC) {
2783 * The BSP is constantly updating tsc0_offset, figure out
2784 * the relative difference to synchronize ktrdump.
2786 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2789 /* BSP may have changed PTD while we're waiting for the lock */
2792 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2796 /* Build our map of 'other' CPUs. */
2797 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2799 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2801 /* A quick check from sanity claus */
2802 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
2803 if (mycpu->gd_cpuid != apic_id) {
2804 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2805 kprintf("SMP: apic_id = %d\n", apic_id);
2806 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2807 panic("cpuid mismatch! boom!!");
2810 /* Initialize AP's local APIC for irq's */
2813 /* Set memory range attributes for this CPU to match the BSP */
2814 mem_range_AP_init();
2817 * Once we go active we must process any IPIQ messages that may
2818 * have been queued, because no actual IPI will occur until we
2819 * set our bit in the smp_active_mask. If we don't the IPI
2820 * message interlock could be left set which would also prevent
2823 * The idle loop doesn't expect the BGL to be held and while
2824 * lwkt_switch() normally cleans things up this is a special case
2825 * because we returning almost directly into the idle loop.
2827 * The idle thread is never placed on the runq, make sure
2828 * nothing we've done put it there.
2830 KKASSERT(get_mplock_count(curthread) == 1);
2831 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2834 * Enable interrupts here. idle_restore will also do it, but
2835 * doing it here lets us clean up any strays that got posted to
2836 * the CPU during the AP boot while we are still in a critical
2839 __asm __volatile("sti; pause; pause"::);
2840 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2842 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2843 lwkt_process_ipiq();
2846 * Releasing the mp lock lets the BSP finish up the SMP init
2849 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2853 * Get SMP fully working before we start initializing devices.
2861 kprintf("Finish MP startup\n");
2862 if (cpu_feature & CPUID_TSC)
2863 tsc0_offset = rdtsc();
2866 while (smp_active_mask != smp_startup_mask) {
2868 if (cpu_feature & CPUID_TSC)
2869 tsc0_offset = rdtsc();
2871 while (try_mplock() == 0)
2874 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2877 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2880 cpu_send_ipiq(int dcpu)
2882 if (CPUMASK(dcpu) & smp_active_mask)
2883 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2886 #if 0 /* single_apic_ipi_passive() not working yet */
2888 * Returns 0 on failure, 1 on success
2891 cpu_send_ipiq_passive(int dcpu)
2894 if (CPUMASK(dcpu) & smp_active_mask) {
2895 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2896 APIC_DELMODE_FIXED);
2903 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2905 struct mptable_bus_info *bus_info = xarg;
2906 const struct BUSENTRY *ent;
2907 struct mptable_bus *bus;
2913 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2914 if (bus->mb_id == ent->bus_id) {
2915 kprintf("mptable_bus_info_alloc: duplicated bus id "
2916 "(%d)\n", bus->mb_id);
2922 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2923 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2924 bus->mb_type = MPTABLE_BUS_PCI;
2925 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2926 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2927 bus->mb_type = MPTABLE_BUS_ISA;
2931 bus->mb_id = ent->bus_id;
2932 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2938 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2942 bzero(bus_info, sizeof(*bus_info));
2943 TAILQ_INIT(&bus_info->mbi_list);
2945 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2947 mptable_bus_info_free(bus_info);
2951 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2953 struct mptable_bus *bus;
2955 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2956 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2961 struct mptable_lapic_cbarg1 {
2964 u_int ht_apicid_mask;
2968 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2970 const struct PROCENTRY *ent;
2971 struct mptable_lapic_cbarg1 *arg = xarg;
2977 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2981 if (ent->apic_id < 32) {
2982 arg->ht_apicid_mask |= 1 << ent->apic_id;
2983 } else if (arg->ht_fixup) {
2984 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2990 struct mptable_lapic_cbarg2 {
2997 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2999 const struct PROCENTRY *ent;
3000 struct mptable_lapic_cbarg2 *arg = xarg;
3006 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3007 KKASSERT(!arg->found_bsp);
3011 if (processor_entry(ent, arg->cpu))
3014 if (arg->logical_cpus) {
3015 struct PROCENTRY proc;
3019 * Create fake mptable processor entries
3020 * and feed them to processor_entry() to
3021 * enumerate the logical CPUs.
3023 bzero(&proc, sizeof(proc));
3025 proc.cpu_flags = PROCENTRY_FLAG_EN;
3026 proc.apic_id = ent->apic_id;
3028 for (i = 1; i < arg->logical_cpus; i++) {
3030 processor_entry(&proc, arg->cpu);
3038 mptable_lapic_default(void)
3040 int ap_apicid, bsp_apicid;
3042 mp_naps = 1; /* exclude BSP */
3044 /* Map local apic before the id field is accessed */
3045 lapic_map(DEFAULT_APIC_BASE);
3047 bsp_apicid = APIC_ID(lapic.id);
3048 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3051 mp_set_cpuids(0, bsp_apicid);
3052 /* one and only AP */
3053 mp_set_cpuids(1, ap_apicid);
3059 * ID_TO_CPU(N), APIC ID to logical CPU table
3060 * CPU_TO_ID(N), logical CPU to APIC ID table
3063 mptable_lapic_enumerate(struct lapic_enumerator *e)
3065 struct mptable_pos mpt;
3066 struct mptable_lapic_cbarg1 arg1;
3067 struct mptable_lapic_cbarg2 arg2;
3069 int error, logical_cpus = 0;
3070 vm_offset_t lapic_addr;
3072 if (mptable_use_default) {
3073 mptable_lapic_default();
3077 error = mptable_map(&mpt);
3079 panic("mptable_lapic_enumerate mptable_map failed\n");
3080 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3084 /* Save local apic address */
3085 lapic_addr = (vm_offset_t)cth->apic_address;
3086 KKASSERT(lapic_addr != 0);
3089 * Find out how many CPUs do we have
3091 bzero(&arg1, sizeof(arg1));
3092 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3094 error = mptable_iterate_entries(cth,
3095 mptable_lapic_pass1_callback, &arg1);
3097 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3098 KKASSERT(arg1.cpu_count != 0);
3100 /* See if we need to fixup HT logical CPUs. */
3101 if (arg1.ht_fixup) {
3102 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3104 if (logical_cpus != 0)
3105 arg1.cpu_count *= logical_cpus;
3107 mp_naps = arg1.cpu_count;
3109 /* Qualify the numbers again, after possible HT fixup */
3110 if (mp_naps > MAXCPU) {
3111 kprintf("Warning: only using %d of %d available CPUs!\n",
3116 --mp_naps; /* subtract the BSP */
3119 * Link logical CPU id to local apic id
3121 bzero(&arg2, sizeof(arg2));
3123 arg2.logical_cpus = logical_cpus;
3125 error = mptable_iterate_entries(cth,
3126 mptable_lapic_pass2_callback, &arg2);
3128 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3129 KKASSERT(arg2.found_bsp);
3131 /* Map local apic */
3132 lapic_map(lapic_addr);
3134 mptable_unmap(&mpt);
3137 struct mptable_lapic_probe_cbarg {
3143 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3145 const struct PROCENTRY *ent;
3146 struct mptable_lapic_probe_cbarg *arg = xarg;
3152 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3156 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3157 if (arg->found_bsp) {
3158 kprintf("more than one BSP in base MP table\n");
3167 mptable_lapic_probe(struct lapic_enumerator *e)
3169 struct mptable_pos mpt;
3170 struct mptable_lapic_probe_cbarg arg;
3174 if (mptable_fps_phyaddr == 0)
3177 if (mptable_use_default)
3180 error = mptable_map(&mpt);
3183 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3188 if (cth->apic_address == 0)
3191 bzero(&arg, sizeof(arg));
3192 error = mptable_iterate_entries(cth,
3193 mptable_lapic_probe_callback, &arg);
3195 if (arg.cpu_count == 0) {
3196 kprintf("MP table contains no processor entries\n");
3198 } else if (!arg.found_bsp) {
3199 kprintf("MP table does not contains BSP entry\n");
3204 mptable_unmap(&mpt);
3208 static struct lapic_enumerator mptable_lapic_enumerator = {
3209 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3210 .lapic_probe = mptable_lapic_probe,
3211 .lapic_enumerate = mptable_lapic_enumerate
3215 mptable_lapic_enum_register(void)
3217 lapic_enumerator_register(&mptable_lapic_enumerator);
3219 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3220 mptable_lapic_enum_register, 0);
3223 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
3225 const struct IOAPICENTRY *ent;
3226 struct mptable_ioapic *nioapic, *ioapic;
3232 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3235 if (ent->apic_address == 0) {
3236 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
3240 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3241 if (ioapic->mio_apic_id == ent->apic_id) {
3242 kprintf("mptable_ioapic_create_list: duplicated "
3243 "apic id %d\n", ioapic->mio_apic_id);
3246 if (ioapic->mio_addr == (uint32_t)ent->apic_address) {
3247 kprintf("mptable_ioapic_create_list: overlapped "
3248 "IOAPIC addr 0x%08x", ioapic->mio_addr);
3253 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3254 nioapic->mio_apic_id = ent->apic_id;
3255 nioapic->mio_addr = (uint32_t)ent->apic_address;
3258 * Create IOAPIC list in ascending order of APIC ID
3260 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
3261 mptable_ioapic_list, mio_link) {
3262 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
3263 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
3264 ioapic, nioapic, mio_link);
3269 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
3275 mptable_ioapic_create_list(void)
3277 struct mptable_ioapic *ioapic;
3278 struct mptable_pos mpt;
3281 if (mptable_fps_phyaddr == 0)
3284 if (mptable_use_default) {
3285 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3286 ioapic->mio_idx = 0;
3287 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
3288 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
3290 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
3294 error = mptable_map(&mpt);
3296 panic("mptable_ioapic_create_list: mptable_map failed\n");
3297 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3299 error = mptable_iterate_entries(mpt.mp_cth,
3300 mptable_ioapic_list_callback, NULL);
3302 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
3303 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
3304 kfree(ioapic, M_DEVBUF);
3310 * Assign index number for each IOAPIC
3313 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3314 ioapic->mio_idx = idx;
3318 mptable_unmap(&mpt);
3320 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
3321 mptable_ioapic_create_list, 0);
3324 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3326 const struct mptable_bus_info *bus_info = xarg;
3327 const struct mptable_ioapic *ioapic;
3328 const struct mptable_bus *bus;
3329 struct mptable_pci_int *pci_int;
3330 const struct INTENTRY *ent;
3331 int pci_pin, pci_dev;
3337 if (ent->int_type != 0)
3340 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3341 if (bus->mb_type == MPTABLE_BUS_PCI &&
3342 bus->mb_id == ent->src_bus_id)
3348 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3349 if (ioapic->mio_apic_id == ent->dst_apic_id)
3352 if (ioapic == NULL) {
3353 kprintf("MPTABLE: warning PCI int dst apic id %d "
3354 "does not exist\n", ent->dst_apic_id);
3358 pci_pin = ent->src_bus_irq & 0x3;
3359 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3361 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3362 if (pci_int->mpci_bus == ent->src_bus_id &&
3363 pci_int->mpci_dev == pci_dev &&
3364 pci_int->mpci_pin == pci_pin) {
3365 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
3366 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3367 kprintf("MPTABLE: warning duplicated "
3368 "PCI int entry for "
3369 "bus %d, dev %d, pin %d\n",
3375 kprintf("mptable_pci_int_register: "
3376 "conflict PCI int entry for "
3377 "bus %d, dev %d, pin %d, "
3378 "IOAPIC %d.%d -> %d.%d\n",
3382 pci_int->mpci_ioapic_idx,
3383 pci_int->mpci_ioapic_pin,
3391 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3393 pci_int->mpci_bus = ent->src_bus_id;
3394 pci_int->mpci_dev = pci_dev;
3395 pci_int->mpci_pin = pci_pin;
3396 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
3397 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3399 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3405 mptable_pci_int_register(void)
3407 struct mptable_bus_info bus_info;
3408 const struct mptable_bus *bus;
3409 struct mptable_pci_int *pci_int;
3410 struct mptable_pos mpt;
3411 int error, force_pci0, npcibus;
3414 if (mptable_fps_phyaddr == 0)
3417 if (mptable_use_default)
3420 if (TAILQ_EMPTY(&mptable_ioapic_list))
3423 error = mptable_map(&mpt);
3425 panic("mptable_pci_int_register: mptable_map failed\n");
3426 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3430 mptable_bus_info_alloc(cth, &bus_info);
3431 if (TAILQ_EMPTY(&bus_info.mbi_list))
3435 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3436 if (bus->mb_type == MPTABLE_BUS_PCI)
3440 mptable_bus_info_free(&bus_info);
3442 } else if (npcibus == 1) {
3446 error = mptable_iterate_entries(cth,
3447 mptable_pci_int_callback, &bus_info);
3449 mptable_bus_info_free(&bus_info);
3452 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3453 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3454 kfree(pci_int, M_DEVBUF);
3460 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3461 pci_int->mpci_bus = 0;
3464 mptable_unmap(&mpt);
3466 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3467 mptable_pci_int_register, 0);
3469 struct mptable_ioapic_probe_cbarg {
3470 const struct mptable_bus_info *bus_info;
3474 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3476 struct mptable_ioapic_probe_cbarg *arg = xarg;
3477 const struct mptable_ioapic *ioapic;
3478 const struct mptable_bus *bus;
3479 const struct INTENTRY *ent;
3485 if (ent->int_type != 0)
3488 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3489 if (bus->mb_type == MPTABLE_BUS_ISA &&
3490 bus->mb_id == ent->src_bus_id)
3496 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3497 if (ioapic->mio_apic_id == ent->dst_apic_id)
3500 if (ioapic == NULL) {
3501 kprintf("MPTABLE: warning ISA int dst apic id %d "
3502 "does not exist\n", ent->dst_apic_id);
3506 /* XXX magic number */
3507 if (ent->src_bus_irq >= 16) {
3508 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
3516 mptable_ioapic_probe(struct ioapic_enumerator *e)
3518 struct mptable_ioapic_probe_cbarg arg;
3519 struct mptable_bus_info bus_info;
3520 struct mptable_pos mpt;
3524 if (mptable_fps_phyaddr == 0)
3527 if (mptable_use_default)
3530 if (TAILQ_EMPTY(&mptable_ioapic_list))
3533 error = mptable_map(&mpt);
3535 panic("mptable_ioapic_probe: mptable_map failed\n");
3536 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3540 mptable_bus_info_alloc(cth, &bus_info);
3542 bzero(&arg, sizeof(arg));
3543 arg.bus_info = &bus_info;
3545 error = mptable_iterate_entries(cth,
3546 mptable_ioapic_probe_callback, &arg);
3548 mptable_bus_info_free(&bus_info);
3549 mptable_unmap(&mpt);
3554 struct mptable_ioapic_int_cbarg {
3555 const struct mptable_bus_info *bus_info;
3560 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3562 struct mptable_ioapic_int_cbarg *arg = xarg;
3563 const struct mptable_ioapic *ioapic;
3564 const struct mptable_bus *bus;
3565 const struct INTENTRY *ent;
3573 if (ent->int_type != 0)
3576 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3577 if (bus->mb_type == MPTABLE_BUS_ISA &&
3578 bus->mb_id == ent->src_bus_id)
3584 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3585 if (ioapic->mio_apic_id == ent->dst_apic_id)
3588 if (ioapic == NULL) {
3589 kprintf("MPTABLE: warning ISA int dst apic id %d "
3590 "does not exist\n", ent->dst_apic_id);
3594 if (!ioapic_use_old) {
3597 if (ent->dst_apic_int >= ioapic->mio_npin) {
3598 panic("mptable_ioapic_enumerate: invalid I/O APIC "
3599 "pin %d, should be < %d",
3600 ent->dst_apic_int, ioapic->mio_npin);
3602 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
3604 if (ent->src_bus_irq != gsi) {
3606 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3607 ent->src_bus_irq, gsi);
3609 ioapic_intsrc(ent->src_bus_irq, gsi);
3612 /* XXX rough estimation */
3613 if (ent->src_bus_irq != ent->dst_apic_int) {
3615 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3616 ent->src_bus_irq, ent->dst_apic_int);
3624 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3626 struct mptable_bus_info bus_info;
3627 struct mptable_ioapic *ioapic;
3628 struct mptable_pos mpt;
3632 KKASSERT(mptable_fps_phyaddr != 0);
3633 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
3635 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3636 if (!ioapic_use_old) {
3637 const struct mptable_ioapic *prev_ioapic;
3641 addr = ioapic_map(ioapic->mio_addr);
3643 ver = ioapic_read(addr, IOAPIC_VER);
3644 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
3645 >> MAXREDIRSHIFT) + 1;
3647 prev_ioapic = TAILQ_PREV(ioapic,
3648 mptable_ioapic_list, mio_link);
3649 if (prev_ioapic == NULL) {
3650 ioapic->mio_gsi_base = 0;
3652 ioapic->mio_gsi_base =
3653 prev_ioapic->mio_gsi_base +
3654 prev_ioapic->mio_npin;
3656 ioapic_add(addr, ioapic->mio_gsi_base,
3660 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
3661 "apic id %d, idx %d, gsi base %d, npin %d\n",
3663 ioapic->mio_apic_id,
3665 ioapic->mio_gsi_base,
3670 if (mptable_use_default) {
3672 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3673 ioapic_intsrc(0, 2);
3677 error = mptable_map(&mpt);
3679 panic("mptable_ioapic_probe: mptable_map failed\n");
3680 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3684 mptable_bus_info_alloc(cth, &bus_info);
3686 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3688 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3689 ioapic_intsrc(0, 2);
3691 struct mptable_ioapic_int_cbarg arg;
3693 bzero(&arg, sizeof(arg));
3694 arg.bus_info = &bus_info;
3696 error = mptable_iterate_entries(cth,
3697 mptable_ioapic_int_callback, &arg);
3699 panic("mptable_ioapic_int failed\n");
3701 if (arg.ioapic_nint == 0) {
3703 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3706 ioapic_intsrc(0, 2);
3710 mptable_bus_info_free(&bus_info);
3712 mptable_unmap(&mpt);
3715 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3716 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3717 .ioapic_probe = mptable_ioapic_probe,
3718 .ioapic_enumerate = mptable_ioapic_enumerate
3722 mptable_ioapic_enum_register(void)
3724 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3726 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3727 mptable_ioapic_enum_register, 0);