2 * Copyright 1996 Massachusetts Institute of Technology
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5 * its documentation for any purpose and without fee is hereby
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29 * $FreeBSD: src/sys/i386/i386/perfmon.c,v 1.21 1999/09/25 18:24:04 phk Exp $
30 * $DragonFly: src/sys/platform/pc32/i386/perfmon.c,v 1.9 2006/07/28 02:17:39 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/device.h>
37 #include <sys/fcntl.h>
41 #include <machine/cputypes.h>
43 #include <machine/clock.h>
44 #include <machine/perfmon.h>
46 static int perfmon_inuse;
47 static int perfmon_cpuok;
49 static int msr_ctl[NPMC];
51 static int msr_pmc[NPMC];
52 static unsigned int ctl_shadow[NPMC];
53 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
54 static int (*writectl)(int);
56 static int writectl5(int);
57 static int writectl6(int);
60 static d_close_t perfmon_close;
61 static d_open_t perfmon_open;
62 static d_ioctl_t perfmon_ioctl;
64 #define CDEV_MAJOR 2 /* We're really a minor of mem.c */
65 static struct dev_ops perfmon_ops = {
66 { "perfmon", CDEV_MAJOR, 0 },
67 .d_open = perfmon_open,
68 .d_close = perfmon_close,
69 .d_ioctl = perfmon_ioctl,
73 * Must be called after cpu_class is set up.
103 /* NOTE: really a minor of mem. perfmon gets 32-47 */
104 dev_ops_add(&perfmon_ops, 0xf0, 32);
105 make_dev(&perfmon_ops, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
111 return perfmon_cpuok;
115 perfmon_setup(int pmc, unsigned int control)
117 if (pmc < 0 || pmc >= NPMC)
120 perfmon_inuse |= (1 << pmc);
121 control &= ~(PMCF_SYS_FLAGS << 16);
122 mpintr_lock(); /* doesn't have to be mpintr_lock YYY */
123 ctl_shadow[pmc] = control;
125 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
131 perfmon_get(int pmc, unsigned int *control)
133 if (pmc < 0 || pmc >= NPMC)
136 if (perfmon_inuse & (1 << pmc)) {
137 *control = ctl_shadow[pmc];
140 return EBUSY; /* XXX reversed sense */
144 perfmon_fini(int pmc)
146 if (pmc < 0 || pmc >= NPMC)
149 if (perfmon_inuse & (1 << pmc)) {
152 perfmon_inuse &= ~(1 << pmc);
155 return EBUSY; /* XXX reversed sense */
159 perfmon_start(int pmc)
161 if (pmc < 0 || pmc >= NPMC)
164 if (perfmon_inuse & (1 << pmc)) {
165 mpintr_lock(); /* doesn't have to be mpintr YYY */
166 ctl_shadow[pmc] |= (PMCF_EN << 16);
167 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
176 perfmon_stop(int pmc)
178 if (pmc < 0 || pmc >= NPMC)
181 if (perfmon_inuse & (1 << pmc)) {
183 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
184 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
193 perfmon_read(int pmc, quad_t *val)
195 if (pmc < 0 || pmc >= NPMC)
198 if (perfmon_inuse & (1 << pmc)) {
199 if (ctl_shadow[pmc] & (PMCF_EN << 16))
200 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
202 *val = pmc_shadow[pmc];
210 perfmon_reset(int pmc)
212 if (pmc < 0 || pmc >= NPMC)
215 if (perfmon_inuse & (1 << pmc)) {
216 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
224 * Unfortunately, the performance-monitoring registers are laid out
225 * differently in the P5 and P6. We keep everything in P6 format
226 * internally (except for the event code), and convert to P5
227 * format as needed on those CPUs. The writectl function pointer
228 * is set up to point to one of these functions by perfmon_init().
233 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
234 wrmsr(msr_ctl[pmc], 0);
236 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
241 #define P5FLAG_P 0x200
242 #define P5FLAG_E 0x100
243 #define P5FLAG_USR 0x80
244 #define P5FLAG_OS 0x40
251 if (ctl_shadow[1] & (PMCF_EN << 16)) {
252 if (ctl_shadow[1] & (PMCF_USR << 16))
253 newval |= P5FLAG_USR << 16;
254 if (ctl_shadow[1] & (PMCF_OS << 16))
255 newval |= P5FLAG_OS << 16;
256 if (!(ctl_shadow[1] & (PMCF_E << 16)))
257 newval |= P5FLAG_E << 16;
258 newval |= (ctl_shadow[1] & 0x3f) << 16;
260 if (ctl_shadow[0] & (PMCF_EN << 16)) {
261 if (ctl_shadow[0] & (PMCF_USR << 16))
262 newval |= P5FLAG_USR;
263 if (ctl_shadow[0] & (PMCF_OS << 16))
265 if (!(ctl_shadow[0] & (PMCF_E << 16)))
267 newval |= ctl_shadow[0] & 0x3f;
270 wrmsr(msr_ctl[0], newval);
271 return 0; /* XXX should check for unimplemented bits */
276 * Now the user-mode interface, called from a subdevice of mem.c.
279 static int writerpmc;
282 perfmon_open(struct dev_open_args *ap)
287 if (ap->a_oflags & FWRITE) {
299 perfmon_close(struct dev_close_args *ap)
301 if (ap->a_fflag & FWRITE) {
304 for (i = 0; i < NPMC; i++) {
305 if (writerpmc & (1 << i))
314 perfmon_ioctl(struct dev_ioctl_args *ap)
316 caddr_t param = ap->a_data;
318 struct pmc_data *pmcd;
319 struct pmc_tstamp *pmct;
325 if (!(ap->a_fflag & FWRITE))
327 pmc = (struct pmc *)param;
329 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
331 writerpmc |= (1 << pmc->pmc_num);
336 pmc = (struct pmc *)param;
337 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
341 if (!(ap->a_fflag & FWRITE))
345 rv = perfmon_start(*ip);
349 if (!(ap->a_fflag & FWRITE))
353 rv = perfmon_stop(*ip);
357 if (!(ap->a_fflag & FWRITE))
361 rv = perfmon_reset(*ip);
365 pmcd = (struct pmc_data *)param;
366 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
374 pmct = (struct pmc_tstamp *)param;
375 /* XXX interface loses precision. */
376 pmct->pmct_rate = tsc_freq / 1000000;
377 pmct->pmct_value = rdtsc();