sys/dev/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include <uapi_drm/radeon_drm.h>
  31 #include "radeon_asic.h"
  32 #include "radeon_kms.h"
  33
  34 #include <linux/slab.h>
  35
  36 /**
  37  * radeon_driver_unload_kms - Main unload function for KMS.
  38  *
  39  * @dev: drm dev pointer
  40  *
  41  * This is the main unload function for KMS (all asics).
  42  * It calls radeon_modeset_fini() to tear down the
  43  * displays, and radeon_device_fini() to tear down
  44  * the rest of the device (CP, writeback, etc.).
  45  * Returns 0 on success.
  46  */
  47 int radeon_driver_unload_kms(struct drm_device *dev)
  48 {
  49         struct radeon_device *rdev = dev->dev_private;
  50
  51         if (rdev == NULL)
  52                 return 0;
  53         if (rdev->rmmio == NULL)
  54                 goto done_free;
  55         radeon_acpi_fini(rdev);
  56         radeon_modeset_fini(rdev);
  57         radeon_device_fini(rdev);
  58
  59 done_free:
  60         kfree(rdev);
  61         dev->dev_private = NULL;
  62         return 0;
  63 }
  64
  65 /**
  66  * radeon_driver_load_kms - Main load function for KMS.
  67  *
  68  * @dev: drm dev pointer
  69  * @flags: device flags
  70  *
  71  * This is the main load function for KMS (all asics).
  72  * It calls radeon_device_init() to set up the non-display
  73  * parts of the chip (asic init, CP, writeback, etc.), and
  74  * radeon_modeset_init() to set up the display parts
  75  * (crtcs, encoders, hotplug detect, etc.).
  76  * Returns 0 on success, error on failure.
  77  */
  78 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  79 {
  80         struct radeon_device *rdev;
  81         int r, acpi_status;
  82
  83         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  84         if (rdev == NULL) {
  85                 return -ENOMEM;
  86         }
  87         dev->dev_private = (void *)rdev;
  88
  89         /* update BUS flag */
  90         if (drm_device_is_agp(dev)) {
  91                 DRM_INFO("RADEON_IS_AGP\n");
  92                 flags |= RADEON_IS_AGP;
  93         } else if (drm_device_is_pcie(dev)) {
  94                 DRM_INFO("RADEON_IS_PCIE\n");
  95                 flags |= RADEON_IS_PCIE;
  96         } else {
  97                 DRM_INFO("RADEON_IS_PCI\n");
  98                 flags |= RADEON_IS_PCI;
  99         }
 100
 101         /* radeon_device_init should report only fatal error
 102          * like memory allocation failure or iomapping failure,
 103          * or memory manager initialization failure, it must
 104          * properly initialize the GPU MC controller and permit
 105          * VRAM allocation
 106          */
 107         r = radeon_device_init(rdev, dev, flags);
 108         if (r) {
 109                 dev_err(dev->dev, "Fatal error during GPU init\n");
 110                 goto out;
 111         }
 112
 113         /* Again modeset_init should fail only on fatal error
 114          * otherwise it should provide enough functionalities
 115          * for shadowfb to run
 116          */
 117         r = radeon_modeset_init(rdev);
 118         if (r)
 119                 dev_err(dev->dev, "Fatal error during modeset init\n");
 120
 121         /* Call ACPI methods: require modeset init
 122          * but failure is not fatal
 123          */
 124         if (!r) {
 125                 acpi_status = radeon_acpi_init(rdev);
 126                 if (acpi_status)
 127                 dev_dbg(dev->dev,
 128                                 "Error during ACPI methods call\n");
 129         }
 130
 131 out:
 132         if (r)
 133                 radeon_driver_unload_kms(dev);
 134         return r;
 135 }
 136
 137 /**
 138  * radeon_set_filp_rights - Set filp right.
 139  *
 140  * @dev: drm dev pointer
 141  * @owner: drm file
 142  * @applier: drm file
 143  * @value: value
 144  *
 145  * Sets the filp rights for the device (all asics).
 146  */
 147 static void radeon_set_filp_rights(struct drm_device *dev,
 148                                    struct drm_file **owner,
 149                                    struct drm_file *applier,
 150                                    uint32_t *value)
 151 {
 152         DRM_LOCK(dev);
 153         if (*value == 1) {
 154                 /* wants rights */
 155                 if (!*owner)
 156                         *owner = applier;
 157         } else if (*value == 0) {
 158                 /* revokes rights */
 159                 if (*owner == applier)
 160                         *owner = NULL;
 161         }
 162         *value = *owner == applier ? 1 : 0;
 163         DRM_UNLOCK(dev);
 164 }
 165
 166 /*
 167  * Userspace get information ioctl
 168  */
 169 /**
 170  * radeon_info_ioctl - answer a device specific request.
 171  *
 172  * @rdev: radeon device pointer
 173  * @data: request object
 174  * @filp: drm filp
 175  *
 176  * This function is used to pass device specific parameters to the userspace
 177  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 178  * etc. (all asics).
 179  * Returns 0 on success, -EINVAL on failure.
 180  */
 181 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 182 {
 183         struct radeon_device *rdev = dev->dev_private;
 184         struct drm_radeon_info *info = data;
 185         struct radeon_mode_info *minfo = &rdev->mode_info;
 186         uint32_t *value, value_tmp, *value_ptr, value_size;
 187         uint64_t value64;
 188         struct drm_crtc *crtc;
 189         int i, found;
 190
 191         value_ptr = (uint32_t *)((unsigned long)info->value);
 192         value = &value_tmp;
 193         value_size = sizeof(uint32_t);
 194
 195         switch (info->request) {
 196         case RADEON_INFO_DEVICE_ID:
 197                 *value = dev->pci_device;
 198                 break;
 199         case RADEON_INFO_NUM_GB_PIPES:
 200                 *value = rdev->num_gb_pipes;
 201                 break;
 202         case RADEON_INFO_NUM_Z_PIPES:
 203                 *value = rdev->num_z_pipes;
 204                 break;
 205         case RADEON_INFO_ACCEL_WORKING:
 206                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 207                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 208                         *value = false;
 209                 else
 210                         *value = rdev->accel_working;
 211                 break;
 212         case RADEON_INFO_CRTC_FROM_ID:
 213                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 214                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 215                         return -EFAULT;
 216                 }
 217                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 218                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 219                         if (crtc && crtc->base.id == *value) {
 220                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 221                                 *value = radeon_crtc->crtc_id;
 222                                 found = 1;
 223                                 break;
 224                         }
 225                 }
 226                 if (!found) {
 227                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 228                         return -EINVAL;
 229                 }
 230                 break;
 231         case RADEON_INFO_ACCEL_WORKING2:
 232                 *value = rdev->accel_working;
 233                 break;
 234         case RADEON_INFO_TILING_CONFIG:
 235                 if (rdev->family >= CHIP_BONAIRE)
 236                         *value = rdev->config.cik.tile_config;
 237                 else if (rdev->family >= CHIP_TAHITI)
 238                         *value = rdev->config.si.tile_config;
 239                 else if (rdev->family >= CHIP_CAYMAN)
 240                         *value = rdev->config.cayman.tile_config;
 241                 else if (rdev->family >= CHIP_CEDAR)
 242                         *value = rdev->config.evergreen.tile_config;
 243                 else if (rdev->family >= CHIP_RV770)
 244                         *value = rdev->config.rv770.tile_config;
 245                 else if (rdev->family >= CHIP_R600)
 246                         *value = rdev->config.r600.tile_config;
 247                 else {
 248                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 249                         return -EINVAL;
 250                 }
 251                 break;
 252         case RADEON_INFO_WANT_HYPERZ:
 253                 /* The "value" here is both an input and output parameter.
 254                  * If the input value is 1, filp requests hyper-z access.
 255                  * If the input value is 0, filp revokes its hyper-z access.
 256                  *
 257                  * When returning, the value is 1 if filp owns hyper-z access,
 258                  * 0 otherwise. */
 259                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 260                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 261                         return -EFAULT;
 262                 }
 263                 if (*value >= 2) {
 264                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 265                         return -EINVAL;
 266                 }
 267                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 268                 break;
 269         case RADEON_INFO_WANT_CMASK:
 270                 /* The same logic as Hyper-Z. */
 271                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 272                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 273                         return -EFAULT;
 274                 }
 275                 if (*value >= 2) {
 276                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 277                         return -EINVAL;
 278                 }
 279                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 280                 break;
 281         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 282                 /* return clock value in KHz */
 283                 if (rdev->asic->get_xclk)
 284                         *value = radeon_get_xclk(rdev) * 10;
 285                 else
 286                         *value = rdev->clock.spll.reference_freq * 10;
 287                 break;
 288         case RADEON_INFO_NUM_BACKENDS:
 289                 if (rdev->family >= CHIP_BONAIRE)
 290                         *value = rdev->config.cik.max_backends_per_se *
 291                                 rdev->config.cik.max_shader_engines;
 292                 else if (rdev->family >= CHIP_TAHITI)
 293                         *value = rdev->config.si.max_backends_per_se *
 294                                 rdev->config.si.max_shader_engines;
 295                 else if (rdev->family >= CHIP_CAYMAN)
 296                         *value = rdev->config.cayman.max_backends_per_se *
 297                                 rdev->config.cayman.max_shader_engines;
 298                 else if (rdev->family >= CHIP_CEDAR)
 299                         *value = rdev->config.evergreen.max_backends;
 300                 else if (rdev->family >= CHIP_RV770)
 301                         *value = rdev->config.rv770.max_backends;
 302                 else if (rdev->family >= CHIP_R600)
 303                         *value = rdev->config.r600.max_backends;
 304                 else {
 305                         return -EINVAL;
 306                 }
 307                 break;
 308         case RADEON_INFO_NUM_TILE_PIPES:
 309                 if (rdev->family >= CHIP_BONAIRE)
 310                         *value = rdev->config.cik.max_tile_pipes;
 311                 else if (rdev->family >= CHIP_TAHITI)
 312                         *value = rdev->config.si.max_tile_pipes;
 313                 else if (rdev->family >= CHIP_CAYMAN)
 314                         *value = rdev->config.cayman.max_tile_pipes;
 315                 else if (rdev->family >= CHIP_CEDAR)
 316                         *value = rdev->config.evergreen.max_tile_pipes;
 317                 else if (rdev->family >= CHIP_RV770)
 318                         *value = rdev->config.rv770.max_tile_pipes;
 319                 else if (rdev->family >= CHIP_R600)
 320                         *value = rdev->config.r600.max_tile_pipes;
 321                 else {
 322                         return -EINVAL;
 323                 }
 324                 break;
 325         case RADEON_INFO_FUSION_GART_WORKING:
 326                 *value = 1;
 327                 break;
 328         case RADEON_INFO_BACKEND_MAP:
 329                 if (rdev->family >= CHIP_BONAIRE)
 330                         return -EINVAL;
 331                 else if (rdev->family >= CHIP_TAHITI)
 332                         *value = rdev->config.si.backend_map;
 333                 else if (rdev->family >= CHIP_CAYMAN)
 334                         *value = rdev->config.cayman.backend_map;
 335                 else if (rdev->family >= CHIP_CEDAR)
 336                         *value = rdev->config.evergreen.backend_map;
 337                 else if (rdev->family >= CHIP_RV770)
 338                         *value = rdev->config.rv770.backend_map;
 339                 else if (rdev->family >= CHIP_R600)
 340                         *value = rdev->config.r600.backend_map;
 341                 else {
 342                         return -EINVAL;
 343                 }
 344                 break;
 345         case RADEON_INFO_VA_START:
 346                 /* this is where we report if vm is supported or not */
 347                 if (rdev->family < CHIP_CAYMAN)
 348                         return -EINVAL;
 349                 *value = RADEON_VA_RESERVED_SIZE;
 350                 break;
 351         case RADEON_INFO_IB_VM_MAX_SIZE:
 352                 /* this is where we report if vm is supported or not */
 353                 if (rdev->family < CHIP_CAYMAN)
 354                         return -EINVAL;
 355                 *value = RADEON_IB_VM_MAX_SIZE;
 356                 break;
 357         case RADEON_INFO_MAX_PIPES:
 358                 if (rdev->family >= CHIP_BONAIRE)
 359                         *value = rdev->config.cik.max_cu_per_sh;
 360                 else if (rdev->family >= CHIP_TAHITI)
 361                         *value = rdev->config.si.max_cu_per_sh;
 362                 else if (rdev->family >= CHIP_CAYMAN)
 363                         *value = rdev->config.cayman.max_pipes_per_simd;
 364                 else if (rdev->family >= CHIP_CEDAR)
 365                         *value = rdev->config.evergreen.max_pipes;
 366                 else if (rdev->family >= CHIP_RV770)
 367                         *value = rdev->config.rv770.max_pipes;
 368                 else if (rdev->family >= CHIP_R600)
 369                         *value = rdev->config.r600.max_pipes;
 370                 else {
 371                         return -EINVAL;
 372                 }
 373                 break;
 374         case RADEON_INFO_TIMESTAMP:
 375                 if (rdev->family < CHIP_R600) {
 376                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 377                         return -EINVAL;
 378                 }
 379                 value = (uint32_t*)&value64;
 380                 value_size = sizeof(uint64_t);
 381                 value64 = radeon_get_gpu_clock_counter(rdev);
 382                 break;
 383         case RADEON_INFO_MAX_SE:
 384                 if (rdev->family >= CHIP_BONAIRE)
 385                         *value = rdev->config.cik.max_shader_engines;
 386                 else if (rdev->family >= CHIP_TAHITI)
 387                         *value = rdev->config.si.max_shader_engines;
 388                 else if (rdev->family >= CHIP_CAYMAN)
 389                         *value = rdev->config.cayman.max_shader_engines;
 390                 else if (rdev->family >= CHIP_CEDAR)
 391                         *value = rdev->config.evergreen.num_ses;
 392                 else
 393                         *value = 1;
 394                 break;
 395         case RADEON_INFO_MAX_SH_PER_SE:
 396                 if (rdev->family >= CHIP_BONAIRE)
 397                         *value = rdev->config.cik.max_sh_per_se;
 398                 else if (rdev->family >= CHIP_TAHITI)
 399                         *value = rdev->config.si.max_sh_per_se;
 400                 else
 401                         return -EINVAL;
 402                 break;
 403         case RADEON_INFO_FASTFB_WORKING:
 404                 *value = rdev->fastfb_working;
 405                 break;
 406         case RADEON_INFO_RING_WORKING:
 407                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
 408                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 409                         return -EFAULT;
 410                 }
 411                 switch (*value) {
 412                 case RADEON_CS_RING_GFX:
 413                 case RADEON_CS_RING_COMPUTE:
 414                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 415                         break;
 416                 case RADEON_CS_RING_DMA:
 417                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 418                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 419                         break;
 420                 case RADEON_CS_RING_UVD:
 421                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 422                         break;
 423                 default:
 424                         return -EINVAL;
 425                 }
 426                 break;
 427         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 428                 if (rdev->family >= CHIP_BONAIRE) {
 429                         value = rdev->config.cik.tile_mode_array;
 430                         value_size = sizeof(uint32_t)*32;
 431                 } else if (rdev->family >= CHIP_TAHITI) {
 432                         value = rdev->config.si.tile_mode_array;
 433                         value_size = sizeof(uint32_t)*32;
 434                 } else {
 435                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
 436                         return -EINVAL;
 437                 }
 438                 break;
 439         case RADEON_INFO_SI_CP_DMA_COMPUTE:
 440                 *value = 1;
 441                 break;
 442         default:
 443                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 444                 return -EINVAL;
 445         }
 446         if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) {
 447                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 448                 return -EFAULT;
 449         }
 450         return 0;
 451 }
 452
 453
 454 /*
 455  * Outdated mess for old drm with Xorg being in charge (void function now).
 456  */
 457 /**
 458  * radeon_driver_firstopen_kms - drm callback for last close
 459  *
 460  * @dev: drm dev pointer
 461  *
 462  * Switch vga switcheroo state after last close (all asics).
 463  */
 464 void radeon_driver_lastclose_kms(struct drm_device *dev)
 465 {
 466 #ifdef DUMBBELL_WIP
 467         vga_switcheroo_process_delayed_switch();
 468 #endif /* DUMBBELL_WIP */
 469 }
 470
 471 /**
 472  * radeon_driver_open_kms - drm callback for open
 473  *
 474  * @dev: drm dev pointer
 475  * @file_priv: drm file
 476  *
 477  * On device open, init vm on cayman+ (all asics).
 478  * Returns 0 on success, error on failure.
 479  */
 480 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 481 {
 482         struct radeon_device *rdev = dev->dev_private;
 483
 484         file_priv->driver_priv = NULL;
 485
 486         /* new gpu have virtual address space support */
 487         if (rdev->family >= CHIP_CAYMAN) {
 488                 struct radeon_fpriv *fpriv;
 489                 struct radeon_bo_va *bo_va;
 490                 int r;
 491
 492                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 493                 if (unlikely(!fpriv)) {
 494                         return -ENOMEM;
 495                 }
 496
 497                 radeon_vm_init(rdev, &fpriv->vm);
 498
 499                 /* map the ib pool buffer read only into
 500                  * virtual address space */
 501                 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
 502                                          rdev->ring_tmp_bo.bo);
 503                 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
 504                                           RADEON_VM_PAGE_READABLE |
 505                                           RADEON_VM_PAGE_SNOOPED);
 506                 if (r) {
 507                         radeon_vm_fini(rdev, &fpriv->vm);
 508                         kfree(fpriv);
 509                         return r;
 510                 }
 511
 512                 file_priv->driver_priv = fpriv;
 513         }
 514         return 0;
 515 }
 516
 517 /**
 518  * radeon_driver_postclose_kms - drm callback for post close
 519  *
 520  * @dev: drm dev pointer
 521  * @file_priv: drm file
 522  *
 523  * On device post close, tear down vm on cayman+ (all asics).
 524  */
 525 void radeon_driver_postclose_kms(struct drm_device *dev,
 526                                  struct drm_file *file_priv)
 527 {
 528         struct radeon_device *rdev = dev->dev_private;
 529
 530         /* new gpu have virtual address space support */
 531         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 532                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 533                 struct radeon_bo_va *bo_va;
 534                 int r;
 535
 536                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 537                 if (!r) {
 538                         bo_va = radeon_vm_bo_find(&fpriv->vm,
 539                                                   rdev->ring_tmp_bo.bo);
 540                         if (bo_va)
 541                                 radeon_vm_bo_rmv(rdev, bo_va);
 542                         radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 543                 }
 544
 545                 radeon_vm_fini(rdev, &fpriv->vm);
 546                 kfree(fpriv);
 547                 file_priv->driver_priv = NULL;
 548         }
 549 }
 550
 551 /**
 552  * radeon_driver_preclose_kms - drm callback for pre close
 553  *
 554  * @dev: drm dev pointer
 555  * @file_priv: drm file
 556  *
 557  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
 558  * (all asics).
 559  */
 560 void radeon_driver_preclose_kms(struct drm_device *dev,
 561                                 struct drm_file *file_priv)
 562 {
 563         struct radeon_device *rdev = dev->dev_private;
 564         if (rdev->hyperz_filp == file_priv)
 565                 rdev->hyperz_filp = NULL;
 566         if (rdev->cmask_filp == file_priv)
 567                 rdev->cmask_filp = NULL;
 568         radeon_uvd_free_handles(rdev, file_priv);
 569 }
 570
 571 /*
 572  * VBlank related functions.
 573  */
 574 /**
 575  * radeon_get_vblank_counter_kms - get frame count
 576  *
 577  * @dev: drm dev pointer
 578  * @crtc: crtc to get the frame count from
 579  *
 580  * Gets the frame count on the requested crtc (all asics).
 581  * Returns frame count on success, -EINVAL on failure.
 582  */
 583 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 584 {
 585         struct radeon_device *rdev = dev->dev_private;
 586
 587         if (crtc < 0 || crtc >= rdev->num_crtc) {
 588                 DRM_ERROR("Invalid crtc %d\n", crtc);
 589                 return -EINVAL;
 590         }
 591
 592         return radeon_get_vblank_counter(rdev, crtc);
 593 }
 594
 595 /**
 596  * radeon_enable_vblank_kms - enable vblank interrupt
 597  *
 598  * @dev: drm dev pointer
 599  * @crtc: crtc to enable vblank interrupt for
 600  *
 601  * Enable the interrupt on the requested crtc (all asics).
 602  * Returns 0 on success, -EINVAL on failure.
 603  */
 604 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 605 {
 606         struct radeon_device *rdev = dev->dev_private;
 607         int r;
 608
 609         if (crtc < 0 || crtc >= rdev->num_crtc) {
 610                 DRM_ERROR("Invalid crtc %d\n", crtc);
 611                 return -EINVAL;
 612         }
 613
 614         lockmgr(&rdev->irq.lock, LK_EXCLUSIVE);
 615         rdev->irq.crtc_vblank_int[crtc] = true;
 616         r = radeon_irq_set(rdev);
 617         lockmgr(&rdev->irq.lock, LK_RELEASE);
 618         return r;
 619 }
 620
 621 /**
 622  * radeon_disable_vblank_kms - disable vblank interrupt
 623  *
 624  * @dev: drm dev pointer
 625  * @crtc: crtc to disable vblank interrupt for
 626  *
 627  * Disable the interrupt on the requested crtc (all asics).
 628  */
 629 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 630 {
 631         struct radeon_device *rdev = dev->dev_private;
 632
 633         if (crtc < 0 || crtc >= rdev->num_crtc) {
 634                 DRM_ERROR("Invalid crtc %d\n", crtc);
 635                 return;
 636         }
 637
 638         lockmgr(&rdev->irq.lock, LK_EXCLUSIVE);
 639         rdev->irq.crtc_vblank_int[crtc] = false;
 640         radeon_irq_set(rdev);
 641         lockmgr(&rdev->irq.lock, LK_RELEASE);
 642 }
 643
 644 /**
 645  * radeon_get_vblank_timestamp_kms - get vblank timestamp
 646  *
 647  * @dev: drm dev pointer
 648  * @crtc: crtc to get the timestamp for
 649  * @max_error: max error
 650  * @vblank_time: time value
 651  * @flags: flags passed to the driver
 652  *
 653  * Gets the timestamp on the requested crtc based on the
 654  * scanout position.  (all asics).
 655  * Returns postive status flags on success, negative error on failure.
 656  */
 657 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 658                                     int *max_error,
 659                                     struct timeval *vblank_time,
 660                                     unsigned flags)
 661 {
 662         struct drm_crtc *drmcrtc;
 663         struct radeon_device *rdev = dev->dev_private;
 664
 665         if (crtc < 0 || crtc >= dev->num_crtcs) {
 666                 DRM_ERROR("Invalid crtc %d\n", crtc);
 667                 return -EINVAL;
 668         }
 669
 670         /* Get associated drm_crtc: */
 671         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 672
 673         /* Helper routine in DRM core does all the work: */
 674         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 675                                                      vblank_time, flags,
 676                                                      drmcrtc, &drmcrtc->hwmode);
 677 }
 678
 679 #define KMS_INVALID_IOCTL(name)                                         \
 680 static int                                                              \
 681 name(struct drm_device *dev, void *data, struct drm_file *file_priv)    \
 682 {                                                                       \
 683         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 684         return -EINVAL;                                                 \
 685 }
 686
 687 /*
 688  * All these ioctls are invalid in kms world.
 689  */
 690 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 691 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 692 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 693 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 694 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 695 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 696 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 697 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 698 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 699 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 700 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 701 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 702 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 703 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 704 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 705 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 706 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 707 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 708 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 709 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 710 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 711 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 712 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 713 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 714 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 715 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 716 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 717
 718
 719 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 720         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 721         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 722         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 723         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 724         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 725         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 726         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 727         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 728         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 729         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 730         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 731         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 732         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 733         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 734         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 735         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 736         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 737         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 738         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 739         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 740         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 741         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 742         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 743         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 744         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 745         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 746         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 747         /* KMS */
 748         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 749         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 750         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 751         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 752         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 753         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 754         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 755         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 756         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 757         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 758         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 759         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 760         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 761 };
 762 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);