sys/dev/drm/radeon/sumo_dpm.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sumod.h"
  28 #include "r600_dpm.h"
  29 #include "cypress_dpm.h"
  30 #include "sumo_dpm.h"
  31 #include <linux/seq_file.h>
  32
  33 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
  34 #define SUMO_MINIMUM_ENGINE_CLOCK 800
  35 #define BOOST_DPM_LEVEL 7
  36
  37 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
  38 {
  39         SUMO_UTC_DFLT_00,
  40         SUMO_UTC_DFLT_01,
  41         SUMO_UTC_DFLT_02,
  42         SUMO_UTC_DFLT_03,
  43         SUMO_UTC_DFLT_04,
  44         SUMO_UTC_DFLT_05,
  45         SUMO_UTC_DFLT_06,
  46         SUMO_UTC_DFLT_07,
  47         SUMO_UTC_DFLT_08,
  48         SUMO_UTC_DFLT_09,
  49         SUMO_UTC_DFLT_10,
  50         SUMO_UTC_DFLT_11,
  51         SUMO_UTC_DFLT_12,
  52         SUMO_UTC_DFLT_13,
  53         SUMO_UTC_DFLT_14,
  54 };
  55
  56 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
  57 {
  58         SUMO_DTC_DFLT_00,
  59         SUMO_DTC_DFLT_01,
  60         SUMO_DTC_DFLT_02,
  61         SUMO_DTC_DFLT_03,
  62         SUMO_DTC_DFLT_04,
  63         SUMO_DTC_DFLT_05,
  64         SUMO_DTC_DFLT_06,
  65         SUMO_DTC_DFLT_07,
  66         SUMO_DTC_DFLT_08,
  67         SUMO_DTC_DFLT_09,
  68         SUMO_DTC_DFLT_10,
  69         SUMO_DTC_DFLT_11,
  70         SUMO_DTC_DFLT_12,
  71         SUMO_DTC_DFLT_13,
  72         SUMO_DTC_DFLT_14,
  73 };
  74
  75 struct sumo_ps *sumo_get_ps(struct radeon_ps *rps);
  76 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
  77 void sumo_dpm_reset_asic(struct radeon_device *rdev);
  78
  79 struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
  80 {
  81         struct sumo_ps *ps = rps->ps_priv;
  82
  83         return ps;
  84 }
  85
  86 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
  87 {
  88         struct sumo_power_info *pi = rdev->pm.dpm.priv;
  89
  90         return pi;
  91 }
  92
  93 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
  94 {
  95         if (enable)
  96                 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
  97         else {
  98                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
  99                 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
 100                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
 101                 RREG32(GB_ADDR_CONFIG);
 102         }
 103 }
 104
 105 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
 106 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
 107
 108 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
 109 {
 110         u32 local0;
 111         u32 local1;
 112
 113         local0 = RREG32(CG_CGTT_LOCAL_0);
 114         local1 = RREG32(CG_CGTT_LOCAL_1);
 115
 116         if (enable) {
 117                 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
 118                 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
 119         } else {
 120                 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
 121                 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
 122         }
 123 }
 124
 125 static void sumo_program_git(struct radeon_device *rdev)
 126 {
 127         u32 p, u;
 128         u32 xclk = radeon_get_xclk(rdev);
 129
 130         r600_calculate_u_and_p(SUMO_GICST_DFLT,
 131                                xclk, 16, &p, &u);
 132
 133         WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
 134 }
 135
 136 static void sumo_program_grsd(struct radeon_device *rdev)
 137 {
 138         u32 p, u;
 139         u32 xclk = radeon_get_xclk(rdev);
 140         u32 grs = 256 * 25 / 100;
 141
 142         r600_calculate_u_and_p(1, xclk, 14, &p, &u);
 143
 144         WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
 145 }
 146
 147 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
 148 {
 149         sumo_program_git(rdev);
 150         sumo_program_grsd(rdev);
 151 }
 152
 153 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
 154 {
 155         u32 rcu_pwr_gating_cntl;
 156         u32 p, u;
 157         u32 p_c, p_p, d_p;
 158         u32 r_t, i_t;
 159         u32 xclk = radeon_get_xclk(rdev);
 160
 161         if (rdev->family == CHIP_PALM) {
 162                 p_c = 4;
 163                 d_p = 10;
 164                 r_t = 10;
 165                 i_t = 4;
 166                 p_p = 50 + 1000/200 + 6 * 32;
 167         } else {
 168                 p_c = 16;
 169                 d_p = 50;
 170                 r_t = 50;
 171                 i_t  = 50;
 172                 p_p = 113;
 173         }
 174
 175         WREG32(CG_SCRATCH2, 0x01B60A17);
 176
 177         r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
 178                                xclk, 16, &p, &u);
 179
 180         WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
 181                  ~(PGP_MASK | PGU_MASK));
 182
 183         r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
 184                                xclk, 16, &p, &u);
 185
 186         WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
 187                  ~(PGP_MASK | PGU_MASK));
 188
 189         if (rdev->family == CHIP_PALM) {
 190                 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
 191                 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
 192         } else {
 193                 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
 194                 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
 195         }
 196
 197         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 198         rcu_pwr_gating_cntl &=
 199                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 200         rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
 201         if (rdev->family == CHIP_PALM) {
 202                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 203                 rcu_pwr_gating_cntl |= PCP(0x77);
 204         }
 205         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 206
 207         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 208         rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 209         rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
 210         WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 211
 212         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 213         rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 214         rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
 215         WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 216
 217         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
 218         rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
 219         rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
 220         WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
 221
 222         if (rdev->family == CHIP_PALM)
 223                 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
 224
 225         sumo_smu_pg_init(rdev);
 226
 227         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 228         rcu_pwr_gating_cntl &=
 229                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 230         rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
 231         if (rdev->family == CHIP_PALM) {
 232                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 233                 rcu_pwr_gating_cntl |= PCP(0x77);
 234         }
 235         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 236
 237         if (rdev->family == CHIP_PALM) {
 238                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 239                 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 240                 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
 241                 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 242
 243                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 244                 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 245                 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
 246                 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 247         }
 248
 249         sumo_smu_pg_init(rdev);
 250
 251         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
 252         rcu_pwr_gating_cntl &=
 253                 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
 254         rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
 255
 256         if (rdev->family == CHIP_PALM) {
 257                 rcu_pwr_gating_cntl |= PCV(4);
 258                 rcu_pwr_gating_cntl &= ~PCP_MASK;
 259                 rcu_pwr_gating_cntl |= PCP(0x77);
 260         } else
 261                 rcu_pwr_gating_cntl |= PCV(11);
 262         WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
 263
 264         if (rdev->family == CHIP_PALM) {
 265                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
 266                 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
 267                 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
 268                 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
 269
 270                 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
 271                 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
 272                 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
 273                 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
 274         }
 275
 276         sumo_smu_pg_init(rdev);
 277 }
 278
 279 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
 280 {
 281         if (enable)
 282                 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
 283         else {
 284                 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
 285                 RREG32(GB_ADDR_CONFIG);
 286         }
 287 }
 288
 289 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
 290 {
 291         struct sumo_power_info *pi = sumo_get_pi(rdev);
 292
 293         if (pi->enable_gfx_clock_gating)
 294                 sumo_gfx_clockgating_initialize(rdev);
 295         if (pi->enable_gfx_power_gating)
 296                 sumo_gfx_powergating_initialize(rdev);
 297         if (pi->enable_mg_clock_gating)
 298                 sumo_mg_clockgating_enable(rdev, true);
 299         if (pi->enable_gfx_clock_gating)
 300                 sumo_gfx_clockgating_enable(rdev, true);
 301         if (pi->enable_gfx_power_gating)
 302                 sumo_gfx_powergating_enable(rdev, true);
 303
 304         return 0;
 305 }
 306
 307 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
 308 {
 309         struct sumo_power_info *pi = sumo_get_pi(rdev);
 310
 311         if (pi->enable_gfx_clock_gating)
 312                 sumo_gfx_clockgating_enable(rdev, false);
 313         if (pi->enable_gfx_power_gating)
 314                 sumo_gfx_powergating_enable(rdev, false);
 315         if (pi->enable_mg_clock_gating)
 316                 sumo_mg_clockgating_enable(rdev, false);
 317 }
 318
 319 static void sumo_calculate_bsp(struct radeon_device *rdev,
 320                                u32 high_clk)
 321 {
 322         struct sumo_power_info *pi = sumo_get_pi(rdev);
 323         u32 xclk = radeon_get_xclk(rdev);
 324
 325         pi->pasi = 65535 * 100 / high_clk;
 326         pi->asi = 65535 * 100 / high_clk;
 327
 328         r600_calculate_u_and_p(pi->asi,
 329                                xclk, 16, &pi->bsp, &pi->bsu);
 330
 331         r600_calculate_u_and_p(pi->pasi,
 332                                xclk, 16, &pi->pbsp, &pi->pbsu);
 333
 334         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
 335         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
 336 }
 337
 338 static void sumo_init_bsp(struct radeon_device *rdev)
 339 {
 340         struct sumo_power_info *pi = sumo_get_pi(rdev);
 341
 342         WREG32(CG_BSP_0, pi->psp);
 343 }
 344
 345
 346 static void sumo_program_bsp(struct radeon_device *rdev,
 347                              struct radeon_ps *rps)
 348 {
 349         struct sumo_power_info *pi = sumo_get_pi(rdev);
 350         struct sumo_ps *ps = sumo_get_ps(rps);
 351         u32 i;
 352         u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
 353
 354         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 355                 highest_engine_clock = pi->boost_pl.sclk;
 356
 357         sumo_calculate_bsp(rdev, highest_engine_clock);
 358
 359         for (i = 0; i < ps->num_levels - 1; i++)
 360                 WREG32(CG_BSP_0 + (i * 4), pi->dsp);
 361
 362         WREG32(CG_BSP_0 + (i * 4), pi->psp);
 363
 364         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 365                 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
 366 }
 367
 368 static void sumo_write_at(struct radeon_device *rdev,
 369                           u32 index, u32 value)
 370 {
 371         if (index == 0)
 372                 WREG32(CG_AT_0, value);
 373         else if (index == 1)
 374                 WREG32(CG_AT_1, value);
 375         else if (index == 2)
 376                 WREG32(CG_AT_2, value);
 377         else if (index == 3)
 378                 WREG32(CG_AT_3, value);
 379         else if (index == 4)
 380                 WREG32(CG_AT_4, value);
 381         else if (index == 5)
 382                 WREG32(CG_AT_5, value);
 383         else if (index == 6)
 384                 WREG32(CG_AT_6, value);
 385         else if (index == 7)
 386                 WREG32(CG_AT_7, value);
 387 }
 388
 389 static void sumo_program_at(struct radeon_device *rdev,
 390                             struct radeon_ps *rps)
 391 {
 392         struct sumo_power_info *pi = sumo_get_pi(rdev);
 393         struct sumo_ps *ps = sumo_get_ps(rps);
 394         u32 asi;
 395         u32 i;
 396         u32 m_a;
 397         u32 a_t;
 398         u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
 399         u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
 400
 401         r[0] = SUMO_R_DFLT0;
 402         r[1] = SUMO_R_DFLT1;
 403         r[2] = SUMO_R_DFLT2;
 404         r[3] = SUMO_R_DFLT3;
 405         r[4] = SUMO_R_DFLT4;
 406
 407         l[0] = SUMO_L_DFLT0;
 408         l[1] = SUMO_L_DFLT1;
 409         l[2] = SUMO_L_DFLT2;
 410         l[3] = SUMO_L_DFLT3;
 411         l[4] = SUMO_L_DFLT4;
 412
 413         for (i = 0; i < ps->num_levels; i++) {
 414                 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
 415
 416                 m_a = asi * ps->levels[i].sclk / 100;
 417
 418                 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
 419
 420                 sumo_write_at(rdev, i, a_t);
 421         }
 422
 423         if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
 424                 asi = pi->pasi;
 425
 426                 m_a = asi * pi->boost_pl.sclk / 100;
 427
 428                 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
 429                         CG_L(m_a * l[ps->num_levels - 1] / 100);
 430
 431                 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
 432         }
 433 }
 434
 435 static void sumo_program_tp(struct radeon_device *rdev)
 436 {
 437         int i;
 438         enum r600_td td = R600_TD_DFLT;
 439
 440         for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
 441                 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
 442                 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
 443         }
 444
 445         if (td == R600_TD_AUTO)
 446                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
 447         else
 448                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
 449
 450         if (td == R600_TD_UP)
 451                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
 452
 453         if (td == R600_TD_DOWN)
 454                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
 455 }
 456
 457 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
 458 {
 459         WREG32(CG_FTV, vrc);
 460 }
 461
 462 void sumo_clear_vc(struct radeon_device *rdev)
 463 {
 464         WREG32(CG_FTV, 0);
 465 }
 466
 467 void sumo_program_sstp(struct radeon_device *rdev)
 468 {
 469         u32 p, u;
 470         u32 xclk = radeon_get_xclk(rdev);
 471
 472         r600_calculate_u_and_p(SUMO_SST_DFLT,
 473                                xclk, 16, &p, &u);
 474
 475         WREG32(CG_SSP, SSTU(u) | SST(p));
 476 }
 477
 478 static void sumo_set_divider_value(struct radeon_device *rdev,
 479                                    u32 index, u32 divider)
 480 {
 481         u32 reg_index = index / 4;
 482         u32 field_index = index % 4;
 483
 484         if (field_index == 0)
 485                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 486                          SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
 487         else if (field_index == 1)
 488                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 489                          SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
 490         else if (field_index == 2)
 491                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 492                          SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
 493         else if (field_index == 3)
 494                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 495                          SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
 496 }
 497
 498 static void sumo_set_ds_dividers(struct radeon_device *rdev,
 499                                  u32 index, u32 divider)
 500 {
 501         struct sumo_power_info *pi = sumo_get_pi(rdev);
 502
 503         if (pi->enable_sclk_ds) {
 504                 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
 505
 506                 dpm_ctrl &= ~(0x7 << (index * 3));
 507                 dpm_ctrl |= (divider << (index * 3));
 508                 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
 509         }
 510 }
 511
 512 static void sumo_set_ss_dividers(struct radeon_device *rdev,
 513                                  u32 index, u32 divider)
 514 {
 515         struct sumo_power_info *pi = sumo_get_pi(rdev);
 516
 517         if (pi->enable_sclk_ds) {
 518                 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
 519
 520                 dpm_ctrl &= ~(0x7 << (index * 3));
 521                 dpm_ctrl |= (divider << (index * 3));
 522                 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
 523         }
 524 }
 525
 526 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
 527 {
 528         u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
 529
 530         voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
 531         voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
 532         WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
 533 }
 534
 535 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
 536 {
 537         struct sumo_power_info *pi = sumo_get_pi(rdev);
 538         u32 temp = gnb_slow;
 539         u32 cg_sclk_dpm_ctrl_3;
 540
 541         if (pi->driver_nbps_policy_disable)
 542                 temp = 1;
 543
 544         cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
 545         cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
 546         cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
 547
 548         WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
 549 }
 550
 551 static void sumo_program_power_level(struct radeon_device *rdev,
 552                                      struct sumo_pl *pl, u32 index)
 553 {
 554         struct sumo_power_info *pi = sumo_get_pi(rdev);
 555         int ret;
 556         struct atom_clock_dividers dividers;
 557         u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
 558
 559         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 560                                              pl->sclk, false, &dividers);
 561         if (ret)
 562                 return;
 563
 564         sumo_set_divider_value(rdev, index, dividers.post_div);
 565
 566         sumo_set_vid(rdev, index, pl->vddc_index);
 567
 568         if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
 569                 if (ds_en)
 570                         WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
 571         } else {
 572                 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
 573                 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
 574
 575                 if (!ds_en)
 576                         WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
 577         }
 578
 579         sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
 580
 581         if (pi->enable_boost)
 582                 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
 583 }
 584
 585 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
 586 {
 587         u32 reg_index = index / 4;
 588         u32 field_index = index % 4;
 589
 590         if (field_index == 0)
 591                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 592                          enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
 593         else if (field_index == 1)
 594                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 595                          enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
 596         else if (field_index == 2)
 597                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 598                          enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
 599         else if (field_index == 3)
 600                 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
 601                          enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
 602 }
 603
 604 static bool sumo_dpm_enabled(struct radeon_device *rdev)
 605 {
 606         if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
 607                 return true;
 608         else
 609                 return false;
 610 }
 611
 612 static void sumo_start_dpm(struct radeon_device *rdev)
 613 {
 614         WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
 615 }
 616
 617 static void sumo_stop_dpm(struct radeon_device *rdev)
 618 {
 619         WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
 620 }
 621
 622 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
 623 {
 624         if (enable)
 625                 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
 626         else
 627                 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
 628 }
 629
 630 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
 631 {
 632         int i;
 633
 634         sumo_set_forced_mode(rdev, true);
 635         for (i = 0; i < rdev->usec_timeout; i++) {
 636                 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
 637                         break;
 638                 udelay(1);
 639         }
 640 }
 641
 642 static void sumo_wait_for_level_0(struct radeon_device *rdev)
 643 {
 644         int i;
 645
 646         for (i = 0; i < rdev->usec_timeout; i++) {
 647                 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
 648                         break;
 649                 udelay(1);
 650         }
 651         for (i = 0; i < rdev->usec_timeout; i++) {
 652                 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
 653                         break;
 654                 udelay(1);
 655         }
 656 }
 657
 658 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
 659 {
 660         sumo_set_forced_mode(rdev, false);
 661 }
 662
 663 static void sumo_enable_power_level_0(struct radeon_device *rdev)
 664 {
 665         sumo_power_level_enable(rdev, 0, true);
 666 }
 667
 668 static void sumo_patch_boost_state(struct radeon_device *rdev,
 669                                    struct radeon_ps *rps)
 670 {
 671         struct sumo_power_info *pi = sumo_get_pi(rdev);
 672         struct sumo_ps *new_ps = sumo_get_ps(rps);
 673
 674         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
 675                 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
 676                 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
 677                 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
 678                 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
 679         }
 680 }
 681
 682 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
 683                                              struct radeon_ps *new_rps,
 684                                              struct radeon_ps *old_rps)
 685 {
 686         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 687         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 688         u32 nbps1_old = 0;
 689         u32 nbps1_new = 0;
 690
 691         if (old_ps != NULL)
 692                 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
 693
 694         nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
 695
 696         if (nbps1_old == 1 && nbps1_new == 0)
 697                 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
 698 }
 699
 700 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
 701                                               struct radeon_ps *new_rps,
 702                                               struct radeon_ps *old_rps)
 703 {
 704         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 705         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 706         u32 nbps1_old = 0;
 707         u32 nbps1_new = 0;
 708
 709         if (old_ps != NULL)
 710                 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
 711
 712         nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
 713
 714         if (nbps1_old == 0 && nbps1_new == 1)
 715                 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
 716 }
 717
 718 static void sumo_enable_boost(struct radeon_device *rdev,
 719                               struct radeon_ps *rps,
 720                               bool enable)
 721 {
 722         struct sumo_ps *new_ps = sumo_get_ps(rps);
 723
 724         if (enable) {
 725                 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 726                         sumo_boost_state_enable(rdev, true);
 727         } else
 728                 sumo_boost_state_enable(rdev, false);
 729 }
 730
 731 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
 732 {
 733         WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
 734 }
 735
 736 static void sumo_set_forced_level_0(struct radeon_device *rdev)
 737 {
 738         sumo_set_forced_level(rdev, 0);
 739 }
 740
 741 static void sumo_program_wl(struct radeon_device *rdev,
 742                             struct radeon_ps *rps)
 743 {
 744         struct sumo_ps *new_ps = sumo_get_ps(rps);
 745         u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
 746
 747         dpm_ctrl4 &= 0xFFFFFF00;
 748         dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
 749
 750         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 751                 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
 752
 753         WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
 754 }
 755
 756 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
 757                                              struct radeon_ps *new_rps,
 758                                              struct radeon_ps *old_rps)
 759 {
 760         struct sumo_power_info *pi = sumo_get_pi(rdev);
 761         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 762         struct sumo_ps *old_ps = sumo_get_ps(old_rps);
 763         u32 i;
 764         u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
 765
 766         for (i = 0; i < new_ps->num_levels; i++) {
 767                 sumo_program_power_level(rdev, &new_ps->levels[i], i);
 768                 sumo_power_level_enable(rdev, i, true);
 769         }
 770
 771         for (i = new_ps->num_levels; i < n_current_state_levels; i++)
 772                 sumo_power_level_enable(rdev, i, false);
 773
 774         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
 775                 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
 776 }
 777
 778 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
 779 {
 780         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
 781 }
 782
 783 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
 784 {
 785         WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
 786 }
 787
 788 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
 789 {
 790         struct sumo_power_info *pi = sumo_get_pi(rdev);
 791         struct atom_clock_dividers dividers;
 792         int ret;
 793
 794         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 795                                              pi->acpi_pl.sclk,
 796                                              false, &dividers);
 797         if (ret)
 798                 return;
 799
 800         WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
 801         WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
 802 }
 803
 804 static void sumo_program_bootup_state(struct radeon_device *rdev)
 805 {
 806         struct sumo_power_info *pi = sumo_get_pi(rdev);
 807         u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
 808         u32 i;
 809
 810         sumo_program_power_level(rdev, &pi->boot_pl, 0);
 811
 812         dpm_ctrl4 &= 0xFFFFFF00;
 813         WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
 814
 815         for (i = 1; i < 8; i++)
 816                 sumo_power_level_enable(rdev, i, false);
 817 }
 818
 819 static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
 820                                   struct radeon_ps *new_rps,
 821                                   struct radeon_ps *old_rps)
 822 {
 823         struct sumo_power_info *pi = sumo_get_pi(rdev);
 824
 825         if (pi->enable_gfx_power_gating) {
 826                 sumo_gfx_powergating_enable(rdev, false);
 827         }
 828
 829         radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
 830
 831         if (pi->enable_gfx_power_gating) {
 832                 if (!pi->disable_gfx_power_gating_in_uvd ||
 833                     !r600_is_uvd_state(new_rps->class, new_rps->class2))
 834                         sumo_gfx_powergating_enable(rdev, true);
 835         }
 836 }
 837
 838 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
 839                                                     struct radeon_ps *new_rps,
 840                                                     struct radeon_ps *old_rps)
 841 {
 842         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 843         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
 844
 845         if ((new_rps->vclk == old_rps->vclk) &&
 846             (new_rps->dclk == old_rps->dclk))
 847                 return;
 848
 849         if (new_ps->levels[new_ps->num_levels - 1].sclk >=
 850             current_ps->levels[current_ps->num_levels - 1].sclk)
 851                 return;
 852
 853         sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
 854 }
 855
 856 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
 857                                                    struct radeon_ps *new_rps,
 858                                                    struct radeon_ps *old_rps)
 859 {
 860         struct sumo_ps *new_ps = sumo_get_ps(new_rps);
 861         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
 862
 863         if ((new_rps->vclk == old_rps->vclk) &&
 864             (new_rps->dclk == old_rps->dclk))
 865                 return;
 866
 867         if (new_ps->levels[new_ps->num_levels - 1].sclk <
 868             current_ps->levels[current_ps->num_levels - 1].sclk)
 869                 return;
 870
 871         sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
 872 }
 873
 874 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
 875 {
 876 /* This bit selects who handles display phy powergating.
 877  * Clear the bit to let atom handle it.
 878  * Set it to let the driver handle it.
 879  * For now we just let atom handle it.
 880  */
 881 #if 0
 882         u32 v = RREG32(DOUT_SCRATCH3);
 883
 884         if (enable)
 885                 v |= 0x4;
 886         else
 887                 v &= 0xFFFFFFFB;
 888
 889         WREG32(DOUT_SCRATCH3, v);
 890 #endif
 891 }
 892
 893 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
 894 {
 895         if (enable) {
 896                 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
 897                 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
 898                 u32 t = 1;
 899
 900                 deep_sleep_cntl &= ~R_DIS;
 901                 deep_sleep_cntl &= ~HS_MASK;
 902                 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
 903
 904                 deep_sleep_cntl2 |= LB_UFP_EN;
 905                 deep_sleep_cntl2 &= INOUT_C_MASK;
 906                 deep_sleep_cntl2 |= INOUT_C(0xf);
 907
 908                 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
 909                 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
 910         } else
 911                 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
 912 }
 913
 914 static void sumo_program_bootup_at(struct radeon_device *rdev)
 915 {
 916         WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
 917         WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
 918 }
 919
 920 static void sumo_reset_am(struct radeon_device *rdev)
 921 {
 922         WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
 923 }
 924
 925 static void sumo_start_am(struct radeon_device *rdev)
 926 {
 927         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
 928 }
 929
 930 static void sumo_program_ttp(struct radeon_device *rdev)
 931 {
 932         u32 xclk = radeon_get_xclk(rdev);
 933         u32 p, u;
 934         u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
 935
 936         r600_calculate_u_and_p(1000,
 937                                xclk, 16, &p, &u);
 938
 939         cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
 940         cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
 941
 942         WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
 943 }
 944
 945 static void sumo_program_ttt(struct radeon_device *rdev)
 946 {
 947         u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
 948         struct sumo_power_info *pi = sumo_get_pi(rdev);
 949
 950         cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
 951         cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
 952
 953         WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
 954 }
 955
 956
 957 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
 958 {
 959         if (enable) {
 960                 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
 961                 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
 962         } else {
 963                 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
 964                 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
 965         }
 966 }
 967
 968 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
 969 {
 970         WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
 971                  ~CNB_THERMTHRO_MASK_SCLK);
 972 }
 973
 974 static void sumo_program_dc_hto(struct radeon_device *rdev)
 975 {
 976         u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
 977         u32 p, u;
 978         u32 xclk = radeon_get_xclk(rdev);
 979
 980         r600_calculate_u_and_p(100000,
 981                                xclk, 14, &p, &u);
 982
 983         cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
 984         cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
 985
 986         WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
 987 }
 988
 989 static void sumo_force_nbp_state(struct radeon_device *rdev,
 990                                  struct radeon_ps *rps)
 991 {
 992         struct sumo_power_info *pi = sumo_get_pi(rdev);
 993         struct sumo_ps *new_ps = sumo_get_ps(rps);
 994
 995         if (!pi->driver_nbps_policy_disable) {
 996                 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
 997                         WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
 998                 else
 999                         WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
1000         }
1001 }
1002
1003 u32 sumo_get_sleep_divider_from_id(u32 id)
1004 {
1005         return 1 << id;
1006 }
1007
1008 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1009                                          u32 sclk,
1010                                          u32 min_sclk_in_sr)
1011 {
1012         struct sumo_power_info *pi = sumo_get_pi(rdev);
1013         u32 i;
1014         u32 temp;
1015         u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
1016                 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
1017
1018         if (sclk < min)
1019                 return 0;
1020
1021         if (!pi->enable_sclk_ds)
1022                 return 0;
1023
1024         for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1025                 temp = sclk / sumo_get_sleep_divider_from_id(i);
1026
1027                 if (temp >= min || i == 0)
1028                         break;
1029         }
1030         return i;
1031 }
1032
1033 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1034                                        u32 lower_limit)
1035 {
1036         struct sumo_power_info *pi = sumo_get_pi(rdev);
1037         u32 i;
1038
1039         for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1040                 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1041                         return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1042         }
1043
1044         return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1045 }
1046
1047 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1048                                      struct sumo_ps *ps,
1049                                      struct sumo_ps *current_ps)
1050 {
1051         struct sumo_power_info *pi = sumo_get_pi(rdev);
1052         u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1053         u32 current_vddc;
1054         u32 current_sclk;
1055         u32 current_index = 0;
1056
1057         if (current_ps) {
1058                 current_vddc = current_ps->levels[current_index].vddc_index;
1059                 current_sclk = current_ps->levels[current_index].sclk;
1060         } else {
1061                 current_vddc = pi->boot_pl.vddc_index;
1062                 current_sclk = pi->boot_pl.sclk;
1063         }
1064
1065         ps->levels[0].vddc_index = current_vddc;
1066
1067         if (ps->levels[0].sclk > current_sclk)
1068                 ps->levels[0].sclk = current_sclk;
1069
1070         ps->levels[0].ss_divider_index =
1071                 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1072
1073         ps->levels[0].ds_divider_index =
1074                 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1075
1076         if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1077                 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1078
1079         if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1080                 if (ps->levels[0].ss_divider_index > 1)
1081                         ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1082         }
1083
1084         if (ps->levels[0].ss_divider_index == 0)
1085                 ps->levels[0].ds_divider_index = 0;
1086
1087         if (ps->levels[0].ds_divider_index == 0)
1088                 ps->levels[0].ss_divider_index = 0;
1089 }
1090
1091 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1092                                           struct radeon_ps *new_rps,
1093                                           struct radeon_ps *old_rps)
1094 {
1095         struct sumo_ps *ps = sumo_get_ps(new_rps);
1096         struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1097         struct sumo_power_info *pi = sumo_get_pi(rdev);
1098         u32 min_voltage = 0; /* ??? */
1099         u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1100         u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1101         u32 i;
1102
1103         if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1104                 return sumo_patch_thermal_state(rdev, ps, current_ps);
1105
1106         if (pi->enable_boost) {
1107                 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1108                         ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1109         }
1110
1111         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1112             (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1113             (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1114                 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1115
1116         for (i = 0; i < ps->num_levels; i++) {
1117                 if (ps->levels[i].vddc_index < min_voltage)
1118                         ps->levels[i].vddc_index = min_voltage;
1119
1120                 if (ps->levels[i].sclk < min_sclk)
1121                         ps->levels[i].sclk =
1122                                 sumo_get_valid_engine_clock(rdev, min_sclk);
1123
1124                 ps->levels[i].ss_divider_index =
1125                         sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1126
1127                 ps->levels[i].ds_divider_index =
1128                         sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1129
1130                 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1131                         ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1132
1133                 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1134                         if (ps->levels[i].ss_divider_index > 1)
1135                                 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1136                 }
1137
1138                 if (ps->levels[i].ss_divider_index == 0)
1139                         ps->levels[i].ds_divider_index = 0;
1140
1141                 if (ps->levels[i].ds_divider_index == 0)
1142                         ps->levels[i].ss_divider_index = 0;
1143
1144                 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1145                         ps->levels[i].allow_gnb_slow = 1;
1146                 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1147                          (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1148                         ps->levels[i].allow_gnb_slow = 0;
1149                 else if (i == ps->num_levels - 1)
1150                         ps->levels[i].allow_gnb_slow = 0;
1151                 else
1152                         ps->levels[i].allow_gnb_slow = 1;
1153         }
1154 }
1155
1156 static void sumo_cleanup_asic(struct radeon_device *rdev)
1157 {
1158         sumo_take_smu_control(rdev, false);
1159 }
1160
1161 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1162                                               int min_temp, int max_temp)
1163 {
1164         int low_temp = 0 * 1000;
1165         int high_temp = 255 * 1000;
1166
1167         if (low_temp < min_temp)
1168                 low_temp = min_temp;
1169         if (high_temp > max_temp)
1170                 high_temp = max_temp;
1171         if (high_temp < low_temp) {
1172                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1173                 return -EINVAL;
1174         }
1175
1176         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1177         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1178
1179         rdev->pm.dpm.thermal.min_temp = low_temp;
1180         rdev->pm.dpm.thermal.max_temp = high_temp;
1181
1182         return 0;
1183 }
1184
1185 static void sumo_update_current_ps(struct radeon_device *rdev,
1186                                    struct radeon_ps *rps)
1187 {
1188         struct sumo_ps *new_ps = sumo_get_ps(rps);
1189         struct sumo_power_info *pi = sumo_get_pi(rdev);
1190
1191         pi->current_rps = *rps;
1192         pi->current_ps = *new_ps;
1193         pi->current_rps.ps_priv = &pi->current_ps;
1194 }
1195
1196 static void sumo_update_requested_ps(struct radeon_device *rdev,
1197                                      struct radeon_ps *rps)
1198 {
1199         struct sumo_ps *new_ps = sumo_get_ps(rps);
1200         struct sumo_power_info *pi = sumo_get_pi(rdev);
1201
1202         pi->requested_rps = *rps;
1203         pi->requested_ps = *new_ps;
1204         pi->requested_rps.ps_priv = &pi->requested_ps;
1205 }
1206
1207 int sumo_dpm_enable(struct radeon_device *rdev)
1208 {
1209         struct sumo_power_info *pi = sumo_get_pi(rdev);
1210         int ret;
1211
1212         if (sumo_dpm_enabled(rdev))
1213                 return -EINVAL;
1214
1215         ret = sumo_enable_clock_power_gating(rdev);
1216         if (ret)
1217                 return ret;
1218         sumo_program_bootup_state(rdev);
1219         sumo_init_bsp(rdev);
1220         sumo_reset_am(rdev);
1221         sumo_program_tp(rdev);
1222         sumo_program_bootup_at(rdev);
1223         sumo_start_am(rdev);
1224         if (pi->enable_auto_thermal_throttling) {
1225                 sumo_program_ttp(rdev);
1226                 sumo_program_ttt(rdev);
1227         }
1228         sumo_program_dc_hto(rdev);
1229         sumo_program_power_level_enter_state(rdev);
1230         sumo_enable_voltage_scaling(rdev, true);
1231         sumo_program_sstp(rdev);
1232         sumo_program_vc(rdev, SUMO_VRC_DFLT);
1233         sumo_override_cnb_thermal_events(rdev);
1234         sumo_start_dpm(rdev);
1235         sumo_wait_for_level_0(rdev);
1236         if (pi->enable_sclk_ds)
1237                 sumo_enable_sclk_ds(rdev, true);
1238         if (pi->enable_boost)
1239                 sumo_enable_boost_timer(rdev);
1240
1241         if (rdev->irq.installed &&
1242             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1243                 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1244                 if (ret)
1245                         return ret;
1246                 rdev->irq.dpm_thermal = true;
1247                 radeon_irq_set(rdev);
1248         }
1249
1250         sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1251
1252         return 0;
1253 }
1254
1255 void sumo_dpm_disable(struct radeon_device *rdev)
1256 {
1257         struct sumo_power_info *pi = sumo_get_pi(rdev);
1258
1259         if (!sumo_dpm_enabled(rdev))
1260                 return;
1261         sumo_disable_clock_power_gating(rdev);
1262         if (pi->enable_sclk_ds)
1263                 sumo_enable_sclk_ds(rdev, false);
1264         sumo_clear_vc(rdev);
1265         sumo_wait_for_level_0(rdev);
1266         sumo_stop_dpm(rdev);
1267         sumo_enable_voltage_scaling(rdev, false);
1268
1269         if (rdev->irq.installed &&
1270             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1271                 rdev->irq.dpm_thermal = false;
1272                 radeon_irq_set(rdev);
1273         }
1274
1275         sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1276 }
1277
1278 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1279 {
1280         struct sumo_power_info *pi = sumo_get_pi(rdev);
1281         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1282         struct radeon_ps *new_ps = &requested_ps;
1283
1284         sumo_update_requested_ps(rdev, new_ps);
1285
1286         if (pi->enable_dynamic_patch_ps)
1287                 sumo_apply_state_adjust_rules(rdev,
1288                                               &pi->requested_rps,
1289                                               &pi->current_rps);
1290
1291         return 0;
1292 }
1293
1294 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1295 {
1296         struct sumo_power_info *pi = sumo_get_pi(rdev);
1297         struct radeon_ps *new_ps = &pi->requested_rps;
1298         struct radeon_ps *old_ps = &pi->current_rps;
1299
1300         if (pi->enable_dpm)
1301                 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1302         if (pi->enable_boost) {
1303                 sumo_enable_boost(rdev, new_ps, false);
1304                 sumo_patch_boost_state(rdev, new_ps);
1305         }
1306         if (pi->enable_dpm) {
1307                 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1308                 sumo_enable_power_level_0(rdev);
1309                 sumo_set_forced_level_0(rdev);
1310                 sumo_set_forced_mode_enabled(rdev);
1311                 sumo_wait_for_level_0(rdev);
1312                 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1313                 sumo_program_wl(rdev, new_ps);
1314                 sumo_program_bsp(rdev, new_ps);
1315                 sumo_program_at(rdev, new_ps);
1316                 sumo_force_nbp_state(rdev, new_ps);
1317                 sumo_set_forced_mode_disabled(rdev);
1318                 sumo_set_forced_mode_enabled(rdev);
1319                 sumo_set_forced_mode_disabled(rdev);
1320                 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1321         }
1322         if (pi->enable_boost)
1323                 sumo_enable_boost(rdev, new_ps, true);
1324         if (pi->enable_dpm)
1325                 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1326
1327         return 0;
1328 }
1329
1330 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1331 {
1332         struct sumo_power_info *pi = sumo_get_pi(rdev);
1333         struct radeon_ps *new_ps = &pi->requested_rps;
1334
1335         sumo_update_current_ps(rdev, new_ps);
1336 }
1337
1338 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1339 {
1340         sumo_program_bootup_state(rdev);
1341         sumo_enable_power_level_0(rdev);
1342         sumo_set_forced_level_0(rdev);
1343         sumo_set_forced_mode_enabled(rdev);
1344         sumo_wait_for_level_0(rdev);
1345         sumo_set_forced_mode_disabled(rdev);
1346         sumo_set_forced_mode_enabled(rdev);
1347         sumo_set_forced_mode_disabled(rdev);
1348 }
1349
1350 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1351 {
1352         struct sumo_power_info *pi = sumo_get_pi(rdev);
1353
1354         sumo_initialize_m3_arb(rdev);
1355         pi->fw_version = sumo_get_running_fw_version(rdev);
1356         DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1357         sumo_program_acpi_power_level(rdev);
1358         sumo_enable_acpi_pm(rdev);
1359         sumo_take_smu_control(rdev, true);
1360 }
1361
1362 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1363 {
1364
1365 }
1366
1367 union power_info {
1368         struct _ATOM_POWERPLAY_INFO info;
1369         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1370         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1371         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1372         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1373         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1374 };
1375
1376 union pplib_clock_info {
1377         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1378         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1379         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1380         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1381 };
1382
1383 union pplib_power_state {
1384         struct _ATOM_PPLIB_STATE v1;
1385         struct _ATOM_PPLIB_STATE_V2 v2;
1386 };
1387
1388 static void sumo_patch_boot_state(struct radeon_device *rdev,
1389                                   struct sumo_ps *ps)
1390 {
1391         struct sumo_power_info *pi = sumo_get_pi(rdev);
1392
1393         ps->num_levels = 1;
1394         ps->flags = 0;
1395         ps->levels[0] = pi->boot_pl;
1396 }
1397
1398 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1399                                             struct radeon_ps *rps,
1400                                             struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1401                                             u8 table_rev)
1402 {
1403         struct sumo_ps *ps = sumo_get_ps(rps);
1404
1405         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1406         rps->class = le16_to_cpu(non_clock_info->usClassification);
1407         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1408
1409         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1410                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1411                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1412         } else {
1413                 rps->vclk = 0;
1414                 rps->dclk = 0;
1415         }
1416
1417         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1418                 rdev->pm.dpm.boot_ps = rps;
1419                 sumo_patch_boot_state(rdev, ps);
1420         }
1421         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1422                 rdev->pm.dpm.uvd_ps = rps;
1423 }
1424
1425 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1426                                         struct radeon_ps *rps, int index,
1427                                         union pplib_clock_info *clock_info)
1428 {
1429         struct sumo_power_info *pi = sumo_get_pi(rdev);
1430         struct sumo_ps *ps = sumo_get_ps(rps);
1431         struct sumo_pl *pl = &ps->levels[index];
1432         u32 sclk;
1433
1434         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1435         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1436         pl->sclk = sclk;
1437         pl->vddc_index = clock_info->sumo.vddcIndex;
1438         pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1439
1440         ps->num_levels = index + 1;
1441
1442         if (pi->enable_sclk_ds) {
1443                 pl->ds_divider_index = 5;
1444                 pl->ss_divider_index = 4;
1445         }
1446 }
1447
1448 static int sumo_parse_power_table(struct radeon_device *rdev)
1449 {
1450         struct radeon_mode_info *mode_info = &rdev->mode_info;
1451         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1452         union pplib_power_state *power_state;
1453         int i, j, k, non_clock_array_index, clock_array_index;
1454         union pplib_clock_info *clock_info;
1455         struct _StateArray *state_array;
1456         struct _ClockInfoArray *clock_info_array;
1457         struct _NonClockInfoArray *non_clock_info_array;
1458         union power_info *power_info;
1459         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1460         u16 data_offset;
1461         u8 frev, crev;
1462         u8 *power_state_offset;
1463         struct sumo_ps *ps;
1464
1465         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1466                                    &frev, &crev, &data_offset))
1467                 return -EINVAL;
1468         power_info = (union power_info *)((uint8_t*)mode_info->atom_context->bios + data_offset);
1469
1470         state_array = (struct _StateArray *)
1471                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1472                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
1473         clock_info_array = (struct _ClockInfoArray *)
1474                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1475                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1476         non_clock_info_array = (struct _NonClockInfoArray *)
1477                 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1478                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1479
1480         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1481                                   state_array->ucNumEntries, GFP_KERNEL);
1482         if (!rdev->pm.dpm.ps)
1483                 return -ENOMEM;
1484         power_state_offset = (u8 *)state_array->states;
1485         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
1486         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
1487         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
1488         for (i = 0; i < state_array->ucNumEntries; i++) {
1489                 u8 *idx;
1490                 power_state = (union pplib_power_state *)power_state_offset;
1491                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1492                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1493                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
1494                 if (!rdev->pm.power_state[i].clock_info)
1495                         return -EINVAL;
1496                 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1497                 if (ps == NULL) {
1498                         kfree(rdev->pm.dpm.ps);
1499                         return -ENOMEM;
1500                 }
1501                 rdev->pm.dpm.ps[i].ps_priv = ps;
1502                 k = 0;
1503                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1504                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1505                         clock_array_index = idx[j];
1506                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1507                                 break;
1508
1509                         clock_info = (union pplib_clock_info *)
1510                                 ((u8 *)&clock_info_array->clockInfo[0] +
1511                                  (clock_array_index * clock_info_array->ucEntrySize));
1512                         sumo_parse_pplib_clock_info(rdev,
1513                                                     &rdev->pm.dpm.ps[i], k,
1514                                                     clock_info);
1515                         k++;
1516                 }
1517                 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1518                                                 non_clock_info,
1519                                                 non_clock_info_array->ucEntrySize);
1520                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1521         }
1522         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1523         return 0;
1524 }
1525
1526 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1527                               struct sumo_vid_mapping_table *vid_mapping_table,
1528                               u32 vid_2bit)
1529 {
1530         u32 i;
1531
1532         for (i = 0; i < vid_mapping_table->num_entries; i++) {
1533                 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1534                         return vid_mapping_table->entries[i].vid_7bit;
1535         }
1536
1537         return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1538 }
1539
1540 u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,
1541                               struct sumo_vid_mapping_table *vid_mapping_table,
1542                               u32 vid_7bit)
1543 {
1544         u32 i;
1545
1546         for (i = 0; i < vid_mapping_table->num_entries; i++) {
1547                 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
1548                         return vid_mapping_table->entries[i].vid_2bit;
1549         }
1550
1551         return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
1552 }
1553
1554 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1555                                                u32 vid_2bit)
1556 {
1557         struct sumo_power_info *pi = sumo_get_pi(rdev);
1558         u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1559
1560         if (vid_7bit > 0x7C)
1561                 return 0;
1562
1563         return (15500 - vid_7bit * 125 + 5) / 10;
1564 }
1565
1566 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1567                                                          struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1568                                                          ATOM_CLK_VOLT_CAPABILITY *table)
1569 {
1570         u32 i;
1571
1572         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1573                 if (table[i].ulMaximumSupportedCLK == 0)
1574                         break;
1575
1576                 disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1577                         table[i].ulMaximumSupportedCLK;
1578         }
1579
1580         disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1581
1582         if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1583                 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1584                 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1585         }
1586 }
1587
1588 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1589                                                struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1590                                                ATOM_AVAILABLE_SCLK_LIST *table)
1591 {
1592         u32 i;
1593         u32 n = 0;
1594         u32 prev_sclk = 0;
1595
1596         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1597                 if (table[i].ulSupportedSCLK > prev_sclk) {
1598                         sclk_voltage_mapping_table->entries[n].sclk_frequency =
1599                                 table[i].ulSupportedSCLK;
1600                         sclk_voltage_mapping_table->entries[n].vid_2bit =
1601                                 table[i].usVoltageIndex;
1602                         prev_sclk = table[i].ulSupportedSCLK;
1603                         n++;
1604                 }
1605         }
1606
1607         sclk_voltage_mapping_table->num_max_dpm_entries = n;
1608 }
1609
1610 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1611                                       struct sumo_vid_mapping_table *vid_mapping_table,
1612                                       ATOM_AVAILABLE_SCLK_LIST *table)
1613 {
1614         u32 i, j;
1615
1616         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1617                 if (table[i].ulSupportedSCLK != 0) {
1618                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1619                                 table[i].usVoltageID;
1620                         vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1621                                 table[i].usVoltageIndex;
1622                 }
1623         }
1624
1625         for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1626                 if (vid_mapping_table->entries[i].vid_7bit == 0) {
1627                         for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1628                                 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1629                                         vid_mapping_table->entries[i] =
1630                                                 vid_mapping_table->entries[j];
1631                                         vid_mapping_table->entries[j].vid_7bit = 0;
1632                                         break;
1633                                 }
1634                         }
1635
1636                         if (j == SUMO_MAX_NUMBER_VOLTAGES)
1637                                 break;
1638                 }
1639         }
1640
1641         vid_mapping_table->num_entries = i;
1642 }
1643
1644 union igp_info {
1645         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1646         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1647         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1648         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1649 };
1650
1651 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1652 {
1653         struct sumo_power_info *pi = sumo_get_pi(rdev);
1654         struct radeon_mode_info *mode_info = &rdev->mode_info;
1655         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1656         union igp_info *igp_info;
1657         u8 frev, crev;
1658         u16 data_offset;
1659         int i;
1660
1661         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1662                                    &frev, &crev, &data_offset)) {
1663                 igp_info = (union igp_info *)((uint8_t*)mode_info->atom_context->bios +
1664                                               data_offset);
1665
1666                 if (crev != 6) {
1667                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1668                         return -EINVAL;
1669                 }
1670                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1671                 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1672                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1673                 pi->sys_info.bootup_nb_voltage_index =
1674                         le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1675                 if (igp_info->info_6.ucHtcTmpLmt == 0)
1676                         pi->sys_info.htc_tmp_lmt = 203;
1677                 else
1678                         pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1679                 if (igp_info->info_6.ucHtcHystLmt == 0)
1680                         pi->sys_info.htc_hyst_lmt = 5;
1681                 else
1682                         pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1683                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1684                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1685                 }
1686                 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1687                         pi->sys_info.csr_m3_arb_cntl_default[i] =
1688                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1689                         pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1690                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1691                         pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1692                                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1693                 }
1694                 pi->sys_info.sclk_dpm_boost_margin =
1695                         le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1696                 pi->sys_info.sclk_dpm_throttle_margin =
1697                         le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1698                 pi->sys_info.sclk_dpm_tdp_limit_pg =
1699                         le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1700                 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1701                 pi->sys_info.sclk_dpm_tdp_limit_boost =
1702                         le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1703                 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1704                 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1705                 if (igp_info->info_6.EnableBoost)
1706                         pi->sys_info.enable_boost = true;
1707                 else
1708                         pi->sys_info.enable_boost = false;
1709                 sumo_construct_display_voltage_mapping_table(rdev,
1710                                                              &pi->sys_info.disp_clk_voltage_mapping_table,
1711                                                              igp_info->info_6.sDISPCLK_Voltage);
1712                 sumo_construct_sclk_voltage_mapping_table(rdev,
1713                                                           &pi->sys_info.sclk_voltage_mapping_table,
1714                                                           igp_info->info_6.sAvail_SCLK);
1715                 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1716                                                  igp_info->info_6.sAvail_SCLK);
1717
1718         }
1719         return 0;
1720 }
1721
1722 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1723 {
1724         struct sumo_power_info *pi = sumo_get_pi(rdev);
1725
1726         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1727         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1728         pi->boot_pl.ds_divider_index = 0;
1729         pi->boot_pl.ss_divider_index = 0;
1730         pi->boot_pl.allow_gnb_slow = 1;
1731         pi->acpi_pl = pi->boot_pl;
1732         pi->current_ps.num_levels = 1;
1733         pi->current_ps.levels[0] = pi->boot_pl;
1734 }
1735
1736 int sumo_dpm_init(struct radeon_device *rdev)
1737 {
1738         struct sumo_power_info *pi;
1739         u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1740         int ret;
1741
1742         pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1743         if (pi == NULL)
1744                 return -ENOMEM;
1745         rdev->pm.dpm.priv = pi;
1746
1747         pi->driver_nbps_policy_disable = false;
1748         if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1749                 pi->disable_gfx_power_gating_in_uvd = true;
1750         else
1751                 pi->disable_gfx_power_gating_in_uvd = false;
1752         pi->enable_alt_vddnb = true;
1753         pi->enable_sclk_ds = true;
1754         pi->enable_dynamic_m3_arbiter = false;
1755         pi->enable_dynamic_patch_ps = true;
1756         /* Some PALM chips don't seem to properly ungate gfx when UVD is in use;
1757          * for now just disable gfx PG.
1758          */
1759         if (rdev->family == CHIP_PALM)
1760                 pi->enable_gfx_power_gating = false;
1761         else
1762                 pi->enable_gfx_power_gating = true;
1763         pi->enable_gfx_clock_gating = true;
1764         pi->enable_mg_clock_gating = true;
1765         pi->enable_auto_thermal_throttling = true;
1766
1767         ret = sumo_parse_sys_info_table(rdev);
1768         if (ret)
1769                 return ret;
1770
1771         sumo_construct_boot_and_acpi_state(rdev);
1772
1773         ret = sumo_parse_power_table(rdev);
1774         if (ret)
1775                 return ret;
1776
1777         pi->pasi = CYPRESS_HASI_DFLT;
1778         pi->asi = RV770_ASI_DFLT;
1779         pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1780         pi->enable_boost = pi->sys_info.enable_boost;
1781         pi->enable_dpm = true;
1782
1783         return 0;
1784 }
1785
1786 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1787                                 struct radeon_ps *rps)
1788 {
1789         int i;
1790         struct sumo_ps *ps = sumo_get_ps(rps);
1791
1792         r600_dpm_print_class_info(rps->class, rps->class2);
1793         r600_dpm_print_cap_info(rps->caps);
1794         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1795         for (i = 0; i < ps->num_levels; i++) {
1796                 struct sumo_pl *pl = &ps->levels[i];
1797                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
1798                        i, pl->sclk,
1799                        sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1800         }
1801         r600_dpm_print_ps_status(rdev, rps);
1802 }
1803
1804 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1805                                                       struct seq_file *m)
1806 {
1807         struct sumo_power_info *pi = sumo_get_pi(rdev);
1808         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1809         struct sumo_ps *ps = sumo_get_ps(rps);
1810         struct sumo_pl *pl;
1811         u32 current_index =
1812                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1813                 CURR_INDEX_SHIFT;
1814
1815         if (current_index == BOOST_DPM_LEVEL) {
1816                 pl = &pi->boost_pl;
1817                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1818                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1819                            current_index, pl->sclk,
1820                            sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1821         } else if (current_index >= ps->num_levels) {
1822                 seq_printf(m, "invalid dpm profile %d\n", current_index);
1823         } else {
1824                 pl = &ps->levels[current_index];
1825                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1826                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1827                            current_index, pl->sclk,
1828                            sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1829         }
1830 }
1831
1832 void sumo_dpm_fini(struct radeon_device *rdev)
1833 {
1834         int i;
1835
1836         sumo_cleanup_asic(rdev); /* ??? */
1837
1838         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1839                 kfree(rdev->pm.dpm.ps[i].ps_priv);
1840         }
1841         kfree(rdev->pm.dpm.ps);
1842         kfree(rdev->pm.dpm.priv);
1843 }
1844
1845 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1846 {
1847         struct sumo_power_info *pi = sumo_get_pi(rdev);
1848         struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1849
1850         if (low)
1851                 return requested_state->levels[0].sclk;
1852         else
1853                 return requested_state->levels[requested_state->num_levels - 1].sclk;
1854 }
1855
1856 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1857 {
1858         struct sumo_power_info *pi = sumo_get_pi(rdev);
1859
1860         return pi->sys_info.bootup_uma_clk;
1861 }
1862
1863 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
1864                                      enum radeon_dpm_forced_level level)
1865 {
1866         struct sumo_power_info *pi = sumo_get_pi(rdev);
1867         struct radeon_ps *rps = &pi->current_rps;
1868         struct sumo_ps *ps = sumo_get_ps(rps);
1869         int i;
1870
1871         if (ps->num_levels <= 1)
1872                 return 0;
1873
1874         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1875                 if (pi->enable_boost)
1876                         sumo_enable_boost(rdev, rps, false);
1877                 sumo_power_level_enable(rdev, ps->num_levels - 1, true);
1878                 sumo_set_forced_level(rdev, ps->num_levels - 1);
1879                 sumo_set_forced_mode_enabled(rdev);
1880                 for (i = 0; i < ps->num_levels - 1; i++) {
1881                         sumo_power_level_enable(rdev, i, false);
1882                 }
1883                 sumo_set_forced_mode(rdev, false);
1884                 sumo_set_forced_mode_enabled(rdev);
1885                 sumo_set_forced_mode(rdev, false);
1886         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1887                 if (pi->enable_boost)
1888                         sumo_enable_boost(rdev, rps, false);
1889                 sumo_power_level_enable(rdev, 0, true);
1890                 sumo_set_forced_level(rdev, 0);
1891                 sumo_set_forced_mode_enabled(rdev);
1892                 for (i = 1; i < ps->num_levels; i++) {
1893                         sumo_power_level_enable(rdev, i, false);
1894                 }
1895                 sumo_set_forced_mode(rdev, false);
1896                 sumo_set_forced_mode_enabled(rdev);
1897                 sumo_set_forced_mode(rdev, false);
1898         } else {
1899                 for (i = 0; i < ps->num_levels; i++) {
1900                         sumo_power_level_enable(rdev, i, true);
1901                 }
1902                 if (pi->enable_boost)
1903                         sumo_enable_boost(rdev, rps, true);
1904         }
1905
1906         rdev->pm.dpm.forced_level = level;
1907
1908         return 0;
1909 }