2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * $FreeBSD: src/sys/i386/isa/if_le.c,v 1.56.2.4 2002/06/05 23:24:10 paul Exp $
25 * $DragonFly: src/sys/dev/netif/le/if_le.c,v 1.24 2005/05/27 15:36:09 joerg Exp $
29 * DEC EtherWORKS 2 Ethernet Controllers
30 * DEC EtherWORKS 3 Ethernet Controllers
32 * Written by Matt Thomas
33 * BPF support code stolen directly from if_ec.c
35 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
36 * DE2002, DE203, DE204, DE205, and DE422 cards.
43 #include <sys/param.h>
44 #include <sys/systm.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/malloc.h>
50 #include <sys/linker_set.h>
51 #include <sys/module.h>
53 #include <net/ethernet.h>
55 #include <net/ifq_var.h>
56 #include <net/if_types.h>
57 #include <net/if_dl.h>
59 #include <netinet/in.h>
60 #include <netinet/if_ether.h>
62 #include <bus/isa/i386/isa_device.h>
63 #include <i386/isa/icu.h>
70 typedef u_short le_mcbits_t;
71 #define LE_MC_NBPW_LOG2 4
72 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
77 int (*bd_probe)(struct le_softc *sc, const struct le_board *bd, int *msize);
81 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
83 * Start of DEC EtherWORKS III (LEMAC) dependent structures
86 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
88 DECLARE_DUMMY_MODULE(if_le);
90 static int lemac_probe(struct le_softc *sc, const struct le_board *bd, int *msize);
92 struct le_lemac_info {
93 u_int lemac__lastpage; /* last 2K page */
94 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
95 u_int lemac__membase; /* Physical address of start of RAM */
96 u_int lemac__txctl; /* Transmit Control Byte */
97 u_int lemac__txmax; /* Maximum # of outstanding transmits */
98 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
99 /* local copy of multicast table */
100 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
101 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
102 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
103 #define lemac_memmode le_un.un_lemac.lemac__memmode
104 #define lemac_membase le_un.un_lemac.lemac__membase
105 #define lemac_txctl le_un.un_lemac.lemac__txctl
106 #define lemac_txmax le_un.un_lemac.lemac__txmax
107 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
108 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
109 #define lemac_prodname le_un.un_lemac.lemac__prodname
113 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
115 * Start of DEC EtherWORKS II (LANCE) dependent structures
119 #include <i386/isa/ic/am7990.h>
125 static int depca_probe(struct le_softc *sc, const struct le_board *bd, int *msize);
127 typedef struct lance_descinfo lance_descinfo_t;
128 typedef struct lance_ring lance_ring_t;
130 typedef unsigned lance_addr_t;
132 struct lance_descinfo {
133 caddr_t di_addr; /* address of descriptor */
134 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
135 unsigned di_buflen; /* size of buffer owned by descriptor */
136 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
140 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
141 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
142 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
143 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
144 unsigned ri_max; /* Size of Ring - 1 */
145 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
146 lance_addr_t ri_heap; /* Start of RAM for this ring */
147 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
148 lance_addr_t ri_outptr; /* Pointer to first output byte */
149 unsigned ri_outsize; /* Space remaining for output */
152 struct le_lance_info {
153 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
154 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
155 unsigned lance__csr3; /* Copy of CSR3 */
156 unsigned lance__rap; /* IO Port Offset of RAP */
157 unsigned lance__rdp; /* IO Port Offset of RDP */
158 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
159 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
160 unsigned lance__rxbufsize; /* Size of a receive buffer */
161 ln_initb_t lance__initb; /* local copy of LANCE initblock */
162 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
163 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
164 lance_ring_t lance__rxinfo; /* Receive ring information */
165 lance_ring_t lance__txinfo; /* Transmit ring information */
166 #define lance_csr1 le_un.un_lance.lance__csr1
167 #define lance_csr2 le_un.un_lance.lance__csr2
168 #define lance_csr3 le_un.un_lance.lance__csr3
169 #define lance_rap le_un.un_lance.lance__rap
170 #define lance_rdp le_un.un_lance.lance__rdp
171 #define lance_ramoffset le_un.un_lance.lance__ramoffset
172 #define lance_ramsize le_un.un_lance.lance__ramsize
173 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
174 #define lance_initb le_un.un_lance.lance__initb
175 #define lance_raminitb le_un.un_lance.lance__raminitb
176 #define lance_ramdesc le_un.un_lance.lance__ramdesc
177 #define lance_rxinfo le_un.un_lance.lance__rxinfo
178 #define lance_txinfo le_un.un_lance.lance__txinfo
182 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
184 * Start of Common Code
188 static void (*le_intrvec[NLE])(struct le_softc *sc);
191 * Ethernet status, per interface.
194 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
195 void (*if_init) (void *);/* Interface init routine */
196 void (*if_reset) (struct le_softc*);/* Interface reset routine */
197 caddr_t le_membase; /* Starting memory address (virtual) */
198 unsigned le_iobase; /* Starting I/O base address */
199 unsigned le_irq; /* Interrupt Request Value */
200 unsigned le_flags; /* local copy of if_flags */
201 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
202 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
203 le_mcbits_t *le_mctbl; /* pointer to multicast table */
204 const char *le_prodname; /* product name DE20x-xx */
205 u_char le_hwaddr[6]; /* local copy of hwaddr */
207 struct le_lemac_info un_lemac; /* LEMAC specific information */
208 struct le_lance_info un_lance; /* Am7990 specific information */
211 #define le_if le_ac.ac_if
214 static int le_probe(struct isa_device *dvp);
215 static int le_attach(struct isa_device *dvp);
216 static ointhand2_t le_intr;
217 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
219 static void le_input(struct le_softc *sc, caddr_t seg1, size_t total_len,
220 size_t len2, caddr_t seg2);
221 static void le_multi_filter(struct le_softc *sc);
222 static void le_multi_op(struct le_softc *sc, const u_char *mca, int oper_flg);
223 static int le_read_macaddr(struct le_softc *sc, int ioreg, int skippat);
225 static struct le_softc le_softc[NLE];
227 static const struct le_board le_boards[] = {
228 { lemac_probe }, /* DE20[345] */
229 { depca_probe }, /* DE{20[012],422} */
230 { NULL } /* Must Be Last! */
234 * This tells the autoconf code how to set us up.
236 struct isa_driver ledriver = {
237 le_probe, le_attach, "le",
240 static unsigned le_intrs[NLE];
242 #define LE_INL(sc, reg) inl((sc)->le_iobase + (reg))
243 #define LE_OUTL(sc, reg, data) outl((sc)->le_iobase + (reg), data)
244 #define LE_INW(sc, reg) inw((sc)->le_iobase + (reg))
245 #define LE_OUTW(sc, reg, data) outw((sc)->le_iobase + (reg), data)
246 #define LE_INB(sc, reg) inb((sc)->le_iobase + (reg))
247 #define LE_OUTB(sc, reg, data) outb((sc)->le_iobase + (reg), data)
250 le_probe(struct isa_device *dvp)
252 struct le_softc *sc = &le_softc[dvp->id_unit];
253 const struct le_board *bd;
256 if (dvp->id_unit >= NLE) {
257 printf("%s%d not configured -- too many devices\n",
258 ledriver.name, dvp->id_unit);
262 sc->le_iobase = dvp->id_iobase;
263 sc->le_membase = (u_char *) dvp->id_maddr;
264 sc->le_irq = dvp->id_irq;
265 if_initname(&(sc->le_if), ledriver.name, dvp->id_unit);
268 * Find and Initialize board..
271 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
273 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
274 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
283 le_attach(struct isa_device *dvp)
285 struct le_softc *sc = &le_softc[dvp->id_unit];
286 struct ifnet *ifp = &sc->le_if;
288 dvp->id_ointr = le_intr;
290 ifp->if_mtu = ETHERMTU;
292 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
293 ifp->if_ioctl = le_ioctl;
294 ifp->if_type = IFT_ETHER;
297 ifp->if_init = sc->if_init;
298 ifp->if_baudrate = 10000000;
299 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
300 ifq_set_ready(&ifp->if_snd);
302 ether_ifattach(ifp, sc->le_ac.ac_enaddr);
313 (*le_intrvec[unit])(&le_softc[unit]);
321 le_input(struct le_softc *sc, caddr_t seg1, size_t total_len,
322 size_t len1, caddr_t seg2)
324 struct ether_header eh;
327 if (total_len - sizeof(eh) > ETHERMTU
328 || total_len - sizeof(eh) < ETHERMIN) {
329 sc->le_if.if_ierrors++;
332 bcopy(seg1, &eh, ETHER_HDR_LEN);
334 seg1 += ETHER_HDR_LEN;
335 total_len -= ETHER_HDR_LEN;
336 len1 -= ETHER_HDR_LEN;
338 MGETHDR(m, MB_DONTWAIT, MT_DATA);
340 sc->le_if.if_ierrors++;
343 m->m_pkthdr.len = total_len;
344 m->m_pkthdr.rcvif = &sc->le_if;
345 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
346 MCLGET(m, MB_DONTWAIT);
347 if ((m->m_flags & M_EXT) == 0) {
349 sc->le_if.if_ierrors++;
352 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
353 MGET(m->m_next, MB_DONTWAIT, MT_DATA);
354 if (m->m_next == NULL) {
356 sc->le_if.if_ierrors++;
359 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
360 len1 = total_len = MHLEN - LE_XTRA;
361 bcopy(&seg1[MHLEN-LE_XTRA], mtod(m->m_next, caddr_t), m->m_next->m_len);
362 } else if (total_len + LE_XTRA > MHLEN) {
363 panic("le_input: pkt of unknown length");
365 m->m_data += LE_XTRA;
366 m->m_len = total_len;
367 bcopy(seg1, mtod(m, caddr_t), len1);
369 bcopy(seg2, mtod(m, caddr_t) + len1, total_len - len1);
370 ether_input(&sc->le_if, &eh, m);
374 le_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
376 struct le_softc *sc = ifp->if_softc;
379 if ((sc->le_flags & IFF_UP) == 0)
393 * Update multicast listeners
400 error = ether_ioctl(ifp, cmd, data);
409 * This is the standard method of reading the DEC Address ROMS.
410 * I don't understand it but it does work.
413 le_read_macaddr(struct le_softc *sc, int ioreg, int skippat)
415 int cksum, rom_cksum;
418 int idx, idx2, found, octet;
419 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
422 for (idx = 0; idx < 32; idx++) {
423 octet = LE_INB(sc, ioreg);
425 if (octet == testpat[idx2]) {
426 if (++idx2 == sizeof testpat) {
440 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
441 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
443 cksum = *(u_short *) &sc->le_hwaddr[0];
445 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
446 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
448 if (cksum > 65535) cksum -= 65535;
449 cksum += *(u_short *) &sc->le_hwaddr[2];
450 if (cksum > 65535) cksum -= 65535;
452 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
453 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
455 if (cksum > 65535) cksum -= 65535;
456 cksum += *(u_short *) &sc->le_hwaddr[4];
457 if (cksum >= 65535) cksum -= 65535;
459 rom_cksum = LE_INB(sc, ioreg);
460 rom_cksum |= LE_INB(sc, ioreg) << 8;
462 if (cksum != rom_cksum)
468 le_multi_filter(struct le_softc *sc)
470 struct ifnet *ifp = &sc->le_ac.ac_if;
471 struct ifmultiaddr *ifma;
473 bzero(sc->le_mctbl, (sc->le_mcmask + 1) / 8);
475 if (sc->le_if.if_flags & IFF_ALLMULTI) {
476 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
479 sc->le_flags &= ~IFF_MULTICAST;
480 /* if (interface has had an address assigned) { */
481 le_multi_op(sc, ifp->if_broadcastaddr, TRUE);
482 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
485 sc->le_flags |= IFF_MULTICAST;
487 for (ifma = ifp->if_multiaddrs.lh_first; ifma;
488 ifma = ifma->ifma_link.le_next) {
489 if (ifma->ifma_addr->sa_family != AF_LINK)
492 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
493 sc->le_flags &= ~LE_BRDCSTONLY;
498 le_multi_op(struct le_softc *sc, const u_char *mca, int enable)
500 uint32_t bit, idx, crc;
502 crc = ether_crc32_le(mca, ETHER_ADDR_LEN);
505 * The following two line convert the N bit index into a longword index
506 * and a longword mask.
508 crc &= sc->le_mcmask;
509 bit = 1 << (crc & (LE_MC_NBPW -1));
510 idx = crc >> (LE_MC_NBPW_LOG2);
513 * Set or clear hash filter bit in our table.
516 sc->le_mctbl[idx] |= bit; /* Set Bit */
518 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
523 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
525 * Start of DEC EtherWORKS III (LEMAC) dependent code
529 #define LEMAC_INTR_ENABLE(sc) \
530 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
532 #define LEMAC_INTR_DISABLE(sc) \
533 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
535 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
536 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
537 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
539 static void lemac_init(void *xsc);
540 static void lemac_start(struct ifnet *ifp);
541 static void lemac_reset(struct le_softc *sc);
542 static void lemac_intr(struct le_softc *sc);
543 static void lemac_rne_intr(struct le_softc *sc);
544 static void lemac_tne_intr(struct le_softc *sc);
545 static void lemac_txd_intr(struct le_softc *sc, unsigned cs_value);
546 static void lemac_rxd_intr(struct le_softc *sc, unsigned cs_value);
547 static int lemac_read_eeprom(struct le_softc *sc);
548 static void lemac_init_adapmem(struct le_softc *sc);
550 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
552 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
553 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
554 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
555 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
556 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
559 * An IRQ mapping table. Less space than switch statement.
561 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
564 * Some tuning/monitoring variables.
566 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
567 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
569 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
570 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
571 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
572 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
575 lemac_probe(struct le_softc *sc, const struct le_board *bd, int *msize)
579 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
580 DELAY(LEMAC_EEP_DELAY);
583 * Read Ethernet address if card is present.
585 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
588 bcopy(sc->le_hwaddr, sc->le_ac.ac_enaddr, ETHER_ADDR_LEN);
590 * Clear interrupts and set IRQ.
593 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
594 irq = lemac_irqs[portval >> 5];
595 LE_OUTB(sc, LEMAC_REG_IC, portval);
598 * Make sure settings match.
601 if (irq != sc->le_irq) {
602 if_printf(&sc->le_if, "lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
608 * Try to reset the unit
610 sc->if_init = lemac_init;
611 sc->le_if.if_start = lemac_start;
612 sc->if_reset = lemac_reset;
613 sc->lemac_memmode = 2;
615 if ((sc->le_flags & IFF_UP) == 0)
619 * Check for correct memory base configuration.
621 if (vtophys(sc->le_membase) != sc->lemac_membase) {
622 if_printf(&sc->le_if, "lemac configuration error: expected iomem 0x%llx actual 0x%x\n",
623 vtophys(sc->le_membase), sc->lemac_membase);
627 sc->le_prodname = sc->lemac_prodname;
628 sc->le_mctbl = sc->lemac_mctbl;
629 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
630 sc->lemac_txmax = lemac_deftxmax;
632 le_intrvec[sc->le_if.if_dunit] = lemac_intr;
634 return LEMAC_IOSPACE;
638 * Do a hard reset of the board;
641 lemac_reset(struct le_softc *sc)
643 struct ifnet *ifp = &sc->le_if;
650 sc->le_flags &= IFF_UP;
651 ifp->if_flags &= ~IFF_OACTIVE;
652 LEMAC_INTR_DISABLE(sc);
654 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
655 DELAY(LEMAC_EEP_DELAY);
657 /* Disable Interrupts */
658 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
661 * Read EEPROM information. NOTE - the placement of this function
662 * is important because functions hereafter may rely on information
663 * read from the EEPROM.
665 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
666 if_printf(ifp, "reset: EEPROM checksum failed (0x%x)\n", cksum);
671 * Force to 2K mode if not already configured.
674 portval = LE_INB(sc, LEMAC_REG_MBR);
675 if (!LEMAC_2K_MODE(portval)) {
676 if (LEMAC_64K_MODE(portval)) {
677 portval = (((portval * 2) & 0xF) << 4);
678 sc->lemac_memmode = 64;
679 } else if (LEMAC_32K_MODE(portval)) {
680 portval = ((portval & 0xF) << 4);
681 sc->lemac_memmode = 32;
683 LE_OUTB(sc, LEMAC_REG_MBR, portval);
685 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
688 * Initialize Free Memory Queue, Init mcast table with broadcast.
691 lemac_init_adapmem(sc);
692 sc->le_flags |= IFF_UP;
696 lemac_init(void *xsc)
698 struct le_softc *sc = (struct le_softc *)xsc;
701 if ((sc->le_flags & IFF_UP) == 0)
707 * If the interface has the up flag
709 if (sc->le_if.if_flags & IFF_UP) {
710 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
711 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
712 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
713 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
714 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
715 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
716 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
717 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
719 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
721 if (sc->le_if.if_flags & IFF_PROMISC) {
722 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
724 LEMAC_INTR_DISABLE(sc);
726 LE_OUTB(sc, LEMAC_REG_MPN, 0);
727 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
728 bcopy(lemac_allmulti_mctbl, &sc->le_membase[LEMAC_MCTBL_OFF], sizeof(lemac_allmulti_mctbl));
730 bcopy(sc->lemac_mctbl, &sc->le_membase[LEMAC_MCTBL_OFF], sizeof(sc->lemac_mctbl));
732 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
735 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
737 LEMAC_INTR_ENABLE(sc);
738 sc->le_if.if_flags |= IFF_RUNNING;
740 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
742 LEMAC_INTR_DISABLE(sc);
743 sc->le_if.if_flags &= ~IFF_RUNNING;
749 * What to do upon receipt of an interrupt.
752 lemac_intr(struct le_softc *sc)
756 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
759 * Determine cause of interrupt. Receive events take
760 * priority over Transmit.
763 cs_value = LE_INB(sc, LEMAC_REG_CS);
766 * Check for Receive Queue not being empty.
767 * Check for Transmit Done Queue not being empty.
770 if (cs_value & LEMAC_CS_RNE)
772 if (cs_value & LEMAC_CS_TNE)
776 * Check for Transmitter Disabled.
777 * Check for Receiver Disabled.
780 if (cs_value & LEMAC_CS_TXD)
781 lemac_txd_intr(sc, cs_value);
782 if (cs_value & LEMAC_CS_RXD)
783 lemac_rxd_intr(sc, cs_value);
786 * Toggle LED and unmask interrupts.
789 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
790 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
794 lemac_rne_intr(struct le_softc *sc)
796 int rxcount, rxlen, rxpg;
800 rxcount = LE_INB(sc, LEMAC_REG_RQC);
802 rxpg = LE_INB(sc, LEMAC_REG_RQ);
803 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
805 rxptr = sc->le_membase;
806 sc->le_if.if_ipackets++;
807 if (*rxptr & LEMAC_RX_OK) {
810 * Get receive length - subtract out checksum.
813 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
814 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
815 } else { /* end if (*rxptr & LEMAC_RX_OK) */
816 sc->le_if.if_ierrors++;
818 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
819 } /* end while (recv_count--) */
823 lemac_rxd_intr(struct le_softc *sc, unsigned cs_value)
826 * Handle CS_RXD (Receiver disabled) here.
828 * Check Free Memory Queue Count. If not equal to zero
829 * then just turn Receiver back on. If it is equal to
830 * zero then check to see if transmitter is disabled.
831 * Process transmit TXD loop once more. If all else
832 * fails then do software init (0xC0 to EEPROM Init)
833 * and rebuild Free Memory Queue.
839 * Re-enable Receiver.
842 cs_value &= ~LEMAC_CS_RXD;
843 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
845 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
848 if (cs_value & LEMAC_CS_TXD)
849 lemac_txd_intr(sc, cs_value);
851 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
854 if_printf(&sc->le_if, "fatal RXD error, attempting recovery\n");
857 if (sc->le_flags & IFF_UP) {
863 * Error during initializion. Mark card as disabled.
865 if_printf(&sc->le_if, "recovery failed -- board disabled\n");
869 lemac_start(struct ifnet *ifp)
871 struct le_softc *sc = (struct le_softc *) ifp;
873 if ((ifp->if_flags & IFF_RUNNING) == 0)
876 LEMAC_INTR_DISABLE(sc);
878 while (!ifq_is_empty(&ifp->if_snd)) {
883 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
884 ifp->if_flags |= IFF_OACTIVE;
888 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
890 * Check for good transmit page.
892 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
894 ifp->if_flags |= IFF_OACTIVE;
898 m = ifq_dequeue(&ifp->if_snd);
899 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
902 * The first four bytes of each transmit buffer are for
903 * control information. The first byte is the control
904 * byte, then the length (why not word aligned?), then
905 * the off to the buffer.
908 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
909 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
910 *(u_int *) sc->le_membase = txhdr;
913 * Copy the packet to the board
916 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
918 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
922 m_freem(m); /* free the mbuf */
924 LEMAC_INTR_ENABLE(sc);
928 lemac_tne_intr(struct le_softc *sc)
930 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
934 txsts = LE_INB(sc, LEMAC_REG_TDQ);
935 sc->le_if.if_opackets++; /* another one done */
936 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
937 sc->le_if.if_collisions++;
939 sc->le_if.if_flags &= ~IFF_OACTIVE;
940 lemac_start(&sc->le_if);
944 lemac_txd_intr(struct le_softc *sc, unsigned cs_value)
947 * Read transmit status, remove transmit buffer from
948 * transmit queue and place on free memory queue,
949 * then reset transmitter.
950 * Increment appropriate counters.
954 sc->le_if.if_oerrors++;
955 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
956 sc->le_if.if_collisions++;
957 sc->le_if.if_flags &= ~IFF_OACTIVE;
959 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
960 /* Get Page number and write it back out */
962 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
963 /* Turn back on transmitter */
967 lemac_read_eeprom(struct le_softc *sc)
974 ep = sc->lemac_eeprom;
975 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
976 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
977 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
979 DELAY(LEMAC_EEP_DELAY);
981 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
982 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
986 * Set up Transmit Control Byte for use later during transmit.
989 sc->lemac_txctl |= LEMAC_TX_FLAGS;
991 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
992 sc->lemac_txctl &= ~LEMAC_TX_SQE;
994 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
995 sc->lemac_txctl |= LEMAC_TX_LAB;
997 bcopy(&sc->lemac_eeprom[LEMAC_EEP_PRDNM], sc->lemac_prodname, LEMAC_EEP_PRDNMSZ);
998 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1004 lemac_init_adapmem(struct le_softc *sc)
1008 conf = LE_INB(sc, LEMAC_REG_CNF);
1010 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1011 sc->lemac_lastpage = 63;
1012 conf &= ~LEMAC_CNF_DRAM;
1014 sc->lemac_lastpage = 127;
1015 conf |= LEMAC_CNF_DRAM;
1018 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1020 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1021 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1027 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1029 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1032 static void depca_intr(struct le_softc *sc);
1033 static int lance_init_adapmem(struct le_softc *sc);
1034 static int lance_init_ring(struct le_softc *sc, ln_ring_t *rp, lance_ring_t *ri,
1035 unsigned ndescs, unsigned bufoffset,
1036 unsigned descoffset);
1037 static void lance_init(void *xsc);
1038 static void lance_reset(struct le_softc *sc);
1039 static void lance_intr(struct le_softc *sc);
1040 static int lance_rx_intr(struct le_softc *sc);
1041 static void lance_start(struct ifnet *ifp);
1042 static int lance_tx_intr(struct le_softc *sc);
1044 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1045 #define LN_TXDESC_RATIO 2048
1046 #define LN_DESC_MAX 128
1050 unsigned lance_rx_misses;
1051 unsigned lance_rx_badcrc;
1052 unsigned lance_rx_badalign;
1053 unsigned lance_rx_badframe;
1054 unsigned lance_rx_buferror;
1055 unsigned lance_tx_deferred;
1056 unsigned lance_tx_single_collisions;
1057 unsigned lance_tx_multiple_collisions;
1058 unsigned lance_tx_excessive_collisions;
1059 unsigned lance_tx_late_collisions;
1061 unsigned lance_memory_errors;
1062 unsigned lance_inits;
1063 unsigned lance_tx_intrs;
1064 unsigned lance_tx_nospc[2];
1065 unsigned lance_tx_drains[2];
1066 unsigned lance_tx_orphaned;
1067 unsigned lance_tx_adoptions;
1068 unsigned lance_tx_emptied;
1069 unsigned lance_tx_deftxint;
1070 unsigned lance_tx_buferror;
1071 unsigned lance_high_txoutptr;
1072 unsigned lance_low_txheapsize;
1073 unsigned lance_low_txfree;
1074 unsigned lance_tx_intr_hidescs;
1075 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1077 unsigned lance_rx_intrs;
1078 unsigned lance_rx_badsop;
1079 unsigned lance_rx_contig;
1080 unsigned lance_rx_noncontig;
1081 unsigned lance_rx_intr_hidescs;
1082 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1083 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1086 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1087 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1088 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1091 #define LN_STAT(stat) 0
1092 #define LN_MINSTAT(stat, val) 0
1093 #define LN_MAXSTAT(stat, val) 0
1096 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1097 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1099 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1100 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1103 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1104 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1106 #define LN_SETFLAG(sc, vaddr, val) \
1107 (((volatile u_char *) vaddr)[3] = (val))
1109 #define LN_PUTDESC(sc, desc, vaddr) \
1110 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1111 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1112 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1115 * Only get the descriptor flags and length/status. All else
1118 #define LN_GETDESC(sc, desc, vaddr) \
1119 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1120 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1123 * These definitions are specific to the DEC "DEPCA-style" NICs.
1124 * (DEPCA, DE10x, DE20[012], DE422)
1127 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1128 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1129 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1130 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1131 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1133 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1134 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1135 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1136 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1137 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1138 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1139 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1140 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1141 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1143 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1144 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1146 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1148 #define DEPCA_REG_EISAID 0x80
1149 #define DEPCA_EISAID_MASK 0xf0ffffff
1150 #define DEPCA_EISAID_DE422 0x2042A310
1154 DEPCA_DE100, DEPCA_DE101,
1156 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1161 static const char *depca_signatures[] = {
1165 "DE200", "DE201", "DE202",
1171 depca_probe(struct le_softc *sc, const struct le_board *bd, int *msize)
1173 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1176 * Find out how memory we are dealing with. Adjust
1177 * the ID string offset approriately if we are at
1178 * 32K. Make sure the ROM is enabled.
1180 nicsr = DEPCA_RDNICSR(sc);
1181 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1183 if (nicsr & DEPCA_NICSR_32KRAM) {
1185 * Make we are going to read the upper
1186 * 32K so we do read the ROM.
1188 sc->lance_ramsize = 32 * 1024;
1189 nicsr &= ~DEPCA_NICSR_LOW32K;
1190 sc->lance_ramoffset = 32 * 1024;
1191 idstr_offset -= sc->lance_ramsize;
1193 sc->lance_ramsize = 64 * 1024;
1194 sc->lance_ramoffset = 0;
1196 DEPCA_WRNICSR(sc, nicsr);
1198 sc->le_prodname = NULL;
1199 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1200 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1201 sc->le_prodname = depca_signatures[idx];
1206 if (sc->le_prodname == NULL) {
1208 * Try to get the EISA device if it's a DE422.
1210 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1211 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1212 == DEPCA_EISAID_DE422) {
1213 sc->le_prodname = "DE422";
1218 if (idx == DEPCA_CLASSIC)
1219 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1222 * Try to read the address ROM.
1223 * Stop the LANCE, reset the Address ROM Counter (AAC),
1224 * read the NICSR to "clock" in the reset, and then
1225 * re-enable the Address ROM Counter. Now read the
1228 sc->lance_rdp = DEPCA_REG_RDP;
1229 sc->lance_rap = DEPCA_REG_RAP;
1230 sc->lance_csr3 = LN_CSR3_ALE;
1231 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1232 sc->le_mcmask = LN_MC_MASK;
1233 LN_SELCSR(sc, LN_CSR0);
1234 LN_WRCSR(sc, LN_CSR0_STOP);
1236 if (idx < DEPCA_DE200) {
1237 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1238 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1241 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1244 bcopy(sc->le_hwaddr, sc->le_ac.ac_enaddr, ETHER_ADDR_LEN);
1246 * Renable shared RAM.
1248 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1250 le_intrvec[sc->le_if.if_dunit] = depca_intr;
1251 if (!lance_init_adapmem(sc))
1254 sc->if_reset = lance_reset;
1255 sc->if_init = lance_init;
1256 sc->le_if.if_start = lance_start;
1257 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1260 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1261 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1262 *msize = sc->lance_ramsize;
1263 return DEPCA_IOSPACE;
1267 depca_intr(struct le_softc *sc)
1269 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1274 * Here's as good a place to describe our paritioning of the
1275 * LANCE shared RAM space. (NOTE: this driver does not yet support
1276 * the concept of a LANCE being able to DMA).
1278 * First is the 24 (00:23) bytes for LANCE Initialization Block
1279 * Next are the recieve descriptors. The number is calculated from
1280 * how many LN_BUFSIZE buffers we can allocate (this number must
1281 * be a power of 2). Next are the transmit descriptors. The amount
1282 * of transmit descriptors is derived from the size of the RAM
1283 * divided by 1K. Now come the receive buffers (one for each receive
1284 * descriptor). Finally is the transmit heap. (no fixed buffers are
1285 * allocated so as to make the most use of the limited space).
1288 lance_init_adapmem(struct le_softc *sc)
1290 lance_addr_t rxbufoffset;
1291 lance_addr_t rxdescoffset, txdescoffset;
1292 unsigned rxdescs, txdescs;
1295 * First calculate how many descriptors we heap.
1296 * Note this assumes the ramsize is a power of two.
1298 sc->lance_rxbufsize = LN_BUFSIZE;
1300 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1303 if (rxdescs > LN_DESC_MAX) {
1304 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1305 rxdescs = LN_DESC_MAX;
1307 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1308 if (txdescs > LN_DESC_MAX)
1309 txdescs = LN_DESC_MAX;
1312 * Now calculate where everything goes in memory
1314 rxdescoffset = sizeof(ln_initb_t);
1315 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1316 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1318 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1320 * Remember these for debugging.
1322 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1323 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1326 * Initialize the rings.
1328 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1329 rxdescs, rxbufoffset, rxdescoffset))
1331 sc->lance_rxinfo.ri_heap = rxbufoffset;
1332 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1334 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1335 txdescs, 0, txdescoffset))
1337 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1338 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1341 * Set CSR1 and CSR2 to the address of the init block (which
1342 * for us is always 0.
1344 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1345 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1350 lance_init_ring(struct le_softc *sc, ln_ring_t *rp, lance_ring_t *ri,
1351 unsigned ndescs, lance_addr_t bufoffset, lance_addr_t descoffset)
1353 lance_descinfo_t *di;
1356 * Initialize the ring pointer in the LANCE InitBlock
1358 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1359 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1360 rp->r_log2_size = ffs(ndescs) - 1;
1363 * Allocate the ring entry descriptors and initialize
1364 * our ring information data structure. All these are
1365 * our copies and do not live in the LANCE RAM.
1367 ri->ri_first = malloc(ndescs * sizeof(*di), M_DEVBUF, M_WAITOK);
1368 ri->ri_free = ri->ri_max = ndescs;
1369 ri->ri_last = ri->ri_first + ri->ri_max;
1370 for (di = ri->ri_first; di < ri->ri_last; di++) {
1371 di->di_addr = sc->le_membase + descoffset;
1374 di->di_bufaddr = bufoffset;
1375 di->di_buflen = sc->lance_rxbufsize;
1376 bufoffset += sc->lance_rxbufsize;
1378 descoffset += sizeof(ln_desc_t);
1384 lance_dumpcsrs(struct le_softc *sc, const char *id)
1386 if_printf(&sc->le_if, "%s: nicsr=%04x", id, DEPCA_RDNICSR(sc));
1387 LN_SELCSR(sc, LN_CSR0);
1388 printf(" csr0=%04x", LN_RDCSR(sc));
1389 LN_SELCSR(sc, LN_CSR1);
1390 printf(" csr1=%04x", LN_RDCSR(sc));
1391 LN_SELCSR(sc, LN_CSR2);
1392 printf(" csr2=%04x", LN_RDCSR(sc));
1393 LN_SELCSR(sc, LN_CSR3);
1394 printf(" csr3=%04x\n", LN_RDCSR(sc));
1395 LN_SELCSR(sc, LN_CSR0);
1399 lance_reset(struct le_softc *sc)
1403 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1405 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1406 LN_WRCSR(sc, LN_CSR0_STOP);
1409 sc->le_flags &= ~IFF_UP;
1410 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1412 le_multi_filter(sc); /* initialize the multicast table */
1413 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1414 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1415 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1416 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1417 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1419 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1420 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1421 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1422 if (sc->le_if.if_flags & IFF_PROMISC) {
1423 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1425 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1428 * We force the init block to be at the start
1429 * of the LANCE's RAM buffer.
1431 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1432 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1433 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1434 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1436 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1439 * clear INITDONE and INIT the chip
1441 LN_SELCSR(sc, LN_CSR0);
1442 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1447 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1452 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1453 lance_dumpcsrs(sc, "lance_reset: reset failure");
1455 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1456 sc->le_if.if_flags |= IFF_UP;
1457 sc->le_flags |= IFF_UP;
1462 lance_init(void *xsc)
1464 struct le_softc *sc = (struct le_softc *)xsc;
1466 lance_descinfo_t *di;
1470 if (sc->le_if.if_flags & IFF_RUNNING) {
1474 * If we were running, abort any pending transmits.
1476 ri = &sc->lance_txinfo;
1477 di = ri->ri_nextout;
1478 while (ri->ri_free < ri->ri_max) {
1479 if (--di == ri->ri_first)
1480 di = ri->ri_nextout - 1;
1481 if (di->di_mbuf == NULL)
1483 m_free(di->di_mbuf);
1492 * Reset the transmit ring. Make sure we own all the buffers.
1493 * Also reset the transmit heap.
1495 sc->le_if.if_flags &= ~IFF_OACTIVE;
1496 ri = &sc->lance_txinfo;
1497 for (di = ri->ri_first; di < ri->ri_last; di++) {
1498 if (di->di_mbuf != NULL) {
1499 m_freem(di->di_mbuf);
1503 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1504 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1506 LN_PUTDESC(sc, &desc, di->di_addr);
1508 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1509 ri->ri_free = ri->ri_max;
1510 ri->ri_outptr = ri->ri_heap;
1511 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1513 ri = &sc->lance_rxinfo;
1514 desc.d_flag = LN_DFLAG_OWNER;
1515 desc.d_buflen = 0 - sc->lance_rxbufsize;
1516 for (di = ri->ri_first; di < ri->ri_last; di++) {
1517 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1518 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1519 LN_PUTDESC(sc, &desc, di->di_addr);
1521 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1522 ri->ri_outptr = ri->ri_heap;
1523 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1526 if (sc->le_if.if_flags & IFF_UP) {
1527 sc->le_if.if_flags |= IFF_RUNNING;
1528 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1529 /* lance_dumpcsrs(sc, "lance_init: up"); */
1530 lance_start(&sc->le_if);
1532 /* lance_dumpcsrs(sc, "lance_init: down"); */
1533 sc->le_if.if_flags &= ~IFF_RUNNING;
1538 lance_intr(struct le_softc *sc)
1542 oldcsr = LN_RDCSR(sc);
1543 oldcsr &= ~LN_CSR0_ENABINTR;
1544 LN_WRCSR(sc, oldcsr);
1545 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1547 if (oldcsr & LN_CSR0_ERRSUM) {
1548 if (oldcsr & LN_CSR0_MISS) {
1550 * LN_CSR0_MISS is signaled when the LANCE receiver
1551 * loses a packet because it doesn't own a receive
1552 * descriptor. Rev. D LANCE chips, which are no
1553 * longer used, require a chip reset as described
1556 LN_STAT(rx_misses++);
1558 if (oldcsr & LN_CSR0_MEMERROR) {
1559 LN_STAT(memory_errors++);
1560 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1567 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1572 if (oldcsr & LN_CSR0_TXINT) {
1573 if (lance_tx_intr(sc))
1574 lance_start(&sc->le_if);
1577 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1578 if_printf(&sc->le_if, "lance_intr: stray interrupt\n");
1582 lance_rx_intr(struct le_softc *sc)
1584 lance_ring_t *ri = &sc->lance_rxinfo;
1585 lance_descinfo_t *eop;
1587 int ndescs, total_len, rxdescs;
1589 LN_STAT(rx_intrs++);
1591 for (rxdescs = 0;;) {
1593 * Now to try to find the end of this packet chain.
1595 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1597 * If we don't own this descriptor, the packet ain't
1598 * all here so return because we are done.
1600 LN_GETDESC(sc, &desc, eop->di_addr);
1601 if (desc.d_flag & LN_DFLAG_OWNER)
1604 * In case we have missed a packet and gotten the
1605 * LANCE confused, make sure we are pointing at the
1606 * start of a packet. If we aren't, something is really
1607 * strange so reinit the LANCE.
1609 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1610 LN_STAT(rx_buferror++);
1613 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1614 LN_STAT(rx_badsop++);
1617 if (desc.d_flag & LN_DFLAG_EOP)
1619 if (++eop == ri->ri_last)
1623 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1624 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1626 * Valid Packet -- If the SOP is less than or equal to the EOP
1627 * or the length is less than the receive buffer size, then the
1628 * packet is contiguous in memory and can be copied in one shot.
1629 * Otherwise we need to copy two segments to get the entire
1632 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1633 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1634 total_len, total_len, NULL);
1635 LN_STAT(rx_contig++);
1637 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1639 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1640 sc->le_membase + ri->ri_first->di_bufaddr);
1641 LN_STAT(rx_noncontig++);
1645 * If the packet is bad, increment the
1648 sc->le_if.if_ierrors++;
1649 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1650 LN_STAT(rx_badcrc++);
1651 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1652 LN_STAT(rx_badalign++);
1653 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1654 LN_STAT(rx_badframe++);
1656 sc->le_if.if_ipackets++;
1657 LN_STAT(rx_ndescs[ndescs-1]++);
1659 while (ndescs-- > 0) {
1660 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1661 if (++ri->ri_nextin == ri->ri_last)
1662 ri->ri_nextin = ri->ri_first;
1665 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1666 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1672 lance_start(struct ifnet *ifp)
1674 struct le_softc *sc = (struct le_softc *) ifp;
1675 lance_ring_t *ri = &sc->lance_txinfo;
1676 lance_descinfo_t *di;
1679 struct mbuf *m, *m0;
1682 if ((ifp->if_flags & IFF_RUNNING) == 0)
1686 m = ifq_poll(&ifp->if_snd);
1691 * Make the packet meets the minimum size for Ethernet.
1692 * The slop is so that we also use an even number of longwards.
1694 len = ETHERMIN + sizeof(struct ether_header);
1695 if (m->m_pkthdr.len > len)
1696 len = m->m_pkthdr.len;
1698 slop = (8 - len) & 3;
1700 * If there are no free ring entries (there must be always
1701 * one owned by the host), or there's not enough space for
1702 * this packet, or this packet would wrap around the end
1703 * of LANCE RAM then wait for the transmits to empty for
1704 * space and ring entries to become available.
1706 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1708 * Try to see if we can free up anything off the transit ring.
1710 if (lance_tx_intr(sc) > 0) {
1711 LN_STAT(tx_drains[0]++);
1714 LN_STAT(tx_nospc[0]++);
1718 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1720 * Since the packet won't fit in the end of the transmit
1721 * heap, see if there is space at the beginning of the transmit
1722 * heap. If not, try again when there is space.
1724 LN_STAT(tx_orphaned++);
1725 slop += ri->ri_heapend - ri->ri_outptr;
1726 if (len + slop > ri->ri_outsize) {
1727 LN_STAT(tx_nospc[1]++);
1731 * Point to the beginning of the heap
1733 ri->ri_outptr = ri->ri_heap;
1734 LN_STAT(tx_adoptions++);
1738 * Initialize the descriptor (saving the buffer address,
1739 * buffer length, and mbuf) and write the packet out
1742 di = ri->ri_nextout;
1743 di->di_bufaddr = ri->ri_outptr;
1744 di->di_buflen = len + slop;
1746 bp = sc->le_membase + di->di_bufaddr;
1747 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1748 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1752 * Zero out the remainder if needed (< ETHERMIN).
1754 if (m->m_pkthdr.len < len)
1755 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1757 m = ifq_dequeue(&ifp->if_snd);
1760 * Finally, copy out the descriptor and tell the
1761 * LANCE to transmit!.
1763 desc.d_buflen = 0 - len;
1764 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1765 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1766 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1767 LN_PUTDESC(sc, &desc, di->di_addr);
1768 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1771 * Do our bookkeeping with our transmit heap.
1772 * (if we wrap, point back to the beginning).
1774 ri->ri_outptr += di->di_buflen;
1775 ri->ri_outsize -= di->di_buflen;
1776 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1777 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1779 if (ri->ri_outptr == ri->ri_heapend)
1780 ri->ri_outptr = ri->ri_heap;
1783 if (++ri->ri_nextout == ri->ri_last)
1784 ri->ri_nextout = ri->ri_first;
1785 LN_MINSTAT(low_txfree, ri->ri_free);
1788 ifp->if_flags |= IFF_OACTIVE;
1792 lance_tx_intr(struct le_softc *sc)
1794 lance_ring_t *ri = &sc->lance_txinfo;
1797 LN_STAT(tx_intrs++);
1798 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1801 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1802 if (desc.d_flag & LN_DFLAG_OWNER)
1805 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1806 sc->le_if.if_collisions++;
1807 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1808 LN_STAT(tx_deferred++);
1809 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1810 LN_STAT(tx_single_collisions++);
1811 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1812 LN_STAT(tx_multiple_collisions++);
1814 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1815 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1816 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1817 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1819 LN_STAT(tx_excessive_collisions++);
1820 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1822 if_printf(&sc->le_if, "lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1823 tdr, (tdr*99)/1000, (tdr*117)/1000);
1826 if (desc.d_status & LN_DSTS_TxBUFERROR)
1827 LN_STAT(tx_buferror++);
1828 sc->le_if.if_oerrors++;
1829 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1833 LN_STAT(tx_late_collisions++);
1837 m_freem(ri->ri_nextin->di_mbuf);
1838 ri->ri_nextin->di_mbuf = NULL;
1839 sc->le_if.if_opackets++;
1841 ri->ri_outsize += ri->ri_nextin->di_buflen;
1842 if (++ri->ri_nextin == ri->ri_last)
1843 ri->ri_nextin = ri->ri_first;
1844 sc->le_if.if_flags &= ~IFF_OACTIVE;
1847 if (ri->ri_free == ri->ri_max)
1848 LN_STAT(tx_emptied++);
1849 /* LN_STAT(tx_intr_descs[xmits]++); */
1850 LN_MAXSTAT(tx_intr_hidescs, xmits);