2 * Copyright (c) 2003-2011 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * pmap invalidation support code. Certain hardware requirements must
37 * be dealt with when manipulating page table entries and page directory
38 * entries within a pmap. In particular, we cannot safely manipulate
39 * page tables which are in active use by another cpu (even if it is
40 * running in userland) for two reasons: First, TLB writebacks will
41 * race against our own modifications and tests. Second, even if we
42 * were to use bus-locked instruction we can still screw up the
43 * target cpu's instruction pipeline due to Intel cpu errata.
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/vmmeter.h>
51 #include <sys/thread2.h>
52 #include <sys/sysctl.h>
56 #include <vm/vm_object.h>
58 #include <machine/cputypes.h>
59 #include <machine/md_var.h>
60 #include <machine/specialreg.h>
61 #include <machine/smp.h>
62 #include <machine/globaldata.h>
63 #include <machine/pmap.h>
64 #include <machine/pmap_inval.h>
65 #include <machine/clock.h>
68 #define LOOPRECOVER /* enable watchdog */
72 * Watchdog recovery interval, in seconds.
74 * The watchdog value is generous for two reasons. First, because the
75 * situation is not supposed to happen at all (but does), and second,
76 * because VMs could be very slow at handling IPIs.
78 #define LOOPRECOVER_TIMEOUT1 2 /* initial recovery */
79 #define LOOPRECOVER_TIMEOUT2 1 /* repeated recoveries */
81 #define MAX_INVAL_PAGES 128
83 struct pmap_inval_info {
88 enum { INVDONE, INVSTORE, INVCMPSET } mode;
100 typedef struct pmap_inval_info pmap_inval_info_t;
102 static pmap_inval_info_t invinfo[MAXCPU];
103 extern cpumask_t smp_invmask;
106 extern cpumask_t smp_in_mask;
108 extern cpumask_t smp_smurf_mask;
110 static long pmap_inval_bulk_count;
111 static int pmap_inval_watchdog_print; /* must always default off */
113 SYSCTL_LONG(_machdep, OID_AUTO, pmap_inval_bulk_count, CTLFLAG_RW,
114 &pmap_inval_bulk_count, 0, "");
115 SYSCTL_INT(_machdep, OID_AUTO, pmap_inval_watchdog_print, CTLFLAG_RW,
116 &pmap_inval_watchdog_print, 0, "");
119 pmap_inval_init(pmap_t pmap)
124 crit_enter_id("inval");
126 if (pmap != &kernel_pmap) {
128 olock = pmap->pm_active_lock;
130 nlock = olock | CPULOCK_EXCL;
131 if (olock != nlock &&
132 atomic_cmpset_int(&pmap->pm_active_lock,
139 atomic_add_acq_long(&pmap->pm_invgen, 1);
144 pmap_inval_done(pmap_t pmap)
146 if (pmap != &kernel_pmap) {
147 atomic_add_acq_long(&pmap->pm_invgen, 1);
148 atomic_clear_int(&pmap->pm_active_lock, CPULOCK_EXCL);
150 crit_exit_id("inval");
156 * Debugging and lost IPI recovery code.
161 loopwdog(struct pmap_inval_info *info)
166 if (info->tsc_target - tsc < 0 && tsc_frequency) {
167 info->tsc_target = tsc + (tsc_frequency * LOOPRECOVER_TIMEOUT2);
175 loopdebug(const char *msg, pmap_inval_info_t *info)
178 int cpu = mycpu->gd_cpuid;
181 * Don't kprintf() anything if the pmap inval watchdog gets hit.
182 * DRM can cause an occassional watchdog hit (at least with a 1/16
183 * second watchdog), and attempting to kprintf to the KVM frame buffer
184 * from Xinvltlb, which ignores critical sections, can implode the
187 if (pmap_inval_watchdog_print == 0)
192 atomic_add_long(&smp_smurf_mask.ary[0], 0);
194 kprintf("ipilost-%s! %d mode=%d m=%08jx d=%08jx "
204 , msg, cpu, info->mode,
208 , info->sigmask.ary[0]
214 , smp_smurf_mask.ary[0]
218 for (p = 0; p < ncpus; ++p)
219 kprintf(" %d", CPU_prvspace[p]->mdglobaldata.gd_xinvaltlb);
227 #define CHECKSIGMASK(info) _checksigmask(info, __FILE__, __LINE__)
231 _checksigmask(pmap_inval_info_t *info, const char *file, int line)
236 CPUMASK_ANDMASK(tmp, info->sigmask);
237 if (CPUMASK_CMPMASKNEQ(tmp, info->mask)) {
238 kprintf("\"%s\" line %d: bad sig/mask %08jx %08jx\n",
239 file, line, info->sigmask.ary[0], info->mask.ary[0]);
245 #define CHECKSIGMASK(info)
250 * Invalidate the specified va across all cpus associated with the pmap.
251 * If va == (vm_offset_t)-1, we invltlb() instead of invlpg(). The operation
252 * will be done fully synchronously with storing npte into *ptep and returning
255 * If ptep is NULL the operation will execute semi-synchronously.
256 * ptep must be NULL if npgs > 1
259 pmap_inval_smp(pmap_t pmap, vm_offset_t va, int npgs,
260 pt_entry_t *ptep, pt_entry_t npte)
262 globaldata_t gd = mycpu;
263 pmap_inval_info_t *info;
265 int cpu = gd->gd_cpuid;
267 unsigned long rflags;
270 * Initialize invalidation for pmap and enter critical section.
274 pmap_inval_init(pmap);
277 * Shortcut single-cpu case if possible.
279 if (CPUMASK_CMPMASKEQ(pmap->pm_active, gd->gd_cpumask)) {
281 * Convert to invltlb if there are too many pages to
284 if (npgs > MAX_INVAL_PAGES) {
286 va = (vm_offset_t)-1;
290 * Invalidate the specified pages, handle invltlb if requested.
295 opte = atomic_swap_long(ptep, npte);
298 if (va == (vm_offset_t)-1)
300 cpu_invlpg((void *)va);
303 if (va == (vm_offset_t)-1)
305 pmap_inval_done(pmap);
311 * We need a critical section to prevent getting preempted while
312 * we setup our command. A preemption might execute its own
313 * pmap_inval*() command and create confusion below.
315 * tsc_target is our watchdog timeout that will attempt to recover
316 * from a lost IPI. Set to 1/16 second for now.
318 info = &invinfo[cpu];
319 info->tsc_target = rdtsc() + (tsc_frequency * LOOPRECOVER_TIMEOUT1);
322 * We must wait for other cpus which may still be finishing up a
323 * prior operation that we requested.
325 * We do not have to disable interrupts here. An Xinvltlb can occur
326 * at any time (even within a critical section), but it will not
327 * act on our command until we set our done bits.
329 while (CPUMASK_TESTNZERO(info->done)) {
331 if (loopwdog(info)) {
333 loopdebug("A", info);
334 /* XXX recover from possible bug */
335 CPUMASK_ASSZERO(info->done);
340 KKASSERT(info->mode == INVDONE);
343 * Must set our cpu in the invalidation scan mask before
344 * any possibility of [partial] execution (remember, XINVLTLB
345 * can interrupt a critical section).
347 ATOMIC_CPUMASK_ORBIT(smp_invmask, cpu);
357 info->mode = INVSTORE;
359 tmpmask = pmap->pm_active; /* volatile (bits may be cleared) */
361 CPUMASK_ANDMASK(tmpmask, smp_active_mask);
364 * If ptep is NULL the operation can be semi-synchronous, which means
365 * we can improve performance by flagging and removing idle cpus
366 * (see the idleinvlclr function in mp_machdep.c).
368 * Typically kernel page table operation is semi-synchronous.
371 smp_smurf_idleinvlclr(&tmpmask);
372 CPUMASK_ORBIT(tmpmask, cpu);
373 info->mask = tmpmask;
376 * Command may start executing the moment 'done' is initialized,
377 * disable current cpu interrupt to prevent 'done' field from
378 * changing (other cpus can't clear done bits until the originating
379 * cpu clears its mask bit, but other cpus CAN start clearing their
383 info->sigmask = tmpmask;
387 rflags = read_rflags();
390 ATOMIC_CPUMASK_COPY(info->done, tmpmask);
391 /* execution can begin here due to races */
394 * Pass our copy of the done bits (so they don't change out from
395 * under us) to generate the Xinvltlb interrupt on the targets.
397 smp_invlpg(&tmpmask);
399 KKASSERT(info->mode == INVDONE);
402 * Target cpus will be in their loop exiting concurrently with our
403 * cleanup. They will not lose the bitmask they obtained before so
404 * we can safely clear this bit.
406 ATOMIC_CPUMASK_NANDBIT(smp_invmask, cpu);
407 write_rflags(rflags);
408 pmap_inval_done(pmap);
414 * API function - invalidate the pte at (va) and replace *ptep with npte
415 * atomically only if *ptep equals opte, across the pmap's active cpus.
417 * Returns 1 on success, 0 on failure (caller typically retries).
420 pmap_inval_smp_cmpset(pmap_t pmap, vm_offset_t va, pt_entry_t *ptep,
421 pt_entry_t opte, pt_entry_t npte)
423 globaldata_t gd = mycpu;
424 pmap_inval_info_t *info;
426 int cpu = gd->gd_cpuid;
428 unsigned long rflags;
431 * Initialize invalidation for pmap and enter critical section.
435 pmap_inval_init(pmap);
438 * Shortcut single-cpu case if possible.
440 if (CPUMASK_CMPMASKEQ(pmap->pm_active, gd->gd_cpumask)) {
441 if (atomic_cmpset_long(ptep, opte, npte)) {
442 if (va == (vm_offset_t)-1)
445 cpu_invlpg((void *)va);
446 pmap_inval_done(pmap);
449 pmap_inval_done(pmap);
455 * We need a critical section to prevent getting preempted while
456 * we setup our command. A preemption might execute its own
457 * pmap_inval*() command and create confusion below.
459 info = &invinfo[cpu];
460 info->tsc_target = rdtsc() + (tsc_frequency * LOOPRECOVER_TIMEOUT1);
463 * We must wait for other cpus which may still be finishing
464 * up a prior operation.
466 while (CPUMASK_TESTNZERO(info->done)) {
468 if (loopwdog(info)) {
470 loopdebug("B", info);
471 /* XXX recover from possible bug */
472 CPUMASK_ASSZERO(info->done);
477 KKASSERT(info->mode == INVDONE);
480 * Must set our cpu in the invalidation scan mask before
481 * any possibility of [partial] execution (remember, XINVLTLB
482 * can interrupt a critical section).
484 ATOMIC_CPUMASK_ORBIT(smp_invmask, cpu);
487 info->npgs = 1; /* unused */
494 info->mode = INVCMPSET;
497 tmpmask = pmap->pm_active; /* volatile */
499 CPUMASK_ANDMASK(tmpmask, smp_active_mask);
500 CPUMASK_ORBIT(tmpmask, cpu);
501 info->mask = tmpmask;
504 * Command may start executing the moment 'done' is initialized,
505 * disable current cpu interrupt to prevent 'done' field from
506 * changing (other cpus can't clear done bits until the originating
507 * cpu clears its mask bit).
510 info->sigmask = tmpmask;
514 rflags = read_rflags();
517 ATOMIC_CPUMASK_COPY(info->done, tmpmask);
520 * Pass our copy of the done bits (so they don't change out from
521 * under us) to generate the Xinvltlb interrupt on the targets.
523 smp_invlpg(&tmpmask);
524 success = info->success;
525 KKASSERT(info->mode == INVDONE);
527 ATOMIC_CPUMASK_NANDBIT(smp_invmask, cpu);
528 write_rflags(rflags);
529 pmap_inval_done(pmap);
535 pmap_inval_bulk_init(pmap_inval_bulk_t *bulk, struct pmap *pmap)
544 pmap_inval_bulk(pmap_inval_bulk_t *bulk, vm_offset_t va,
545 pt_entry_t *ptep, pt_entry_t npte)
550 * Degenerate case, localized or we don't care (e.g. because we
551 * are jacking the entire page table) or the pmap is not in-use
552 * by anyone. No invalidations are done on any cpu.
555 pte = atomic_swap_long(ptep, npte);
560 * If it isn't the kernel pmap we execute the operation synchronously
561 * on all cpus belonging to the pmap, which avoids concurrency bugs in
562 * the hw related to changing pte's out from under threads.
564 * Eventually I would like to implement streaming pmap invalidation
565 * for user pmaps to reduce mmap/munmap overheads for heavily-loaded
568 if (bulk->pmap != &kernel_pmap) {
569 pte = pmap_inval_smp(bulk->pmap, va, 1, ptep, npte);
574 * This is the kernel_pmap. All unmap operations presume that there
575 * are no other cpus accessing the addresses in question. Implement
576 * the bulking algorithm. collect the required information and
577 * synchronize once at the end.
579 pte = atomic_swap_long(ptep, npte);
580 if (va == (vm_offset_t)-1) {
582 } else if (bulk->va_beg == bulk->va_end) {
584 bulk->va_end = va + PAGE_SIZE;
585 } else if (va == bulk->va_end) {
586 bulk->va_end = va + PAGE_SIZE;
588 bulk->va_beg = (vm_offset_t)-1;
591 pmap_inval_bulk_flush(bulk);
593 if (va == (vm_offset_t)-1) {
598 bulk->va_end = va + PAGE_SIZE;
608 pmap_inval_bulk_flush(pmap_inval_bulk_t *bulk)
613 pmap_inval_bulk_count += (bulk->count - 1);
614 if (bulk->va_beg != bulk->va_end) {
615 if (bulk->va_beg == (vm_offset_t)-1) {
616 pmap_inval_smp(bulk->pmap, bulk->va_beg, 1, NULL, 0);
620 n = (bulk->va_end - bulk->va_beg) >> PAGE_SHIFT;
621 pmap_inval_smp(bulk->pmap, bulk->va_beg, n, NULL, 0);
630 * Called with a critical section held and interrupts enabled.
633 pmap_inval_intr(cpumask_t *cpumaskp, int toolong)
635 globaldata_t gd = mycpu;
636 pmap_inval_info_t *info;
642 * Check all cpus for invalidations we may need to service.
648 while (CPUMASK_TESTNZERO(cpumask)) {
649 int n = BSFCPUMASK(cpumask);
652 KKASSERT(n >= 0 && n < MAXCPU);
655 CPUMASK_NANDBIT(cpumask, n);
659 * Due to interrupts/races we can catch a new operation
660 * in an older interrupt. A fence is needed once we detect
661 * the (not) done bit.
663 if (!CPUMASK_TESTBIT(info->done, cpu))
668 kprintf("pminvl %d->%d %08jx %08jx mode=%d\n",
669 cpu, n, info->done.ary[0], info->mask.ary[0],
675 * info->mask and info->done always contain the originating
676 * cpu until the originator is done. Targets may still be
677 * present in info->done after the originator is done (they
678 * will be finishing up their loops).
680 * Clear info->mask bits on other cpus to indicate that they
681 * have quiesced (entered the loop). Once the other mask bits
682 * are clear we can execute the operation on the original,
683 * then clear the mask and done bits on the originator. The
684 * targets will then finish up their side and clear their
687 * The command is considered 100% done when all done bits have
692 * Command state machine for 'other' cpus.
694 if (CPUMASK_TESTBIT(info->mask, cpu)) {
696 * Other cpu indicate to originator that they
699 ATOMIC_CPUMASK_NANDBIT(info->mask, cpu);
701 } else if (info->ptep &&
702 CPUMASK_TESTBIT(info->mask, n)) {
704 * Other cpu must wait for the originator (n)
705 * to complete its command if ptep is not NULL.
710 * Other cpu detects that the originator has
711 * completed its command, or there was no
714 * Now that the page table entry has changed,
715 * we can follow up with our own invalidation.
717 vm_offset_t va = info->va;
720 if (va == (vm_offset_t)-1 ||
721 info->npgs > MAX_INVAL_PAGES) {
724 for (npgs = info->npgs; npgs; --npgs) {
725 cpu_invlpg((void *)va);
729 ATOMIC_CPUMASK_NANDBIT(info->done, cpu);
730 /* info invalid now */
731 /* loopme left alone */
733 } else if (CPUMASK_TESTBIT(info->mask, cpu)) {
735 * Originator is waiting for other cpus
737 if (CPUMASK_CMPMASKNEQ(info->mask, gd->gd_cpumask)) {
739 * Originator waits for other cpus to enter
740 * their loop (aka quiesce).
742 * If this bugs out the IPI may have been lost,
743 * try to reissue by resetting our own
744 * reentrancy bit and clearing the smurf mask
745 * for the cpus that did not respond, then
750 if (loopwdog(info)) {
752 loopdebug("C", info);
753 /* XXX recover from possible bug */
754 mdcpu->gd_xinvaltlb = 0;
755 ATOMIC_CPUMASK_NANDMASK(smp_smurf_mask,
758 smp_invlpg(&smp_active_mask);
761 * Force outer-loop retest of Xinvltlb
762 * requests (see mp_machdep.c).
764 mdcpu->gd_xinvaltlb = 2;
770 * Originator executes operation and clears
771 * mask to allow other cpus to finish.
773 KKASSERT(info->mode != INVDONE);
774 if (info->mode == INVSTORE) {
776 info->opte = atomic_swap_long(info->ptep, info->npte);
778 ATOMIC_CPUMASK_NANDBIT(info->mask, cpu);
781 if (atomic_cmpset_long(info->ptep,
782 info->opte, info->npte)) {
788 ATOMIC_CPUMASK_NANDBIT(info->mask, cpu);
795 * Originator does not have to wait for the other
796 * cpus to finish. It clears its done bit. A new
797 * command will not be initiated by the originator
798 * until the other cpus have cleared their done bits
801 vm_offset_t va = info->va;
804 if (va == (vm_offset_t)-1 ||
805 info->npgs > MAX_INVAL_PAGES) {
808 for (npgs = info->npgs; npgs; --npgs) {
809 cpu_invlpg((void *)va);
814 /* leave loopme alone */
815 /* other cpus may still be finishing up */
816 /* can't race originator since that's us */
817 info->mode = INVDONE;
818 ATOMIC_CPUMASK_NANDBIT(info->done, cpu);