Remove spl*() calls from the bus/ infrastructure, replacing them with
[dragonfly.git] / sys / bus / firewire / fwohci.c
1 /*
2  * Copyright (c) 2003 Hidetoshi Shimokawa
3  * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the acknowledgement as bellow:
16  *
17  *    This product includes software developed by K. Kobayashi and H. Shimokawa
18  *
19  * 4. The name of the author may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32  * POSSIBILITY OF SUCH DAMAGE.
33  * 
34  * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.72 2004/01/22 14:41:17 simokawa Exp $
35  * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.1.2.19 2003/05/01 06:24:37 simokawa Exp $
36  * $DragonFly: src/sys/bus/firewire/fwohci.c,v 1.9 2005/06/02 20:40:33 dillon Exp $
37  */
38
39 #define ATRQ_CH 0
40 #define ATRS_CH 1
41 #define ARRQ_CH 2
42 #define ARRS_CH 3
43 #define ITX_CH 4
44 #define IRX_CH 0x24
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/mbuf.h>
49 #include <sys/malloc.h>
50 #include <sys/sockio.h>
51 #include <sys/bus.h>
52 #include <sys/kernel.h>
53 #include <sys/conf.h>
54 #include <sys/endian.h>
55 #include <sys/thread2.h>
56
57 #include <machine/bus.h>
58
59 #if defined(__DragonFly__) || __FreeBSD_version < 500000
60 #include <machine/clock.h>              /* for DELAY() */
61 #endif
62
63 #ifdef __DragonFly__
64 #include "firewire.h"
65 #include "firewirereg.h"
66 #include "fwdma.h"
67 #include "fwohcireg.h"
68 #include "fwohcivar.h"
69 #include "firewire_phy.h"
70 #else
71 #include <dev/firewire/firewire.h>
72 #include <dev/firewire/firewirereg.h>
73 #include <dev/firewire/fwdma.h>
74 #include <dev/firewire/fwohcireg.h>
75 #include <dev/firewire/fwohcivar.h>
76 #include <dev/firewire/firewire_phy.h>
77 #endif
78
79 #undef OHCI_DEBUG
80
81 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
82                 "STOR","LOAD","NOP ","STOP",};
83
84 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
85                 "UNDEF","REG","SYS","DEV"};
86 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
87 char fwohcicode[32][0x20]={
88         "No stat","Undef","long","miss Ack err",
89         "underrun","overrun","desc err", "data read err",
90         "data write err","bus reset","timeout","tcode err",
91         "Undef","Undef","unknown event","flushed",
92         "Undef","ack complete","ack pend","Undef",
93         "ack busy_X","ack busy_A","ack busy_B","Undef",
94         "Undef","Undef","Undef","ack tardy",
95         "Undef","ack data_err","ack type_err",""};
96
97 #define MAX_SPEED 3
98 extern char *linkspeed[];
99 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
100
101 static struct tcode_info tinfo[] = {
102 /*              hdr_len block   flag*/
103 /* 0 WREQQ  */ {16,     FWTI_REQ | FWTI_TLABEL},
104 /* 1 WREQB  */ {16,     FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
105 /* 2 WRES   */ {12,     FWTI_RES},
106 /* 3 XXX    */ { 0,     0},
107 /* 4 RREQQ  */ {12,     FWTI_REQ | FWTI_TLABEL},
108 /* 5 RREQB  */ {16,     FWTI_REQ | FWTI_TLABEL},
109 /* 6 RRESQ  */ {16,     FWTI_RES},
110 /* 7 RRESB  */ {16,     FWTI_RES | FWTI_BLOCK_ASY},
111 /* 8 CYCS   */ { 0,     0},
112 /* 9 LREQ   */ {16,     FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
113 /* a STREAM */ { 4,     FWTI_REQ | FWTI_BLOCK_STR},
114 /* b LRES   */ {16,     FWTI_RES | FWTI_BLOCK_ASY},
115 /* c XXX    */ { 0,     0},
116 /* d XXX    */ { 0,     0},
117 /* e PHY    */ {12,     FWTI_REQ},
118 /* f XXX    */ { 0,     0}
119 };
120
121 #define OHCI_WRITE_SIGMASK 0xffff0000
122 #define OHCI_READ_SIGMASK 0xffff0000
123
124 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
125 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
126
127 static void fwohci_ibr (struct firewire_comm *);
128 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
129 static void fwohci_db_free (struct fwohci_dbch *);
130 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
131 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
132 static void fwohci_start_atq (struct firewire_comm *);
133 static void fwohci_start_ats (struct firewire_comm *);
134 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
135 static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t);
136 static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t);
137 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
138 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
139 static int fwohci_irx_enable (struct firewire_comm *, int);
140 static int fwohci_irx_disable (struct firewire_comm *, int);
141 #if BYTE_ORDER == BIG_ENDIAN
142 static void fwohci_irx_post (struct firewire_comm *, u_int32_t *);
143 #endif
144 static int fwohci_itxbuf_enable (struct firewire_comm *, int);
145 static int fwohci_itx_disable (struct firewire_comm *, int);
146 static void fwohci_timeout (void *);
147 static void fwohci_set_intr (struct firewire_comm *, int);
148
149 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
150 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
151 static void     dump_db (struct fwohci_softc *, u_int32_t);
152 static void     print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t);
153 static void     dump_dma (struct fwohci_softc *, u_int32_t);
154 static u_int32_t fwohci_cyctimer (struct firewire_comm *);
155 static void fwohci_rbuf_update (struct fwohci_softc *, int);
156 static void fwohci_tbuf_update (struct fwohci_softc *, int);
157 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
158 #if FWOHCI_TASKQUEUE
159 static void fwohci_complete(void *, int);
160 #endif
161
162 /*
163  * memory allocated for DMA programs
164  */
165 #define DMA_PROG_ALLOC          (8 * PAGE_SIZE)
166
167 #define NDB FWMAXQUEUE
168
169 #define OHCI_VERSION            0x00
170 #define OHCI_ATRETRY            0x08
171 #define OHCI_CROMHDR            0x18
172 #define OHCI_BUS_OPT            0x20
173 #define OHCI_BUSIRMC            (1 << 31)
174 #define OHCI_BUSCMC             (1 << 30)
175 #define OHCI_BUSISC             (1 << 29)
176 #define OHCI_BUSBMC             (1 << 28)
177 #define OHCI_BUSPMC             (1 << 27)
178 #define OHCI_BUSFNC             OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
179                                 OHCI_BUSBMC | OHCI_BUSPMC
180
181 #define OHCI_EUID_HI            0x24
182 #define OHCI_EUID_LO            0x28
183
184 #define OHCI_CROMPTR            0x34
185 #define OHCI_HCCCTL             0x50
186 #define OHCI_HCCCTLCLR          0x54
187 #define OHCI_AREQHI             0x100
188 #define OHCI_AREQHICLR          0x104
189 #define OHCI_AREQLO             0x108
190 #define OHCI_AREQLOCLR          0x10c
191 #define OHCI_PREQHI             0x110
192 #define OHCI_PREQHICLR          0x114
193 #define OHCI_PREQLO             0x118
194 #define OHCI_PREQLOCLR          0x11c
195 #define OHCI_PREQUPPER          0x120
196
197 #define OHCI_SID_BUF            0x64
198 #define OHCI_SID_CNT            0x68
199 #define OHCI_SID_ERR            (1 << 31)
200 #define OHCI_SID_CNT_MASK       0xffc
201
202 #define OHCI_IT_STAT            0x90
203 #define OHCI_IT_STATCLR         0x94
204 #define OHCI_IT_MASK            0x98
205 #define OHCI_IT_MASKCLR         0x9c
206
207 #define OHCI_IR_STAT            0xa0
208 #define OHCI_IR_STATCLR         0xa4
209 #define OHCI_IR_MASK            0xa8
210 #define OHCI_IR_MASKCLR         0xac
211
212 #define OHCI_LNKCTL             0xe0
213 #define OHCI_LNKCTLCLR          0xe4
214
215 #define OHCI_PHYACCESS          0xec
216 #define OHCI_CYCLETIMER         0xf0
217
218 #define OHCI_DMACTL(off)        (off)
219 #define OHCI_DMACTLCLR(off)     (off + 4)
220 #define OHCI_DMACMD(off)        (off + 0xc)
221 #define OHCI_DMAMATCH(off)      (off + 0x10)
222
223 #define OHCI_ATQOFF             0x180
224 #define OHCI_ATQCTL             OHCI_ATQOFF
225 #define OHCI_ATQCTLCLR          (OHCI_ATQOFF + 4)
226 #define OHCI_ATQCMD             (OHCI_ATQOFF + 0xc)
227 #define OHCI_ATQMATCH           (OHCI_ATQOFF + 0x10)
228
229 #define OHCI_ATSOFF             0x1a0
230 #define OHCI_ATSCTL             OHCI_ATSOFF
231 #define OHCI_ATSCTLCLR          (OHCI_ATSOFF + 4)
232 #define OHCI_ATSCMD             (OHCI_ATSOFF + 0xc)
233 #define OHCI_ATSMATCH           (OHCI_ATSOFF + 0x10)
234
235 #define OHCI_ARQOFF             0x1c0
236 #define OHCI_ARQCTL             OHCI_ARQOFF
237 #define OHCI_ARQCTLCLR          (OHCI_ARQOFF + 4)
238 #define OHCI_ARQCMD             (OHCI_ARQOFF + 0xc)
239 #define OHCI_ARQMATCH           (OHCI_ARQOFF + 0x10)
240
241 #define OHCI_ARSOFF             0x1e0
242 #define OHCI_ARSCTL             OHCI_ARSOFF
243 #define OHCI_ARSCTLCLR          (OHCI_ARSOFF + 4)
244 #define OHCI_ARSCMD             (OHCI_ARSOFF + 0xc)
245 #define OHCI_ARSMATCH           (OHCI_ARSOFF + 0x10)
246
247 #define OHCI_ITOFF(CH)          (0x200 + 0x10 * (CH))
248 #define OHCI_ITCTL(CH)          (OHCI_ITOFF(CH))
249 #define OHCI_ITCTLCLR(CH)       (OHCI_ITOFF(CH) + 4)
250 #define OHCI_ITCMD(CH)          (OHCI_ITOFF(CH) + 0xc)
251
252 #define OHCI_IROFF(CH)          (0x400 + 0x20 * (CH))
253 #define OHCI_IRCTL(CH)          (OHCI_IROFF(CH))
254 #define OHCI_IRCTLCLR(CH)       (OHCI_IROFF(CH) + 4)
255 #define OHCI_IRCMD(CH)          (OHCI_IROFF(CH) + 0xc)
256 #define OHCI_IRMATCH(CH)        (OHCI_IROFF(CH) + 0x10)
257
258 d_ioctl_t fwohci_ioctl;
259
260 /*
261  * Communication with PHY device
262  */
263 static u_int32_t
264 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
265 {
266         u_int32_t fun;
267
268         addr &= 0xf;
269         data &= 0xff;
270
271         fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
272         OWRITE(sc, OHCI_PHYACCESS, fun);
273         DELAY(100);
274
275         return(fwphy_rddata( sc, addr));
276 }
277
278 static u_int32_t
279 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
280 {
281         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
282         int i;
283         u_int32_t bm;
284
285 #define OHCI_CSR_DATA   0x0c
286 #define OHCI_CSR_COMP   0x10
287 #define OHCI_CSR_CONT   0x14
288 #define OHCI_BUS_MANAGER_ID     0
289
290         OWRITE(sc, OHCI_CSR_DATA, node);
291         OWRITE(sc, OHCI_CSR_COMP, 0x3f);
292         OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
293         for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
294                 DELAY(10);
295         bm = OREAD(sc, OHCI_CSR_DATA);
296         if((bm & 0x3f) == 0x3f)
297                 bm = node;
298         if (bootverbose)
299                 device_printf(sc->fc.dev,
300                         "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
301
302         return(bm);
303 }
304
305 static u_int32_t
306 fwphy_rddata(struct fwohci_softc *sc,  u_int addr)
307 {
308         u_int32_t fun, stat;
309         u_int i, retry = 0;
310
311         addr &= 0xf;
312 #define MAX_RETRY 100
313 again:
314         OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
315         fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
316         OWRITE(sc, OHCI_PHYACCESS, fun);
317         for ( i = 0 ; i < MAX_RETRY ; i ++ ){
318                 fun = OREAD(sc, OHCI_PHYACCESS);
319                 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
320                         break;
321                 DELAY(100);
322         }
323         if(i >= MAX_RETRY) {
324                 if (bootverbose)
325                         device_printf(sc->fc.dev, "phy read failed(1).\n");
326                 if (++retry < MAX_RETRY) {
327                         DELAY(100);
328                         goto again;
329                 }
330         }
331         /* Make sure that SCLK is started */
332         stat = OREAD(sc, FWOHCI_INTSTAT);
333         if ((stat & OHCI_INT_REG_FAIL) != 0 ||
334                         ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
335                 if (bootverbose)
336                         device_printf(sc->fc.dev, "phy read failed(2).\n");
337                 if (++retry < MAX_RETRY) {
338                         DELAY(100);
339                         goto again;
340                 }
341         }
342         if (bootverbose || retry >= MAX_RETRY)
343                 device_printf(sc->fc.dev, 
344                     "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
345 #undef MAX_RETRY
346         return((fun >> PHYDEV_RDDATA )& 0xff);
347 }
348 /* Device specific ioctl. */
349 int
350 fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
351 {
352         struct firewire_softc *sc;
353         struct fwohci_softc *fc;
354         int unit = DEV2UNIT(dev);
355         int err = 0;
356         struct fw_reg_req_t *reg  = (struct fw_reg_req_t *) data;
357         u_int32_t *dmach = (u_int32_t *) data;
358
359         sc = devclass_get_softc(firewire_devclass, unit);
360         if(sc == NULL){
361                 return(EINVAL);
362         }
363         fc = (struct fwohci_softc *)sc->fc;
364
365         if (!data)
366                 return(EINVAL);
367
368         switch (cmd) {
369         case FWOHCI_WRREG:
370 #define OHCI_MAX_REG 0x800
371                 if(reg->addr <= OHCI_MAX_REG){
372                         OWRITE(fc, reg->addr, reg->data);
373                         reg->data = OREAD(fc, reg->addr);
374                 }else{
375                         err = EINVAL;
376                 }
377                 break;
378         case FWOHCI_RDREG:
379                 if(reg->addr <= OHCI_MAX_REG){
380                         reg->data = OREAD(fc, reg->addr);
381                 }else{
382                         err = EINVAL;
383                 }
384                 break;
385 /* Read DMA descriptors for debug  */
386         case DUMPDMA:
387                 if(*dmach <= OHCI_MAX_DMA_CH ){
388                         dump_dma(fc, *dmach);
389                         dump_db(fc, *dmach);
390                 }else{
391                         err = EINVAL;
392                 }
393                 break;
394 /* Read/Write Phy registers */
395 #define OHCI_MAX_PHY_REG 0xf
396         case FWOHCI_RDPHYREG:
397                 if (reg->addr <= OHCI_MAX_PHY_REG)
398                         reg->data = fwphy_rddata(fc, reg->addr);
399                 else
400                         err = EINVAL;
401                 break;
402         case FWOHCI_WRPHYREG:
403                 if (reg->addr <= OHCI_MAX_PHY_REG)
404                         reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
405                 else
406                         err = EINVAL;
407                 break;
408         default:
409                 err = EINVAL;
410                 break;
411         }
412         return err;
413 }
414
415 static int
416 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
417 {
418         u_int32_t reg, reg2;
419         int e1394a = 1;
420 /*
421  * probe PHY parameters
422  * 0. to prove PHY version, whether compliance of 1394a.
423  * 1. to probe maximum speed supported by the PHY and 
424  *    number of port supported by core-logic.
425  *    It is not actually available port on your PC .
426  */
427         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
428         reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
429
430         if((reg >> 5) != 7 ){
431                 sc->fc.mode &= ~FWPHYASYST;
432                 sc->fc.nport = reg & FW_PHY_NP;
433                 sc->fc.speed = reg & FW_PHY_SPD >> 6;
434                 if (sc->fc.speed > MAX_SPEED) {
435                         device_printf(dev, "invalid speed %d (fixed to %d).\n",
436                                 sc->fc.speed, MAX_SPEED);
437                         sc->fc.speed = MAX_SPEED;
438                 }
439                 device_printf(dev,
440                         "Phy 1394 only %s, %d ports.\n",
441                         linkspeed[sc->fc.speed], sc->fc.nport);
442         }else{
443                 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
444                 sc->fc.mode |= FWPHYASYST;
445                 sc->fc.nport = reg & FW_PHY_NP;
446                 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
447                 if (sc->fc.speed > MAX_SPEED) {
448                         device_printf(dev, "invalid speed %d (fixed to %d).\n",
449                                 sc->fc.speed, MAX_SPEED);
450                         sc->fc.speed = MAX_SPEED;
451                 }
452                 device_printf(dev,
453                         "Phy 1394a available %s, %d ports.\n",
454                         linkspeed[sc->fc.speed], sc->fc.nport);
455
456                 /* check programPhyEnable */
457                 reg2 = fwphy_rddata(sc, 5);
458 #if 0
459                 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
460 #else   /* XXX force to enable 1394a */
461                 if (e1394a) {
462 #endif
463                         if (bootverbose)
464                                 device_printf(dev,
465                                         "Enable 1394a Enhancements\n");
466                         /* enable EAA EMC */
467                         reg2 |= 0x03;
468                         /* set aPhyEnhanceEnable */
469                         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
470                         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
471                 } else {
472                         /* for safe */
473                         reg2 &= ~0x83;
474                 }
475                 reg2 = fwphy_wrdata(sc, 5, reg2);
476         }
477
478         reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
479         if((reg >> 5) == 7 ){
480                 reg = fwphy_rddata(sc, 4);
481                 reg |= 1 << 6;
482                 fwphy_wrdata(sc, 4, reg);
483                 reg = fwphy_rddata(sc, 4);
484         }
485         return 0;
486 }
487
488
489 void
490 fwohci_reset(struct fwohci_softc *sc, device_t dev)
491 {
492         int i, max_rec, speed;
493         u_int32_t reg, reg2;
494         struct fwohcidb_tr *db_tr;
495
496         /* Disable interrupt */ 
497         OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
498
499         /* Now stopping all DMA channel */
500         OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
501         OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
502         OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
503         OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
504
505         OWRITE(sc,  OHCI_IR_MASKCLR, ~0);
506         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
507                 OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
508                 OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
509         }
510
511         /* FLUSH FIFO and reset Transmitter/Reciever */
512         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
513         if (bootverbose)
514                 device_printf(dev, "resetting OHCI...");
515         i = 0;
516         while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
517                 if (i++ > 100) break;
518                 DELAY(1000);
519         }
520         if (bootverbose)
521                 printf("done (loop=%d)\n", i);
522
523         /* Probe phy */
524         fwohci_probe_phy(sc, dev);
525
526         /* Probe link */
527         reg = OREAD(sc,  OHCI_BUS_OPT);
528         reg2 = reg | OHCI_BUSFNC;
529         max_rec = (reg & 0x0000f000) >> 12;
530         speed = (reg & 0x00000007);
531         device_printf(dev, "Link %s, max_rec %d bytes.\n",
532                         linkspeed[speed], MAXREC(max_rec));
533         /* XXX fix max_rec */
534         sc->fc.maxrec = sc->fc.speed + 8;
535         if (max_rec != sc->fc.maxrec) {
536                 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
537                 device_printf(dev, "max_rec %d -> %d\n",
538                                 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
539         }
540         if (bootverbose)
541                 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
542         OWRITE(sc,  OHCI_BUS_OPT, reg2);
543
544         /* Initialize registers */
545         OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
546         OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
547         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
548         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
549         OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
550         OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
551
552         /* Enable link */
553         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
554
555         /* Force to start async RX DMA */
556         sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
557         sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
558         fwohci_rx_enable(sc, &sc->arrq);
559         fwohci_rx_enable(sc, &sc->arrs);
560
561         /* Initialize async TX */
562         OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
563         OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
564
565         /* AT Retries */
566         OWRITE(sc, FWOHCI_RETRY,
567                 /* CycleLimit   PhyRespRetries ATRespRetries ATReqRetries */
568                 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
569
570         sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
571         sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
572         sc->atrq.bottom = sc->atrq.top;
573         sc->atrs.bottom = sc->atrs.top;
574
575         for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
576                                 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
577                 db_tr->xfer = NULL;
578         }
579         for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
580                                 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
581                 db_tr->xfer = NULL;
582         }
583
584
585         /* Enable interrupt */
586         OWRITE(sc, FWOHCI_INTMASK,
587                         OHCI_INT_ERR  | OHCI_INT_PHY_SID 
588                         | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 
589                         | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
590                         | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
591         fwohci_set_intr(&sc->fc, 1);
592
593 }
594
595 int
596 fwohci_init(struct fwohci_softc *sc, device_t dev)
597 {
598         int i, mver;
599         u_int32_t reg;
600         u_int8_t ui[8];
601
602 #if FWOHCI_TASKQUEUE
603         TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
604 #endif
605
606 /* OHCI version */
607         reg = OREAD(sc, OHCI_VERSION);
608         mver = (reg >> 16) & 0xff;
609         device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
610                         mver, reg & 0xff, (reg>>24) & 1);
611         if (mver < 1 || mver > 9) {
612                 device_printf(dev, "invalid OHCI version\n");
613                 return (ENXIO);
614         }
615
616 /* Available Isochrounous DMA channel probe */
617         OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
618         OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
619         reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
620         OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
621         OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
622         for (i = 0; i < 0x20; i++)
623                 if ((reg & (1 << i)) == 0)
624                         break;
625         sc->fc.nisodma = i;
626         device_printf(dev, "No. of Isochronous channel is %d.\n", i);
627         if (i == 0)
628                 return (ENXIO);
629
630         sc->fc.arq = &sc->arrq.xferq;
631         sc->fc.ars = &sc->arrs.xferq;
632         sc->fc.atq = &sc->atrq.xferq;
633         sc->fc.ats = &sc->atrs.xferq;
634
635         sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
636         sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
637         sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
638         sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
639
640         sc->arrq.xferq.start = NULL;
641         sc->arrs.xferq.start = NULL;
642         sc->atrq.xferq.start = fwohci_start_atq;
643         sc->atrs.xferq.start = fwohci_start_ats;
644
645         sc->arrq.xferq.buf = NULL;
646         sc->arrs.xferq.buf = NULL;
647         sc->atrq.xferq.buf = NULL;
648         sc->atrs.xferq.buf = NULL;
649
650         sc->arrq.xferq.dmach = -1;
651         sc->arrs.xferq.dmach = -1;
652         sc->atrq.xferq.dmach = -1;
653         sc->atrs.xferq.dmach = -1;
654
655         sc->arrq.ndesc = 1;
656         sc->arrs.ndesc = 1;
657         sc->atrq.ndesc = 8;     /* equal to maximum of mbuf chains */
658         sc->atrs.ndesc = 2;
659
660         sc->arrq.ndb = NDB;
661         sc->arrs.ndb = NDB / 2;
662         sc->atrq.ndb = NDB;
663         sc->atrs.ndb = NDB / 2;
664
665         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
666                 sc->fc.it[i] = &sc->it[i].xferq;
667                 sc->fc.ir[i] = &sc->ir[i].xferq;
668                 sc->it[i].xferq.dmach = i;
669                 sc->ir[i].xferq.dmach = i;
670                 sc->it[i].ndb = 0;
671                 sc->ir[i].ndb = 0;
672         }
673
674         sc->fc.tcode = tinfo;
675         sc->fc.dev = dev;
676
677         sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
678                                                 &sc->crom_dma, BUS_DMA_WAITOK);
679         if(sc->fc.config_rom == NULL){
680                 device_printf(dev, "config_rom alloc failed.");
681                 return ENOMEM;
682         }
683
684 #if 0
685         bzero(&sc->fc.config_rom[0], CROMSIZE);
686         sc->fc.config_rom[1] = 0x31333934;
687         sc->fc.config_rom[2] = 0xf000a002;
688         sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
689         sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
690         sc->fc.config_rom[5] = 0;
691         sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
692
693         sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
694 #endif
695
696
697 /* SID recieve buffer must allign 2^11 */
698 #define OHCI_SIDSIZE    (1 << 11)
699         sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
700                                                 &sc->sid_dma, BUS_DMA_WAITOK);
701         if (sc->sid_buf == NULL) {
702                 device_printf(dev, "sid_buf alloc failed.");
703                 return ENOMEM;
704         }
705
706         fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t),
707                                         &sc->dummy_dma, BUS_DMA_WAITOK);
708
709         if (sc->dummy_dma.v_addr == NULL) {
710                 device_printf(dev, "dummy_dma alloc failed.");
711                 return ENOMEM;
712         }
713
714         fwohci_db_init(sc, &sc->arrq);
715         if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
716                 return ENOMEM;
717
718         fwohci_db_init(sc, &sc->arrs);
719         if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
720                 return ENOMEM;
721
722         fwohci_db_init(sc, &sc->atrq);
723         if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
724                 return ENOMEM;
725
726         fwohci_db_init(sc, &sc->atrs);
727         if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
728                 return ENOMEM;
729
730         sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
731         sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
732         for( i = 0 ; i < 8 ; i ++)
733                 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
734         device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
735                 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
736
737         sc->fc.ioctl = fwohci_ioctl;
738         sc->fc.cyctimer = fwohci_cyctimer;
739         sc->fc.set_bmr = fwohci_set_bus_manager;
740         sc->fc.ibr = fwohci_ibr;
741         sc->fc.irx_enable = fwohci_irx_enable;
742         sc->fc.irx_disable = fwohci_irx_disable;
743
744         sc->fc.itx_enable = fwohci_itxbuf_enable;
745         sc->fc.itx_disable = fwohci_itx_disable;
746 #if BYTE_ORDER == BIG_ENDIAN
747         sc->fc.irx_post = fwohci_irx_post;
748 #else
749         sc->fc.irx_post = NULL;
750 #endif
751         sc->fc.itx_post = NULL;
752         sc->fc.timeout = fwohci_timeout;
753         sc->fc.poll = fwohci_poll;
754         sc->fc.set_intr = fwohci_set_intr;
755
756         sc->intmask = sc->irstat = sc->itstat = 0;
757
758         fw_init(&sc->fc);
759         fwohci_reset(sc, dev);
760
761         return 0;
762 }
763
764 void
765 fwohci_timeout(void *arg)
766 {
767         struct fwohci_softc *sc;
768
769         sc = (struct fwohci_softc *)arg;
770 }
771
772 u_int32_t
773 fwohci_cyctimer(struct firewire_comm *fc)
774 {
775         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
776         return(OREAD(sc, OHCI_CYCLETIMER));
777 }
778
779 int
780 fwohci_detach(struct fwohci_softc *sc, device_t dev)
781 {
782         int i;
783
784         if (sc->sid_buf != NULL)
785                 fwdma_free(&sc->fc, &sc->sid_dma);
786         if (sc->fc.config_rom != NULL)
787                 fwdma_free(&sc->fc, &sc->crom_dma);
788
789         fwohci_db_free(&sc->arrq);
790         fwohci_db_free(&sc->arrs);
791
792         fwohci_db_free(&sc->atrq);
793         fwohci_db_free(&sc->atrs);
794
795         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
796                 fwohci_db_free(&sc->it[i]);
797                 fwohci_db_free(&sc->ir[i]);
798         }
799
800         return 0;
801 }
802
803 #define LAST_DB(dbtr, db) do {                                          \
804         struct fwohcidb_tr *_dbtr = (dbtr);                             \
805         int _cnt = _dbtr->dbcnt;                                        \
806         db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0];                   \
807 } while (0)
808         
809 static void
810 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
811 {
812         struct fwohcidb_tr *db_tr;
813         struct fwohcidb *db;
814         bus_dma_segment_t *s;
815         int i;
816
817         db_tr = (struct fwohcidb_tr *)arg;
818         db = &db_tr->db[db_tr->dbcnt];
819         if (error) {
820                 if (firewire_debug || error != EFBIG)
821                         printf("fwohci_execute_db: error=%d\n", error);
822                 return;
823         }
824         for (i = 0; i < nseg; i++) {
825                 s = &segs[i];
826                 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
827                 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
828                 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
829                 db++;
830                 db_tr->dbcnt++;
831         }
832 }
833
834 static void
835 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
836                                                 bus_size_t size, int error)
837 {
838         fwohci_execute_db(arg, segs, nseg, error);
839 }
840
841 static void
842 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
843 {
844         int i;
845         int tcode, hdr_len, pl_off;
846         int fsegment = -1;
847         u_int32_t off;
848         struct fw_xfer *xfer;
849         struct fw_pkt *fp;
850         struct fwohci_txpkthdr *ohcifp;
851         struct fwohcidb_tr *db_tr;
852         struct fwohcidb *db;
853         u_int32_t *ld;
854         struct tcode_info *info;
855         static int maxdesc=0;
856
857         if(&sc->atrq == dbch){
858                 off = OHCI_ATQOFF;
859         }else if(&sc->atrs == dbch){
860                 off = OHCI_ATSOFF;
861         }else{
862                 return;
863         }
864
865         if (dbch->flags & FWOHCI_DBCH_FULL)
866                 return;
867
868         crit_enter();
869         db_tr = dbch->top;
870 txloop:
871         xfer = STAILQ_FIRST(&dbch->xferq.q);
872         if(xfer == NULL){
873                 goto kick;
874         }
875         if(dbch->xferq.queued == 0 ){
876                 device_printf(sc->fc.dev, "TX queue empty\n");
877         }
878         STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
879         db_tr->xfer = xfer;
880         xfer->state = FWXF_START;
881
882         fp = &xfer->send.hdr;
883         tcode = fp->mode.common.tcode;
884
885         ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
886         info = &tinfo[tcode];
887         hdr_len = pl_off = info->hdr_len;
888
889         ld = &ohcifp->mode.ld[0];
890         ld[0] = ld[1] = ld[2] = ld[3] = 0;
891         for( i = 0 ; i < pl_off ; i+= 4)
892                 ld[i/4] = fp->mode.ld[i/4];
893
894         ohcifp->mode.common.spd = xfer->send.spd & 0x7;
895         if (tcode == FWTCODE_STREAM ){
896                 hdr_len = 8;
897                 ohcifp->mode.stream.len = fp->mode.stream.len;
898         } else if (tcode == FWTCODE_PHY) {
899                 hdr_len = 12;
900                 ld[1] = fp->mode.ld[1];
901                 ld[2] = fp->mode.ld[2];
902                 ohcifp->mode.common.spd = 0;
903                 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
904         } else {
905                 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
906                 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
907                 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
908         }
909         db = &db_tr->db[0];
910         FWOHCI_DMA_WRITE(db->db.desc.cmd,
911                         OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
912         FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
913         FWOHCI_DMA_WRITE(db->db.desc.res, 0);
914 /* Specify bound timer of asy. responce */
915         if(&sc->atrs == dbch){
916                 FWOHCI_DMA_WRITE(db->db.desc.res,
917                          (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
918         }
919 #if BYTE_ORDER == BIG_ENDIAN
920         if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
921                 hdr_len = 12;
922         for (i = 0; i < hdr_len/4; i ++)
923                 FWOHCI_DMA_WRITE(ld[i], ld[i]);
924 #endif
925
926 again:
927         db_tr->dbcnt = 2;
928         db = &db_tr->db[db_tr->dbcnt];
929         if (xfer->send.pay_len > 0) {
930                 int err;
931                 /* handle payload */
932                 if (xfer->mbuf == NULL) {
933                         err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
934                                 &xfer->send.payload[0], xfer->send.pay_len,
935                                 fwohci_execute_db, db_tr,
936                                 /*flags*/0);
937                 } else {
938                         /* XXX we can handle only 6 (=8-2) mbuf chains */
939                         err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
940                                 xfer->mbuf,
941                                 fwohci_execute_db2, db_tr,
942                                 /* flags */0);
943                         if (err == EFBIG) {
944                                 struct mbuf *m0;
945
946                                 if (firewire_debug)
947                                         device_printf(sc->fc.dev, "EFBIG.\n");
948                                 m0 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
949                                 if (m0 != NULL) {
950                                         m_copydata(xfer->mbuf, 0,
951                                                 xfer->mbuf->m_pkthdr.len,
952                                                 mtod(m0, caddr_t));
953                                         m0->m_len = m0->m_pkthdr.len = 
954                                                 xfer->mbuf->m_pkthdr.len;
955                                         m_freem(xfer->mbuf);
956                                         xfer->mbuf = m0;
957                                         goto again;
958                                 }
959                                 device_printf(sc->fc.dev, "m_getcl failed.\n");
960                         }
961                 }
962                 if (err)
963                         printf("dmamap_load: err=%d\n", err);
964                 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
965                                                 BUS_DMASYNC_PREWRITE);
966 #if 0 /* OHCI_OUTPUT_MODE == 0 */
967                 for (i = 2; i < db_tr->dbcnt; i++)
968                         FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
969                                                 OHCI_OUTPUT_MORE);
970 #endif
971         }
972         if (maxdesc < db_tr->dbcnt) {
973                 maxdesc = db_tr->dbcnt;
974                 if (bootverbose)
975                         device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
976         }
977         /* last db */
978         LAST_DB(db_tr, db);
979         FWOHCI_DMA_SET(db->db.desc.cmd,
980                 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
981         FWOHCI_DMA_WRITE(db->db.desc.depend,
982                         STAILQ_NEXT(db_tr, link)->bus_addr);
983
984         if(fsegment == -1 )
985                 fsegment = db_tr->dbcnt;
986         if (dbch->pdb_tr != NULL) {
987                 LAST_DB(dbch->pdb_tr, db);
988                 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
989         }
990         dbch->pdb_tr = db_tr;
991         db_tr = STAILQ_NEXT(db_tr, link);
992         if(db_tr != dbch->bottom){
993                 goto txloop;
994         } else {
995                 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
996                 dbch->flags |= FWOHCI_DBCH_FULL;
997         }
998 kick:
999         /* kick asy q */
1000         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1001         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1002
1003         if(dbch->xferq.flag & FWXFERQ_RUNNING) {
1004                 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1005         } else {
1006                 if (bootverbose)
1007                         device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1008                                         OREAD(sc, OHCI_DMACTL(off)));
1009                 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1010                 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1011                 dbch->xferq.flag |= FWXFERQ_RUNNING;
1012         }
1013
1014         dbch->top = db_tr;
1015         crit_exit();
1016         return;
1017 }
1018
1019 static void
1020 fwohci_start_atq(struct firewire_comm *fc)
1021 {
1022         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1023         fwohci_start( sc, &(sc->atrq));
1024         return;
1025 }
1026
1027 static void
1028 fwohci_start_ats(struct firewire_comm *fc)
1029 {
1030         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1031         fwohci_start( sc, &(sc->atrs));
1032         return;
1033 }
1034
1035 void
1036 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1037 {
1038         int ch, err = 0;
1039         struct fwohcidb_tr *tr;
1040         struct fwohcidb *db;
1041         struct fw_xfer *xfer;
1042         u_int32_t off;
1043         u_int stat, status;
1044         int     packets;
1045         struct firewire_comm *fc = (struct firewire_comm *)sc;
1046
1047         if(&sc->atrq == dbch){
1048                 off = OHCI_ATQOFF;
1049                 ch = ATRQ_CH;
1050         }else if(&sc->atrs == dbch){
1051                 off = OHCI_ATSOFF;
1052                 ch = ATRS_CH;
1053         }else{
1054                 return;
1055         }
1056         crit_enter();
1057         tr = dbch->bottom;
1058         packets = 0;
1059         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1060         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1061         while(dbch->xferq.queued > 0){
1062                 LAST_DB(tr, db);
1063                 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1064                 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1065                         if (fc->status != FWBUSRESET) 
1066                                 /* maybe out of order?? */
1067                                 goto out;
1068                 }
1069                 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1070                         BUS_DMASYNC_POSTWRITE);
1071                 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1072 #if 1
1073                 if (firewire_debug)
1074                         dump_db(sc, ch);
1075 #endif
1076                 if(status & OHCI_CNTL_DMA_DEAD) {
1077                         /* Stop DMA */
1078                         OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1079                         device_printf(sc->fc.dev, "force reset AT FIFO\n");
1080                         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1081                         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1082                         OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1083                 }
1084                 stat = status & FWOHCIEV_MASK;
1085                 switch(stat){
1086                 case FWOHCIEV_ACKPEND:
1087                 case FWOHCIEV_ACKCOMPL:
1088                         err = 0;
1089                         break;
1090                 case FWOHCIEV_ACKBSA:
1091                 case FWOHCIEV_ACKBSB:
1092                 case FWOHCIEV_ACKBSX:
1093                         device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1094                         err = EBUSY;
1095                         break;
1096                 case FWOHCIEV_FLUSHED:
1097                 case FWOHCIEV_ACKTARD:
1098                         device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1099                         err = EAGAIN;
1100                         break;
1101                 case FWOHCIEV_MISSACK:
1102                 case FWOHCIEV_UNDRRUN:
1103                 case FWOHCIEV_OVRRUN:
1104                 case FWOHCIEV_DESCERR:
1105                 case FWOHCIEV_DTRDERR:
1106                 case FWOHCIEV_TIMEOUT:
1107                 case FWOHCIEV_TCODERR:
1108                 case FWOHCIEV_UNKNOWN:
1109                 case FWOHCIEV_ACKDERR:
1110                 case FWOHCIEV_ACKTERR:
1111                 default:
1112                         device_printf(sc->fc.dev, "txd err=%2x %s\n",
1113                                                         stat, fwohcicode[stat]);
1114                         err = EINVAL;
1115                         break;
1116                 }
1117                 if (tr->xfer != NULL) {
1118                         xfer = tr->xfer;
1119                         if (xfer->state == FWXF_RCVD) {
1120 #if 0
1121                                 if (firewire_debug)
1122                                         printf("already rcvd\n");
1123 #endif
1124                                 fw_xfer_done(xfer);
1125                         } else {
1126                                 xfer->state = FWXF_SENT;
1127                                 if (err == EBUSY && fc->status != FWBUSRESET) {
1128                                         xfer->state = FWXF_BUSY;
1129                                         xfer->resp = err;
1130                                         if (xfer->retry_req != NULL)
1131                                                 xfer->retry_req(xfer);
1132                                         else {
1133                                                 xfer->recv.pay_len = 0;
1134                                                 fw_xfer_done(xfer);
1135                                         }
1136                                 } else if (stat != FWOHCIEV_ACKPEND) {
1137                                         if (stat != FWOHCIEV_ACKCOMPL)
1138                                                 xfer->state = FWXF_SENTERR;
1139                                         xfer->resp = err;
1140                                         xfer->recv.pay_len = 0;
1141                                         fw_xfer_done(xfer);
1142                                 }
1143                         }
1144                         /*
1145                          * The watchdog timer takes care of split
1146                          * transcation timeout for ACKPEND case.
1147                          */
1148                 } else {
1149                         printf("this shouldn't happen\n");
1150                 }
1151                 dbch->xferq.queued --;
1152                 tr->xfer = NULL;
1153
1154                 packets ++;
1155                 tr = STAILQ_NEXT(tr, link);
1156                 dbch->bottom = tr;
1157                 if (dbch->bottom == dbch->top) {
1158                         /* we reaches the end of context program */
1159                         if (firewire_debug && dbch->xferq.queued > 0)
1160                                 printf("queued > 0\n");
1161                         break;
1162                 }
1163         }
1164 out:
1165         if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1166                 printf("make free slot\n");
1167                 dbch->flags &= ~FWOHCI_DBCH_FULL;
1168                 fwohci_start(sc, dbch);
1169         }
1170         crit_exit();
1171 }
1172
1173 static void
1174 fwohci_db_free(struct fwohci_dbch *dbch)
1175 {
1176         struct fwohcidb_tr *db_tr;
1177         int idb;
1178
1179         if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1180                 return;
1181
1182         for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1183                         db_tr = STAILQ_NEXT(db_tr, link), idb++){
1184                 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1185                                         db_tr->buf != NULL) {
1186                         fwdma_free_size(dbch->dmat, db_tr->dma_map,
1187                                         db_tr->buf, dbch->xferq.psize);
1188                         db_tr->buf = NULL;
1189                 } else if (db_tr->dma_map != NULL)
1190                         bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1191         }
1192         dbch->ndb = 0;
1193         db_tr = STAILQ_FIRST(&dbch->db_trq);
1194         fwdma_free_multiseg(dbch->am);
1195         free(db_tr, M_FW);
1196         STAILQ_INIT(&dbch->db_trq);
1197         dbch->flags &= ~FWOHCI_DBCH_INIT;
1198 }
1199
1200 static void
1201 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1202 {
1203         int     idb;
1204         struct fwohcidb_tr *db_tr;
1205
1206         if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1207                 goto out;
1208
1209         /* create dma_tag for buffers */
1210 #define MAX_REQCOUNT    0xffff
1211         if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1212                         /*alignment*/ 1, /*boundary*/ 0,
1213                         /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1214                         /*highaddr*/ BUS_SPACE_MAXADDR,
1215                         /*filter*/NULL, /*filterarg*/NULL,
1216                         /*maxsize*/ dbch->xferq.psize,
1217                         /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1218                         /*maxsegsz*/ MAX_REQCOUNT,
1219                         /*flags*/ 0,
1220 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102
1221                         /*lockfunc*/busdma_lock_mutex,
1222                         /*lockarg*/&Giant,
1223 #endif
1224                         &dbch->dmat))
1225                 return;
1226
1227         /* allocate DB entries and attach one to each DMA channels */
1228         /* DB entry must start at 16 bytes bounary. */
1229         STAILQ_INIT(&dbch->db_trq);
1230         db_tr = (struct fwohcidb_tr *)
1231                 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1232                 M_FW, M_WAITOK | M_ZERO);
1233         if(db_tr == NULL){
1234                 printf("fwohci_db_init: malloc(1) failed\n");
1235                 return;
1236         }
1237
1238 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1239         dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1240                 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1241         if (dbch->am == NULL) {
1242                 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1243                 free(db_tr, M_FW);
1244                 return;
1245         }
1246         /* Attach DB to DMA ch. */
1247         for(idb = 0 ; idb < dbch->ndb ; idb++){
1248                 db_tr->dbcnt = 0;
1249                 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1250                 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1251                 /* create dmamap for buffers */
1252                 /* XXX do we need 4bytes alignment tag? */
1253                 /* XXX don't alloc dma_map for AR */
1254                 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1255                         printf("bus_dmamap_create failed\n");
1256                         dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1257                         fwohci_db_free(dbch);
1258                         return;
1259                 }
1260                 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1261                 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1262                         if (idb % dbch->xferq.bnpacket == 0)
1263                                 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1264                                                 ].start = (caddr_t)db_tr;
1265                         if ((idb + 1) % dbch->xferq.bnpacket == 0)
1266                                 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1267                                                 ].end = (caddr_t)db_tr;
1268                 }
1269                 db_tr++;
1270         }
1271         STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1272                         = STAILQ_FIRST(&dbch->db_trq);
1273 out:
1274         dbch->xferq.queued = 0;
1275         dbch->pdb_tr = NULL;
1276         dbch->top = STAILQ_FIRST(&dbch->db_trq);
1277         dbch->bottom = dbch->top;
1278         dbch->flags = FWOHCI_DBCH_INIT;
1279 }
1280
1281 static int
1282 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1283 {
1284         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1285         int sleepch;
1286
1287         OWRITE(sc, OHCI_ITCTLCLR(dmach), 
1288                         OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1289         OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1290         OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1291         /* XXX we cannot free buffers until the DMA really stops */
1292         tsleep((void *)&sleepch, FWPRI, "fwitxd", hz);
1293         fwohci_db_free(&sc->it[dmach]);
1294         sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1295         return 0;
1296 }
1297
1298 static int
1299 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1300 {
1301         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1302         int sleepch;
1303
1304         OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1305         OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1306         OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1307         /* XXX we cannot free buffers until the DMA really stops */
1308         tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1309         fwohci_db_free(&sc->ir[dmach]);
1310         sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1311         return 0;
1312 }
1313
1314 #if BYTE_ORDER == BIG_ENDIAN
1315 static void
1316 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1317 {
1318         qld[0] = FWOHCI_DMA_READ(qld[0]);
1319         return;
1320 }
1321 #endif
1322
1323 static int
1324 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1325 {
1326         int err = 0;
1327         int idb, z, i, dmach = 0, ldesc;
1328         u_int32_t off = 0;
1329         struct fwohcidb_tr *db_tr;
1330         struct fwohcidb *db;
1331
1332         if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1333                 err = EINVAL;
1334                 return err;
1335         }
1336         z = dbch->ndesc;
1337         for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1338                 if( &sc->it[dmach] == dbch){
1339                         off = OHCI_ITOFF(dmach);
1340                         break;
1341                 }
1342         }
1343         if(off == 0){
1344                 err = EINVAL;
1345                 return err;
1346         }
1347         if(dbch->xferq.flag & FWXFERQ_RUNNING)
1348                 return err;
1349         dbch->xferq.flag |= FWXFERQ_RUNNING;
1350         for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1351                 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1352         }
1353         db_tr = dbch->top;
1354         for (idb = 0; idb < dbch->ndb; idb ++) {
1355                 fwohci_add_tx_buf(dbch, db_tr, idb);
1356                 if(STAILQ_NEXT(db_tr, link) == NULL){
1357                         break;
1358                 }
1359                 db = db_tr->db;
1360                 ldesc = db_tr->dbcnt - 1;
1361                 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1362                                 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1363                 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1364                 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1365                         if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1366                                 FWOHCI_DMA_SET(
1367                                         db[ldesc].db.desc.cmd,
1368                                         OHCI_INTERRUPT_ALWAYS);
1369                                 /* OHCI 1.1 and above */
1370                                 FWOHCI_DMA_SET(
1371                                         db[0].db.desc.cmd,
1372                                         OHCI_INTERRUPT_ALWAYS);
1373                         }
1374                 }
1375                 db_tr = STAILQ_NEXT(db_tr, link);
1376         }
1377         FWOHCI_DMA_CLEAR(
1378                 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1379         return err;
1380 }
1381
1382 static int
1383 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1384 {
1385         int err = 0;
1386         int idb, z, i, dmach = 0, ldesc;
1387         u_int32_t off = 0;
1388         struct fwohcidb_tr *db_tr;
1389         struct fwohcidb *db;
1390
1391         z = dbch->ndesc;
1392         if(&sc->arrq == dbch){
1393                 off = OHCI_ARQOFF;
1394         }else if(&sc->arrs == dbch){
1395                 off = OHCI_ARSOFF;
1396         }else{
1397                 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1398                         if( &sc->ir[dmach] == dbch){
1399                                 off = OHCI_IROFF(dmach);
1400                                 break;
1401                         }
1402                 }
1403         }
1404         if(off == 0){
1405                 err = EINVAL;
1406                 return err;
1407         }
1408         if(dbch->xferq.flag & FWXFERQ_STREAM){
1409                 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1410                         return err;
1411         }else{
1412                 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1413                         err = EBUSY;
1414                         return err;
1415                 }
1416         }
1417         dbch->xferq.flag |= FWXFERQ_RUNNING;
1418         dbch->top = STAILQ_FIRST(&dbch->db_trq);
1419         for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1420                 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1421         }
1422         db_tr = dbch->top;
1423         for (idb = 0; idb < dbch->ndb; idb ++) {
1424                 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1425                 if (STAILQ_NEXT(db_tr, link) == NULL)
1426                         break;
1427                 db = db_tr->db;
1428                 ldesc = db_tr->dbcnt - 1;
1429                 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1430                         STAILQ_NEXT(db_tr, link)->bus_addr | z);
1431                 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1432                         if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1433                                 FWOHCI_DMA_SET(
1434                                         db[ldesc].db.desc.cmd,
1435                                         OHCI_INTERRUPT_ALWAYS);
1436                                 FWOHCI_DMA_CLEAR(
1437                                         db[ldesc].db.desc.depend,
1438                                         0xf);
1439                         }
1440                 }
1441                 db_tr = STAILQ_NEXT(db_tr, link);
1442         }
1443         FWOHCI_DMA_CLEAR(
1444                 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1445         dbch->buf_offset = 0;
1446         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1447         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1448         if(dbch->xferq.flag & FWXFERQ_STREAM){
1449                 return err;
1450         }else{
1451                 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1452         }
1453         OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1454         return err;
1455 }
1456
1457 static int
1458 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1459 {
1460         int sec, cycle, cycle_match;
1461
1462         cycle = cycle_now & 0x1fff;
1463         sec = cycle_now >> 13;
1464 #define CYCLE_MOD       0x10
1465 #if 1
1466 #define CYCLE_DELAY     8       /* min delay to start DMA */
1467 #else
1468 #define CYCLE_DELAY     7000    /* min delay to start DMA */
1469 #endif
1470         cycle = cycle + CYCLE_DELAY;
1471         if (cycle >= 8000) {
1472                 sec ++;
1473                 cycle -= 8000;
1474         }
1475         cycle = roundup2(cycle, CYCLE_MOD);
1476         if (cycle >= 8000) {
1477                 sec ++;
1478                 if (cycle == 8000)
1479                         cycle = 0;
1480                 else
1481                         cycle = CYCLE_MOD;
1482         }
1483         cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1484
1485         return(cycle_match);
1486 }
1487
1488 static int
1489 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1490 {
1491         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1492         int err = 0;
1493         unsigned short tag, ich;
1494         struct fwohci_dbch *dbch;
1495         int cycle_match, cycle_now, ldesc;
1496         u_int32_t stat;
1497         struct fw_bulkxfer *first, *chunk, *prev;
1498         struct fw_xferq *it;
1499
1500         dbch = &sc->it[dmach];
1501         it = &dbch->xferq;
1502
1503         tag = (it->flag >> 6) & 3;
1504         ich = it->flag & 0x3f;
1505         if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1506                 dbch->ndb = it->bnpacket * it->bnchunk;
1507                 dbch->ndesc = 3;
1508                 fwohci_db_init(sc, dbch);
1509                 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1510                         return ENOMEM;
1511                 err = fwohci_tx_enable(sc, dbch);
1512         }
1513         if(err)
1514                 return err;
1515
1516         ldesc = dbch->ndesc - 1;
1517         crit_enter();
1518         prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1519         while  ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1520                 struct fwohcidb *db;
1521
1522                 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1523                                         BUS_DMASYNC_PREWRITE);
1524                 fwohci_txbufdb(sc, dmach, chunk);
1525                 if (prev != NULL) {
1526                         db = ((struct fwohcidb_tr *)(prev->end))->db;
1527 #if 0 /* XXX necessary? */
1528                         FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1529                                                 OHCI_BRANCH_ALWAYS);
1530 #endif
1531 #if 0 /* if bulkxfer->npacket changes */
1532                         db[ldesc].db.desc.depend = db[0].db.desc.depend = 
1533                                 ((struct fwohcidb_tr *)
1534                                 (chunk->start))->bus_addr | dbch->ndesc;
1535 #else
1536                         FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1537                         FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1538 #endif
1539                 }
1540                 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1541                 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1542                 prev = chunk;
1543         }
1544         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1545         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1546         crit_exit();
1547         stat = OREAD(sc, OHCI_ITCTL(dmach));
1548         if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1549                 printf("stat 0x%x\n", stat);
1550
1551         if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1552                 return 0;
1553
1554 #if 0
1555         OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1556 #endif
1557         OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1558         OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1559         OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1560         OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1561
1562         first = STAILQ_FIRST(&it->stdma);
1563         OWRITE(sc, OHCI_ITCMD(dmach),
1564                 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1565         if (firewire_debug) {
1566                 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1567 #if 1
1568                 dump_dma(sc, ITX_CH + dmach);
1569 #endif
1570         }
1571         if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1572 #if 1
1573                 /* Don't start until all chunks are buffered */
1574                 if (STAILQ_FIRST(&it->stfree) != NULL)
1575                         goto out;
1576 #endif
1577 #if 1
1578                 /* Clear cycle match counter bits */
1579                 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1580
1581                 /* 2bit second + 13bit cycle */
1582                 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1583                 cycle_match = fwohci_next_cycle(fc, cycle_now);
1584
1585                 OWRITE(sc, OHCI_ITCTL(dmach),
1586                                 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1587                                 | OHCI_CNTL_DMA_RUN);
1588 #else
1589                 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1590 #endif
1591                 if (firewire_debug) {
1592                         printf("cycle_match: 0x%04x->0x%04x\n",
1593                                                 cycle_now, cycle_match);
1594                         dump_dma(sc, ITX_CH + dmach);
1595                         dump_db(sc, ITX_CH + dmach);
1596                 }
1597         } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1598                 device_printf(sc->fc.dev,
1599                         "IT DMA underrun (0x%08x)\n", stat);
1600                 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1601         }
1602 out:
1603         return err;
1604 }
1605
1606 static int
1607 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1608 {
1609         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1610         int err = 0, ldesc;
1611         unsigned short tag, ich;
1612         u_int32_t stat;
1613         struct fwohci_dbch *dbch;
1614         struct fwohcidb_tr *db_tr;
1615         struct fw_bulkxfer *first, *prev, *chunk;
1616         struct fw_xferq *ir;
1617
1618         dbch = &sc->ir[dmach];
1619         ir = &dbch->xferq;
1620
1621         if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1622                 tag = (ir->flag >> 6) & 3;
1623                 ich = ir->flag & 0x3f;
1624                 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1625
1626                 ir->queued = 0;
1627                 dbch->ndb = ir->bnpacket * ir->bnchunk;
1628                 dbch->ndesc = 2;
1629                 fwohci_db_init(sc, dbch);
1630                 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1631                         return ENOMEM;
1632                 err = fwohci_rx_enable(sc, dbch);
1633         }
1634         if(err)
1635                 return err;
1636
1637         first = STAILQ_FIRST(&ir->stfree);
1638         if (first == NULL) {
1639                 device_printf(fc->dev, "IR DMA no free chunk\n");
1640                 return 0;
1641         }
1642
1643         ldesc = dbch->ndesc - 1;
1644         crit_enter();
1645         prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1646         while  ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1647                 struct fwohcidb *db;
1648
1649 #if 1 /* XXX for if_fwe */
1650                 if (chunk->mbuf != NULL) {
1651                         db_tr = (struct fwohcidb_tr *)(chunk->start);
1652                         db_tr->dbcnt = 1;
1653                         err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1654                                         chunk->mbuf, fwohci_execute_db2, db_tr,
1655                                         /* flags */0);
1656                         FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1657                                 OHCI_UPDATE | OHCI_INPUT_LAST |
1658                                 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1659                 }
1660 #endif
1661                 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1662                 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1663                 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1664                 if (prev != NULL) {
1665                         db = ((struct fwohcidb_tr *)(prev->end))->db;
1666                         FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1667                 }
1668                 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1669                 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1670                 prev = chunk;
1671         }
1672         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1673         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1674         crit_exit();
1675         stat = OREAD(sc, OHCI_IRCTL(dmach));
1676         if (stat & OHCI_CNTL_DMA_ACTIVE)
1677                 return 0;
1678         if (stat & OHCI_CNTL_DMA_RUN) {
1679                 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1680                 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1681         }
1682
1683         if (firewire_debug)
1684                 printf("start IR DMA 0x%x\n", stat);
1685         OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1686         OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1687         OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1688         OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1689         OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1690         OWRITE(sc, OHCI_IRCMD(dmach),
1691                 ((struct fwohcidb_tr *)(first->start))->bus_addr
1692                                                         | dbch->ndesc);
1693         OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1694         OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1695 #if 0
1696         dump_db(sc, IRX_CH + dmach);
1697 #endif
1698         return err;
1699 }
1700
1701 int
1702 fwohci_stop(struct fwohci_softc *sc, device_t dev)
1703 {
1704         u_int i;
1705
1706 /* Now stopping all DMA channel */
1707         OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1708         OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1709         OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1710         OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1711
1712         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1713                 OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1714                 OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1715         }
1716
1717 /* FLUSH FIFO and reset Transmitter/Reciever */
1718         OWRITE(sc,  OHCI_HCCCTL, OHCI_HCC_RESET);
1719
1720 /* Stop interrupt */
1721         OWRITE(sc, FWOHCI_INTMASKCLR,
1722                         OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1723                         | OHCI_INT_PHY_INT
1724                         | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 
1725                         | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1726                         | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 
1727                         | OHCI_INT_PHY_BUS_R);
1728
1729         if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1730                 fw_drain_txq(&sc->fc);
1731
1732 /* XXX Link down?  Bus reset? */
1733         return 0;
1734 }
1735
1736 int
1737 fwohci_resume(struct fwohci_softc *sc, device_t dev)
1738 {
1739         int i;
1740         struct fw_xferq *ir;
1741         struct fw_bulkxfer *chunk;
1742
1743         fwohci_reset(sc, dev);
1744         /* XXX resume isochronus receive automatically. (how about TX?) */
1745         for(i = 0; i < sc->fc.nisodma; i ++) {
1746                 ir = &sc->ir[i].xferq;
1747                 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1748                         device_printf(sc->fc.dev,
1749                                 "resume iso receive ch: %d\n", i);
1750                         ir->flag &= ~FWXFERQ_RUNNING;
1751                         /* requeue stdma to stfree */
1752                         while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1753                                 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1754                                 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1755                         }
1756                         sc->fc.irx_enable(&sc->fc, i);
1757                 }
1758         }
1759
1760         bus_generic_resume(dev);
1761         sc->fc.ibr(&sc->fc);
1762         return 0;
1763 }
1764
1765 #define ACK_ALL
1766 static void
1767 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1768 {
1769         u_int32_t irstat, itstat;
1770         u_int i;
1771         struct firewire_comm *fc = (struct firewire_comm *)sc;
1772
1773 #ifdef OHCI_DEBUG
1774         if(stat & OREAD(sc, FWOHCI_INTMASK))
1775                 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1776                         stat & OHCI_INT_EN ? "DMA_EN ":"",
1777                         stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1778                         stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1779                         stat & OHCI_INT_ERR ? "INT_ERR ":"",
1780                         stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1781                         stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1782                         stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1783                         stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1784                         stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1785                         stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1786                         stat & OHCI_INT_PHY_SID ? "SID ":"",
1787                         stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1788                         stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1789                         stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1790                         stat & OHCI_INT_DMA_IT  ? "DMA_IT " :"",
1791                         stat & OHCI_INT_DMA_PRRS  ? "DMA_PRRS " :"",
1792                         stat & OHCI_INT_DMA_PRRQ  ? "DMA_PRRQ " :"",
1793                         stat & OHCI_INT_DMA_ARRS  ? "DMA_ARRS " :"",
1794                         stat & OHCI_INT_DMA_ARRQ  ? "DMA_ARRQ " :"",
1795                         stat & OHCI_INT_DMA_ATRS  ? "DMA_ATRS " :"",
1796                         stat & OHCI_INT_DMA_ATRQ  ? "DMA_ATRQ " :"",
1797                         stat, OREAD(sc, FWOHCI_INTMASK) 
1798                 );
1799 #endif
1800 /* Bus reset */
1801         if(stat & OHCI_INT_PHY_BUS_R ){
1802                 if (fc->status == FWBUSRESET)
1803                         goto busresetout;
1804                 /* Disable bus reset interrupt until sid recv. */
1805                 OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_PHY_BUS_R);
1806         
1807                 device_printf(fc->dev, "BUS reset\n");
1808                 OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
1809                 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1810
1811                 OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1812                 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1813                 OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1814                 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1815
1816 #ifndef ACK_ALL
1817                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1818 #endif
1819                 fw_busreset(fc);
1820                 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1821                 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
1822         }
1823 busresetout:
1824         if((stat & OHCI_INT_DMA_IR )){
1825 #ifndef ACK_ALL
1826                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1827 #endif
1828 #if defined(__DragonFly__) || __FreeBSD_version < 500000
1829                 irstat = sc->irstat;
1830                 sc->irstat = 0;
1831 #else
1832                 irstat = atomic_readandclear_int(&sc->irstat);
1833 #endif
1834                 for(i = 0; i < fc->nisodma ; i++){
1835                         struct fwohci_dbch *dbch;
1836
1837                         if((irstat & (1 << i)) != 0){
1838                                 dbch = &sc->ir[i];
1839                                 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1840                                         device_printf(sc->fc.dev,
1841                                                 "dma(%d) not active\n", i);
1842                                         continue;
1843                                 }
1844                                 fwohci_rbuf_update(sc, i);
1845                         }
1846                 }
1847         }
1848         if((stat & OHCI_INT_DMA_IT )){
1849 #ifndef ACK_ALL
1850                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1851 #endif
1852 #if defined(__DragonFly__) || __FreeBSD_version < 500000
1853                 itstat = sc->itstat;
1854                 sc->itstat = 0;
1855 #else
1856                 itstat = atomic_readandclear_int(&sc->itstat);
1857 #endif
1858                 for(i = 0; i < fc->nisodma ; i++){
1859                         if((itstat & (1 << i)) != 0){
1860                                 fwohci_tbuf_update(sc, i);
1861                         }
1862                 }
1863         }
1864         if((stat & OHCI_INT_DMA_PRRS )){
1865 #ifndef ACK_ALL
1866                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1867 #endif
1868 #if 0
1869                 dump_dma(sc, ARRS_CH);
1870                 dump_db(sc, ARRS_CH);
1871 #endif
1872                 fwohci_arcv(sc, &sc->arrs, count);
1873         }
1874         if((stat & OHCI_INT_DMA_PRRQ )){
1875 #ifndef ACK_ALL
1876                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1877 #endif
1878 #if 0
1879                 dump_dma(sc, ARRQ_CH);
1880                 dump_db(sc, ARRQ_CH);
1881 #endif
1882                 fwohci_arcv(sc, &sc->arrq, count);
1883         }
1884         if(stat & OHCI_INT_PHY_SID){
1885                 u_int32_t *buf, node_id;
1886                 int plen;
1887
1888 #ifndef ACK_ALL
1889                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1890 #endif
1891                 /* Enable bus reset interrupt */
1892                 OWRITE(sc, FWOHCI_INTMASK,  OHCI_INT_PHY_BUS_R);
1893                 /* Allow async. request to us */
1894                 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1895                 /* XXX insecure ?? */
1896                 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1897                 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1898                 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1899                 /* Set ATRetries register */
1900                 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1901 /*
1902 ** Checking whether the node is root or not. If root, turn on 
1903 ** cycle master.
1904 */
1905                 node_id = OREAD(sc, FWOHCI_NODEID);
1906                 plen = OREAD(sc, OHCI_SID_CNT);
1907
1908                 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1909                         node_id, (plen >> 16) & 0xff);
1910                 if (!(node_id & OHCI_NODE_VALID)) {
1911                         printf("Bus reset failure\n");
1912                         goto sidout;
1913                 }
1914                 if (node_id & OHCI_NODE_ROOT) {
1915                         printf("CYCLEMASTER mode\n");
1916                         OWRITE(sc, OHCI_LNKCTL,
1917                                 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1918                 } else {
1919                         printf("non CYCLEMASTER mode\n");
1920                         OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1921                         OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1922                 }
1923                 fc->nodeid = node_id & 0x3f;
1924
1925                 if (plen & OHCI_SID_ERR) {
1926                         device_printf(fc->dev, "SID Error\n");
1927                         goto sidout;
1928                 }
1929                 plen &= OHCI_SID_CNT_MASK;
1930                 if (plen < 4 || plen > OHCI_SIDSIZE) {
1931                         device_printf(fc->dev, "invalid SID len = %d\n", plen);
1932                         goto sidout;
1933                 }
1934                 plen -= 4; /* chop control info */
1935                 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_INTWAIT);
1936                 if (buf == NULL) {
1937                         device_printf(fc->dev, "malloc failed\n");
1938                         goto sidout;
1939                 }
1940                 for (i = 0; i < plen / 4; i ++)
1941                         buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1942 #if 1
1943                 /* pending all pre-bus_reset packets */
1944                 fwohci_txd(sc, &sc->atrq);
1945                 fwohci_txd(sc, &sc->atrs);
1946                 fwohci_arcv(sc, &sc->arrs, -1);
1947                 fwohci_arcv(sc, &sc->arrq, -1);
1948                 fw_drain_txq(fc);
1949 #endif
1950                 fw_sidrcv(fc, buf, plen);
1951                 free(buf, M_FW);
1952         }
1953 sidout:
1954         if((stat & OHCI_INT_DMA_ATRQ )){
1955 #ifndef ACK_ALL
1956                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1957 #endif
1958                 fwohci_txd(sc, &(sc->atrq));
1959         }
1960         if((stat & OHCI_INT_DMA_ATRS )){
1961 #ifndef ACK_ALL
1962                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1963 #endif
1964                 fwohci_txd(sc, &(sc->atrs));
1965         }
1966         if((stat & OHCI_INT_PW_ERR )){
1967 #ifndef ACK_ALL
1968                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1969 #endif
1970                 device_printf(fc->dev, "posted write error\n");
1971         }
1972         if((stat & OHCI_INT_ERR )){
1973 #ifndef ACK_ALL
1974                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1975 #endif
1976                 device_printf(fc->dev, "unrecoverable error\n");
1977         }
1978         if((stat & OHCI_INT_PHY_INT)) {
1979 #ifndef ACK_ALL
1980                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1981 #endif
1982                 device_printf(fc->dev, "phy int\n");
1983         }
1984
1985         return;
1986 }
1987
1988 #if FWOHCI_TASKQUEUE
1989 static void
1990 fwohci_complete(void *arg, int pending)
1991 {
1992         struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1993         u_int32_t stat;
1994
1995 again:
1996         stat = atomic_readandclear_int(&sc->intstat);
1997         if (stat)
1998                 fwohci_intr_body(sc, stat, -1);
1999         else
2000                 return;
2001         goto again;
2002 }
2003 #endif
2004
2005 static u_int32_t
2006 fwochi_check_stat(struct fwohci_softc *sc)
2007 {
2008         u_int32_t stat, irstat, itstat;
2009
2010         stat = OREAD(sc, FWOHCI_INTSTAT);
2011         if (stat == 0xffffffff) {
2012                 device_printf(sc->fc.dev, 
2013                         "device physically ejected?\n");
2014                 return(stat);
2015         }
2016 #ifdef ACK_ALL
2017         if (stat)
2018                 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
2019 #endif
2020         if (stat & OHCI_INT_DMA_IR) {
2021                 irstat = OREAD(sc, OHCI_IR_STAT);
2022                 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2023                 atomic_set_int(&sc->irstat, irstat);
2024         }
2025         if (stat & OHCI_INT_DMA_IT) {
2026                 itstat = OREAD(sc, OHCI_IT_STAT);
2027                 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2028                 atomic_set_int(&sc->itstat, itstat);
2029         }
2030         return(stat);
2031 }
2032
2033 void
2034 fwohci_intr(void *arg)
2035 {
2036         struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2037         u_int32_t stat;
2038 #if !FWOHCI_TASKQUEUE
2039         u_int32_t bus_reset = 0;
2040 #endif
2041
2042         if (!(sc->intmask & OHCI_INT_EN)) {
2043                 /* polling mode */
2044                 return;
2045         }
2046
2047 #if !FWOHCI_TASKQUEUE
2048 again:
2049 #endif
2050         stat = fwochi_check_stat(sc);
2051         if (stat == 0 || stat == 0xffffffff)
2052                 return;
2053 #if FWOHCI_TASKQUEUE
2054         atomic_set_int(&sc->intstat, stat);
2055         /* XXX mask bus reset intr. during bus reset phase */
2056         if (stat)
2057                 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete);
2058 #else
2059         /* We cannot clear bus reset event during bus reset phase */
2060         if ((stat & ~bus_reset) == 0)
2061                 return;
2062         bus_reset = stat & OHCI_INT_PHY_BUS_R;
2063         fwohci_intr_body(sc, stat, -1);
2064         goto again;
2065 #endif
2066 }
2067
2068 void
2069 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2070 {
2071         u_int32_t stat;
2072         struct fwohci_softc *sc;
2073
2074
2075         sc = (struct fwohci_softc *)fc;
2076         stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2077                 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2078                 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2079 #if 0
2080         if (!quick) {
2081 #else
2082         if (1) {
2083 #endif
2084                 stat = fwochi_check_stat(sc);
2085                 if (stat == 0 || stat == 0xffffffff)
2086                         return;
2087         }
2088         crit_enter();
2089         fwohci_intr_body(sc, stat, count);
2090         crit_exit();
2091 }
2092
2093 static void
2094 fwohci_set_intr(struct firewire_comm *fc, int enable)
2095 {
2096         struct fwohci_softc *sc;
2097
2098         sc = (struct fwohci_softc *)fc;
2099         if (bootverbose)
2100                 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2101         if (enable) {
2102                 sc->intmask |= OHCI_INT_EN;
2103                 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2104         } else {
2105                 sc->intmask &= ~OHCI_INT_EN;
2106                 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2107         }
2108 }
2109
2110 static void
2111 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2112 {
2113         struct firewire_comm *fc = &sc->fc;
2114         struct fwohcidb *db;
2115         struct fw_bulkxfer *chunk;
2116         struct fw_xferq *it;
2117         u_int32_t stat, count;
2118         int w=0, ldesc;
2119
2120         it = fc->it[dmach];
2121         ldesc = sc->it[dmach].ndesc - 1;
2122         crit_enter();   /* unnecessary? */
2123         fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2124         if (firewire_debug)
2125                 dump_db(sc, ITX_CH + dmach);
2126         while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2127                 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2128                 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 
2129                                 >> OHCI_STATUS_SHIFT;
2130                 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2131                 /* timestamp */
2132                 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2133                                 & OHCI_COUNT_MASK;
2134                 if (stat == 0)
2135                         break;
2136                 STAILQ_REMOVE_HEAD(&it->stdma, link);
2137                 switch (stat & FWOHCIEV_MASK){
2138                 case FWOHCIEV_ACKCOMPL:
2139 #if 0
2140                         device_printf(fc->dev, "0x%08x\n", count);
2141 #endif
2142                         break;
2143                 default:
2144                         device_printf(fc->dev,
2145                                 "Isochronous transmit err %02x(%s)\n",
2146                                         stat, fwohcicode[stat & 0x1f]);
2147                 }
2148                 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2149                 w++;
2150         }
2151         crit_exit();
2152         if (w)
2153                 wakeup(it);
2154 }
2155
2156 static void
2157 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2158 {
2159         struct firewire_comm *fc = &sc->fc;
2160         struct fwohcidb_tr *db_tr;
2161         struct fw_bulkxfer *chunk;
2162         struct fw_xferq *ir;
2163         u_int32_t stat;
2164         int w=0, ldesc;
2165
2166         ir = fc->ir[dmach];
2167         ldesc = sc->ir[dmach].ndesc - 1;
2168 #if 0
2169         dump_db(sc, dmach);
2170 #endif
2171         crit_enter();
2172         fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2173         while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2174                 db_tr = (struct fwohcidb_tr *)chunk->end;
2175                 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2176                                 >> OHCI_STATUS_SHIFT;
2177                 if (stat == 0)
2178                         break;
2179
2180                 if (chunk->mbuf != NULL) {
2181                         bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2182                                                 BUS_DMASYNC_POSTREAD);
2183                         bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2184                 } else if (ir->buf != NULL) {
2185                         fwdma_sync_multiseg(ir->buf, chunk->poffset,
2186                                 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2187                 } else {
2188                         /* XXX */
2189                         printf("fwohci_rbuf_update: this shouldn't happend\n");
2190                 }
2191
2192                 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2193                 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2194                 switch (stat & FWOHCIEV_MASK) {
2195                 case FWOHCIEV_ACKCOMPL:
2196                         chunk->resp = 0;
2197                         break;
2198                 default:
2199                         chunk->resp = EINVAL;
2200                         device_printf(fc->dev,
2201                                 "Isochronous receive err %02x(%s)\n",
2202                                         stat, fwohcicode[stat & 0x1f]);
2203                 }
2204                 w++;
2205         }
2206         crit_exit();
2207         if (w) {
2208                 if (ir->flag & FWXFERQ_HANDLER) 
2209                         ir->hand(ir);
2210                 else
2211                         wakeup(ir);
2212         }
2213 }
2214
2215 void
2216 dump_dma(struct fwohci_softc *sc, u_int32_t ch)
2217 {
2218         u_int32_t off, cntl, stat, cmd, match;
2219
2220         if(ch == 0){
2221                 off = OHCI_ATQOFF;
2222         }else if(ch == 1){
2223                 off = OHCI_ATSOFF;
2224         }else if(ch == 2){
2225                 off = OHCI_ARQOFF;
2226         }else if(ch == 3){
2227                 off = OHCI_ARSOFF;
2228         }else if(ch < IRX_CH){
2229                 off = OHCI_ITCTL(ch - ITX_CH);
2230         }else{
2231                 off = OHCI_IRCTL(ch - IRX_CH);
2232         }
2233         cntl = stat = OREAD(sc, off);
2234         cmd = OREAD(sc, off + 0xc);
2235         match = OREAD(sc, off + 0x10);
2236
2237         device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2238                 ch,
2239                 cntl, 
2240                 cmd, 
2241                 match);
2242         stat &= 0xffff ;
2243         if (stat) {
2244                 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2245                         ch,
2246                         stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2247                         stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2248                         stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2249                         stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2250                         stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2251                         stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2252                         fwohcicode[stat & 0x1f],
2253                         stat & 0x1f
2254                 );
2255         }else{
2256                 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2257         }
2258 }
2259
2260 void
2261 dump_db(struct fwohci_softc *sc, u_int32_t ch)
2262 {
2263         struct fwohci_dbch *dbch;
2264         struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2265         struct fwohcidb *curr = NULL, *prev, *next = NULL;
2266         int idb, jdb;
2267         u_int32_t cmd, off;
2268         if(ch == 0){
2269                 off = OHCI_ATQOFF;
2270                 dbch = &sc->atrq;
2271         }else if(ch == 1){
2272                 off = OHCI_ATSOFF;
2273                 dbch = &sc->atrs;
2274         }else if(ch == 2){
2275                 off = OHCI_ARQOFF;
2276                 dbch = &sc->arrq;
2277         }else if(ch == 3){
2278                 off = OHCI_ARSOFF;
2279                 dbch = &sc->arrs;
2280         }else if(ch < IRX_CH){
2281                 off = OHCI_ITCTL(ch - ITX_CH);
2282                 dbch = &sc->it[ch - ITX_CH];
2283         }else {
2284                 off = OHCI_IRCTL(ch - IRX_CH);
2285                 dbch = &sc->ir[ch - IRX_CH];
2286         }
2287         cmd = OREAD(sc, off + 0xc);
2288
2289         if( dbch->ndb == 0 ){
2290                 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2291                 return;
2292         }
2293         pp = dbch->top;
2294         prev = pp->db;
2295         for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2296                 if(pp == NULL){
2297                         curr = NULL;
2298                         goto outdb;
2299                 }
2300                 cp = STAILQ_NEXT(pp, link);
2301                 if(cp == NULL){
2302                         curr = NULL;
2303                         goto outdb;
2304                 }
2305                 np = STAILQ_NEXT(cp, link);
2306                 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2307                         if ((cmd  & 0xfffffff0) == cp->bus_addr) {
2308                                 curr = cp->db;
2309                                 if(np != NULL){
2310                                         next = np->db;
2311                                 }else{
2312                                         next = NULL;
2313                                 }
2314                                 goto outdb;
2315                         }
2316                 }
2317                 pp = STAILQ_NEXT(pp, link);
2318                 prev = pp->db;
2319         }
2320 outdb:
2321         if( curr != NULL){
2322 #if 0
2323                 printf("Prev DB %d\n", ch);
2324                 print_db(pp, prev, ch, dbch->ndesc);
2325 #endif
2326                 printf("Current DB %d\n", ch);
2327                 print_db(cp, curr, ch, dbch->ndesc);
2328 #if 0
2329                 printf("Next DB %d\n", ch);
2330                 print_db(np, next, ch, dbch->ndesc);
2331 #endif
2332         }else{
2333                 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2334         }
2335         return;
2336 }
2337
2338 void
2339 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2340                 u_int32_t ch, u_int32_t max)
2341 {
2342         fwohcireg_t stat;
2343         int i, key;
2344         u_int32_t cmd, res;
2345
2346         if(db == NULL){
2347                 printf("No Descriptor is found\n");
2348                 return;
2349         }
2350
2351         printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2352                 ch,
2353                 "Current",
2354                 "OP  ",
2355                 "KEY",
2356                 "INT",
2357                 "BR ",
2358                 "len",
2359                 "Addr",
2360                 "Depend",
2361                 "Stat",
2362                 "Cnt");
2363         for( i = 0 ; i <= max ; i ++){
2364                 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2365                 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2366                 key = cmd & OHCI_KEY_MASK;
2367                 stat = res >> OHCI_STATUS_SHIFT;
2368 #if defined(__DragonFly__) || __FreeBSD_version < 500000
2369                 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2370                                 db_tr->bus_addr,
2371 #else
2372                 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2373                                 (uintmax_t)db_tr->bus_addr,
2374 #endif
2375                                 dbcode[(cmd >> 28) & 0xf],
2376                                 dbkey[(cmd >> 24) & 0x7],
2377                                 dbcond[(cmd >> 20) & 0x3],
2378                                 dbcond[(cmd >> 18) & 0x3],
2379                                 cmd & OHCI_COUNT_MASK,
2380                                 FWOHCI_DMA_READ(db[i].db.desc.addr),
2381                                 FWOHCI_DMA_READ(db[i].db.desc.depend),
2382                                 stat,
2383                                 res & OHCI_COUNT_MASK);
2384                 if(stat & 0xff00){
2385                         printf(" %s%s%s%s%s%s %s(%x)\n",
2386                                 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2387                                 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2388                                 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2389                                 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2390                                 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2391                                 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2392                                 fwohcicode[stat & 0x1f],
2393                                 stat & 0x1f
2394                         );
2395                 }else{
2396                         printf(" Nostat\n");
2397                 }
2398                 if(key == OHCI_KEY_ST2 ){
2399                         printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 
2400                                 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2401                                 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2402                                 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2403                                 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2404                 }
2405                 if(key == OHCI_KEY_DEVICE){
2406                         return;
2407                 }
2408                 if((cmd & OHCI_BRANCH_MASK) 
2409                                 == OHCI_BRANCH_ALWAYS){
2410                         return;
2411                 }
2412                 if((cmd & OHCI_CMD_MASK) 
2413                                 == OHCI_OUTPUT_LAST){
2414                         return;
2415                 }
2416                 if((cmd & OHCI_CMD_MASK) 
2417                                 == OHCI_INPUT_LAST){
2418                         return;
2419                 }
2420                 if(key == OHCI_KEY_ST2 ){
2421                         i++;
2422                 }
2423         }
2424         return;
2425 }
2426
2427 void
2428 fwohci_ibr(struct firewire_comm *fc)
2429 {
2430         struct fwohci_softc *sc;
2431         u_int32_t fun;
2432
2433         device_printf(fc->dev, "Initiate bus reset\n");
2434         sc = (struct fwohci_softc *)fc;
2435
2436         /*
2437          * Set root hold-off bit so that non cyclemaster capable node
2438          * shouldn't became the root node.
2439          */
2440 #if 1
2441         fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2442         fun |= FW_PHY_IBR | FW_PHY_RHB;
2443         fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2444 #else   /* Short bus reset */
2445         fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2446         fun |= FW_PHY_ISBR | FW_PHY_RHB;
2447         fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2448 #endif
2449 }
2450
2451 void
2452 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2453 {
2454         struct fwohcidb_tr *db_tr, *fdb_tr;
2455         struct fwohci_dbch *dbch;
2456         struct fwohcidb *db;
2457         struct fw_pkt *fp;
2458         struct fwohci_txpkthdr *ohcifp;
2459         unsigned short chtag;
2460         int idb;
2461
2462         dbch = &sc->it[dmach];
2463         chtag = sc->it[dmach].xferq.flag & 0xff;
2464
2465         db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2466         fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2467 /*
2468 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2469 */
2470         for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2471                 db = db_tr->db;
2472                 fp = (struct fw_pkt *)db_tr->buf;
2473                 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
2474                 ohcifp->mode.ld[0] = fp->mode.ld[0];
2475                 ohcifp->mode.common.spd = 0 & 0x7;
2476                 ohcifp->mode.stream.len = fp->mode.stream.len;
2477                 ohcifp->mode.stream.chtag = chtag;
2478                 ohcifp->mode.stream.tcode = 0xa;
2479 #if BYTE_ORDER == BIG_ENDIAN
2480                 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 
2481                 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 
2482 #endif
2483
2484                 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2485                 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2486                 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2487 #if 0 /* if bulkxfer->npackets changes */
2488                 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2489                         | OHCI_UPDATE
2490                         | OHCI_BRANCH_ALWAYS;
2491                 db[0].db.desc.depend =
2492                         = db[dbch->ndesc - 1].db.desc.depend
2493                         = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2494 #else
2495                 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2496                 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2497 #endif
2498                 bulkxfer->end = (caddr_t)db_tr;
2499                 db_tr = STAILQ_NEXT(db_tr, link);
2500         }
2501         db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2502         FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2503         FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2504 #if 0 /* if bulkxfer->npackets changes */
2505         db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2506         /* OHCI 1.1 and above */
2507         db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2508 #endif
2509 /*
2510         db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2511         fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2512 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2513 */
2514         return;
2515 }
2516
2517 static int
2518 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2519                                                                 int poffset)
2520 {
2521         struct fwohcidb *db = db_tr->db;
2522         struct fw_xferq *it;
2523         int err = 0;
2524
2525         it = &dbch->xferq;
2526         if(it->buf == 0){
2527                 err = EINVAL;
2528                 return err;
2529         }
2530         db_tr->buf = fwdma_v_addr(it->buf, poffset);
2531         db_tr->dbcnt = 3;
2532
2533         FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2534                 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2535         FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2536         bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2537         FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2538         fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2539
2540         FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2541                 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2542 #if 1
2543         FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2544         FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2545 #endif
2546         return 0;
2547 }
2548
2549 int
2550 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2551                 int poffset, struct fwdma_alloc *dummy_dma)
2552 {
2553         struct fwohcidb *db = db_tr->db;
2554         struct fw_xferq *ir;
2555         int i, ldesc;
2556         bus_addr_t dbuf[2];
2557         int dsiz[2];
2558
2559         ir = &dbch->xferq;
2560         if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2561                 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map,
2562                         ir->psize, &dbuf[0], BUS_DMA_NOWAIT);
2563                 if (db_tr->buf == NULL)
2564                         return(ENOMEM);
2565                 db_tr->dbcnt = 1;
2566                 dsiz[0] = ir->psize;
2567                 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2568                         BUS_DMASYNC_PREREAD);
2569         } else {
2570                 db_tr->dbcnt = 0;
2571                 if (dummy_dma != NULL) {
2572                         dsiz[db_tr->dbcnt] = sizeof(u_int32_t);
2573                         dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2574                 }
2575                 dsiz[db_tr->dbcnt] = ir->psize;
2576                 if (ir->buf != NULL) {
2577                         db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2578                         dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2579                 }
2580                 db_tr->dbcnt++;
2581         }
2582         for(i = 0 ; i < db_tr->dbcnt ; i++){
2583                 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2584                 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2585                 if (ir->flag & FWXFERQ_STREAM) {
2586                         FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2587                 }
2588                 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2589         }
2590         ldesc = db_tr->dbcnt - 1;
2591         if (ir->flag & FWXFERQ_STREAM) {
2592                 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2593         }
2594         FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2595         return 0;
2596 }
2597
2598
2599 static int
2600 fwohci_arcv_swap(struct fw_pkt *fp, int len)
2601 {
2602         struct fw_pkt *fp0;
2603         u_int32_t ld0;
2604         int slen, hlen;
2605 #if BYTE_ORDER == BIG_ENDIAN
2606         int i;
2607 #endif
2608
2609         ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2610 #if 0
2611         printf("ld0: x%08x\n", ld0);
2612 #endif
2613         fp0 = (struct fw_pkt *)&ld0;
2614         /* determine length to swap */
2615         switch (fp0->mode.common.tcode) {
2616         case FWTCODE_RREQQ:
2617         case FWTCODE_WRES:
2618         case FWTCODE_WREQQ:
2619         case FWTCODE_RRESQ:
2620         case FWOHCITCODE_PHY:
2621                 slen = 12;
2622                 break;
2623         case FWTCODE_RREQB:
2624         case FWTCODE_WREQB:
2625         case FWTCODE_LREQ:
2626         case FWTCODE_RRESB:
2627         case FWTCODE_LRES:
2628                 slen = 16;
2629                 break;
2630         default:
2631                 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2632                 return(0);
2633         }
2634         hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2635         if (hlen > len) {
2636                 if (firewire_debug)
2637                         printf("splitted header\n");
2638                 return(-hlen);
2639         }
2640 #if BYTE_ORDER == BIG_ENDIAN
2641         for(i = 0; i < slen/4; i ++)
2642                 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2643 #endif
2644         return(hlen);
2645 }
2646
2647 static int
2648 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2649 {
2650         struct tcode_info *info;
2651         int r;
2652
2653         info = &tinfo[fp->mode.common.tcode];
2654         r = info->hdr_len + sizeof(u_int32_t);
2655         if ((info->flag & FWTI_BLOCK_ASY) != 0)
2656                 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t));
2657
2658         if (r == sizeof(u_int32_t))
2659                 /* XXX */
2660                 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2661                                                 fp->mode.common.tcode);
2662
2663         if (r > dbch->xferq.psize) {
2664                 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2665                 /* panic ? */
2666         }
2667
2668         return r;
2669 }
2670
2671 static void
2672 fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr)
2673 {
2674         struct fwohcidb *db = &db_tr->db[0];
2675
2676         FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2677         FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2678         FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2679         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2680         dbch->bottom = db_tr;
2681 }
2682
2683 static void
2684 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2685 {
2686         struct fwohcidb_tr *db_tr;
2687         struct iovec vec[2];
2688         struct fw_pkt pktbuf;
2689         int nvec;
2690         struct fw_pkt *fp;
2691         u_int8_t *ld;
2692         u_int32_t stat, off, status;
2693         u_int spd;
2694         int len, plen, hlen, pcnt, offset;
2695         caddr_t buf;
2696         int resCount;
2697
2698         if(&sc->arrq == dbch){
2699                 off = OHCI_ARQOFF;
2700         }else if(&sc->arrs == dbch){
2701                 off = OHCI_ARSOFF;
2702         }else{
2703                 return;
2704         }
2705
2706         crit_enter();
2707         db_tr = dbch->top;
2708         pcnt = 0;
2709         /* XXX we cannot handle a packet which lies in more than two buf */
2710         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2711         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2712         status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2713         resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2714 #if 0
2715         printf("status 0x%04x, resCount 0x%04x\n", status, resCount);
2716 #endif
2717         while (status & OHCI_CNTL_DMA_ACTIVE) {
2718                 len = dbch->xferq.psize - resCount;
2719                 ld = (u_int8_t *)db_tr->buf;
2720                 if (dbch->pdb_tr == NULL) {
2721                         len -= dbch->buf_offset;
2722                         ld += dbch->buf_offset;
2723                 }
2724                 if (len > 0)
2725                         bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2726                                         BUS_DMASYNC_POSTREAD);
2727                 while (len > 0 ) {
2728                         if (count >= 0 && count-- == 0)
2729                                 goto out;
2730                         if(dbch->pdb_tr != NULL){
2731                                 /* we have a fragment in previous buffer */
2732                                 int rlen;
2733
2734                                 offset = dbch->buf_offset;
2735                                 if (offset < 0)
2736                                         offset = - offset;
2737                                 buf = dbch->pdb_tr->buf + offset;
2738                                 rlen = dbch->xferq.psize - offset;
2739                                 if (firewire_debug)
2740                                         printf("rlen=%d, offset=%d\n",
2741                                                 rlen, dbch->buf_offset);
2742                                 if (dbch->buf_offset < 0) {
2743                                         /* splitted in header, pull up */
2744                                         char *p;
2745
2746                                         p = (char *)&pktbuf;
2747                                         bcopy(buf, p, rlen);
2748                                         p += rlen;
2749                                         /* this must be too long but harmless */
2750                                         rlen = sizeof(pktbuf) - rlen;
2751                                         if (rlen < 0)
2752                                                 printf("why rlen < 0\n");
2753                                         bcopy(db_tr->buf, p, rlen);
2754                                         ld += rlen;
2755                                         len -= rlen;
2756                                         hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2757                                         if (hlen < 0) {
2758                                                 printf("hlen < 0 shouldn't happen");
2759                                         }
2760                                         offset = sizeof(pktbuf);
2761                                         vec[0].iov_base = (char *)&pktbuf;
2762                                         vec[0].iov_len = offset;
2763                                 } else {
2764                                         /* splitted in payload */
2765                                         offset = rlen;
2766                                         vec[0].iov_base = buf;
2767                                         vec[0].iov_len = rlen;
2768                                 }
2769                                 fp=(struct fw_pkt *)vec[0].iov_base;
2770                                 nvec = 1;
2771                         } else {
2772                                 /* no fragment in previous buffer */
2773                                 fp=(struct fw_pkt *)ld;
2774                                 hlen = fwohci_arcv_swap(fp, len);
2775                                 if (hlen == 0)
2776                                         /* XXX need reset */
2777                                         goto out;
2778                                 if (hlen < 0) {
2779                                         dbch->pdb_tr = db_tr;
2780                                         dbch->buf_offset = - dbch->buf_offset;
2781                                         /* sanity check */
2782                                         if (resCount != 0) 
2783                                                 printf("resCount = %d !?\n",
2784                                                     resCount);
2785                                         /* XXX clear pdb_tr */
2786                                         goto out;
2787                                 }
2788                                 offset = 0;
2789                                 nvec = 0;
2790                         }
2791                         plen = fwohci_get_plen(sc, dbch, fp) - offset;
2792                         if (plen < 0) {
2793                                 /* minimum header size + trailer
2794                                 = sizeof(fw_pkt) so this shouldn't happens */
2795                                 printf("plen(%d) is negative! offset=%d\n",
2796                                     plen, offset);
2797                                 /* XXX clear pdb_tr */
2798                                 goto out;
2799                         }
2800                         if (plen > 0) {
2801                                 len -= plen;
2802                                 if (len < 0) {
2803                                         dbch->pdb_tr = db_tr;
2804                                         if (firewire_debug)
2805                                                 printf("splitted payload\n");
2806                                         /* sanity check */
2807                                         if (resCount != 0) 
2808                                                 printf("resCount = %d !?\n",
2809                                                     resCount);
2810                                         /* XXX clear pdb_tr */
2811                                         goto out;
2812                                 }
2813                                 vec[nvec].iov_base = ld;
2814                                 vec[nvec].iov_len = plen;
2815                                 nvec ++;
2816                                 ld += plen;
2817                         }
2818                         dbch->buf_offset = ld - (u_int8_t *)db_tr->buf;
2819                         if (nvec == 0)
2820                                 printf("nvec == 0\n");
2821
2822 /* DMA result-code will be written at the tail of packet */
2823 #if BYTE_ORDER == BIG_ENDIAN
2824                         stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
2825 #else
2826                         stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2827 #endif
2828 #if 0
2829                         printf("plen: %d, stat %x\n",
2830                             plen ,stat);
2831 #endif
2832                         spd = (stat >> 5) & 0x3;
2833                         stat &= 0x1f;
2834                         switch(stat){
2835                         case FWOHCIEV_ACKPEND:
2836 #if 0
2837                                 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2838 #endif
2839                                 /* fall through */
2840                         case FWOHCIEV_ACKCOMPL:
2841                         {
2842                                 struct fw_rcv_buf rb;
2843
2844                                 if ((vec[nvec-1].iov_len -=
2845                                         sizeof(struct fwohci_trailer)) == 0)
2846                                         nvec--; 
2847                                 rb.fc = &sc->fc;
2848                                 rb.vec = vec;
2849                                 rb.nvec = nvec;
2850                                 rb.spd = spd;
2851                                 fw_rcv(&rb);
2852                                 break;
2853                         }
2854                         case FWOHCIEV_BUSRST:
2855                                 if (sc->fc.status != FWBUSRESET) 
2856                                         printf("got BUSRST packet!?\n");
2857                                 break;
2858                         default:
2859                                 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2860 #if 0 /* XXX */
2861                                 goto out;
2862 #endif
2863                                 break;
2864                         }
2865                         pcnt ++;
2866                         if (dbch->pdb_tr != NULL) {
2867                                 fwohci_arcv_free_buf(dbch, dbch->pdb_tr);
2868                                 dbch->pdb_tr = NULL;
2869                         }
2870
2871                 }
2872 out:
2873                 if (resCount == 0) {
2874                         /* done on this buffer */
2875                         if (dbch->pdb_tr == NULL) {
2876                                 fwohci_arcv_free_buf(dbch, db_tr);
2877                                 dbch->buf_offset = 0;
2878                         } else
2879                                 if (dbch->pdb_tr != db_tr)
2880                                         printf("pdb_tr != db_tr\n");
2881                         db_tr = STAILQ_NEXT(db_tr, link);
2882                         status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2883                                                 >> OHCI_STATUS_SHIFT;
2884                         resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2885                                                 & OHCI_COUNT_MASK;
2886                         /* XXX check buffer overrun */
2887                         dbch->top = db_tr;
2888                 } else {
2889                         dbch->buf_offset = dbch->xferq.psize - resCount;
2890                         break;
2891                 }
2892                 /* XXX make sure DMA is not dead */
2893         }
2894 #if 0
2895         if (pcnt < 1)
2896                 printf("fwohci_arcv: no packets\n");
2897 #endif
2898         crit_exit();
2899 }