bge: In bge_stop, don't isolate PHY; it is unnecessary
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 /*
37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38  * 
39  * Written by Bill Paul <wpaul@windriver.com>
40  * Senior Engineer, Wind River Systems
41  */
42
43 /*
44  * The Broadcom BCM5700 is based on technology originally developed by
45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49  * frames, highly configurable RX filtering, and 16 RX and TX queues
50  * (which, along with RX filter rules, can be used for QOS applications).
51  * Other features, such as TCP segmentation, may be available as part
52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53  * firmware images can be stored in hardware and need not be compiled
54  * into the driver.
55  *
56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58  * 
59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61  * does not support external SSRAM.
62  *
63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
64  * brand name, which is functionally similar but lacks PCI-X support.
65  *
66  * Without external SSRAM, you can only have at most 4 TX rings,
67  * and the use of the mini RX ring is disabled. This seems to imply
68  * that these features are simply not available on the BCM5701. As a
69  * result, this driver does not implement any support for the mini RX
70  * ring.
71  */
72
73 #include "opt_polling.h"
74
75 #include <sys/param.h>
76 #include <sys/bus.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
79 #include <sys/ktr.h>
80 #include <sys/interrupt.h>
81 #include <sys/mbuf.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
84 #include <sys/rman.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
89
90 #include <net/bpf.h>
91 #include <net/ethernet.h>
92 #include <net/if.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99 #include <net/vlan/if_vlan_ether.h>
100
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
103 #include <dev/netif/mii_layer/brgphyreg.h>
104
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
108
109 #include <dev/netif/bge/if_bgereg.h>
110
111 /* "device miibus" required.  See GENERIC if you get errors here. */
112 #include "miibus_if.h"
113
114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
115 #define BGE_MIN_FRAME           60
116
117 static const struct bge_type bge_devs[] = {
118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119                 "3COM 3C996 Gigabit Ethernet" },
120
121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
122                 "Alteon BCM5700 Gigabit Ethernet" },
123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124                 "Alteon BCM5701 Gigabit Ethernet" },
125
126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127                 "Altima AC1000 Gigabit Ethernet" },
128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129                 "Altima AC1002 Gigabit Ethernet" },
130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131                 "Altima AC9100 Gigabit Ethernet" },
132
133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134                 "Apple BCM5701 Gigabit Ethernet" },
135
136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
137                 "Broadcom BCM5700 Gigabit Ethernet" },
138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
139                 "Broadcom BCM5701 Gigabit Ethernet" },
140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141                 "Broadcom BCM5702 Gigabit Ethernet" },
142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
143                 "Broadcom BCM5702X Gigabit Ethernet" },
144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145                 "Broadcom BCM5702 Gigabit Ethernet" },
146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147                 "Broadcom BCM5703 Gigabit Ethernet" },
148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149                 "Broadcom BCM5703X Gigabit Ethernet" },
150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151                 "Broadcom BCM5703 Gigabit Ethernet" },
152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
159                 "Broadcom BCM5705 Gigabit Ethernet" },
160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161                 "Broadcom BCM5705F Gigabit Ethernet" },
162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163                 "Broadcom BCM5705K Gigabit Ethernet" },
164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
165                 "Broadcom BCM5705M Gigabit Ethernet" },
166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
167                 "Broadcom BCM5705M Gigabit Ethernet" },
168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
169                 "Broadcom BCM5714C Gigabit Ethernet" },
170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171                 "Broadcom BCM5714S Gigabit Ethernet" },
172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173                 "Broadcom BCM5715 Gigabit Ethernet" },
174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175                 "Broadcom BCM5715S Gigabit Ethernet" },
176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177                 "Broadcom BCM5720 Gigabit Ethernet" },
178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179                 "Broadcom BCM5721 Gigabit Ethernet" },
180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181                 "Broadcom BCM5722 Gigabit Ethernet" },
182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183                 "Broadcom BCM5723 Gigabit Ethernet" },
184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185                 "Broadcom BCM5750 Gigabit Ethernet" },
186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187                 "Broadcom BCM5750M Gigabit Ethernet" },
188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189                 "Broadcom BCM5751 Gigabit Ethernet" },
190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191                 "Broadcom BCM5751F Gigabit Ethernet" },
192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193                 "Broadcom BCM5751M Gigabit Ethernet" },
194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195                 "Broadcom BCM5752 Gigabit Ethernet" },
196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197                 "Broadcom BCM5752M Gigabit Ethernet" },
198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199                 "Broadcom BCM5753 Gigabit Ethernet" },
200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201                 "Broadcom BCM5753F Gigabit Ethernet" },
202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203                 "Broadcom BCM5753M Gigabit Ethernet" },
204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205                 "Broadcom BCM5754 Gigabit Ethernet" },
206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207                 "Broadcom BCM5754M Gigabit Ethernet" },
208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209                 "Broadcom BCM5755 Gigabit Ethernet" },
210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211                 "Broadcom BCM5755M Gigabit Ethernet" },
212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213                 "Broadcom BCM5756 Gigabit Ethernet" },
214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215                 "Broadcom BCM5761 Gigabit Ethernet" },
216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217                 "Broadcom BCM5761E Gigabit Ethernet" },
218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219                 "Broadcom BCM5761S Gigabit Ethernet" },
220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221                 "Broadcom BCM5761SE Gigabit Ethernet" },
222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223                 "Broadcom BCM5764 Gigabit Ethernet" },
224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225                 "Broadcom BCM5780 Gigabit Ethernet" },
226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227                 "Broadcom BCM5780S Gigabit Ethernet" },
228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229                 "Broadcom BCM5781 Gigabit Ethernet" },
230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
231                 "Broadcom BCM5782 Gigabit Ethernet" },
232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233                 "Broadcom BCM5784 Gigabit Ethernet" },
234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235                 "Broadcom BCM5785F Gigabit Ethernet" },
236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237                 "Broadcom BCM5785G Gigabit Ethernet" },
238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239                 "Broadcom BCM5786 Gigabit Ethernet" },
240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241                 "Broadcom BCM5787 Gigabit Ethernet" },
242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243                 "Broadcom BCM5787F Gigabit Ethernet" },
244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245                 "Broadcom BCM5787M Gigabit Ethernet" },
246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
247                 "Broadcom BCM5788 Gigabit Ethernet" },
248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249                 "Broadcom BCM5789 Gigabit Ethernet" },
250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251                 "Broadcom BCM5901 Fast Ethernet" },
252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253                 "Broadcom BCM5901A2 Fast Ethernet" },
254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255                 "Broadcom BCM5903M Fast Ethernet" },
256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257                 "Broadcom BCM5906 Fast Ethernet"},
258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259                 "Broadcom BCM5906M Fast Ethernet"},
260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261                 "Broadcom BCM57760 Gigabit Ethernet"},
262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263                 "Broadcom BCM57780 Gigabit Ethernet"},
264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265                 "Broadcom BCM57788 Gigabit Ethernet"},
266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267                 "Broadcom BCM57790 Gigabit Ethernet"},
268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
269                 "SysKonnect Gigabit Ethernet" },
270
271         { 0, 0, NULL }
272 };
273
274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
280
281 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
282
283 static int      bge_probe(device_t);
284 static int      bge_attach(device_t);
285 static int      bge_detach(device_t);
286 static void     bge_txeof(struct bge_softc *);
287 static void     bge_rxeof(struct bge_softc *);
288
289 static void     bge_tick(void *);
290 static void     bge_stats_update(struct bge_softc *);
291 static void     bge_stats_update_regs(struct bge_softc *);
292 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
293
294 #ifdef DEVICE_POLLING
295 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
296 #endif
297 static void     bge_intr(void *);
298 static void     bge_enable_intr(struct bge_softc *);
299 static void     bge_disable_intr(struct bge_softc *);
300 static void     bge_start(struct ifnet *);
301 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
302 static void     bge_init(void *);
303 static void     bge_stop(struct bge_softc *);
304 static void     bge_watchdog(struct ifnet *);
305 static void     bge_shutdown(device_t);
306 static int      bge_suspend(device_t);
307 static int      bge_resume(device_t);
308 static int      bge_ifmedia_upd(struct ifnet *);
309 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
310
311 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
312 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
313
314 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
315 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
316
317 static void     bge_setmulti(struct bge_softc *);
318 static void     bge_setpromisc(struct bge_softc *);
319
320 static int      bge_alloc_jumbo_mem(struct bge_softc *);
321 static void     bge_free_jumbo_mem(struct bge_softc *);
322 static struct bge_jslot
323                 *bge_jalloc(struct bge_softc *);
324 static void     bge_jfree(void *);
325 static void     bge_jref(void *);
326 static int      bge_newbuf_std(struct bge_softc *, int, int);
327 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
328 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
329 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
330 static int      bge_init_rx_ring_std(struct bge_softc *);
331 static void     bge_free_rx_ring_std(struct bge_softc *);
332 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
333 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
334 static void     bge_free_tx_ring(struct bge_softc *);
335 static int      bge_init_tx_ring(struct bge_softc *);
336
337 static int      bge_chipinit(struct bge_softc *);
338 static int      bge_blockinit(struct bge_softc *);
339
340 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
341 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
342 #ifdef notdef
343 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
344 #endif
345 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
346 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
347 static void     bge_writembx(struct bge_softc *, int, int);
348
349 static int      bge_miibus_readreg(device_t, int, int);
350 static int      bge_miibus_writereg(device_t, int, int, int);
351 static void     bge_miibus_statchg(device_t);
352 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
353 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
354 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
355
356 static void     bge_reset(struct bge_softc *);
357
358 static int      bge_dma_alloc(struct bge_softc *);
359 static void     bge_dma_free(struct bge_softc *);
360 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
361                                     bus_dma_tag_t *, bus_dmamap_t *,
362                                     void **, bus_addr_t *);
363 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
364
365 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
366 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
367 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
368 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
369
370 static void     bge_coal_change(struct bge_softc *);
371 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
372 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
373 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
374 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
375 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
376
377 /*
378  * Set following tunable to 1 for some IBM blade servers with the DNLK
379  * switch module. Auto negotiation is broken for those configurations.
380  */
381 static int      bge_fake_autoneg = 0;
382 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
383
384 /* Interrupt moderation control variables. */
385 static int      bge_rx_coal_ticks = 100;        /* usec */
386 static int      bge_tx_coal_ticks = 1023;       /* usec */
387 static int      bge_rx_max_coal_bds = 80;
388 static int      bge_tx_max_coal_bds = 128;
389
390 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
391 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
392 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
393 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
394
395 #if !defined(KTR_IF_BGE)
396 #define KTR_IF_BGE      KTR_ALL
397 #endif
398 KTR_INFO_MASTER(if_bge);
399 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
400 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
401 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
402 #define logif(name)     KTR_LOG(if_bge_ ## name)
403
404 static device_method_t bge_methods[] = {
405         /* Device interface */
406         DEVMETHOD(device_probe,         bge_probe),
407         DEVMETHOD(device_attach,        bge_attach),
408         DEVMETHOD(device_detach,        bge_detach),
409         DEVMETHOD(device_shutdown,      bge_shutdown),
410         DEVMETHOD(device_suspend,       bge_suspend),
411         DEVMETHOD(device_resume,        bge_resume),
412
413         /* bus interface */
414         DEVMETHOD(bus_print_child,      bus_generic_print_child),
415         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
416
417         /* MII interface */
418         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
419         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
420         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
421
422         { 0, 0 }
423 };
424
425 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
426 static devclass_t bge_devclass;
427
428 DECLARE_DUMMY_MODULE(if_bge);
429 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
430 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
431
432 static uint32_t
433 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
434 {
435         device_t dev = sc->bge_dev;
436         uint32_t val;
437
438         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
439         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
440         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
441         return (val);
442 }
443
444 static void
445 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
446 {
447         device_t dev = sc->bge_dev;
448
449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
450         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
451         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
452 }
453
454 #ifdef notdef
455 static uint32_t
456 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
457 {
458         device_t dev = sc->bge_dev;
459
460         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
461         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
462 }
463 #endif
464
465 static void
466 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
467 {
468         device_t dev = sc->bge_dev;
469
470         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
471         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
472 }
473
474 static void
475 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
476 {
477         CSR_WRITE_4(sc, off, val);
478 }
479
480 static void
481 bge_writembx(struct bge_softc *sc, int off, int val)
482 {
483         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
484                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
485
486         CSR_WRITE_4(sc, off, val);
487 }
488
489 static uint8_t
490 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
491 {
492         uint32_t access, byte = 0;
493         int i;
494
495         /* Lock. */
496         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
497         for (i = 0; i < 8000; i++) {
498                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
499                         break;
500                 DELAY(20);
501         }
502         if (i == 8000)
503                 return (1);
504
505         /* Enable access. */
506         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
508
509         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
510         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
511         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
512                 DELAY(10);
513                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
514                         DELAY(10);
515                         break;
516                 }
517         }
518
519         if (i == BGE_TIMEOUT * 10) {
520                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
521                 return (1);
522         }
523
524         /* Get result. */
525         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
526
527         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
528
529         /* Disable access. */
530         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
531
532         /* Unlock. */
533         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
534         CSR_READ_4(sc, BGE_NVRAM_SWARB);
535
536         return (0);
537 }
538
539 /*
540  * Read a sequence of bytes from NVRAM.
541  */
542 static int
543 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
544 {
545         int err = 0, i;
546         uint8_t byte = 0;
547
548         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
549                 return (1);
550
551         for (i = 0; i < cnt; i++) {
552                 err = bge_nvram_getbyte(sc, off + i, &byte);
553                 if (err)
554                         break;
555                 *(dest + i) = byte;
556         }
557
558         return (err ? 1 : 0);
559 }
560
561 /*
562  * Read a byte of data stored in the EEPROM at address 'addr.' The
563  * BCM570x supports both the traditional bitbang interface and an
564  * auto access interface for reading the EEPROM. We use the auto
565  * access method.
566  */
567 static uint8_t
568 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
569 {
570         int i;
571         uint32_t byte = 0;
572
573         /*
574          * Enable use of auto EEPROM access so we can avoid
575          * having to use the bitbang method.
576          */
577         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
578
579         /* Reset the EEPROM, load the clock period. */
580         CSR_WRITE_4(sc, BGE_EE_ADDR,
581             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
582         DELAY(20);
583
584         /* Issue the read EEPROM command. */
585         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
586
587         /* Wait for completion */
588         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
589                 DELAY(10);
590                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
591                         break;
592         }
593
594         if (i == BGE_TIMEOUT) {
595                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
596                 return(1);
597         }
598
599         /* Get result. */
600         byte = CSR_READ_4(sc, BGE_EE_DATA);
601
602         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
603
604         return(0);
605 }
606
607 /*
608  * Read a sequence of bytes from the EEPROM.
609  */
610 static int
611 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
612 {
613         size_t i;
614         int err;
615         uint8_t byte;
616
617         for (byte = 0, err = 0, i = 0; i < len; i++) {
618                 err = bge_eeprom_getbyte(sc, off + i, &byte);
619                 if (err)
620                         break;
621                 *(dest + i) = byte;
622         }
623
624         return(err ? 1 : 0);
625 }
626
627 static int
628 bge_miibus_readreg(device_t dev, int phy, int reg)
629 {
630         struct bge_softc *sc = device_get_softc(dev);
631         struct ifnet *ifp = &sc->arpcom.ac_if;
632         uint32_t val, autopoll;
633         int i;
634
635         /*
636          * Broadcom's own driver always assumes the internal
637          * PHY is at GMII address 1. On some chips, the PHY responds
638          * to accesses at all addresses, which could cause us to
639          * bogusly attach the PHY 32 times at probe type. Always
640          * restricting the lookup to address 1 is simpler than
641          * trying to figure out which chips revisions should be
642          * special-cased.
643          */
644         if (phy != 1)
645                 return(0);
646
647         /* Reading with autopolling on may trigger PCI errors */
648         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
649         if (autopoll & BGE_MIMODE_AUTOPOLL) {
650                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
651                 DELAY(40);
652         }
653
654         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
655             BGE_MIPHY(phy)|BGE_MIREG(reg));
656
657         for (i = 0; i < BGE_TIMEOUT; i++) {
658                 DELAY(10);
659                 val = CSR_READ_4(sc, BGE_MI_COMM);
660                 if (!(val & BGE_MICOMM_BUSY))
661                         break;
662         }
663
664         if (i == BGE_TIMEOUT) {
665                 if_printf(ifp, "PHY read timed out "
666                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
667                 val = 0;
668                 goto done;
669         }
670
671         DELAY(5);
672         val = CSR_READ_4(sc, BGE_MI_COMM);
673
674 done:
675         if (autopoll & BGE_MIMODE_AUTOPOLL) {
676                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
677                 DELAY(40);
678         }
679
680         if (val & BGE_MICOMM_READFAIL)
681                 return(0);
682
683         return(val & 0xFFFF);
684 }
685
686 static int
687 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
688 {
689         struct bge_softc *sc = device_get_softc(dev);
690         uint32_t autopoll;
691         int i;
692
693         /*
694          * See the related comment in bge_miibus_readreg()
695          */
696         if (phy != 1)
697                 return(0);
698
699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
701                return(0);
702
703         /* Reading with autopolling on may trigger PCI errors */
704         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
705         if (autopoll & BGE_MIMODE_AUTOPOLL) {
706                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
707                 DELAY(40);
708         }
709
710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
711             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
712
713         for (i = 0; i < BGE_TIMEOUT; i++) {
714                 DELAY(10);
715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
716                         DELAY(5);
717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
718                         break;
719                 }
720         }
721
722         if (autopoll & BGE_MIMODE_AUTOPOLL) {
723                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
724                 DELAY(40);
725         }
726
727         if (i == BGE_TIMEOUT) {
728                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
729                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
730                 return(0);
731         }
732
733         return(0);
734 }
735
736 static void
737 bge_miibus_statchg(device_t dev)
738 {
739         struct bge_softc *sc;
740         struct mii_data *mii;
741
742         sc = device_get_softc(dev);
743         mii = device_get_softc(sc->bge_miibus);
744
745         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
746         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
747                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
748         } else {
749                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
750         }
751
752         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
753                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
754         } else {
755                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
756         }
757 }
758
759 /*
760  * Memory management for jumbo frames.
761  */
762 static int
763 bge_alloc_jumbo_mem(struct bge_softc *sc)
764 {
765         struct ifnet *ifp = &sc->arpcom.ac_if;
766         struct bge_jslot *entry;
767         uint8_t *ptr;
768         bus_addr_t paddr;
769         int i, error;
770
771         /*
772          * Create tag for jumbo mbufs.
773          * This is really a bit of a kludge. We allocate a special
774          * jumbo buffer pool which (thanks to the way our DMA
775          * memory allocation works) will consist of contiguous
776          * pages. This means that even though a jumbo buffer might
777          * be larger than a page size, we don't really need to
778          * map it into more than one DMA segment. However, the
779          * default mbuf tag will result in multi-segment mappings,
780          * so we have to create a special jumbo mbuf tag that
781          * lets us get away with mapping the jumbo buffers as
782          * a single segment. I think eventually the driver should
783          * be changed so that it uses ordinary mbufs and cluster
784          * buffers, i.e. jumbo frames can span multiple DMA
785          * descriptors. But that's a project for another day.
786          */
787
788         /*
789          * Create DMA stuffs for jumbo RX ring.
790          */
791         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
792                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
793                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
794                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
795                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
796         if (error) {
797                 if_printf(ifp, "could not create jumbo RX ring\n");
798                 return error;
799         }
800
801         /*
802          * Create DMA stuffs for jumbo buffer block.
803          */
804         error = bge_dma_block_alloc(sc, BGE_JMEM,
805                                     &sc->bge_cdata.bge_jumbo_tag,
806                                     &sc->bge_cdata.bge_jumbo_map,
807                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
808                                     &paddr);
809         if (error) {
810                 if_printf(ifp, "could not create jumbo buffer\n");
811                 return error;
812         }
813
814         SLIST_INIT(&sc->bge_jfree_listhead);
815
816         /*
817          * Now divide it up into 9K pieces and save the addresses
818          * in an array. Note that we play an evil trick here by using
819          * the first few bytes in the buffer to hold the the address
820          * of the softc structure for this interface. This is because
821          * bge_jfree() needs it, but it is called by the mbuf management
822          * code which will not pass it to us explicitly.
823          */
824         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
825                 entry = &sc->bge_cdata.bge_jslots[i];
826                 entry->bge_sc = sc;
827                 entry->bge_buf = ptr;
828                 entry->bge_paddr = paddr;
829                 entry->bge_inuse = 0;
830                 entry->bge_slot = i;
831                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
832
833                 ptr += BGE_JLEN;
834                 paddr += BGE_JLEN;
835         }
836         return 0;
837 }
838
839 static void
840 bge_free_jumbo_mem(struct bge_softc *sc)
841 {
842         /* Destroy jumbo RX ring. */
843         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
844                            sc->bge_cdata.bge_rx_jumbo_ring_map,
845                            sc->bge_ldata.bge_rx_jumbo_ring);
846
847         /* Destroy jumbo buffer block. */
848         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
849                            sc->bge_cdata.bge_jumbo_map,
850                            sc->bge_ldata.bge_jumbo_buf);
851 }
852
853 /*
854  * Allocate a jumbo buffer.
855  */
856 static struct bge_jslot *
857 bge_jalloc(struct bge_softc *sc)
858 {
859         struct bge_jslot *entry;
860
861         lwkt_serialize_enter(&sc->bge_jslot_serializer);
862         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
863         if (entry) {
864                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
865                 entry->bge_inuse = 1;
866         } else {
867                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
868         }
869         lwkt_serialize_exit(&sc->bge_jslot_serializer);
870         return(entry);
871 }
872
873 /*
874  * Adjust usage count on a jumbo buffer.
875  */
876 static void
877 bge_jref(void *arg)
878 {
879         struct bge_jslot *entry = (struct bge_jslot *)arg;
880         struct bge_softc *sc = entry->bge_sc;
881
882         if (sc == NULL)
883                 panic("bge_jref: can't find softc pointer!");
884
885         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
886                 panic("bge_jref: asked to reference buffer "
887                     "that we don't manage!");
888         } else if (entry->bge_inuse == 0) {
889                 panic("bge_jref: buffer already free!");
890         } else {
891                 atomic_add_int(&entry->bge_inuse, 1);
892         }
893 }
894
895 /*
896  * Release a jumbo buffer.
897  */
898 static void
899 bge_jfree(void *arg)
900 {
901         struct bge_jslot *entry = (struct bge_jslot *)arg;
902         struct bge_softc *sc = entry->bge_sc;
903
904         if (sc == NULL)
905                 panic("bge_jfree: can't find softc pointer!");
906
907         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
908                 panic("bge_jfree: asked to free buffer that we don't manage!");
909         } else if (entry->bge_inuse == 0) {
910                 panic("bge_jfree: buffer already free!");
911         } else {
912                 /*
913                  * Possible MP race to 0, use the serializer.  The atomic insn
914                  * is still needed for races against bge_jref().
915                  */
916                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
917                 atomic_subtract_int(&entry->bge_inuse, 1);
918                 if (entry->bge_inuse == 0) {
919                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
920                                           entry, jslot_link);
921                 }
922                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
923         }
924 }
925
926
927 /*
928  * Intialize a standard receive ring descriptor.
929  */
930 static int
931 bge_newbuf_std(struct bge_softc *sc, int i, int init)
932 {
933         struct mbuf *m_new = NULL;
934         bus_dma_segment_t seg;
935         bus_dmamap_t map;
936         int error, nsegs;
937
938         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
939         if (m_new == NULL)
940                 return ENOBUFS;
941         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
942
943         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
944                 m_adj(m_new, ETHER_ALIGN);
945
946         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
947                         sc->bge_cdata.bge_rx_tmpmap, m_new,
948                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
949         if (error) {
950                 m_freem(m_new);
951                 return error;
952         }
953
954         if (!init) {
955                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
956                                 sc->bge_cdata.bge_rx_std_dmamap[i],
957                                 BUS_DMASYNC_POSTREAD);
958                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
959                         sc->bge_cdata.bge_rx_std_dmamap[i]);
960         }
961
962         map = sc->bge_cdata.bge_rx_tmpmap;
963         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
964         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
965
966         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
967         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
968
969         bge_setup_rxdesc_std(sc, i);
970         return 0;
971 }
972
973 static void
974 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
975 {
976         struct bge_rxchain *rc;
977         struct bge_rx_bd *r;
978
979         rc = &sc->bge_cdata.bge_rx_std_chain[i];
980         r = &sc->bge_ldata.bge_rx_std_ring[i];
981
982         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
983         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
984         r->bge_len = rc->bge_mbuf->m_len;
985         r->bge_idx = i;
986         r->bge_flags = BGE_RXBDFLAG_END;
987 }
988
989 /*
990  * Initialize a jumbo receive ring descriptor. This allocates
991  * a jumbo buffer from the pool managed internally by the driver.
992  */
993 static int
994 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
995 {
996         struct mbuf *m_new = NULL;
997         struct bge_jslot *buf;
998         bus_addr_t paddr;
999
1000         /* Allocate the mbuf. */
1001         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1002         if (m_new == NULL)
1003                 return ENOBUFS;
1004
1005         /* Allocate the jumbo buffer */
1006         buf = bge_jalloc(sc);
1007         if (buf == NULL) {
1008                 m_freem(m_new);
1009                 return ENOBUFS;
1010         }
1011
1012         /* Attach the buffer to the mbuf. */
1013         m_new->m_ext.ext_arg = buf;
1014         m_new->m_ext.ext_buf = buf->bge_buf;
1015         m_new->m_ext.ext_free = bge_jfree;
1016         m_new->m_ext.ext_ref = bge_jref;
1017         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1018
1019         m_new->m_flags |= M_EXT;
1020
1021         m_new->m_data = m_new->m_ext.ext_buf;
1022         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1023
1024         paddr = buf->bge_paddr;
1025         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1026                 m_adj(m_new, ETHER_ALIGN);
1027                 paddr += ETHER_ALIGN;
1028         }
1029
1030         /* Save necessary information */
1031         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1032         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1033
1034         /* Set up the descriptor. */
1035         bge_setup_rxdesc_jumbo(sc, i);
1036         return 0;
1037 }
1038
1039 static void
1040 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1041 {
1042         struct bge_rx_bd *r;
1043         struct bge_rxchain *rc;
1044
1045         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1046         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1047
1048         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1049         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1050         r->bge_len = rc->bge_mbuf->m_len;
1051         r->bge_idx = i;
1052         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1053 }
1054
1055 static int
1056 bge_init_rx_ring_std(struct bge_softc *sc)
1057 {
1058         int i, error;
1059
1060         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1061                 error = bge_newbuf_std(sc, i, 1);
1062                 if (error)
1063                         return error;
1064         };
1065
1066         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return(0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1079
1080                 if (rc->bge_mbuf != NULL) {
1081                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1082                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1083                         m_freem(rc->bge_mbuf);
1084                         rc->bge_mbuf = NULL;
1085                 }
1086                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1087                     sizeof(struct bge_rx_bd));
1088         }
1089 }
1090
1091 static int
1092 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1093 {
1094         struct bge_rcb *rcb;
1095         int i, error;
1096
1097         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1098                 error = bge_newbuf_jumbo(sc, i, 1);
1099                 if (error)
1100                         return error;
1101         };
1102
1103         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1104
1105         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1106         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1107         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1108
1109         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1110
1111         return(0);
1112 }
1113
1114 static void
1115 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1116 {
1117         int i;
1118
1119         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1120                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1121
1122                 if (rc->bge_mbuf != NULL) {
1123                         m_freem(rc->bge_mbuf);
1124                         rc->bge_mbuf = NULL;
1125                 }
1126                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1127                     sizeof(struct bge_rx_bd));
1128         }
1129 }
1130
1131 static void
1132 bge_free_tx_ring(struct bge_softc *sc)
1133 {
1134         int i;
1135
1136         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1137                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1138                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1139                                           sc->bge_cdata.bge_tx_dmamap[i]);
1140                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1141                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1142                 }
1143                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1144                     sizeof(struct bge_tx_bd));
1145         }
1146 }
1147
1148 static int
1149 bge_init_tx_ring(struct bge_softc *sc)
1150 {
1151         sc->bge_txcnt = 0;
1152         sc->bge_tx_saved_considx = 0;
1153         sc->bge_tx_prodidx = 0;
1154
1155         /* Initialize transmit producer index for host-memory send ring. */
1156         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1157
1158         /* 5700 b2 errata */
1159         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1160                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1161
1162         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1163         /* 5700 b2 errata */
1164         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1165                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1166
1167         return(0);
1168 }
1169
1170 static void
1171 bge_setmulti(struct bge_softc *sc)
1172 {
1173         struct ifnet *ifp;
1174         struct ifmultiaddr *ifma;
1175         uint32_t hashes[4] = { 0, 0, 0, 0 };
1176         int h, i;
1177
1178         ifp = &sc->arpcom.ac_if;
1179
1180         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1181                 for (i = 0; i < 4; i++)
1182                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1183                 return;
1184         }
1185
1186         /* First, zot all the existing filters. */
1187         for (i = 0; i < 4; i++)
1188                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1189
1190         /* Now program new ones. */
1191         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1192                 if (ifma->ifma_addr->sa_family != AF_LINK)
1193                         continue;
1194                 h = ether_crc32_le(
1195                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1196                     ETHER_ADDR_LEN) & 0x7f;
1197                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1198         }
1199
1200         for (i = 0; i < 4; i++)
1201                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1202 }
1203
1204 /*
1205  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1206  * self-test results.
1207  */
1208 static int
1209 bge_chipinit(struct bge_softc *sc)
1210 {
1211         int i;
1212         uint32_t dma_rw_ctl;
1213
1214         /* Set endian type before we access any non-PCI registers. */
1215         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1216
1217         /* Clear the MAC control register */
1218         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1219
1220         /*
1221          * Clear the MAC statistics block in the NIC's
1222          * internal memory.
1223          */
1224         for (i = BGE_STATS_BLOCK;
1225             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1226                 BGE_MEMWIN_WRITE(sc, i, 0);
1227
1228         for (i = BGE_STATUS_BLOCK;
1229             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1230                 BGE_MEMWIN_WRITE(sc, i, 0);
1231
1232         /* Set up the PCI DMA control register. */
1233         if (sc->bge_flags & BGE_FLAG_PCIE) {
1234                 /* PCI Express */
1235                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1236                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1237                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1238         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1239                 /* PCI-X bus */
1240                 if (BGE_IS_5714_FAMILY(sc)) {
1241                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1242                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1243                         /* XXX magic values, Broadcom-supplied Linux driver */
1244                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1245                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | 
1246                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1247                         } else {
1248                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1249                         }
1250                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1251                         /*
1252                          * The 5704 uses a different encoding of read/write
1253                          * watermarks.
1254                          */
1255                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1256                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1257                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1258                 } else {
1259                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1260                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1261                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1262                             (0x0F);
1263                 }
1264
1265                 /*
1266                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1267                  * for hardware bugs.
1268                  */
1269                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1270                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1271                         uint32_t tmp;
1272
1273                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1274                         if (tmp == 0x6 || tmp == 0x7)
1275                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1276                 }
1277         } else {
1278                 /* Conventional PCI bus */
1279                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1280                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1281                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1282                     (0x0F);
1283         }
1284
1285         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1286             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1287             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1288                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1289         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1290
1291         /*
1292          * Set up general mode register.
1293          */
1294         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1295             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1296             BGE_MODECTL_TX_NO_PHDR_CSUM);
1297
1298         /*
1299          * BCM5701 B5 have a bug causing data corruption when using
1300          * 64-bit DMA reads, which can be terminated early and then
1301          * completed later as 32-bit accesses, in combination with
1302          * certain bridges.
1303          */
1304         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1305             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1306                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1307
1308         /*
1309          * Disable memory write invalidate.  Apparently it is not supported
1310          * properly by these devices.
1311          */
1312         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1313
1314         /* Set the timer prescaler (always 66Mhz) */
1315         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1316
1317         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1318                 DELAY(40);      /* XXX */
1319
1320                 /* Put PHY into ready state */
1321                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1322                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1323                 DELAY(40);
1324         }
1325
1326         return(0);
1327 }
1328
1329 static int
1330 bge_blockinit(struct bge_softc *sc)
1331 {
1332         struct bge_rcb *rcb;
1333         bus_size_t vrcb;
1334         bge_hostaddr taddr;
1335         uint32_t val;
1336         int i;
1337
1338         /*
1339          * Initialize the memory window pointer register so that
1340          * we can access the first 32K of internal NIC RAM. This will
1341          * allow us to set up the TX send ring RCBs and the RX return
1342          * ring RCBs, plus other things which live in NIC memory.
1343          */
1344         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1345
1346         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1347
1348         if (!BGE_IS_5705_PLUS(sc)) {
1349                 /* Configure mbuf memory pool */
1350                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1351                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1352                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1353                 else
1354                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1355
1356                 /* Configure DMA resource pool */
1357                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1358                     BGE_DMA_DESCRIPTORS);
1359                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1360         }
1361
1362         /* Configure mbuf pool watermarks */
1363         if (!BGE_IS_5705_PLUS(sc)) {
1364                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1365                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1366                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1367         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1368                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1369                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1370                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1371         } else {
1372                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1373                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1374                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1375         }
1376
1377         /* Configure DMA resource watermarks */
1378         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1379         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1380
1381         /* Enable buffer manager */
1382         if (!BGE_IS_5705_PLUS(sc)) {
1383                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1384                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1385
1386                 /* Poll for buffer manager start indication */
1387                 for (i = 0; i < BGE_TIMEOUT; i++) {
1388                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1389                                 break;
1390                         DELAY(10);
1391                 }
1392
1393                 if (i == BGE_TIMEOUT) {
1394                         if_printf(&sc->arpcom.ac_if,
1395                                   "buffer manager failed to start\n");
1396                         return(ENXIO);
1397                 }
1398         }
1399
1400         /* Enable flow-through queues */
1401         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1402         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1403
1404         /* Wait until queue initialization is complete */
1405         for (i = 0; i < BGE_TIMEOUT; i++) {
1406                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1407                         break;
1408                 DELAY(10);
1409         }
1410
1411         if (i == BGE_TIMEOUT) {
1412                 if_printf(&sc->arpcom.ac_if,
1413                           "flow-through queue init failed\n");
1414                 return(ENXIO);
1415         }
1416
1417         /* Initialize the standard RX ring control block */
1418         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1419         rcb->bge_hostaddr.bge_addr_lo =
1420             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1421         rcb->bge_hostaddr.bge_addr_hi =
1422             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1423         if (BGE_IS_5705_PLUS(sc))
1424                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1425         else
1426                 rcb->bge_maxlen_flags =
1427                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1428         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1429         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1430         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1431         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1432         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1433
1434         /*
1435          * Initialize the jumbo RX ring control block
1436          * We set the 'ring disabled' bit in the flags
1437          * field until we're actually ready to start
1438          * using this ring (i.e. once we set the MTU
1439          * high enough to require it).
1440          */
1441         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1442                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1443
1444                 rcb->bge_hostaddr.bge_addr_lo =
1445                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1446                 rcb->bge_hostaddr.bge_addr_hi =
1447                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1448                 rcb->bge_maxlen_flags =
1449                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1450                     BGE_RCB_FLAG_RING_DISABLED);
1451                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1452                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1453                     rcb->bge_hostaddr.bge_addr_hi);
1454                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1455                     rcb->bge_hostaddr.bge_addr_lo);
1456                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1457                     rcb->bge_maxlen_flags);
1458                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1459
1460                 /* Set up dummy disabled mini ring RCB */
1461                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1462                 rcb->bge_maxlen_flags =
1463                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1464                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1465                     rcb->bge_maxlen_flags);
1466         }
1467
1468         /*
1469          * Set the BD ring replentish thresholds. The recommended
1470          * values are 1/8th the number of descriptors allocated to
1471          * each ring.
1472          */
1473         if (BGE_IS_5705_PLUS(sc))
1474                 val = 8;
1475         else
1476                 val = BGE_STD_RX_RING_CNT / 8;
1477         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1478         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1479
1480         /*
1481          * Disable all unused send rings by setting the 'ring disabled'
1482          * bit in the flags field of all the TX send ring control blocks.
1483          * These are located in NIC memory.
1484          */
1485         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1486         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1487                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1488                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1489                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1490                 vrcb += sizeof(struct bge_rcb);
1491         }
1492
1493         /* Configure TX RCB 0 (we use only the first ring) */
1494         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1495         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1496         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1497         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1498         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1499             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1500         if (!BGE_IS_5705_PLUS(sc)) {
1501                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1502                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1503         }
1504
1505         /* Disable all unused RX return rings */
1506         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1507         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1508                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1509                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1510                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1511                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1512                     BGE_RCB_FLAG_RING_DISABLED));
1513                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1514                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1515                     (i * (sizeof(uint64_t))), 0);
1516                 vrcb += sizeof(struct bge_rcb);
1517         }
1518
1519         /* Initialize RX ring indexes */
1520         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1521         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1522         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1523
1524         /*
1525          * Set up RX return ring 0
1526          * Note that the NIC address for RX return rings is 0x00000000.
1527          * The return rings live entirely within the host, so the
1528          * nicaddr field in the RCB isn't used.
1529          */
1530         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1531         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1532         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1533         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1534         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1535         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1536             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1537
1538         /* Set random backoff seed for TX */
1539         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1540             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1541             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1542             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1543             BGE_TX_BACKOFF_SEED_MASK);
1544
1545         /* Set inter-packet gap */
1546         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1547
1548         /*
1549          * Specify which ring to use for packets that don't match
1550          * any RX rules.
1551          */
1552         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1553
1554         /*
1555          * Configure number of RX lists. One interrupt distribution
1556          * list, sixteen active lists, one bad frames class.
1557          */
1558         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1559
1560         /* Inialize RX list placement stats mask. */
1561         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1562         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1563
1564         /* Disable host coalescing until we get it set up */
1565         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1566
1567         /* Poll to make sure it's shut down. */
1568         for (i = 0; i < BGE_TIMEOUT; i++) {
1569                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1570                         break;
1571                 DELAY(10);
1572         }
1573
1574         if (i == BGE_TIMEOUT) {
1575                 if_printf(&sc->arpcom.ac_if,
1576                           "host coalescing engine failed to idle\n");
1577                 return(ENXIO);
1578         }
1579
1580         /* Set up host coalescing defaults */
1581         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1582         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1583         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1584         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1585         if (!BGE_IS_5705_PLUS(sc)) {
1586                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1587                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1588         }
1589         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1590         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1591
1592         /* Set up address of statistics block */
1593         if (!BGE_IS_5705_PLUS(sc)) {
1594                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1595                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1596                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1597                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1598
1599                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1600                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1601                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1602         }
1603
1604         /* Set up address of status block */
1605         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1606             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1607         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1608             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1609         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1610         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1611
1612         /* Turn on host coalescing state machine */
1613         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1614
1615         /* Turn on RX BD completion state machine and enable attentions */
1616         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1617             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1618
1619         /* Turn on RX list placement state machine */
1620         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1621
1622         /* Turn on RX list selector state machine. */
1623         if (!BGE_IS_5705_PLUS(sc))
1624                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1625
1626         /* Turn on DMA, clear stats */
1627         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1628             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1629             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1630             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1631             ((sc->bge_flags & BGE_FLAG_TBI) ?
1632              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1633
1634         /* Set misc. local control, enable interrupts on attentions */
1635         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1636
1637 #ifdef notdef
1638         /* Assert GPIO pins for PHY reset */
1639         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1640             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1641         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1642             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1643 #endif
1644
1645         /* Turn on DMA completion state machine */
1646         if (!BGE_IS_5705_PLUS(sc))
1647                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1648
1649         /* Turn on write DMA state machine */
1650         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1651         if (BGE_IS_5755_PLUS(sc)) {
1652                 /* Enable host coalescing bug fix. */
1653                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1654         }
1655         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1656         DELAY(40);
1657
1658         /* Turn on read DMA state machine */
1659         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1660         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1661             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1662             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1663                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1664                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1665                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1666         if (sc->bge_flags & BGE_FLAG_PCIE)
1667                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1668         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1669         DELAY(40);
1670
1671         /* Turn on RX data completion state machine */
1672         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1673
1674         /* Turn on RX BD initiator state machine */
1675         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1676
1677         /* Turn on RX data and RX BD initiator state machine */
1678         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1679
1680         /* Turn on Mbuf cluster free state machine */
1681         if (!BGE_IS_5705_PLUS(sc))
1682                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1683
1684         /* Turn on send BD completion state machine */
1685         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1686
1687         /* Turn on send data completion state machine */
1688         val = BGE_SDCMODE_ENABLE;
1689         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1690                 val |= BGE_SDCMODE_CDELAY; 
1691         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1692
1693         /* Turn on send data initiator state machine */
1694         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1695
1696         /* Turn on send BD initiator state machine */
1697         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1698
1699         /* Turn on send BD selector state machine */
1700         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1701
1702         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1703         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1704             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1705
1706         /* ack/clear link change events */
1707         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1708             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1709             BGE_MACSTAT_LINK_CHANGED);
1710         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1711
1712         /* Enable PHY auto polling (for MII/GMII only) */
1713         if (sc->bge_flags & BGE_FLAG_TBI) {
1714                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1715         } else {
1716                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1717                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1718                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1719                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1720                             BGE_EVTENB_MI_INTERRUPT);
1721                 }
1722         }
1723
1724         /*
1725          * Clear any pending link state attention.
1726          * Otherwise some link state change events may be lost until attention
1727          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1728          * It's not necessary on newer BCM chips - perhaps enabling link
1729          * state change attentions implies clearing pending attention.
1730          */
1731         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1732             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1733             BGE_MACSTAT_LINK_CHANGED);
1734
1735         /* Enable link state change attentions. */
1736         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1737
1738         return(0);
1739 }
1740
1741 /*
1742  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1743  * against our list and return its name if we find a match. Note
1744  * that since the Broadcom controller contains VPD support, we
1745  * can get the device name string from the controller itself instead
1746  * of the compiled-in string. This is a little slow, but it guarantees
1747  * we'll always announce the right product name.
1748  */
1749 static int
1750 bge_probe(device_t dev)
1751 {
1752         const struct bge_type *t;
1753         uint16_t product, vendor;
1754
1755         product = pci_get_device(dev);
1756         vendor = pci_get_vendor(dev);
1757
1758         for (t = bge_devs; t->bge_name != NULL; t++) {
1759                 if (vendor == t->bge_vid && product == t->bge_did)
1760                         break;
1761         }
1762         if (t->bge_name == NULL)
1763                 return(ENXIO);
1764
1765         device_set_desc(dev, t->bge_name);
1766         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1767                 struct bge_softc *sc = device_get_softc(dev);
1768                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1769         }
1770         return(0);
1771 }
1772
1773 static int
1774 bge_attach(device_t dev)
1775 {
1776         struct ifnet *ifp;
1777         struct bge_softc *sc;
1778         uint32_t hwcfg = 0;
1779         int error = 0, rid;
1780         uint8_t ether_addr[ETHER_ADDR_LEN];
1781
1782         sc = device_get_softc(dev);
1783         sc->bge_dev = dev;
1784         callout_init(&sc->bge_stat_timer);
1785         lwkt_serialize_init(&sc->bge_jslot_serializer);
1786
1787 #ifndef BURN_BRIDGES
1788         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1789                 uint32_t irq, mem;
1790
1791                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1792                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1793
1794                 device_printf(dev, "chip is in D%d power mode "
1795                     "-- setting to D0\n", pci_get_powerstate(dev));
1796
1797                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1798
1799                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1800                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1801         }
1802 #endif  /* !BURN_BRIDGE */
1803
1804         /*
1805          * Map control/status registers.
1806          */
1807         pci_enable_busmaster(dev);
1808
1809         rid = BGE_PCI_BAR0;
1810         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1811             RF_ACTIVE);
1812
1813         if (sc->bge_res == NULL) {
1814                 device_printf(dev, "couldn't map memory\n");
1815                 return ENXIO;
1816         }
1817
1818         sc->bge_btag = rman_get_bustag(sc->bge_res);
1819         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1820
1821         /* Save various chip information */
1822         sc->bge_chipid =
1823             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1824             BGE_PCIMISCCTL_ASICREV_SHIFT;
1825         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1826                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1827         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1828         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1829
1830         /* Save chipset family. */
1831         switch (sc->bge_asicrev) {
1832         case BGE_ASICREV_BCM5755:
1833         case BGE_ASICREV_BCM5761:
1834         case BGE_ASICREV_BCM5784:
1835         case BGE_ASICREV_BCM5785:
1836         case BGE_ASICREV_BCM5787:
1837         case BGE_ASICREV_BCM57780:
1838             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1839                 BGE_FLAG_5705_PLUS;
1840             break;
1841
1842         case BGE_ASICREV_BCM5700:
1843         case BGE_ASICREV_BCM5701:
1844         case BGE_ASICREV_BCM5703:
1845         case BGE_ASICREV_BCM5704:
1846                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1847                 break;
1848
1849         case BGE_ASICREV_BCM5714_A0:
1850         case BGE_ASICREV_BCM5780:
1851         case BGE_ASICREV_BCM5714:
1852                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1853                 /* Fall through */
1854
1855         case BGE_ASICREV_BCM5750:
1856         case BGE_ASICREV_BCM5752:
1857         case BGE_ASICREV_BCM5906:
1858                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1859                 /* Fall through */
1860
1861         case BGE_ASICREV_BCM5705:
1862                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1863                 break;
1864         }
1865
1866         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1867                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1868
1869         /*
1870          * Set various quirk flags.
1871          */
1872
1873         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1874         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1875             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1876              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1877               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1878             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1879                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1880
1881         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1882             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1883                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1884
1885         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1886             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1887                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1888
1889         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1890                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1891
1892         if (BGE_IS_5705_PLUS(sc) &&
1893                 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
1894                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1895                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1896                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1897                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1898                         if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0)
1899                             sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1900                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1901                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1902                 }
1903         }
1904
1905         /* Allocate interrupt */
1906         rid = 0;
1907
1908         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1909             RF_SHAREABLE | RF_ACTIVE);
1910
1911         if (sc->bge_irq == NULL) {
1912                 device_printf(dev, "couldn't map interrupt\n");
1913                 error = ENXIO;
1914                 goto fail;
1915         }
1916
1917         /*
1918          * Check if this is a PCI-X or PCI Express device.
1919          */
1920         if (BGE_IS_5705_PLUS(sc)) {
1921                 if (pci_is_pcie(dev)) {
1922                         sc->bge_flags |= BGE_FLAG_PCIE;
1923                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1924                 }
1925         } else {
1926                 /*
1927                  * Check if the device is in PCI-X Mode.
1928                  * (This bit is not valid on PCI Express controllers.)
1929                  */
1930                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1931                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1932                         sc->bge_flags |= BGE_FLAG_PCIX;
1933         }
1934
1935         device_printf(dev, "CHIP ID 0x%08x; "
1936                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1937                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1938                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1939                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1940                         "PCI-E" : "PCI"));
1941
1942         /*
1943          * All controllers that are not 5755 or higher have 4GB
1944          * boundary DMA bug.
1945          * Whenever an address crosses a multiple of the 4GB boundary
1946          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
1947          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
1948          * state machine will lockup and cause the device to hang.
1949          */
1950         if (BGE_IS_5755_PLUS(sc) == 0)
1951                 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
1952
1953         /*
1954          * The 40bit DMA bug applies to the 5714/5715 controllers and is
1955          * not actually a MAC controller bug but an issue with the embedded
1956          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
1957          */
1958         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
1959                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
1960
1961         ifp = &sc->arpcom.ac_if;
1962         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1963
1964         /* Try to reset the chip. */
1965         bge_reset(sc);
1966
1967         if (bge_chipinit(sc)) {
1968                 device_printf(dev, "chip initialization failed\n");
1969                 error = ENXIO;
1970                 goto fail;
1971         }
1972
1973         /*
1974          * Get station address
1975          */
1976         error = bge_get_eaddr(sc, ether_addr);
1977         if (error) {
1978                 device_printf(dev, "failed to read station address\n");
1979                 goto fail;
1980         }
1981
1982         /* 5705/5750 limits RX return ring to 512 entries. */
1983         if (BGE_IS_5705_PLUS(sc))
1984                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1985         else
1986                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1987
1988         error = bge_dma_alloc(sc);
1989         if (error)
1990                 goto fail;
1991
1992         /* Set default tuneable values. */
1993         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1994         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1995         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1996         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1997         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1998
1999         /* Set up ifnet structure */
2000         ifp->if_softc = sc;
2001         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2002         ifp->if_ioctl = bge_ioctl;
2003         ifp->if_start = bge_start;
2004 #ifdef DEVICE_POLLING
2005         ifp->if_poll = bge_poll;
2006 #endif
2007         ifp->if_watchdog = bge_watchdog;
2008         ifp->if_init = bge_init;
2009         ifp->if_mtu = ETHERMTU;
2010         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2011         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2012         ifq_set_ready(&ifp->if_snd);
2013
2014         /*
2015          * 5700 B0 chips do not support checksumming correctly due
2016          * to hardware bugs.
2017          */
2018         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2019                 ifp->if_capabilities |= IFCAP_HWCSUM;
2020                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2021         }
2022         ifp->if_capenable = ifp->if_capabilities;
2023
2024         /*
2025          * Figure out what sort of media we have by checking the
2026          * hardware config word in the first 32k of NIC internal memory,
2027          * or fall back to examining the EEPROM if necessary.
2028          * Note: on some BCM5700 cards, this value appears to be unset.
2029          * If that's the case, we have to rely on identifying the NIC
2030          * by its PCI subsystem ID, as we do below for the SysKonnect
2031          * SK-9D41.
2032          */
2033         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2034                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2035         else {
2036                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2037                                     sizeof(hwcfg))) {
2038                         device_printf(dev, "failed to read EEPROM\n");
2039                         error = ENXIO;
2040                         goto fail;
2041                 }
2042                 hwcfg = ntohl(hwcfg);
2043         }
2044
2045         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2046                 sc->bge_flags |= BGE_FLAG_TBI;
2047
2048         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2049         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
2050                 sc->bge_flags |= BGE_FLAG_TBI;
2051
2052         if (sc->bge_flags & BGE_FLAG_TBI) {
2053                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2054                     bge_ifmedia_upd, bge_ifmedia_sts);
2055                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2056                 ifmedia_add(&sc->bge_ifmedia,
2057                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2058                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2059                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2060                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2061         } else {
2062                 /*
2063                  * Do transceiver setup.
2064                  */
2065                 if (mii_phy_probe(dev, &sc->bge_miibus,
2066                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2067                         device_printf(dev, "MII without any PHY!\n");
2068                         error = ENXIO;
2069                         goto fail;
2070                 }
2071         }
2072
2073         /*
2074          * When using the BCM5701 in PCI-X mode, data corruption has
2075          * been observed in the first few bytes of some received packets.
2076          * Aligning the packet buffer in memory eliminates the corruption.
2077          * Unfortunately, this misaligns the packet payloads.  On platforms
2078          * which do not support unaligned accesses, we will realign the
2079          * payloads by copying the received packets.
2080          */
2081         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2082             (sc->bge_flags & BGE_FLAG_PCIX))
2083                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2084
2085         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2086             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2087                 sc->bge_link_upd = bge_bcm5700_link_upd;
2088                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2089         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2090                 sc->bge_link_upd = bge_tbi_link_upd;
2091                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2092         } else {
2093                 sc->bge_link_upd = bge_copper_link_upd;
2094                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2095         }
2096
2097         /*
2098          * Create sysctl nodes.
2099          */
2100         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2101         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2102                                               SYSCTL_STATIC_CHILDREN(_hw),
2103                                               OID_AUTO,
2104                                               device_get_nameunit(dev),
2105                                               CTLFLAG_RD, 0, "");
2106         if (sc->bge_sysctl_tree == NULL) {
2107                 device_printf(dev, "can't add sysctl node\n");
2108                 error = ENXIO;
2109                 goto fail;
2110         }
2111
2112         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2113                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2114                         OID_AUTO, "rx_coal_ticks",
2115                         CTLTYPE_INT | CTLFLAG_RW,
2116                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2117                         "Receive coalescing ticks (usec).");
2118         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2119                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2120                         OID_AUTO, "tx_coal_ticks",
2121                         CTLTYPE_INT | CTLFLAG_RW,
2122                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2123                         "Transmit coalescing ticks (usec).");
2124         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2125                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2126                         OID_AUTO, "rx_max_coal_bds",
2127                         CTLTYPE_INT | CTLFLAG_RW,
2128                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2129                         "Receive max coalesced BD count.");
2130         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2131                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2132                         OID_AUTO, "tx_max_coal_bds",
2133                         CTLTYPE_INT | CTLFLAG_RW,
2134                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2135                         "Transmit max coalesced BD count.");
2136
2137         /*
2138          * Call MI attach routine.
2139          */
2140         ether_ifattach(ifp, ether_addr, NULL);
2141
2142         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2143                                bge_intr, sc, &sc->bge_intrhand, 
2144                                ifp->if_serializer);
2145         if (error) {
2146                 ether_ifdetach(ifp);
2147                 device_printf(dev, "couldn't set up irq\n");
2148                 goto fail;
2149         }
2150
2151         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2152         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2153
2154         return(0);
2155 fail:
2156         bge_detach(dev);
2157         return(error);
2158 }
2159
2160 static int
2161 bge_detach(device_t dev)
2162 {
2163         struct bge_softc *sc = device_get_softc(dev);
2164
2165         if (device_is_attached(dev)) {
2166                 struct ifnet *ifp = &sc->arpcom.ac_if;
2167
2168                 lwkt_serialize_enter(ifp->if_serializer);
2169                 bge_stop(sc);
2170                 bge_reset(sc);
2171                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2172                 lwkt_serialize_exit(ifp->if_serializer);
2173
2174                 ether_ifdetach(ifp);
2175         }
2176
2177         if (sc->bge_flags & BGE_FLAG_TBI)
2178                 ifmedia_removeall(&sc->bge_ifmedia);
2179         if (sc->bge_miibus)
2180                 device_delete_child(dev, sc->bge_miibus);
2181         bus_generic_detach(dev);
2182
2183         if (sc->bge_irq != NULL)
2184                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2185
2186         if (sc->bge_res != NULL)
2187                 bus_release_resource(dev, SYS_RES_MEMORY,
2188                     BGE_PCI_BAR0, sc->bge_res);
2189
2190         if (sc->bge_sysctl_tree != NULL)
2191                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2192
2193         bge_dma_free(sc);
2194
2195         return 0;
2196 }
2197
2198 static void
2199 bge_reset(struct bge_softc *sc)
2200 {
2201         device_t dev;
2202         uint32_t cachesize, command, pcistate, reset;
2203         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2204         int i, val = 0;
2205
2206         dev = sc->bge_dev;
2207
2208         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2209             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2210                 if (sc->bge_flags & BGE_FLAG_PCIE)
2211                         write_op = bge_writemem_direct;
2212                 else
2213                         write_op = bge_writemem_ind;
2214         } else {
2215                 write_op = bge_writereg_ind;
2216         }
2217
2218         /* Save some important PCI state. */
2219         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2220         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2221         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2222
2223         pci_write_config(dev, BGE_PCI_MISC_CTL,
2224             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2225             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2226
2227         /* Disable fastboot on controllers that support it. */
2228         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2229             BGE_IS_5755_PLUS(sc)) {
2230                 if (bootverbose)
2231                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2232                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2233         }
2234
2235         /*
2236          * Write the magic number to SRAM at offset 0xB50.
2237          * When firmware finishes its initialization it will
2238          * write ~BGE_MAGIC_NUMBER to the same location.
2239          */
2240         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2241
2242         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2243
2244         /* XXX: Broadcom Linux driver. */
2245         if (sc->bge_flags & BGE_FLAG_PCIE) {
2246                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2247                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2248                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2249                         /* Prevent PCIE link training during global reset */
2250                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2251                         reset |= (1<<29);
2252                 }
2253         }
2254
2255         /* 
2256          * Set GPHY Power Down Override to leave GPHY
2257          * powered up in D0 uninitialized.
2258          */
2259         if (BGE_IS_5705_PLUS(sc))
2260                 reset |= 0x04000000;
2261
2262         /* Issue global reset */
2263         write_op(sc, BGE_MISC_CFG, reset);
2264
2265         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2266                 uint32_t status, ctrl;
2267
2268                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2269                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2270                     status | BGE_VCPU_STATUS_DRV_RESET);
2271                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2272                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2273                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2274         }
2275
2276         DELAY(1000);
2277
2278         /* XXX: Broadcom Linux driver. */
2279         if (sc->bge_flags & BGE_FLAG_PCIE) {
2280                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2281                         uint32_t v;
2282
2283                         DELAY(500000); /* wait for link training to complete */
2284                         v = pci_read_config(dev, 0xc4, 4);
2285                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2286                 }
2287                 /*
2288                  * Set PCIE max payload size to 128 bytes and
2289                  * clear error status.
2290                  */
2291                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2292         }
2293
2294         /* Reset some of the PCI state that got zapped by reset */
2295         pci_write_config(dev, BGE_PCI_MISC_CTL,
2296             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2297             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2298         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2299         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2300         write_op(sc, BGE_MISC_CFG, (65 << 1));
2301
2302         /* Enable memory arbiter. */
2303         if (BGE_IS_5714_FAMILY(sc)) {
2304                 uint32_t val;
2305
2306                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2307                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2308         } else {
2309                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2310         }
2311
2312         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2313                 for (i = 0; i < BGE_TIMEOUT; i++) {
2314                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2315                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2316                                 break;
2317                         DELAY(100);
2318                 }
2319                 if (i == BGE_TIMEOUT) {
2320                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2321                         return;
2322                 }
2323         } else {
2324                 /*
2325                  * Poll until we see the 1's complement of the magic number.
2326                  * This indicates that the firmware initialization
2327                  * is complete.
2328                  */
2329                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2330                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2331                         if (val == ~BGE_MAGIC_NUMBER)
2332                                 break;
2333                         DELAY(10);
2334                 }
2335                 if (i == BGE_FIRMWARE_TIMEOUT) {
2336                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2337                                   "timed out, found 0x%08x\n", val);
2338                         return;
2339                 }
2340         }
2341
2342         /*
2343          * XXX Wait for the value of the PCISTATE register to
2344          * return to its original pre-reset state. This is a
2345          * fairly good indicator of reset completion. If we don't
2346          * wait for the reset to fully complete, trying to read
2347          * from the device's non-PCI registers may yield garbage
2348          * results.
2349          */
2350         for (i = 0; i < BGE_TIMEOUT; i++) {
2351                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2352                         break;
2353                 DELAY(10);
2354         }
2355
2356         if (sc->bge_flags & BGE_FLAG_PCIE) {
2357                 reset = bge_readmem_ind(sc, 0x7c00);
2358                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2359         }
2360
2361         /* Fix up byte swapping */
2362         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2363             BGE_MODECTL_BYTESWAP_DATA);
2364
2365         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2366
2367         /*
2368          * The 5704 in TBI mode apparently needs some special
2369          * adjustment to insure the SERDES drive level is set
2370          * to 1.2V.
2371          */
2372         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2373             (sc->bge_flags & BGE_FLAG_TBI)) {
2374                 uint32_t serdescfg;
2375
2376                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2377                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2378                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2379         }
2380
2381         /* XXX: Broadcom Linux driver. */
2382         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2383             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2384                 uint32_t v;
2385
2386                 v = CSR_READ_4(sc, 0x7c00);
2387                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2388         }
2389
2390         DELAY(10000);
2391 }
2392
2393 /*
2394  * Frame reception handling. This is called if there's a frame
2395  * on the receive return list.
2396  *
2397  * Note: we have to be able to handle two possibilities here:
2398  * 1) the frame is from the jumbo recieve ring
2399  * 2) the frame is from the standard receive ring
2400  */
2401
2402 static void
2403 bge_rxeof(struct bge_softc *sc)
2404 {
2405         struct ifnet *ifp;
2406         int stdcnt = 0, jumbocnt = 0;
2407
2408         if (sc->bge_rx_saved_considx ==
2409             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2410                 return;
2411
2412         ifp = &sc->arpcom.ac_if;
2413
2414         while (sc->bge_rx_saved_considx !=
2415                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2416                 struct bge_rx_bd        *cur_rx;
2417                 uint32_t                rxidx;
2418                 struct mbuf             *m = NULL;
2419                 uint16_t                vlan_tag = 0;
2420                 int                     have_tag = 0;
2421
2422                 cur_rx =
2423             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2424
2425                 rxidx = cur_rx->bge_idx;
2426                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2427                 logif(rx_pkt);
2428
2429                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2430                         have_tag = 1;
2431                         vlan_tag = cur_rx->bge_vlan_tag;
2432                 }
2433
2434                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2435                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2436                         jumbocnt++;
2437
2438                         if (rxidx != sc->bge_jumbo) {
2439                                 ifp->if_ierrors++;
2440                                 if_printf(ifp, "sw jumbo index(%d) "
2441                                     "and hw jumbo index(%d) mismatch, drop!\n",
2442                                     sc->bge_jumbo, rxidx);
2443                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2444                                 continue;
2445                         }
2446
2447                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2448                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2449                                 ifp->if_ierrors++;
2450                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2451                                 continue;
2452                         }
2453                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2454                                 ifp->if_ierrors++;
2455                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2456                                 continue;
2457                         }
2458                 } else {
2459                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2460                         stdcnt++;
2461
2462                         if (rxidx != sc->bge_std) {
2463                                 ifp->if_ierrors++;
2464                                 if_printf(ifp, "sw std index(%d) "
2465                                     "and hw std index(%d) mismatch, drop!\n",
2466                                     sc->bge_std, rxidx);
2467                                 bge_setup_rxdesc_std(sc, rxidx);
2468                                 continue;
2469                         }
2470
2471                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2472                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2473                                 ifp->if_ierrors++;
2474                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2475                                 continue;
2476                         }
2477                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2478                                 ifp->if_ierrors++;
2479                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2480                                 continue;
2481                         }
2482                 }
2483
2484                 ifp->if_ipackets++;
2485 #ifndef __i386__
2486                 /*
2487                  * The i386 allows unaligned accesses, but for other
2488                  * platforms we must make sure the payload is aligned.
2489                  */
2490                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2491                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2492                             cur_rx->bge_len);
2493                         m->m_data += ETHER_ALIGN;
2494                 }
2495 #endif
2496                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2497                 m->m_pkthdr.rcvif = ifp;
2498
2499                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2500                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2501                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2502                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2503                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2504                         }
2505                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2506                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2507                                 m->m_pkthdr.csum_data =
2508                                         cur_rx->bge_tcp_udp_csum;
2509                                 m->m_pkthdr.csum_flags |=
2510                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2511                         }
2512                 }
2513
2514                 /*
2515                  * If we received a packet with a vlan tag, pass it
2516                  * to vlan_input() instead of ether_input().
2517                  */
2518                 if (have_tag) {
2519                         m->m_flags |= M_VLANTAG;
2520                         m->m_pkthdr.ether_vlantag = vlan_tag;
2521                         have_tag = vlan_tag = 0;
2522                 }
2523                 ifp->if_input(ifp, m);
2524         }
2525
2526         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2527         if (stdcnt)
2528                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2529         if (jumbocnt)
2530                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2531 }
2532
2533 static void
2534 bge_txeof(struct bge_softc *sc)
2535 {
2536         struct bge_tx_bd *cur_tx = NULL;
2537         struct ifnet *ifp;
2538
2539         if (sc->bge_tx_saved_considx ==
2540             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2541                 return;
2542
2543         ifp = &sc->arpcom.ac_if;
2544
2545         /*
2546          * Go through our tx ring and free mbufs for those
2547          * frames that have been sent.
2548          */
2549         while (sc->bge_tx_saved_considx !=
2550                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2551                 uint32_t idx = 0;
2552
2553                 idx = sc->bge_tx_saved_considx;
2554                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2555                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2556                         ifp->if_opackets++;
2557                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2558                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2559                             sc->bge_cdata.bge_tx_dmamap[idx]);
2560                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2561                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2562                 }
2563                 sc->bge_txcnt--;
2564                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2565                 logif(tx_pkt);
2566         }
2567
2568         if (cur_tx != NULL &&
2569             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2570             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2571                 ifp->if_flags &= ~IFF_OACTIVE;
2572
2573         if (sc->bge_txcnt == 0)
2574                 ifp->if_timer = 0;
2575
2576         if (!ifq_is_empty(&ifp->if_snd))
2577                 if_devstart(ifp);
2578 }
2579
2580 #ifdef DEVICE_POLLING
2581
2582 static void
2583 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2584 {
2585         struct bge_softc *sc = ifp->if_softc;
2586         uint32_t status;
2587
2588         switch(cmd) {
2589         case POLL_REGISTER:
2590                 bge_disable_intr(sc);
2591                 break;
2592         case POLL_DEREGISTER:
2593                 bge_enable_intr(sc);
2594                 break;
2595         case POLL_AND_CHECK_STATUS:
2596                 /*
2597                  * Process link state changes.
2598                  */
2599                 status = CSR_READ_4(sc, BGE_MAC_STS);
2600                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2601                         sc->bge_link_evt = 0;
2602                         sc->bge_link_upd(sc, status);
2603                 }
2604                 /* fall through */
2605         case POLL_ONLY:
2606                 if (ifp->if_flags & IFF_RUNNING) {
2607                         bge_rxeof(sc);
2608                         bge_txeof(sc);
2609                 }
2610                 break;
2611         }
2612 }
2613
2614 #endif
2615
2616 static void
2617 bge_intr(void *xsc)
2618 {
2619         struct bge_softc *sc = xsc;
2620         struct ifnet *ifp = &sc->arpcom.ac_if;
2621         uint32_t status;
2622
2623         logif(intr);
2624
2625         /*
2626          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2627          * disable interrupts by writing nonzero like we used to, since with
2628          * our current organization this just gives complications and
2629          * pessimizations for re-enabling interrupts.  We used to have races
2630          * instead of the necessary complications.  Disabling interrupts
2631          * would just reduce the chance of a status update while we are
2632          * running (by switching to the interrupt-mode coalescence
2633          * parameters), but this chance is already very low so it is more
2634          * efficient to get another interrupt than prevent it.
2635          *
2636          * We do the ack first to ensure another interrupt if there is a
2637          * status update after the ack.  We don't check for the status
2638          * changing later because it is more efficient to get another
2639          * interrupt than prevent it, not quite as above (not checking is
2640          * a smaller optimization than not toggling the interrupt enable,
2641          * since checking doesn't involve PCI accesses and toggling require
2642          * the status check).  So toggling would probably be a pessimization
2643          * even with MSI.  It would only be needed for using a task queue.
2644          */
2645         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2646
2647         /*
2648          * Process link state changes.
2649          */
2650         status = CSR_READ_4(sc, BGE_MAC_STS);
2651         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2652                 sc->bge_link_evt = 0;
2653                 sc->bge_link_upd(sc, status);
2654         }
2655
2656         if (ifp->if_flags & IFF_RUNNING) {
2657                 /* Check RX return ring producer/consumer */
2658                 bge_rxeof(sc);
2659
2660                 /* Check TX ring producer/consumer */
2661                 bge_txeof(sc);
2662         }
2663
2664         if (sc->bge_coal_chg)
2665                 bge_coal_change(sc);
2666 }
2667
2668 static void
2669 bge_tick(void *xsc)
2670 {
2671         struct bge_softc *sc = xsc;
2672         struct ifnet *ifp = &sc->arpcom.ac_if;
2673
2674         lwkt_serialize_enter(ifp->if_serializer);
2675
2676         if (BGE_IS_5705_PLUS(sc))
2677                 bge_stats_update_regs(sc);
2678         else
2679                 bge_stats_update(sc);
2680
2681         if (sc->bge_flags & BGE_FLAG_TBI) {
2682                 /*
2683                  * Since in TBI mode auto-polling can't be used we should poll
2684                  * link status manually. Here we register pending link event
2685                  * and trigger interrupt.
2686                  */
2687                 sc->bge_link_evt++;
2688                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2689         } else if (!sc->bge_link) {
2690                 mii_tick(device_get_softc(sc->bge_miibus));
2691         }
2692
2693         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2694
2695         lwkt_serialize_exit(ifp->if_serializer);
2696 }
2697
2698 static void
2699 bge_stats_update_regs(struct bge_softc *sc)
2700 {
2701         struct ifnet *ifp = &sc->arpcom.ac_if;
2702         struct bge_mac_stats_regs stats;
2703         uint32_t *s;
2704         int i;
2705
2706         s = (uint32_t *)&stats;
2707         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2708                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2709                 s++;
2710         }
2711
2712         ifp->if_collisions +=
2713            (stats.dot3StatsSingleCollisionFrames +
2714            stats.dot3StatsMultipleCollisionFrames +
2715            stats.dot3StatsExcessiveCollisions +
2716            stats.dot3StatsLateCollisions) -
2717            ifp->if_collisions;
2718 }
2719
2720 static void
2721 bge_stats_update(struct bge_softc *sc)
2722 {
2723         struct ifnet *ifp = &sc->arpcom.ac_if;
2724         bus_size_t stats;
2725
2726         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2727
2728 #define READ_STAT(sc, stats, stat)      \
2729         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2730
2731         ifp->if_collisions +=
2732            (READ_STAT(sc, stats,
2733                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2734             READ_STAT(sc, stats,
2735                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2736             READ_STAT(sc, stats,
2737                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2738             READ_STAT(sc, stats,
2739                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2740            ifp->if_collisions;
2741
2742 #undef READ_STAT
2743
2744 #ifdef notdef
2745         ifp->if_collisions +=
2746            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2747            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2748            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2749            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2750            ifp->if_collisions;
2751 #endif
2752 }
2753
2754 /*
2755  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2756  * pointers to descriptors.
2757  */
2758 static int
2759 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2760 {
2761         struct bge_tx_bd *d = NULL;
2762         uint16_t csum_flags = 0;
2763         bus_dma_segment_t segs[BGE_NSEG_NEW];
2764         bus_dmamap_t map;
2765         int error, maxsegs, nsegs, idx, i;
2766         struct mbuf *m_head = *m_head0;
2767
2768         if (m_head->m_pkthdr.csum_flags) {
2769                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2770                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2771                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2772                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2773                 if (m_head->m_flags & M_LASTFRAG)
2774                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2775                 else if (m_head->m_flags & M_FRAG)
2776                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2777         }
2778
2779         idx = *txidx;
2780         map = sc->bge_cdata.bge_tx_dmamap[idx];
2781
2782         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2783         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2784                 ("not enough segments %d", maxsegs));
2785
2786         if (maxsegs > BGE_NSEG_NEW)
2787                 maxsegs = BGE_NSEG_NEW;
2788
2789         /*
2790          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2791          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2792          * but when such padded frames employ the bge IP/TCP checksum
2793          * offload, the hardware checksum assist gives incorrect results
2794          * (possibly from incorporating its own padding into the UDP/TCP
2795          * checksum; who knows).  If we pad such runts with zeros, the
2796          * onboard checksum comes out correct.
2797          */
2798         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2799             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2800                 error = m_devpad(m_head, BGE_MIN_FRAME);
2801                 if (error)
2802                         goto back;
2803         }
2804
2805         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2806                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2807         if (error)
2808                 goto back;
2809
2810         m_head = *m_head0;
2811         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2812
2813         for (i = 0; ; i++) {
2814                 d = &sc->bge_ldata.bge_tx_ring[idx];
2815
2816                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2817                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2818                 d->bge_len = segs[i].ds_len;
2819                 d->bge_flags = csum_flags;
2820
2821                 if (i == nsegs - 1)
2822                         break;
2823                 BGE_INC(idx, BGE_TX_RING_CNT);
2824         }
2825         /* Mark the last segment as end of packet... */
2826         d->bge_flags |= BGE_TXBDFLAG_END;
2827
2828         /* Set vlan tag to the first segment of the packet. */
2829         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2830         if (m_head->m_flags & M_VLANTAG) {
2831                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2832                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2833         } else {
2834                 d->bge_vlan_tag = 0;
2835         }
2836
2837         /*
2838          * Insure that the map for this transmission is placed at
2839          * the array index of the last descriptor in this chain.
2840          */
2841         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2842         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2843         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2844         sc->bge_txcnt += nsegs;
2845
2846         BGE_INC(idx, BGE_TX_RING_CNT);
2847         *txidx = idx;
2848 back:
2849         if (error) {
2850                 m_freem(*m_head0);
2851                 *m_head0 = NULL;
2852         }
2853         return error;
2854 }
2855
2856 /*
2857  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2858  * to the mbuf data regions directly in the transmit descriptors.
2859  */
2860 static void
2861 bge_start(struct ifnet *ifp)
2862 {
2863         struct bge_softc *sc = ifp->if_softc;
2864         struct mbuf *m_head = NULL;
2865         uint32_t prodidx;
2866         int need_trans;
2867
2868         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2869                 return;
2870
2871         prodidx = sc->bge_tx_prodidx;
2872
2873         need_trans = 0;
2874         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2875                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2876                 if (m_head == NULL)
2877                         break;
2878
2879                 /*
2880                  * XXX
2881                  * The code inside the if() block is never reached since we
2882                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2883                  * requests to checksum TCP/UDP in a fragmented packet.
2884                  * 
2885                  * XXX
2886                  * safety overkill.  If this is a fragmented packet chain
2887                  * with delayed TCP/UDP checksums, then only encapsulate
2888                  * it if we have enough descriptors to handle the entire
2889                  * chain at once.
2890                  * (paranoia -- may not actually be needed)
2891                  */
2892                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2893                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2894                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2895                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2896                                 ifp->if_flags |= IFF_OACTIVE;
2897                                 ifq_prepend(&ifp->if_snd, m_head);
2898                                 break;
2899                         }
2900                 }
2901
2902                 /*
2903                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2904                  * descriptors of the end of the ring.  Also make
2905                  * sure there are BGE_NSEG_SPARE descriptors for
2906                  * jumbo buffers' defragmentation.
2907                  */
2908                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2909                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2910                         ifp->if_flags |= IFF_OACTIVE;
2911                         ifq_prepend(&ifp->if_snd, m_head);
2912                         break;
2913                 }
2914
2915                 /*
2916                  * Pack the data into the transmit ring. If we
2917                  * don't have room, set the OACTIVE flag and wait
2918                  * for the NIC to drain the ring.
2919                  */
2920                 if (bge_encap(sc, &m_head, &prodidx)) {
2921                         ifp->if_flags |= IFF_OACTIVE;
2922                         ifp->if_oerrors++;
2923                         break;
2924                 }
2925                 need_trans = 1;
2926
2927                 ETHER_BPF_MTAP(ifp, m_head);
2928         }
2929
2930         if (!need_trans)
2931                 return;
2932
2933         /* Transmit */
2934         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2935         /* 5700 b2 errata */
2936         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2937                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2938
2939         sc->bge_tx_prodidx = prodidx;
2940
2941         /*
2942          * Set a timeout in case the chip goes out to lunch.
2943          */
2944         ifp->if_timer = 5;
2945 }
2946
2947 static void
2948 bge_init(void *xsc)
2949 {
2950         struct bge_softc *sc = xsc;
2951         struct ifnet *ifp = &sc->arpcom.ac_if;
2952         uint16_t *m;
2953
2954         ASSERT_SERIALIZED(ifp->if_serializer);
2955
2956         if (ifp->if_flags & IFF_RUNNING)
2957                 return;
2958
2959         /* Cancel pending I/O and flush buffers. */
2960         bge_stop(sc);
2961         bge_reset(sc);
2962         bge_chipinit(sc);
2963
2964         /*
2965          * Init the various state machines, ring
2966          * control blocks and firmware.
2967          */
2968         if (bge_blockinit(sc)) {
2969                 if_printf(ifp, "initialization failure\n");
2970                 bge_stop(sc);
2971                 return;
2972         }
2973
2974         /* Specify MTU. */
2975         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2976             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2977
2978         /* Load our MAC address. */
2979         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2980         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2981         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2982
2983         /* Enable or disable promiscuous mode as needed. */
2984         bge_setpromisc(sc);
2985
2986         /* Program multicast filter. */
2987         bge_setmulti(sc);
2988
2989         /* Init RX ring. */
2990         if (bge_init_rx_ring_std(sc)) {
2991                 if_printf(ifp, "RX ring initialization failed\n");
2992                 bge_stop(sc);
2993                 return;
2994         }
2995
2996         /*
2997          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2998          * memory to insure that the chip has in fact read the first
2999          * entry of the ring.
3000          */
3001         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3002                 uint32_t                v, i;
3003                 for (i = 0; i < 10; i++) {
3004                         DELAY(20);
3005                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3006                         if (v == (MCLBYTES - ETHER_ALIGN))
3007                                 break;
3008                 }
3009                 if (i == 10)
3010                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3011         }
3012
3013         /* Init jumbo RX ring. */
3014         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3015                 if (bge_init_rx_ring_jumbo(sc)) {
3016                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3017                         bge_stop(sc);
3018                         return;
3019                 }
3020         }
3021
3022         /* Init our RX return ring index */
3023         sc->bge_rx_saved_considx = 0;
3024
3025         /* Init TX ring. */
3026         bge_init_tx_ring(sc);
3027
3028         /* Turn on transmitter */
3029         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3030
3031         /* Turn on receiver */
3032         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3033
3034         /* Tell firmware we're alive. */
3035         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3036
3037         /* Enable host interrupts if polling(4) is not enabled. */
3038         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3039 #ifdef DEVICE_POLLING
3040         if (ifp->if_flags & IFF_POLLING)
3041                 bge_disable_intr(sc);
3042         else
3043 #endif
3044         bge_enable_intr(sc);
3045
3046         bge_ifmedia_upd(ifp);
3047
3048         ifp->if_flags |= IFF_RUNNING;
3049         ifp->if_flags &= ~IFF_OACTIVE;
3050
3051         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3052 }
3053
3054 /*
3055  * Set media options.
3056  */
3057 static int
3058 bge_ifmedia_upd(struct ifnet *ifp)
3059 {
3060         struct bge_softc *sc = ifp->if_softc;
3061
3062         /* If this is a 1000baseX NIC, enable the TBI port. */
3063         if (sc->bge_flags & BGE_FLAG_TBI) {
3064                 struct ifmedia *ifm = &sc->bge_ifmedia;
3065
3066                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3067                         return(EINVAL);
3068
3069                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3070                 case IFM_AUTO:
3071                         /*
3072                          * The BCM5704 ASIC appears to have a special
3073                          * mechanism for programming the autoneg
3074                          * advertisement registers in TBI mode.
3075                          */
3076                         if (!bge_fake_autoneg &&
3077                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3078                                 uint32_t sgdig;
3079
3080                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3081                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3082                                 sgdig |= BGE_SGDIGCFG_AUTO |
3083                                          BGE_SGDIGCFG_PAUSE_CAP |
3084                                          BGE_SGDIGCFG_ASYM_PAUSE;
3085                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3086                                             sgdig | BGE_SGDIGCFG_SEND);
3087                                 DELAY(5);
3088                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3089                         }
3090                         break;
3091                 case IFM_1000_SX:
3092                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3093                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3094                                     BGE_MACMODE_HALF_DUPLEX);
3095                         } else {
3096                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3097                                     BGE_MACMODE_HALF_DUPLEX);
3098                         }
3099                         break;
3100                 default:
3101                         return(EINVAL);
3102                 }
3103         } else {
3104                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3105
3106                 sc->bge_link_evt++;
3107                 sc->bge_link = 0;
3108                 if (mii->mii_instance) {
3109                         struct mii_softc *miisc;
3110
3111                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3112                                 mii_phy_reset(miisc);
3113                 }
3114                 mii_mediachg(mii);
3115         }
3116         return(0);
3117 }
3118
3119 /*
3120  * Report current media status.
3121  */
3122 static void
3123 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3124 {
3125         struct bge_softc *sc = ifp->if_softc;
3126
3127         if (sc->bge_flags & BGE_FLAG_TBI) {
3128                 ifmr->ifm_status = IFM_AVALID;
3129                 ifmr->ifm_active = IFM_ETHER;
3130                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3131                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3132                         ifmr->ifm_status |= IFM_ACTIVE;
3133                 } else {
3134                         ifmr->ifm_active |= IFM_NONE;
3135                         return;
3136                 }
3137
3138                 ifmr->ifm_active |= IFM_1000_SX;
3139                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3140                         ifmr->ifm_active |= IFM_HDX;    
3141                 else
3142                         ifmr->ifm_active |= IFM_FDX;
3143         } else {
3144                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3145
3146                 mii_pollstat(mii);
3147                 ifmr->ifm_active = mii->mii_media_active;
3148                 ifmr->ifm_status = mii->mii_media_status;
3149         }
3150 }
3151
3152 static int
3153 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3154 {
3155         struct bge_softc *sc = ifp->if_softc;
3156         struct ifreq *ifr = (struct ifreq *)data;
3157         int mask, error = 0;
3158
3159         ASSERT_SERIALIZED(ifp->if_serializer);
3160
3161         switch (command) {
3162         case SIOCSIFMTU:
3163                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3164                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3165                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3166                         error = EINVAL;
3167                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3168                         ifp->if_mtu = ifr->ifr_mtu;
3169                         ifp->if_flags &= ~IFF_RUNNING;
3170                         bge_init(sc);
3171                 }
3172                 break;
3173         case SIOCSIFFLAGS:
3174                 if (ifp->if_flags & IFF_UP) {
3175                         if (ifp->if_flags & IFF_RUNNING) {
3176                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3177
3178                                 /*
3179                                  * If only the state of the PROMISC flag
3180                                  * changed, then just use the 'set promisc
3181                                  * mode' command instead of reinitializing
3182                                  * the entire NIC. Doing a full re-init
3183                                  * means reloading the firmware and waiting
3184                                  * for it to start up, which may take a
3185                                  * second or two.  Similarly for ALLMULTI.
3186                                  */
3187                                 if (mask & IFF_PROMISC)
3188                                         bge_setpromisc(sc);
3189                                 if (mask & IFF_ALLMULTI)
3190                                         bge_setmulti(sc);
3191                         } else {
3192                                 bge_init(sc);
3193                         }
3194                 } else {
3195                         if (ifp->if_flags & IFF_RUNNING)
3196                                 bge_stop(sc);
3197                 }
3198                 sc->bge_if_flags = ifp->if_flags;
3199                 break;
3200         case SIOCADDMULTI:
3201         case SIOCDELMULTI:
3202                 if (ifp->if_flags & IFF_RUNNING)
3203                         bge_setmulti(sc);
3204                 break;
3205         case SIOCSIFMEDIA:
3206         case SIOCGIFMEDIA:
3207                 if (sc->bge_flags & BGE_FLAG_TBI) {
3208                         error = ifmedia_ioctl(ifp, ifr,
3209                             &sc->bge_ifmedia, command);
3210                 } else {
3211                         struct mii_data *mii;
3212
3213                         mii = device_get_softc(sc->bge_miibus);
3214                         error = ifmedia_ioctl(ifp, ifr,
3215                                               &mii->mii_media, command);
3216                 }
3217                 break;
3218         case SIOCSIFCAP:
3219                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3220                 if (mask & IFCAP_HWCSUM) {
3221                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3222                         if (IFCAP_HWCSUM & ifp->if_capenable)
3223                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3224                         else
3225                                 ifp->if_hwassist = 0;
3226                 }
3227                 break;
3228         default:
3229                 error = ether_ioctl(ifp, command, data);
3230                 break;
3231         }
3232         return error;
3233 }
3234
3235 static void
3236 bge_watchdog(struct ifnet *ifp)
3237 {
3238         struct bge_softc *sc = ifp->if_softc;
3239
3240         if_printf(ifp, "watchdog timeout -- resetting\n");
3241
3242         ifp->if_flags &= ~IFF_RUNNING;
3243         bge_init(sc);
3244
3245         ifp->if_oerrors++;
3246
3247         if (!ifq_is_empty(&ifp->if_snd))
3248                 if_devstart(ifp);
3249 }
3250
3251 /*
3252  * Stop the adapter and free any mbufs allocated to the
3253  * RX and TX lists.
3254  */
3255 static void
3256 bge_stop(struct bge_softc *sc)
3257 {
3258         struct ifnet *ifp = &sc->arpcom.ac_if;
3259
3260         ASSERT_SERIALIZED(ifp->if_serializer);
3261
3262         callout_stop(&sc->bge_stat_timer);
3263
3264         /*
3265          * Disable all of the receiver blocks
3266          */
3267         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3268         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3269         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3270         if (!BGE_IS_5705_PLUS(sc))
3271                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3272         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3273         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3274         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3275
3276         /*
3277          * Disable all of the transmit blocks
3278          */
3279         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3280         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3281         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3282         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3283         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3284         if (!BGE_IS_5705_PLUS(sc))
3285                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3286         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3287
3288         /*
3289          * Shut down all of the memory managers and related
3290          * state machines.
3291          */
3292         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3293         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3294         if (!BGE_IS_5705_PLUS(sc))
3295                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3296         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3297         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3298         if (!BGE_IS_5705_PLUS(sc)) {
3299                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3300                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3301         }
3302
3303         /* Disable host interrupts. */
3304         bge_disable_intr(sc);
3305
3306         /*
3307          * Tell firmware we're shutting down.
3308          */
3309         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3310
3311         /* Free the RX lists. */
3312         bge_free_rx_ring_std(sc);
3313
3314         /* Free jumbo RX list. */
3315         if (BGE_IS_JUMBO_CAPABLE(sc))
3316                 bge_free_rx_ring_jumbo(sc);
3317
3318         /* Free TX buffers. */
3319         bge_free_tx_ring(sc);
3320
3321         sc->bge_link = 0;
3322         sc->bge_coal_chg = 0;
3323
3324         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3325
3326         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3327         ifp->if_timer = 0;
3328 }
3329
3330 /*
3331  * Stop all chip I/O so that the kernel's probe routines don't
3332  * get confused by errant DMAs when rebooting.
3333  */
3334 static void
3335 bge_shutdown(device_t dev)
3336 {
3337         struct bge_softc *sc = device_get_softc(dev);
3338         struct ifnet *ifp = &sc->arpcom.ac_if;
3339
3340         lwkt_serialize_enter(ifp->if_serializer);
3341         bge_stop(sc);
3342         bge_reset(sc);
3343         lwkt_serialize_exit(ifp->if_serializer);
3344 }
3345
3346 static int
3347 bge_suspend(device_t dev)
3348 {
3349         struct bge_softc *sc = device_get_softc(dev);
3350         struct ifnet *ifp = &sc->arpcom.ac_if;
3351
3352         lwkt_serialize_enter(ifp->if_serializer);
3353         bge_stop(sc);
3354         lwkt_serialize_exit(ifp->if_serializer);
3355
3356         return 0;
3357 }
3358
3359 static int
3360 bge_resume(device_t dev)
3361 {
3362         struct bge_softc *sc = device_get_softc(dev);
3363         struct ifnet *ifp = &sc->arpcom.ac_if;
3364
3365         lwkt_serialize_enter(ifp->if_serializer);
3366
3367         if (ifp->if_flags & IFF_UP) {
3368                 bge_init(sc);
3369
3370                 if (!ifq_is_empty(&ifp->if_snd))
3371                         if_devstart(ifp);
3372         }
3373
3374         lwkt_serialize_exit(ifp->if_serializer);
3375
3376         return 0;
3377 }
3378
3379 static void
3380 bge_setpromisc(struct bge_softc *sc)
3381 {
3382         struct ifnet *ifp = &sc->arpcom.ac_if;
3383
3384         if (ifp->if_flags & IFF_PROMISC)
3385                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3386         else
3387                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3388 }
3389
3390 static void
3391 bge_dma_free(struct bge_softc *sc)
3392 {
3393         int i;
3394
3395         /* Destroy RX mbuf DMA stuffs. */
3396         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3397                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3398                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3399                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3400                 }
3401                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3402                                    sc->bge_cdata.bge_rx_tmpmap);
3403                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3404         }
3405
3406         /* Destroy TX mbuf DMA stuffs. */
3407         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3408                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3409                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3410                             sc->bge_cdata.bge_tx_dmamap[i]);
3411                 }
3412                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3413         }
3414
3415         /* Destroy standard RX ring */
3416         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3417                            sc->bge_cdata.bge_rx_std_ring_map,
3418                            sc->bge_ldata.bge_rx_std_ring);
3419
3420         if (BGE_IS_JUMBO_CAPABLE(sc))
3421                 bge_free_jumbo_mem(sc);
3422
3423         /* Destroy RX return ring */
3424         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3425                            sc->bge_cdata.bge_rx_return_ring_map,
3426                            sc->bge_ldata.bge_rx_return_ring);
3427
3428         /* Destroy TX ring */
3429         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3430                            sc->bge_cdata.bge_tx_ring_map,
3431                            sc->bge_ldata.bge_tx_ring);
3432
3433         /* Destroy status block */
3434         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3435                            sc->bge_cdata.bge_status_map,
3436                            sc->bge_ldata.bge_status_block);
3437
3438         /* Destroy statistics block */
3439         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3440                            sc->bge_cdata.bge_stats_map,
3441                            sc->bge_ldata.bge_stats);
3442
3443         /* Destroy the parent tag */
3444         if (sc->bge_cdata.bge_parent_tag != NULL)
3445                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3446 }
3447
3448 static int
3449 bge_dma_alloc(struct bge_softc *sc)
3450 {
3451         struct ifnet *ifp = &sc->arpcom.ac_if;
3452         int i, error;
3453         bus_addr_t lowaddr;
3454         bus_size_t boundary;
3455
3456         boundary = 0;
3457         if (sc->bge_flags & BGE_FLAG_BOUNDARY_4G)
3458                 boundary = BGE_DMA_BOUNDARY_4G;
3459
3460         lowaddr = BUS_SPACE_MAXADDR;
3461         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3462                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3463
3464         /*
3465          * Allocate the parent bus DMA tag appropriate for PCI.
3466          */
3467         error = bus_dma_tag_create(NULL, 1, boundary,
3468                                    lowaddr, BUS_SPACE_MAXADDR,
3469                                    NULL, NULL,
3470                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3471                                    BUS_SPACE_MAXSIZE_32BIT,
3472                                    0, &sc->bge_cdata.bge_parent_tag);
3473         if (error) {
3474                 if_printf(ifp, "could not allocate parent dma tag\n");
3475                 return error;
3476         }
3477
3478         /*
3479          * Create DMA tag and maps for RX mbufs.
3480          */
3481         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3482                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3483                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3484                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3485                                    &sc->bge_cdata.bge_rx_mtag);
3486         if (error) {
3487                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3488                 return error;
3489         }
3490
3491         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3492                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3493         if (error) {
3494                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3495                 sc->bge_cdata.bge_rx_mtag = NULL;
3496                 return error;
3497         }
3498
3499         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3500                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3501                                           BUS_DMA_WAITOK,
3502                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3503                 if (error) {
3504                         int j;
3505
3506                         for (j = 0; j < i; ++j) {
3507                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3508                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3509                         }
3510                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3511                         sc->bge_cdata.bge_rx_mtag = NULL;
3512
3513                         if_printf(ifp, "could not create DMA map for RX\n");
3514                         return error;
3515                 }
3516         }
3517
3518         /*
3519          * Create DMA tag and maps for TX mbufs.
3520          */
3521         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3522                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3523                                    NULL, NULL,
3524                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3525                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3526                                    BUS_DMA_ONEBPAGE,
3527                                    &sc->bge_cdata.bge_tx_mtag);
3528         if (error) {
3529                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3530                 return error;
3531         }
3532
3533         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3534                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3535                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3536                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3537                 if (error) {
3538                         int j;
3539
3540                         for (j = 0; j < i; ++j) {
3541                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3542                                         sc->bge_cdata.bge_tx_dmamap[j]);
3543                         }
3544                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3545                         sc->bge_cdata.bge_tx_mtag = NULL;
3546
3547                         if_printf(ifp, "could not create DMA map for TX\n");
3548                         return error;
3549                 }
3550         }
3551
3552         /*
3553          * Create DMA stuffs for standard RX ring.
3554          */
3555         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3556                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3557                                     &sc->bge_cdata.bge_rx_std_ring_map,
3558                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3559                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3560         if (error) {
3561                 if_printf(ifp, "could not create std RX ring\n");
3562                 return error;
3563         }
3564
3565         /*
3566          * Create jumbo buffer pool.
3567          */
3568         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3569                 error = bge_alloc_jumbo_mem(sc);
3570                 if (error) {
3571                         if_printf(ifp, "could not create jumbo buffer pool\n");
3572                         return error;
3573                 }
3574         }
3575
3576         /*
3577          * Create DMA stuffs for RX return ring.
3578          */
3579         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3580                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3581                                     &sc->bge_cdata.bge_rx_return_ring_map,
3582                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3583                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3584         if (error) {
3585                 if_printf(ifp, "could not create RX ret ring\n");
3586                 return error;
3587         }
3588
3589         /*
3590          * Create DMA stuffs for TX ring.
3591          */
3592         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3593                                     &sc->bge_cdata.bge_tx_ring_tag,
3594                                     &sc->bge_cdata.bge_tx_ring_map,
3595                                     (void *)&sc->bge_ldata.bge_tx_ring,
3596                                     &sc->bge_ldata.bge_tx_ring_paddr);
3597         if (error) {
3598                 if_printf(ifp, "could not create TX ring\n");
3599                 return error;
3600         }
3601
3602         /*
3603          * Create DMA stuffs for status block.
3604          */
3605         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3606                                     &sc->bge_cdata.bge_status_tag,
3607                                     &sc->bge_cdata.bge_status_map,
3608                                     (void *)&sc->bge_ldata.bge_status_block,
3609                                     &sc->bge_ldata.bge_status_block_paddr);
3610         if (error) {
3611                 if_printf(ifp, "could not create status block\n");
3612                 return error;
3613         }
3614
3615         /*
3616          * Create DMA stuffs for statistics block.
3617          */
3618         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3619                                     &sc->bge_cdata.bge_stats_tag,
3620                                     &sc->bge_cdata.bge_stats_map,
3621                                     (void *)&sc->bge_ldata.bge_stats,
3622                                     &sc->bge_ldata.bge_stats_paddr);
3623         if (error) {
3624                 if_printf(ifp, "could not create stats block\n");
3625                 return error;
3626         }
3627         return 0;
3628 }
3629
3630 static int
3631 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3632                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3633 {
3634         bus_dmamem_t dmem;
3635         int error;
3636
3637         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3638                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3639                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3640         if (error)
3641                 return error;
3642
3643         *tag = dmem.dmem_tag;
3644         *map = dmem.dmem_map;
3645         *addr = dmem.dmem_addr;
3646         *paddr = dmem.dmem_busaddr;
3647
3648         return 0;
3649 }
3650
3651 static void
3652 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3653 {
3654         if (tag != NULL) {
3655                 bus_dmamap_unload(tag, map);
3656                 bus_dmamem_free(tag, addr, map);
3657                 bus_dma_tag_destroy(tag);
3658         }
3659 }
3660
3661 /*
3662  * Grrr. The link status word in the status block does
3663  * not work correctly on the BCM5700 rev AX and BX chips,
3664  * according to all available information. Hence, we have
3665  * to enable MII interrupts in order to properly obtain
3666  * async link changes. Unfortunately, this also means that
3667  * we have to read the MAC status register to detect link
3668  * changes, thereby adding an additional register access to
3669  * the interrupt handler.
3670  *
3671  * XXX: perhaps link state detection procedure used for
3672  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3673  */
3674 static void
3675 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3676 {
3677         struct ifnet *ifp = &sc->arpcom.ac_if;
3678         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3679
3680         mii_pollstat(mii);
3681
3682         if (!sc->bge_link &&
3683             (mii->mii_media_status & IFM_ACTIVE) &&
3684             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3685                 sc->bge_link++;
3686                 if (bootverbose)
3687                         if_printf(ifp, "link UP\n");
3688         } else if (sc->bge_link &&
3689             (!(mii->mii_media_status & IFM_ACTIVE) ||
3690             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3691                 sc->bge_link = 0;
3692                 if (bootverbose)
3693                         if_printf(ifp, "link DOWN\n");
3694         }
3695
3696         /* Clear the interrupt. */
3697         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3698         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3699         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3700 }
3701
3702 static void
3703 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3704 {
3705         struct ifnet *ifp = &sc->arpcom.ac_if;
3706
3707 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3708
3709         /*
3710          * Sometimes PCS encoding errors are detected in
3711          * TBI mode (on fiber NICs), and for some reason
3712          * the chip will signal them as link changes.
3713          * If we get a link change event, but the 'PCS
3714          * encoding error' bit in the MAC status register
3715          * is set, don't bother doing a link check.
3716          * This avoids spurious "gigabit link up" messages
3717          * that sometimes appear on fiber NICs during
3718          * periods of heavy traffic.
3719          */
3720         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3721                 if (!sc->bge_link) {
3722                         sc->bge_link++;
3723                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3724                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3725                                     BGE_MACMODE_TBI_SEND_CFGS);
3726                         }
3727                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3728
3729                         if (bootverbose)
3730                                 if_printf(ifp, "link UP\n");
3731
3732                         ifp->if_link_state = LINK_STATE_UP;
3733                         if_link_state_change(ifp);
3734                 }
3735         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3736                 if (sc->bge_link) {
3737                         sc->bge_link = 0;
3738
3739                         if (bootverbose)
3740                                 if_printf(ifp, "link DOWN\n");
3741
3742                         ifp->if_link_state = LINK_STATE_DOWN;
3743                         if_link_state_change(ifp);
3744                 }
3745         }
3746
3747 #undef PCS_ENCODE_ERR
3748
3749         /* Clear the attention. */
3750         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3751             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3752             BGE_MACSTAT_LINK_CHANGED);
3753 }
3754
3755 static void
3756 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3757 {
3758         /*
3759          * Check that the AUTOPOLL bit is set before
3760          * processing the event as a real link change.
3761          * Turning AUTOPOLL on and off in the MII read/write
3762          * functions will often trigger a link status
3763          * interrupt for no reason.
3764          */
3765         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3766                 struct ifnet *ifp = &sc->arpcom.ac_if;
3767                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3768
3769                 mii_pollstat(mii);
3770
3771                 if (!sc->bge_link &&
3772                     (mii->mii_media_status & IFM_ACTIVE) &&
3773                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3774                         sc->bge_link++;
3775                         if (bootverbose)
3776                                 if_printf(ifp, "link UP\n");
3777                 } else if (sc->bge_link &&
3778                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3779                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3780                         sc->bge_link = 0;
3781                         if (bootverbose)
3782                                 if_printf(ifp, "link DOWN\n");
3783                 }
3784         }
3785
3786         /* Clear the attention. */
3787         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3788             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3789             BGE_MACSTAT_LINK_CHANGED);
3790 }
3791
3792 static int
3793 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3794 {
3795         struct bge_softc *sc = arg1;
3796
3797         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3798                                    &sc->bge_rx_coal_ticks,
3799                                    BGE_RX_COAL_TICKS_CHG);
3800 }
3801
3802 static int
3803 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3804 {
3805         struct bge_softc *sc = arg1;
3806
3807         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3808                                    &sc->bge_tx_coal_ticks,
3809                                    BGE_TX_COAL_TICKS_CHG);
3810 }
3811
3812 static int
3813 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3814 {
3815         struct bge_softc *sc = arg1;
3816
3817         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3818                                    &sc->bge_rx_max_coal_bds,
3819                                    BGE_RX_MAX_COAL_BDS_CHG);
3820 }
3821
3822 static int
3823 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3824 {
3825         struct bge_softc *sc = arg1;
3826
3827         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3828                                    &sc->bge_tx_max_coal_bds,
3829                                    BGE_TX_MAX_COAL_BDS_CHG);
3830 }
3831
3832 static int
3833 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3834                     uint32_t coal_chg_mask)
3835 {
3836         struct bge_softc *sc = arg1;
3837         struct ifnet *ifp = &sc->arpcom.ac_if;
3838         int error = 0, v;
3839
3840         lwkt_serialize_enter(ifp->if_serializer);
3841
3842         v = *coal;
3843         error = sysctl_handle_int(oidp, &v, 0, req);
3844         if (!error && req->newptr != NULL) {
3845                 if (v < 0) {
3846                         error = EINVAL;
3847                 } else {
3848                         *coal = v;
3849                         sc->bge_coal_chg |= coal_chg_mask;
3850                 }
3851         }
3852
3853         lwkt_serialize_exit(ifp->if_serializer);
3854         return error;
3855 }
3856
3857 static void
3858 bge_coal_change(struct bge_softc *sc)
3859 {
3860         struct ifnet *ifp = &sc->arpcom.ac_if;
3861         uint32_t val;
3862
3863         ASSERT_SERIALIZED(ifp->if_serializer);
3864
3865         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3866                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3867                             sc->bge_rx_coal_ticks);
3868                 DELAY(10);
3869                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3870
3871                 if (bootverbose) {
3872                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3873                                   sc->bge_rx_coal_ticks);
3874                 }
3875         }
3876
3877         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3878                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3879                             sc->bge_tx_coal_ticks);
3880                 DELAY(10);
3881                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3882
3883                 if (bootverbose) {
3884                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3885                                   sc->bge_tx_coal_ticks);
3886                 }
3887         }
3888
3889         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3890                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3891                             sc->bge_rx_max_coal_bds);
3892                 DELAY(10);
3893                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3894
3895                 if (bootverbose) {
3896                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3897                                   sc->bge_rx_max_coal_bds);
3898                 }
3899         }
3900
3901         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3902                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3903                             sc->bge_tx_max_coal_bds);
3904                 DELAY(10);
3905                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3906
3907                 if (bootverbose) {
3908                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3909                                   sc->bge_tx_max_coal_bds);
3910                 }
3911         }
3912
3913         sc->bge_coal_chg = 0;
3914 }
3915
3916 static void
3917 bge_enable_intr(struct bge_softc *sc)
3918 {
3919         struct ifnet *ifp = &sc->arpcom.ac_if;
3920
3921         lwkt_serialize_handler_enable(ifp->if_serializer);
3922
3923         /*
3924          * Enable interrupt.
3925          */
3926         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3927
3928         /*
3929          * Unmask the interrupt when we stop polling.
3930          */
3931         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3932
3933         /*
3934          * Trigger another interrupt, since above writing
3935          * to interrupt mailbox0 may acknowledge pending
3936          * interrupt.
3937          */
3938         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3939 }
3940
3941 static void
3942 bge_disable_intr(struct bge_softc *sc)
3943 {
3944         struct ifnet *ifp = &sc->arpcom.ac_if;
3945
3946         /*
3947          * Mask the interrupt when we start polling.
3948          */
3949         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3950
3951         /*
3952          * Acknowledge possible asserted interrupt.
3953          */
3954         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3955
3956         lwkt_serialize_handler_disable(ifp->if_serializer);
3957 }
3958
3959 static int
3960 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
3961 {
3962         uint32_t mac_addr;
3963         int ret = 1;
3964
3965         mac_addr = bge_readmem_ind(sc, 0x0c14);
3966         if ((mac_addr >> 16) == 0x484b) {
3967                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3968                 ether_addr[1] = (uint8_t)mac_addr;
3969                 mac_addr = bge_readmem_ind(sc, 0x0c18);
3970                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3971                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3972                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3973                 ether_addr[5] = (uint8_t)mac_addr;
3974                 ret = 0;
3975         }
3976         return ret;
3977 }
3978
3979 static int
3980 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
3981 {
3982         int mac_offset = BGE_EE_MAC_OFFSET;
3983
3984         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
3985                 mac_offset = BGE_EE_MAC_OFFSET_5906;
3986
3987         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
3988 }
3989
3990 static int
3991 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
3992 {
3993         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
3994                 return 1;
3995
3996