sys/dev/drm/r600_cp.c

   1 /*-
   2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Dave Airlie <airlied@redhat.com>
  26  *     Alex Deucher <alexander.deucher@amd.com>
  27  */
  28
  29 #include "dev/drm/drmP.h"
  30 #include "dev/drm/drm.h"
  31 #include "dev/drm/radeon_drm.h"
  32 #include "dev/drm/radeon_drv.h"
  33
  34 #include "dev/drm/r600_microcode.h"
  35
  36 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  37 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  38
  39 #define R600_PTE_VALID     (1 << 0)
  40 #define R600_PTE_SYSTEM    (1 << 1)
  41 #define R600_PTE_SNOOPED   (1 << 2)
  42 #define R600_PTE_READABLE  (1 << 5)
  43 #define R600_PTE_WRITEABLE (1 << 6)
  44
  45 /* MAX values used for gfx init */
  46 #define R6XX_MAX_SH_GPRS           256
  47 #define R6XX_MAX_TEMP_GPRS         16
  48 #define R6XX_MAX_SH_THREADS        256
  49 #define R6XX_MAX_SH_STACK_ENTRIES  4096
  50 #define R6XX_MAX_BACKENDS          8
  51 #define R6XX_MAX_BACKENDS_MASK     0xff
  52 #define R6XX_MAX_SIMDS             8
  53 #define R6XX_MAX_SIMDS_MASK        0xff
  54 #define R6XX_MAX_PIPES             8
  55 #define R6XX_MAX_PIPES_MASK        0xff
  56
  57 #define R7XX_MAX_SH_GPRS           256
  58 #define R7XX_MAX_TEMP_GPRS         16
  59 #define R7XX_MAX_SH_THREADS        256
  60 #define R7XX_MAX_SH_STACK_ENTRIES  4096
  61 #define R7XX_MAX_BACKENDS          8
  62 #define R7XX_MAX_BACKENDS_MASK     0xff
  63 #define R7XX_MAX_SIMDS             16
  64 #define R7XX_MAX_SIMDS_MASK        0xffff
  65 #define R7XX_MAX_PIPES             8
  66 #define R7XX_MAX_PIPES_MASK        0xff
  67
  68 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
  69 {
  70         int i;
  71
  72         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  73
  74         for (i = 0; i < dev_priv->usec_timeout; i++) {
  75                 int slots;
  76                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
  77                         slots = (RADEON_READ(R600_GRBM_STATUS)
  78                                  & R700_CMDFIFO_AVAIL_MASK);
  79                 else
  80                         slots = (RADEON_READ(R600_GRBM_STATUS)
  81                                  & R600_CMDFIFO_AVAIL_MASK);
  82                 if (slots >= entries)
  83                         return 0;
  84                 DRM_UDELAY(1);
  85         }
  86         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
  87                  RADEON_READ(R600_GRBM_STATUS),
  88                  RADEON_READ(R600_GRBM_STATUS2));
  89
  90         return -EBUSY;
  91 }
  92
  93 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
  94 {
  95         int i, ret;
  96
  97         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  98
  99         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 100                 ret = r600_do_wait_for_fifo(dev_priv, 8);
 101         else
 102                 ret = r600_do_wait_for_fifo(dev_priv, 16);
 103         if (ret)
 104                 return ret;
 105         for (i = 0; i < dev_priv->usec_timeout; i++) {
 106                 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
 107                         return 0;
 108                 DRM_UDELAY(1);
 109         }
 110         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 111                  RADEON_READ(R600_GRBM_STATUS),
 112                  RADEON_READ(R600_GRBM_STATUS2));
 113
 114         return -EBUSY;
 115 }
 116
 117 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 118 {
 119 #ifdef __linux__
 120         struct drm_sg_mem *entry = dev->sg;
 121         int max_pages;
 122         int pages;
 123         int i;
 124 #endif
 125         if (gart_info->bus_addr) {
 126 #ifdef __linux__
 127                 max_pages = (gart_info->table_size / sizeof(u32));
 128                 pages = (entry->pages <= max_pages)
 129                   ? entry->pages : max_pages;
 130
 131                 for (i = 0; i < pages; i++) {
 132                         if (!entry->busaddr[i])
 133                                 break;
 134                         pci_unmap_single(dev->pdev, entry->busaddr[i],
 135                                          PAGE_SIZE, PCI_DMA_TODEVICE);
 136                 }
 137 #endif
 138                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 139                         gart_info->bus_addr = 0;
 140         }
 141 }
 142
 143 /* R600 has page table setup */
 144 int r600_page_table_init(struct drm_device *dev)
 145 {
 146         drm_radeon_private_t *dev_priv = dev->dev_private;
 147         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 148         struct drm_sg_mem *entry = dev->sg;
 149         int ret = 0;
 150         int i, j;
 151         int max_pages, pages;
 152         u64 *pci_gart, page_base;
 153         dma_addr_t entry_addr;
 154
 155         /* okay page table is available - lets rock */
 156
 157         /* PTEs are 64-bits */
 158         pci_gart = (u64 *)gart_info->addr;
 159
 160         max_pages = (gart_info->table_size / sizeof(u64));
 161         pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
 162
 163         memset(pci_gart, 0, max_pages * sizeof(u64));
 164
 165         for (i = 0; i < pages; i++) {
 166 #ifdef __linux__
 167                 entry->busaddr[i] = pci_map_single(dev->pdev,
 168                                                    page_address(entry->
 169                                                                 pagelist[i]),
 170                                                    PAGE_SIZE, PCI_DMA_TODEVICE);
 171                 if (entry->busaddr[i] == 0) {
 172                         DRM_ERROR("unable to map PCIGART pages!\n");
 173                         r600_page_table_cleanup(dev, gart_info);
 174                         goto done;
 175                 }
 176 #endif
 177                 entry_addr = entry->busaddr[i];
 178                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 179                         page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
 180                         page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 181                         page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 182
 183                         *pci_gart = page_base;
 184
 185                         if ((i % 128) == 0)
 186                                 DRM_DEBUG("page entry %d: 0x%016llx\n",
 187                                     i, (unsigned long long)page_base);
 188                         pci_gart++;
 189                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 190                 }
 191         }
 192         ret = 1;
 193 #ifdef __linux__
 194 done:
 195 #endif
 196         return ret;
 197 }
 198
 199 static void r600_vm_flush_gart_range(struct drm_device *dev)
 200 {
 201         drm_radeon_private_t *dev_priv = dev->dev_private;
 202         u32 resp, countdown = 1000;
 203         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 204         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 205         RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
 206
 207         do {
 208                 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
 209                 countdown--;
 210                 DRM_UDELAY(1);
 211         } while (((resp & 0xf0) == 0) && countdown);
 212 }
 213
 214 static void r600_vm_init(struct drm_device *dev)
 215 {
 216         drm_radeon_private_t *dev_priv = dev->dev_private;
 217         /* initialise the VM to use the page table we constructed up there */
 218         u32 vm_c0, i;
 219         u32 mc_rd_a;
 220         u32 vm_l2_cntl, vm_l2_cntl3;
 221         /* okay set up the PCIE aperture type thingo */
 222         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 223         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 224         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 225
 226         /* setup MC RD a */
 227         mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
 228                 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
 229                 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
 230
 231         RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
 232         RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
 233
 234         RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
 235         RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
 236
 237         RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
 238         RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
 239
 240         RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
 241         RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
 242
 243         RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
 244         RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
 245
 246         RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
 247         RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
 248
 249         RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
 250         RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
 251
 252         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 253         vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
 254         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 255
 256         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 257         vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
 258                        R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
 259                        R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
 260         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 261
 262         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 263
 264         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 265
 266         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 267
 268         /* disable all other contexts */
 269         for (i = 1; i < 8; i++)
 270                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 271
 272         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 273         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 274         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 275
 276         r600_vm_flush_gart_range(dev);
 277 }
 278
 279 /* load r600 microcode */
 280 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 281 {
 282         const u32 (*cp)[3];
 283         const u32 *pfp;
 284         int i;
 285
 286         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 287         case CHIP_R600:
 288                 DRM_INFO("Loading R600 Microcode\n");
 289                 cp  = R600_cp_microcode;
 290                 pfp = R600_pfp_microcode;
 291                 break;
 292         case CHIP_RV610:
 293                 DRM_INFO("Loading RV610 Microcode\n");
 294                 cp  = RV610_cp_microcode;
 295                 pfp = RV610_pfp_microcode;
 296                 break;
 297         case CHIP_RV630:
 298                 DRM_INFO("Loading RV630 Microcode\n");
 299                 cp  = RV630_cp_microcode;
 300                 pfp = RV630_pfp_microcode;
 301                 break;
 302         case CHIP_RV620:
 303                 DRM_INFO("Loading RV620 Microcode\n");
 304                 cp  = RV620_cp_microcode;
 305                 pfp = RV620_pfp_microcode;
 306                 break;
 307         case CHIP_RV635:
 308                 DRM_INFO("Loading RV635 Microcode\n");
 309                 cp  = RV635_cp_microcode;
 310                 pfp = RV635_pfp_microcode;
 311                 break;
 312         case CHIP_RV670:
 313                 DRM_INFO("Loading RV670 Microcode\n");
 314                 cp  = RV670_cp_microcode;
 315                 pfp = RV670_pfp_microcode;
 316                 break;
 317         case CHIP_RS780:
 318                 DRM_INFO("Loading RS780 Microcode\n");
 319                 cp  = RS780_cp_microcode;
 320                 pfp = RS780_pfp_microcode;
 321                 break;
 322         default:
 323                 return;
 324         }
 325
 326         r600_do_cp_stop(dev_priv);
 327
 328         RADEON_WRITE(R600_CP_RB_CNTL,
 329                      R600_RB_NO_UPDATE |
 330                      R600_RB_BLKSZ(15) |
 331                      R600_RB_BUFSZ(3));
 332
 333         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 334         RADEON_READ(R600_GRBM_SOFT_RESET);
 335         DRM_UDELAY(15000);
 336         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 337
 338         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 339
 340         for (i = 0; i < PM4_UCODE_SIZE; i++) {
 341                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
 342                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
 343                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
 344         }
 345
 346         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 347         for (i = 0; i < PFP_UCODE_SIZE; i++)
 348                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 349
 350         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 351         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 352         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 353 }
 354
 355 static void r700_vm_init(struct drm_device *dev)
 356 {
 357         drm_radeon_private_t *dev_priv = dev->dev_private;
 358         /* initialise the VM to use the page table we constructed up there */
 359         u32 vm_c0, i;
 360         u32 mc_vm_md_l1;
 361         u32 vm_l2_cntl, vm_l2_cntl3;
 362         /* okay set up the PCIE aperture type thingo */
 363         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 364         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 365         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 366
 367         mc_vm_md_l1 = R700_ENABLE_L1_TLB |
 368             R700_ENABLE_L1_FRAGMENT_PROCESSING |
 369             R700_SYSTEM_ACCESS_MODE_IN_SYS |
 370             R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 371             R700_EFFECTIVE_L1_TLB_SIZE(5) |
 372             R700_EFFECTIVE_L1_QUEUE_SIZE(5);
 373
 374         RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
 375         RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
 376         RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
 377         RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
 378         RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
 379         RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
 380         RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
 381
 382         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 383         vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
 384         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 385
 386         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 387         vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
 388         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 389
 390         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 391
 392         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 393
 394         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 395
 396         /* disable all other contexts */
 397         for (i = 1; i < 8; i++)
 398                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 399
 400         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 401         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 402         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 403
 404         r600_vm_flush_gart_range(dev);
 405 }
 406
 407 /* load r600 microcode */
 408 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 409 {
 410         const u32 *pfp;
 411         const u32 *cp;
 412         int i;
 413
 414         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 415         case CHIP_RV770:
 416                 DRM_INFO("Loading RV770/RV790 Microcode\n");
 417                 pfp = RV770_pfp_microcode;
 418                 cp  = RV770_cp_microcode;
 419                 break;
 420         case CHIP_RV730:
 421         case CHIP_RV740:
 422                 DRM_INFO("Loading RV730/RV740 Microcode\n");
 423                 pfp = RV730_pfp_microcode;
 424                 cp  = RV730_cp_microcode;
 425                 break;
 426         case CHIP_RV710:
 427                 DRM_INFO("Loading RV710 Microcode\n");
 428                 pfp = RV710_pfp_microcode;
 429                 cp  = RV710_cp_microcode;
 430                 break;
 431         default:
 432                 return;
 433         }
 434
 435         r600_do_cp_stop(dev_priv);
 436
 437         RADEON_WRITE(R600_CP_RB_CNTL,
 438                      R600_RB_NO_UPDATE |
 439                      (15 << 8) |
 440                      (3 << 0));
 441
 442         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 443         RADEON_READ(R600_GRBM_SOFT_RESET);
 444         DRM_UDELAY(15000);
 445         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 446
 447         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 448         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 449                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 450         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 451
 452         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 453         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 454                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
 455         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 456
 457         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 458         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 459         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 460 }
 461
 462 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
 463 {
 464         u32 tmp;
 465
 466         /* Start with assuming that writeback doesn't work */
 467         dev_priv->writeback_works = 0;
 468
 469         /* Writeback doesn't seem to work everywhere, test it here and possibly
 470          * enable it if it appears to work
 471          */
 472         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
 473
 474         RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
 475
 476         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 477                 u32 val;
 478
 479                 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
 480                 if (val == 0xdeadbeef)
 481                         break;
 482                 DRM_UDELAY(1);
 483         }
 484
 485         if (tmp < dev_priv->usec_timeout) {
 486                 dev_priv->writeback_works = 1;
 487                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 488         } else {
 489                 dev_priv->writeback_works = 0;
 490                 DRM_INFO("writeback test failed\n");
 491         }
 492         if (radeon_no_wb == 1) {
 493                 dev_priv->writeback_works = 0;
 494                 DRM_INFO("writeback forced off\n");
 495         }
 496
 497         if (!dev_priv->writeback_works) {
 498                 /* Disable writeback to avoid unnecessary bus master transfer */
 499                 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
 500                              RADEON_RB_NO_UPDATE);
 501                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
 502         }
 503 }
 504
 505 int r600_do_engine_reset(struct drm_device *dev)
 506 {
 507         drm_radeon_private_t *dev_priv = dev->dev_private;
 508         u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
 509
 510         DRM_INFO("Resetting GPU\n");
 511
 512         cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
 513         cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
 514         RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
 515
 516         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
 517         RADEON_READ(R600_GRBM_SOFT_RESET);
 518         DRM_UDELAY(50);
 519         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 520         RADEON_READ(R600_GRBM_SOFT_RESET);
 521
 522         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
 523         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
 524         RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
 525
 526         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
 527         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
 528         RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
 529         RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
 530
 531         /* Reset the CP ring */
 532         r600_do_cp_reset(dev_priv);
 533
 534         /* The CP is no longer running after an engine reset */
 535         dev_priv->cp_running = 0;
 536
 537         /* Reset any pending vertex, indirect buffers */
 538         radeon_freelist_reset(dev);
 539
 540         return 0;
 541
 542 }
 543
 544 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 545                                              u32 num_backends,
 546                                              u32 backend_disable_mask)
 547 {
 548         u32 backend_map = 0;
 549         u32 enabled_backends_mask;
 550         u32 enabled_backends_count;
 551         u32 cur_pipe;
 552         u32 swizzle_pipe[R6XX_MAX_PIPES];
 553         u32 cur_backend;
 554         u32 i;
 555
 556         if (num_tile_pipes > R6XX_MAX_PIPES)
 557                 num_tile_pipes = R6XX_MAX_PIPES;
 558         if (num_tile_pipes < 1)
 559                 num_tile_pipes = 1;
 560         if (num_backends > R6XX_MAX_BACKENDS)
 561                 num_backends = R6XX_MAX_BACKENDS;
 562         if (num_backends < 1)
 563                 num_backends = 1;
 564
 565         enabled_backends_mask = 0;
 566         enabled_backends_count = 0;
 567         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 568                 if (((backend_disable_mask >> i) & 1) == 0) {
 569                         enabled_backends_mask |= (1 << i);
 570                         ++enabled_backends_count;
 571                 }
 572                 if (enabled_backends_count == num_backends)
 573                         break;
 574         }
 575
 576         if (enabled_backends_count == 0) {
 577                 enabled_backends_mask = 1;
 578                 enabled_backends_count = 1;
 579         }
 580
 581         if (enabled_backends_count != num_backends)
 582                 num_backends = enabled_backends_count;
 583
 584         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 585         switch (num_tile_pipes) {
 586         case 1:
 587                 swizzle_pipe[0] = 0;
 588                 break;
 589         case 2:
 590                 swizzle_pipe[0] = 0;
 591                 swizzle_pipe[1] = 1;
 592                 break;
 593         case 3:
 594                 swizzle_pipe[0] = 0;
 595                 swizzle_pipe[1] = 1;
 596                 swizzle_pipe[2] = 2;
 597                 break;
 598         case 4:
 599                 swizzle_pipe[0] = 0;
 600                 swizzle_pipe[1] = 1;
 601                 swizzle_pipe[2] = 2;
 602                 swizzle_pipe[3] = 3;
 603                 break;
 604         case 5:
 605                 swizzle_pipe[0] = 0;
 606                 swizzle_pipe[1] = 1;
 607                 swizzle_pipe[2] = 2;
 608                 swizzle_pipe[3] = 3;
 609                 swizzle_pipe[4] = 4;
 610                 break;
 611         case 6:
 612                 swizzle_pipe[0] = 0;
 613                 swizzle_pipe[1] = 2;
 614                 swizzle_pipe[2] = 4;
 615                 swizzle_pipe[3] = 5;
 616                 swizzle_pipe[4] = 1;
 617                 swizzle_pipe[5] = 3;
 618                 break;
 619         case 7:
 620                 swizzle_pipe[0] = 0;
 621                 swizzle_pipe[1] = 2;
 622                 swizzle_pipe[2] = 4;
 623                 swizzle_pipe[3] = 6;
 624                 swizzle_pipe[4] = 1;
 625                 swizzle_pipe[5] = 3;
 626                 swizzle_pipe[6] = 5;
 627                 break;
 628         case 8:
 629                 swizzle_pipe[0] = 0;
 630                 swizzle_pipe[1] = 2;
 631                 swizzle_pipe[2] = 4;
 632                 swizzle_pipe[3] = 6;
 633                 swizzle_pipe[4] = 1;
 634                 swizzle_pipe[5] = 3;
 635                 swizzle_pipe[6] = 5;
 636                 swizzle_pipe[7] = 7;
 637                 break;
 638         }
 639
 640         cur_backend = 0;
 641         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 642                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 643                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 644
 645                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 646
 647                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 648         }
 649
 650         return backend_map;
 651 }
 652
 653 static int r600_count_pipe_bits(uint32_t val)
 654 {
 655         int i, ret = 0;
 656         for (i = 0; i < 32; i++) {
 657                 ret += val & 1;
 658                 val >>= 1;
 659         }
 660         return ret;
 661 }
 662
 663 static void r600_gfx_init(struct drm_device *dev,
 664                           drm_radeon_private_t *dev_priv)
 665 {
 666         int i, j, num_qd_pipes;
 667         u32 sx_debug_1;
 668         u32 tc_cntl;
 669         u32 arb_pop;
 670         u32 num_gs_verts_per_thread;
 671         u32 vgt_gs_per_es;
 672         u32 gs_prim_buffer_depth = 0;
 673         u32 sq_ms_fifo_sizes;
 674         u32 sq_config;
 675         u32 sq_gpr_resource_mgmt_1 = 0;
 676         u32 sq_gpr_resource_mgmt_2 = 0;
 677         u32 sq_thread_resource_mgmt = 0;
 678         u32 sq_stack_resource_mgmt_1 = 0;
 679         u32 sq_stack_resource_mgmt_2 = 0;
 680         u32 hdp_host_path_cntl;
 681         u32 backend_map;
 682         u32 gb_tiling_config = 0;
 683         u32 cc_rb_backend_disable = 0;
 684         u32 cc_gc_shader_pipe_config = 0;
 685         u32 ramcfg;
 686
 687         /* setup chip specs */
 688         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 689         case CHIP_R600:
 690                 dev_priv->r600_max_pipes = 4;
 691                 dev_priv->r600_max_tile_pipes = 8;
 692                 dev_priv->r600_max_simds = 4;
 693                 dev_priv->r600_max_backends = 4;
 694                 dev_priv->r600_max_gprs = 256;
 695                 dev_priv->r600_max_threads = 192;
 696                 dev_priv->r600_max_stack_entries = 256;
 697                 dev_priv->r600_max_hw_contexts = 8;
 698                 dev_priv->r600_max_gs_threads = 16;
 699                 dev_priv->r600_sx_max_export_size = 128;
 700                 dev_priv->r600_sx_max_export_pos_size = 16;
 701                 dev_priv->r600_sx_max_export_smx_size = 128;
 702                 dev_priv->r600_sq_num_cf_insts = 2;
 703                 break;
 704         case CHIP_RV630:
 705         case CHIP_RV635:
 706                 dev_priv->r600_max_pipes = 2;
 707                 dev_priv->r600_max_tile_pipes = 2;
 708                 dev_priv->r600_max_simds = 3;
 709                 dev_priv->r600_max_backends = 1;
 710                 dev_priv->r600_max_gprs = 128;
 711                 dev_priv->r600_max_threads = 192;
 712                 dev_priv->r600_max_stack_entries = 128;
 713                 dev_priv->r600_max_hw_contexts = 8;
 714                 dev_priv->r600_max_gs_threads = 4;
 715                 dev_priv->r600_sx_max_export_size = 128;
 716                 dev_priv->r600_sx_max_export_pos_size = 16;
 717                 dev_priv->r600_sx_max_export_smx_size = 128;
 718                 dev_priv->r600_sq_num_cf_insts = 2;
 719                 break;
 720         case CHIP_RV610:
 721         case CHIP_RS780:
 722         case CHIP_RV620:
 723                 dev_priv->r600_max_pipes = 1;
 724                 dev_priv->r600_max_tile_pipes = 1;
 725                 dev_priv->r600_max_simds = 2;
 726                 dev_priv->r600_max_backends = 1;
 727                 dev_priv->r600_max_gprs = 128;
 728                 dev_priv->r600_max_threads = 192;
 729                 dev_priv->r600_max_stack_entries = 128;
 730                 dev_priv->r600_max_hw_contexts = 4;
 731                 dev_priv->r600_max_gs_threads = 4;
 732                 dev_priv->r600_sx_max_export_size = 128;
 733                 dev_priv->r600_sx_max_export_pos_size = 16;
 734                 dev_priv->r600_sx_max_export_smx_size = 128;
 735                 dev_priv->r600_sq_num_cf_insts = 1;
 736                 break;
 737         case CHIP_RV670:
 738                 dev_priv->r600_max_pipes = 4;
 739                 dev_priv->r600_max_tile_pipes = 4;
 740                 dev_priv->r600_max_simds = 4;
 741                 dev_priv->r600_max_backends = 4;
 742                 dev_priv->r600_max_gprs = 192;
 743                 dev_priv->r600_max_threads = 192;
 744                 dev_priv->r600_max_stack_entries = 256;
 745                 dev_priv->r600_max_hw_contexts = 8;
 746                 dev_priv->r600_max_gs_threads = 16;
 747                 dev_priv->r600_sx_max_export_size = 128;
 748                 dev_priv->r600_sx_max_export_pos_size = 16;
 749                 dev_priv->r600_sx_max_export_smx_size = 128;
 750                 dev_priv->r600_sq_num_cf_insts = 2;
 751                 break;
 752         default:
 753                 break;
 754         }
 755
 756         /* Initialize HDP */
 757         j = 0;
 758         for (i = 0; i < 32; i++) {
 759                 RADEON_WRITE((0x2c14 + j), 0x00000000);
 760                 RADEON_WRITE((0x2c18 + j), 0x00000000);
 761                 RADEON_WRITE((0x2c1c + j), 0x00000000);
 762                 RADEON_WRITE((0x2c20 + j), 0x00000000);
 763                 RADEON_WRITE((0x2c24 + j), 0x00000000);
 764                 j += 0x18;
 765         }
 766
 767         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
 768
 769         /* setup tiling, simd, pipe config */
 770         ramcfg = RADEON_READ(R600_RAMCFG);
 771
 772         switch (dev_priv->r600_max_tile_pipes) {
 773         case 1:
 774                 gb_tiling_config |= R600_PIPE_TILING(0);
 775                 break;
 776         case 2:
 777                 gb_tiling_config |= R600_PIPE_TILING(1);
 778                 break;
 779         case 4:
 780                 gb_tiling_config |= R600_PIPE_TILING(2);
 781                 break;
 782         case 8:
 783                 gb_tiling_config |= R600_PIPE_TILING(3);
 784                 break;
 785         default:
 786                 break;
 787         }
 788
 789         gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
 790
 791         gb_tiling_config |= R600_GROUP_SIZE(0);
 792
 793         if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
 794                 gb_tiling_config |= R600_ROW_TILING(3);
 795                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
 796         } else {
 797                 gb_tiling_config |=
 798                         R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 799                 gb_tiling_config |=
 800                         R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 801         }
 802
 803         gb_tiling_config |= R600_BANK_SWAPS(1);
 804
 805         backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
 806                                                         dev_priv->r600_max_backends,
 807                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
 808         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
 809
 810         cc_gc_shader_pipe_config =
 811                 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
 812         cc_gc_shader_pipe_config |=
 813                 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
 814
 815         cc_rb_backend_disable =
 816                 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
 817
 818         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
 819         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 820         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 821
 822         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 823         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 824         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 825
 826         num_qd_pipes =
 827                 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
 828         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
 829         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
 830
 831         /* set HW defaults for 3D engine */
 832         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
 833                                                 R600_ROQ_IB2_START(0x2b)));
 834
 835         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
 836                                               R600_ROQ_END(0x40)));
 837
 838         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
 839                                         R600_SYNC_GRADIENT |
 840                                         R600_SYNC_WALKER |
 841                                         R600_SYNC_ALIGNER));
 842
 843         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
 844                 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
 845
 846         sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
 847         sx_debug_1 |= R600_SMX_EVENT_RELEASE;
 848         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
 849                 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
 850         RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
 851
 852         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 853             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 854             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 855             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 856             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
 857                 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 858         else
 859                 RADEON_WRITE(R600_DB_DEBUG, 0);
 860
 861         RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
 862                                           R600_DEPTH_FLUSH(16) |
 863                                           R600_DEPTH_PENDING_FREE(4) |
 864                                           R600_DEPTH_CACHELINE_FREE(16)));
 865         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
 866         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
 867
 868         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
 869         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
 870
 871         sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
 872         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 873             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 874             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 875                 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
 876                                     R600_FETCH_FIFO_HIWATER(0xa) |
 877                                     R600_DONE_FIFO_HIWATER(0xe0) |
 878                                     R600_ALU_UPDATE_FIFO_HIWATER(0x8));
 879         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 880                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
 881                 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
 882                 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
 883         }
 884         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 885
 886         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 887          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 888          */
 889         sq_config = RADEON_READ(R600_SQ_CONFIG);
 890         sq_config &= ~(R600_PS_PRIO(3) |
 891                        R600_VS_PRIO(3) |
 892                        R600_GS_PRIO(3) |
 893                        R600_ES_PRIO(3));
 894         sq_config |= (R600_DX9_CONSTS |
 895                       R600_VC_ENABLE |
 896                       R600_PS_PRIO(0) |
 897                       R600_VS_PRIO(1) |
 898                       R600_GS_PRIO(2) |
 899                       R600_ES_PRIO(3));
 900
 901         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
 902                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
 903                                           R600_NUM_VS_GPRS(124) |
 904                                           R600_NUM_CLAUSE_TEMP_GPRS(4));
 905                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
 906                                           R600_NUM_ES_GPRS(0));
 907                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
 908                                            R600_NUM_VS_THREADS(48) |
 909                                            R600_NUM_GS_THREADS(4) |
 910                                            R600_NUM_ES_THREADS(4));
 911                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
 912                                             R600_NUM_VS_STACK_ENTRIES(128));
 913                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
 914                                             R600_NUM_ES_STACK_ENTRIES(0));
 915         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 916                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 917                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 918                 /* no vertex cache */
 919                 sq_config &= ~R600_VC_ENABLE;
 920
 921                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 922                                           R600_NUM_VS_GPRS(44) |
 923                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 924                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 925                                           R600_NUM_ES_GPRS(17));
 926                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 927                                            R600_NUM_VS_THREADS(78) |
 928                                            R600_NUM_GS_THREADS(4) |
 929                                            R600_NUM_ES_THREADS(31));
 930                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 931                                             R600_NUM_VS_STACK_ENTRIES(40));
 932                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 933                                             R600_NUM_ES_STACK_ENTRIES(16));
 934         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 935                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
 936                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 937                                           R600_NUM_VS_GPRS(44) |
 938                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 939                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
 940                                           R600_NUM_ES_GPRS(18));
 941                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 942                                            R600_NUM_VS_THREADS(78) |
 943                                            R600_NUM_GS_THREADS(4) |
 944                                            R600_NUM_ES_THREADS(31));
 945                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 946                                             R600_NUM_VS_STACK_ENTRIES(40));
 947                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 948                                             R600_NUM_ES_STACK_ENTRIES(16));
 949         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
 950                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 951                                           R600_NUM_VS_GPRS(44) |
 952                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 953                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 954                                           R600_NUM_ES_GPRS(17));
 955                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 956                                            R600_NUM_VS_THREADS(78) |
 957                                            R600_NUM_GS_THREADS(4) |
 958                                            R600_NUM_ES_THREADS(31));
 959                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
 960                                             R600_NUM_VS_STACK_ENTRIES(64));
 961                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
 962                                             R600_NUM_ES_STACK_ENTRIES(64));
 963         }
 964
 965         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
 966         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 967         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 968         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 969         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 970         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 971
 972         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 973             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 974             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
 975                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
 976         else
 977                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
 978
 979         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
 980                                                     R600_S0_Y(0x4) |
 981                                                     R600_S1_X(0x4) |
 982                                                     R600_S1_Y(0xc)));
 983         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
 984                                                     R600_S0_Y(0xe) |
 985                                                     R600_S1_X(0x2) |
 986                                                     R600_S1_Y(0x2) |
 987                                                     R600_S2_X(0xa) |
 988                                                     R600_S2_Y(0x6) |
 989                                                     R600_S3_X(0x6) |
 990                                                     R600_S3_Y(0xa)));
 991         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
 992                                                         R600_S0_Y(0xb) |
 993                                                         R600_S1_X(0x4) |
 994                                                         R600_S1_Y(0xc) |
 995                                                         R600_S2_X(0x1) |
 996                                                         R600_S2_Y(0x6) |
 997                                                         R600_S3_X(0xa) |
 998                                                         R600_S3_Y(0xe)));
 999         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1000                                                         R600_S4_Y(0x1) |
1001                                                         R600_S5_X(0x0) |
1002                                                         R600_S5_Y(0x0) |
1003                                                         R600_S6_X(0xb) |
1004                                                         R600_S6_Y(0x4) |
1005                                                         R600_S7_X(0x7) |
1006                                                         R600_S7_Y(0x8)));
1007
1008
1009         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1010         case CHIP_R600:
1011         case CHIP_RV630:
1012         case CHIP_RV635:
1013                 gs_prim_buffer_depth = 0;
1014                 break;
1015         case CHIP_RV610:
1016         case CHIP_RS780:
1017         case CHIP_RV620:
1018                 gs_prim_buffer_depth = 32;
1019                 break;
1020         case CHIP_RV670:
1021                 gs_prim_buffer_depth = 128;
1022                 break;
1023         default:
1024                 break;
1025         }
1026
1027         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1028         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1029         /* Max value for this is 256 */
1030         if (vgt_gs_per_es > 256)
1031                 vgt_gs_per_es = 256;
1032
1033         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1034         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1035         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1036         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1037
1038         /* more default values. 2D/3D driver should adjust as needed */
1039         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1040         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1041         RADEON_WRITE(R600_SX_MISC, 0);
1042         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1043         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1044         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1045         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1046         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1047         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1048
1049         /* clear render buffer base addresses */
1050         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1051         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1052         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1053         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1054         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1055         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1056         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1057         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1058
1059         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1060         case CHIP_RV610:
1061         case CHIP_RS780:
1062         case CHIP_RV620:
1063                 tc_cntl = R600_TC_L2_SIZE(8);
1064                 break;
1065         case CHIP_RV630:
1066         case CHIP_RV635:
1067                 tc_cntl = R600_TC_L2_SIZE(4);
1068                 break;
1069         case CHIP_R600:
1070                 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1071                 break;
1072         default:
1073                 tc_cntl = R600_TC_L2_SIZE(0);
1074                 break;
1075         }
1076
1077         RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1078
1079         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1080         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1081
1082         arb_pop = RADEON_READ(R600_ARB_POP);
1083         arb_pop |= R600_ENABLE_TC128;
1084         RADEON_WRITE(R600_ARB_POP, arb_pop);
1085
1086         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1087         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1088                                           R600_NUM_CLIP_SEQ(3)));
1089         RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1090
1091 }
1092
1093 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1094                                              u32 num_backends,
1095                                              u32 backend_disable_mask)
1096 {
1097         u32 backend_map = 0;
1098         u32 enabled_backends_mask;
1099         u32 enabled_backends_count;
1100         u32 cur_pipe;
1101         u32 swizzle_pipe[R7XX_MAX_PIPES];
1102         u32 cur_backend;
1103         u32 i;
1104
1105         if (num_tile_pipes > R7XX_MAX_PIPES)
1106                 num_tile_pipes = R7XX_MAX_PIPES;
1107         if (num_tile_pipes < 1)
1108                 num_tile_pipes = 1;
1109         if (num_backends > R7XX_MAX_BACKENDS)
1110                 num_backends = R7XX_MAX_BACKENDS;
1111         if (num_backends < 1)
1112                 num_backends = 1;
1113
1114         enabled_backends_mask = 0;
1115         enabled_backends_count = 0;
1116         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1117                 if (((backend_disable_mask >> i) & 1) == 0) {
1118                         enabled_backends_mask |= (1 << i);
1119                         ++enabled_backends_count;
1120                 }
1121                 if (enabled_backends_count == num_backends)
1122                         break;
1123         }
1124
1125         if (enabled_backends_count == 0) {
1126                 enabled_backends_mask = 1;
1127                 enabled_backends_count = 1;
1128         }
1129
1130         if (enabled_backends_count != num_backends)
1131                 num_backends = enabled_backends_count;
1132
1133         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1134         switch (num_tile_pipes) {
1135         case 1:
1136                 swizzle_pipe[0] = 0;
1137                 break;
1138         case 2:
1139                 swizzle_pipe[0] = 0;
1140                 swizzle_pipe[1] = 1;
1141                 break;
1142         case 3:
1143                 swizzle_pipe[0] = 0;
1144                 swizzle_pipe[1] = 2;
1145                 swizzle_pipe[2] = 1;
1146                 break;
1147         case 4:
1148                 swizzle_pipe[0] = 0;
1149                 swizzle_pipe[1] = 2;
1150                 swizzle_pipe[2] = 3;
1151                 swizzle_pipe[3] = 1;
1152                 break;
1153         case 5:
1154                 swizzle_pipe[0] = 0;
1155                 swizzle_pipe[1] = 2;
1156                 swizzle_pipe[2] = 4;
1157                 swizzle_pipe[3] = 1;
1158                 swizzle_pipe[4] = 3;
1159                 break;
1160         case 6:
1161                 swizzle_pipe[0] = 0;
1162                 swizzle_pipe[1] = 2;
1163                 swizzle_pipe[2] = 4;
1164                 swizzle_pipe[3] = 5;
1165                 swizzle_pipe[4] = 3;
1166                 swizzle_pipe[5] = 1;
1167                 break;
1168         case 7:
1169                 swizzle_pipe[0] = 0;
1170                 swizzle_pipe[1] = 2;
1171                 swizzle_pipe[2] = 4;
1172                 swizzle_pipe[3] = 6;
1173                 swizzle_pipe[4] = 3;
1174                 swizzle_pipe[5] = 1;
1175                 swizzle_pipe[6] = 5;
1176                 break;
1177         case 8:
1178                 swizzle_pipe[0] = 0;
1179                 swizzle_pipe[1] = 2;
1180                 swizzle_pipe[2] = 4;
1181                 swizzle_pipe[3] = 6;
1182                 swizzle_pipe[4] = 3;
1183                 swizzle_pipe[5] = 1;
1184                 swizzle_pipe[6] = 7;
1185                 swizzle_pipe[7] = 5;
1186                 break;
1187         }
1188
1189         cur_backend = 0;
1190         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1191                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1192                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1193
1194                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1195
1196                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1197         }
1198
1199         return backend_map;
1200 }
1201
1202 static void r700_gfx_init(struct drm_device *dev,
1203                           drm_radeon_private_t *dev_priv)
1204 {
1205         int i, j, num_qd_pipes;
1206         u32 sx_debug_1;
1207         u32 smx_dc_ctl0;
1208         u32 num_gs_verts_per_thread;
1209         u32 vgt_gs_per_es;
1210         u32 gs_prim_buffer_depth = 0;
1211         u32 sq_ms_fifo_sizes;
1212         u32 sq_config;
1213         u32 sq_thread_resource_mgmt;
1214         u32 hdp_host_path_cntl;
1215         u32 sq_dyn_gpr_size_simd_ab_0;
1216         u32 backend_map;
1217         u32 gb_tiling_config = 0;
1218         u32 cc_rb_backend_disable = 0;
1219         u32 cc_gc_shader_pipe_config = 0;
1220         u32 mc_arb_ramcfg;
1221         u32 db_debug4;
1222
1223         /* setup chip specs */
1224         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1225         case CHIP_RV770:
1226                 dev_priv->r600_max_pipes = 4;
1227                 dev_priv->r600_max_tile_pipes = 8;
1228                 dev_priv->r600_max_simds = 10;
1229                 dev_priv->r600_max_backends = 4;
1230                 dev_priv->r600_max_gprs = 256;
1231                 dev_priv->r600_max_threads = 248;
1232                 dev_priv->r600_max_stack_entries = 512;
1233                 dev_priv->r600_max_hw_contexts = 8;
1234                 dev_priv->r600_max_gs_threads = 16 * 2;
1235                 dev_priv->r600_sx_max_export_size = 128;
1236                 dev_priv->r600_sx_max_export_pos_size = 16;
1237                 dev_priv->r600_sx_max_export_smx_size = 112;
1238                 dev_priv->r600_sq_num_cf_insts = 2;
1239
1240                 dev_priv->r700_sx_num_of_sets = 7;
1241                 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1242                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1243                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1244                 break;
1245         case CHIP_RV740:
1246                 dev_priv->r600_max_pipes = 4;
1247                 dev_priv->r600_max_tile_pipes = 4;
1248                 dev_priv->r600_max_simds = 8;
1249                 dev_priv->r600_max_backends = 4;
1250                 dev_priv->r600_max_gprs = 256;
1251                 dev_priv->r600_max_threads = 248;
1252                 dev_priv->r600_max_stack_entries = 512;
1253                 dev_priv->r600_max_hw_contexts = 8;
1254                 dev_priv->r600_max_gs_threads = 16 * 2;
1255                 dev_priv->r600_sx_max_export_size = 256;
1256                 dev_priv->r600_sx_max_export_pos_size = 32;
1257                 dev_priv->r600_sx_max_export_smx_size = 224;
1258                 dev_priv->r600_sq_num_cf_insts = 2;
1259
1260                 dev_priv->r700_sx_num_of_sets = 7;
1261                 dev_priv->r700_sc_prim_fifo_size = 0x100;
1262                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1263                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1264
1265                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1266                         dev_priv->r600_sx_max_export_pos_size -= 16;
1267                         dev_priv->r600_sx_max_export_smx_size += 16;
1268                 }
1269                 break;
1270         case CHIP_RV730:
1271                 dev_priv->r600_max_pipes = 2;
1272                 dev_priv->r600_max_tile_pipes = 4;
1273                 dev_priv->r600_max_simds = 8;
1274                 dev_priv->r600_max_backends = 2;
1275                 dev_priv->r600_max_gprs = 128;
1276                 dev_priv->r600_max_threads = 248;
1277                 dev_priv->r600_max_stack_entries = 256;
1278                 dev_priv->r600_max_hw_contexts = 8;
1279                 dev_priv->r600_max_gs_threads = 16 * 2;
1280                 dev_priv->r600_sx_max_export_size = 256;
1281                 dev_priv->r600_sx_max_export_pos_size = 32;
1282                 dev_priv->r600_sx_max_export_smx_size = 224;
1283                 dev_priv->r600_sq_num_cf_insts = 2;
1284
1285                 dev_priv->r700_sx_num_of_sets = 7;
1286                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1287                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1288                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1289
1290                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1291                         dev_priv->r600_sx_max_export_pos_size -= 16;
1292                         dev_priv->r600_sx_max_export_smx_size += 16;
1293                 }
1294                 break;
1295         case CHIP_RV710:
1296                 dev_priv->r600_max_pipes = 2;
1297                 dev_priv->r600_max_tile_pipes = 2;
1298                 dev_priv->r600_max_simds = 2;
1299                 dev_priv->r600_max_backends = 1;
1300                 dev_priv->r600_max_gprs = 256;
1301                 dev_priv->r600_max_threads = 192;
1302                 dev_priv->r600_max_stack_entries = 256;
1303                 dev_priv->r600_max_hw_contexts = 4;
1304                 dev_priv->r600_max_gs_threads = 8 * 2;
1305                 dev_priv->r600_sx_max_export_size = 128;
1306                 dev_priv->r600_sx_max_export_pos_size = 16;
1307                 dev_priv->r600_sx_max_export_smx_size = 112;
1308                 dev_priv->r600_sq_num_cf_insts = 1;
1309
1310                 dev_priv->r700_sx_num_of_sets = 7;
1311                 dev_priv->r700_sc_prim_fifo_size = 0x40;
1312                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1313                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1314                 break;
1315         default:
1316                 break;
1317         }
1318
1319         /* Initialize HDP */
1320         j = 0;
1321         for (i = 0; i < 32; i++) {
1322                 RADEON_WRITE((0x2c14 + j), 0x00000000);
1323                 RADEON_WRITE((0x2c18 + j), 0x00000000);
1324                 RADEON_WRITE((0x2c1c + j), 0x00000000);
1325                 RADEON_WRITE((0x2c20 + j), 0x00000000);
1326                 RADEON_WRITE((0x2c24 + j), 0x00000000);
1327                 j += 0x18;
1328         }
1329
1330         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1331
1332         /* setup tiling, simd, pipe config */
1333         mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1334
1335         switch (dev_priv->r600_max_tile_pipes) {
1336         case 1:
1337                 gb_tiling_config |= R600_PIPE_TILING(0);
1338                 break;
1339         case 2:
1340                 gb_tiling_config |= R600_PIPE_TILING(1);
1341                 break;
1342         case 4:
1343                 gb_tiling_config |= R600_PIPE_TILING(2);
1344                 break;
1345         case 8:
1346                 gb_tiling_config |= R600_PIPE_TILING(3);
1347                 break;
1348         default:
1349                 break;
1350         }
1351
1352         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1353                 gb_tiling_config |= R600_BANK_TILING(1);
1354         else
1355                 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1356
1357         gb_tiling_config |= R600_GROUP_SIZE(0);
1358
1359         if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1360                 gb_tiling_config |= R600_ROW_TILING(3);
1361                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1362         } else {
1363                 gb_tiling_config |=
1364                         R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1365                 gb_tiling_config |=
1366                         R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1367         }
1368
1369         gb_tiling_config |= R600_BANK_SWAPS(1);
1370
1371         backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1372                                                         dev_priv->r600_max_backends,
1373                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
1374         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1375
1376         cc_gc_shader_pipe_config =
1377                 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1378         cc_gc_shader_pipe_config |=
1379                 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1380
1381         cc_rb_backend_disable =
1382                 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1383
1384         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
1385         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1386         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1387
1388         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
1389         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
1390         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1391
1392         RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1393         RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1394         RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1395         RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1396         RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1397
1398         num_qd_pipes =
1399                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1400         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1401         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1402
1403         /* set HW defaults for 3D engine */
1404         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1405                                                 R600_ROQ_IB2_START(0x2b)));
1406
1407         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1408
1409         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1410                                         R600_SYNC_GRADIENT |
1411                                         R600_SYNC_WALKER |
1412                                         R600_SYNC_ALIGNER));
1413
1414         sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1415         sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1416         RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1417
1418         smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1419         smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1420         smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1421         RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1422
1423         RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1424                                           R700_GS_FLUSH_CTL(4) |
1425                                           R700_ACK_FLUSH_CTL(3) |
1426                                           R700_SYNC_FLUSH_CTL));
1427
1428         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1429                 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1430         else {
1431                 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1432                 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1433                 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1434         }
1435
1436         RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1437                                                    R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1438                                                    R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1439
1440         RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1441                                                  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1442                                                  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1443
1444         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1445
1446         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1447
1448         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1449
1450         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1451
1452         RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1453
1454         sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1455                             R600_DONE_FIFO_HIWATER(0xe0) |
1456                             R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1457         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1458         case CHIP_RV770:
1459                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1460                 break;
1461         case CHIP_RV740:
1462         case CHIP_RV730:
1463         case CHIP_RV710:
1464         default:
1465                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1466                 break;
1467         }
1468         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1469
1470         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1471          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1472          */
1473         sq_config = RADEON_READ(R600_SQ_CONFIG);
1474         sq_config &= ~(R600_PS_PRIO(3) |
1475                        R600_VS_PRIO(3) |
1476                        R600_GS_PRIO(3) |
1477                        R600_ES_PRIO(3));
1478         sq_config |= (R600_DX9_CONSTS |
1479                       R600_VC_ENABLE |
1480                       R600_EXPORT_SRC_C |
1481                       R600_PS_PRIO(0) |
1482                       R600_VS_PRIO(1) |
1483                       R600_GS_PRIO(2) |
1484                       R600_ES_PRIO(3));
1485         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1486                 /* no vertex cache */
1487                 sq_config &= ~R600_VC_ENABLE;
1488
1489         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1490
1491         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1492                                                     R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1493                                                     R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1494
1495         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1496                                                     R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1497
1498         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1499                                    R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1500                                    R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1501         if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1502                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1503         else
1504                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1505         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1506
1507         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1508                                                      R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1509
1510         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1511                                                      R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1512
1513         sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1514                                      R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1515                                      R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1516                                      R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1517
1518         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1519         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1520         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1521         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1522         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1523         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1524         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1525         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1526
1527         RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1528                                                      R700_FORCE_EOV_MAX_REZ_CNT(255)));
1529
1530         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1531                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1532                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1533         else
1534                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1535                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1536
1537         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1538         case CHIP_RV770:
1539         case CHIP_RV740:
1540         case CHIP_RV730:
1541                 gs_prim_buffer_depth = 384;
1542                 break;
1543         case CHIP_RV710:
1544                 gs_prim_buffer_depth = 128;
1545                 break;
1546         default:
1547                 break;
1548         }
1549
1550         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1551         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1552         /* Max value for this is 256 */
1553         if (vgt_gs_per_es > 256)
1554                 vgt_gs_per_es = 256;
1555
1556         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1557         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1558         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1559
1560         /* more default values. 2D/3D driver should adjust as needed */
1561         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1562         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1563         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1564         RADEON_WRITE(R600_SX_MISC, 0);
1565         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1566         RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1567         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1568         RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1569         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1570         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1571         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1572         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1573
1574         /* clear render buffer base addresses */
1575         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1576         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1577         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1578         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1579         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1580         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1581         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1582         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1583
1584         RADEON_WRITE(R700_TCP_CNTL, 0);
1585
1586         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1587         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1588
1589         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1590
1591         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1592                                           R600_NUM_CLIP_SEQ(3)));
1593
1594 }
1595
1596 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1597                                        drm_radeon_private_t *dev_priv,
1598                                        struct drm_file *file_priv)
1599 {
1600         u32 ring_start;
1601         u64 rptr_addr;
1602
1603         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1604                 r700_gfx_init(dev, dev_priv);
1605         else
1606                 r600_gfx_init(dev, dev_priv);
1607
1608         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1609         RADEON_READ(R600_GRBM_SOFT_RESET);
1610         DRM_UDELAY(15000);
1611         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1612
1613
1614         /* Set ring buffer size */
1615 #ifdef __BIG_ENDIAN
1616         RADEON_WRITE(R600_CP_RB_CNTL,
1617                      RADEON_BUF_SWAP_32BIT |
1618                      RADEON_RB_NO_UPDATE |
1619                      (dev_priv->ring.rptr_update_l2qw << 8) |
1620                      dev_priv->ring.size_l2qw);
1621 #else
1622         RADEON_WRITE(R600_CP_RB_CNTL,
1623                      RADEON_RB_NO_UPDATE |
1624                      (dev_priv->ring.rptr_update_l2qw << 8) |
1625                      dev_priv->ring.size_l2qw);
1626 #endif
1627
1628         RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1629
1630         /* Set the write pointer delay */
1631         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1632
1633 #ifdef __BIG_ENDIAN
1634         RADEON_WRITE(R600_CP_RB_CNTL,
1635                      RADEON_BUF_SWAP_32BIT |
1636                      RADEON_RB_NO_UPDATE |
1637                      RADEON_RB_RPTR_WR_ENA |
1638                      (dev_priv->ring.rptr_update_l2qw << 8) |
1639                      dev_priv->ring.size_l2qw);
1640 #else
1641         RADEON_WRITE(R600_CP_RB_CNTL,
1642                      RADEON_RB_NO_UPDATE |
1643                      RADEON_RB_RPTR_WR_ENA |
1644                      (dev_priv->ring.rptr_update_l2qw << 8) |
1645                      dev_priv->ring.size_l2qw);
1646 #endif
1647
1648         /* Initialize the ring buffer's read and write pointers */
1649         RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1650         RADEON_WRITE(R600_CP_RB_WPTR, 0);
1651         SET_RING_HEAD(dev_priv, 0);
1652         dev_priv->ring.tail = 0;
1653
1654 #if __OS_HAS_AGP
1655         if (dev_priv->flags & RADEON_IS_AGP) {
1656                 rptr_addr = dev_priv->ring_rptr->offset
1657                         - dev->agp->base +
1658                         dev_priv->gart_vm_start;
1659         } else
1660 #endif
1661         {
1662                 rptr_addr = dev_priv->ring_rptr->offset
1663                         - ((unsigned long) dev->sg->virtual)
1664                         + dev_priv->gart_vm_start;
1665         }
1666         RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1667                      rptr_addr & 0xffffffff);
1668         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1669                      upper_32_bits(rptr_addr));
1670
1671 #ifdef __BIG_ENDIAN
1672         RADEON_WRITE(R600_CP_RB_CNTL,
1673                      RADEON_BUF_SWAP_32BIT |
1674                      (dev_priv->ring.rptr_update_l2qw << 8) |
1675                      dev_priv->ring.size_l2qw);
1676 #else
1677         RADEON_WRITE(R600_CP_RB_CNTL,
1678                      (dev_priv->ring.rptr_update_l2qw << 8) |
1679                      dev_priv->ring.size_l2qw);
1680 #endif
1681
1682 #if __OS_HAS_AGP
1683         if (dev_priv->flags & RADEON_IS_AGP) {
1684                 /* XXX */
1685                 radeon_write_agp_base(dev_priv, dev->agp->base);
1686
1687                 /* XXX */
1688                 radeon_write_agp_location(dev_priv,
1689                              (((dev_priv->gart_vm_start - 1 +
1690                                 dev_priv->gart_size) & 0xffff0000) |
1691                               (dev_priv->gart_vm_start >> 16)));
1692
1693                 ring_start = (dev_priv->cp_ring->offset
1694                               - dev->agp->base
1695                               + dev_priv->gart_vm_start);
1696         } else
1697 #endif
1698                 ring_start = (dev_priv->cp_ring->offset
1699                               - (unsigned long)dev->sg->virtual
1700                               + dev_priv->gart_vm_start);
1701
1702         RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1703
1704         RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1705
1706         RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1707
1708         /* Initialize the scratch register pointer.  This will cause
1709          * the scratch register values to be written out to memory
1710          * whenever they are updated.
1711          *
1712          * We simply put this behind the ring read pointer, this works
1713          * with PCI GART as well as (whatever kind of) AGP GART
1714          */
1715         {
1716                 u64 scratch_addr;
1717
1718                 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1719                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1720                 scratch_addr += R600_SCRATCH_REG_OFFSET;
1721                 scratch_addr >>= 8;
1722                 scratch_addr &= 0xffffffff;
1723
1724                 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1725         }
1726
1727         RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1728
1729         /* Turn on bus mastering */
1730         radeon_enable_bm(dev_priv);
1731
1732         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1733         RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1734
1735         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1736         RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1737
1738         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1739         RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1740
1741         /* reset sarea copies of these */
1742         if (dev_priv->sarea_priv) {
1743                 dev_priv->sarea_priv->last_frame = 0;
1744                 dev_priv->sarea_priv->last_dispatch = 0;
1745                 dev_priv->sarea_priv->last_clear = 0;
1746         }
1747
1748         r600_do_wait_for_idle(dev_priv);
1749
1750 }
1751
1752 int r600_do_cleanup_cp(struct drm_device *dev)
1753 {
1754         drm_radeon_private_t *dev_priv = dev->dev_private;
1755         DRM_DEBUG("\n");
1756
1757         /* Make sure interrupts are disabled here because the uninstall ioctl
1758          * may not have been called from userspace and after dev_private
1759          * is freed, it's too late.
1760          */
1761         if (dev->irq_enabled)
1762                 drm_irq_uninstall(dev);
1763
1764 #if __OS_HAS_AGP
1765         if (dev_priv->flags & RADEON_IS_AGP) {
1766                 if (dev_priv->cp_ring != NULL) {
1767                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1768                         dev_priv->cp_ring = NULL;
1769                 }
1770                 if (dev_priv->ring_rptr != NULL) {
1771                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1772                         dev_priv->ring_rptr = NULL;
1773                 }
1774                 if (dev->agp_buffer_map != NULL) {
1775                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1776                         dev->agp_buffer_map = NULL;
1777                 }
1778         } else
1779 #endif
1780         {
1781
1782                 if (dev_priv->gart_info.bus_addr)
1783                         r600_page_table_cleanup(dev, &dev_priv->gart_info);
1784
1785                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1786                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1787                         dev_priv->gart_info.addr = 0;
1788                 }
1789         }
1790         /* only clear to the start of flags */
1791         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1792
1793         return 0;
1794 }
1795
1796 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1797                     struct drm_file *file_priv)
1798 {
1799         drm_radeon_private_t *dev_priv = dev->dev_private;
1800
1801         DRM_DEBUG("\n");
1802
1803         /* if we require new memory map but we don't have it fail */
1804         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1805                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1806                 r600_do_cleanup_cp(dev);
1807                 return -EINVAL;
1808         }
1809
1810         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1811                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1812                 dev_priv->flags &= ~RADEON_IS_AGP;
1813                 /* The writeback test succeeds, but when writeback is enabled,
1814                  * the ring buffer read ptr update fails after first 128 bytes.
1815                  */
1816                 radeon_no_wb = 1;
1817         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1818                  && !init->is_pci) {
1819                 DRM_DEBUG("Restoring AGP flag\n");
1820                 dev_priv->flags |= RADEON_IS_AGP;
1821         }
1822
1823         dev_priv->usec_timeout = init->usec_timeout;
1824         if (dev_priv->usec_timeout < 1 ||
1825             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1826                 DRM_DEBUG("TIMEOUT problem!\n");
1827                 r600_do_cleanup_cp(dev);
1828                 return -EINVAL;
1829         }
1830
1831         /* Enable vblank on CRTC1 for older X servers
1832          */
1833         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1834
1835         dev_priv->cp_mode = init->cp_mode;
1836
1837         /* We don't support anything other than bus-mastering ring mode,
1838          * but the ring can be in either AGP or PCI space for the ring
1839          * read pointer.
1840          */
1841         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1842             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1843                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1844                 r600_do_cleanup_cp(dev);
1845                 return -EINVAL;
1846         }
1847
1848         switch (init->fb_bpp) {
1849         case 16:
1850                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1851                 break;
1852         case 32:
1853         default:
1854                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1855                 break;
1856         }
1857         dev_priv->front_offset = init->front_offset;
1858         dev_priv->front_pitch = init->front_pitch;
1859         dev_priv->back_offset = init->back_offset;
1860         dev_priv->back_pitch = init->back_pitch;
1861
1862         dev_priv->ring_offset = init->ring_offset;
1863         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1864         dev_priv->buffers_offset = init->buffers_offset;
1865         dev_priv->gart_textures_offset = init->gart_textures_offset;
1866
1867         dev_priv->sarea = drm_getsarea(dev);
1868         if (!dev_priv->sarea) {
1869                 DRM_ERROR("could not find sarea!\n");
1870                 r600_do_cleanup_cp(dev);
1871                 return -EINVAL;
1872         }
1873
1874         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1875         if (!dev_priv->cp_ring) {
1876                 DRM_ERROR("could not find cp ring region!\n");
1877                 r600_do_cleanup_cp(dev);
1878                 return -EINVAL;
1879         }
1880         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1881         if (!dev_priv->ring_rptr) {
1882                 DRM_ERROR("could not find ring read pointer!\n");
1883                 r600_do_cleanup_cp(dev);
1884                 return -EINVAL;
1885         }
1886         dev->agp_buffer_token = init->buffers_offset;
1887         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1888         if (!dev->agp_buffer_map) {
1889                 DRM_ERROR("could not find dma buffer region!\n");
1890                 r600_do_cleanup_cp(dev);
1891                 return -EINVAL;
1892         }
1893
1894         if (init->gart_textures_offset) {
1895                 dev_priv->gart_textures =
1896                     drm_core_findmap(dev, init->gart_textures_offset);
1897                 if (!dev_priv->gart_textures) {
1898                         DRM_ERROR("could not find GART texture region!\n");
1899                         r600_do_cleanup_cp(dev);
1900                         return -EINVAL;
1901                 }
1902         }
1903
1904         dev_priv->sarea_priv =
1905             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1906                                     init->sarea_priv_offset);
1907
1908 #if __OS_HAS_AGP
1909         /* XXX */
1910         if (dev_priv->flags & RADEON_IS_AGP) {
1911                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1912                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1913                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1914                 if (!dev_priv->cp_ring->handle ||
1915                     !dev_priv->ring_rptr->handle ||
1916                     !dev->agp_buffer_map->handle) {
1917                         DRM_ERROR("could not find ioremap agp regions!\n");
1918                         r600_do_cleanup_cp(dev);
1919                         return -EINVAL;
1920                 }
1921         } else
1922 #endif
1923         {
1924                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1925                 dev_priv->ring_rptr->handle =
1926                     (void *)dev_priv->ring_rptr->offset;
1927                 dev->agp_buffer_map->handle =
1928                     (void *)dev->agp_buffer_map->offset;
1929
1930                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1931                           dev_priv->cp_ring->handle);
1932                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1933                           dev_priv->ring_rptr->handle);
1934                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1935                           dev->agp_buffer_map->handle);
1936         }
1937
1938         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1939         dev_priv->fb_size =
1940                 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1941                 - dev_priv->fb_location;
1942
1943         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1944                                         ((dev_priv->front_offset
1945                                           + dev_priv->fb_location) >> 10));
1946
1947         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1948                                        ((dev_priv->back_offset
1949                                          + dev_priv->fb_location) >> 10));
1950
1951         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1952                                         ((dev_priv->depth_offset
1953                                           + dev_priv->fb_location) >> 10));
1954
1955         dev_priv->gart_size = init->gart_size;
1956
1957         /* New let's set the memory map ... */
1958         if (dev_priv->new_memmap) {
1959                 u32 base = 0;
1960
1961                 DRM_INFO("Setting GART location based on new memory map\n");
1962
1963                 /* If using AGP, try to locate the AGP aperture at the same
1964                  * location in the card and on the bus, though we have to
1965                  * align it down.
1966                  */
1967 #if __OS_HAS_AGP
1968                 /* XXX */
1969                 if (dev_priv->flags & RADEON_IS_AGP) {
1970                         base = dev->agp->base;
1971                         /* Check if valid */
1972                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1973                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1974                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1975                                          dev->agp->base);
1976                                 base = 0;
1977                         }
1978                 }
1979 #endif
1980                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1981                 if (base == 0) {
1982                         base = dev_priv->fb_location + dev_priv->fb_size;
1983                         if (base < dev_priv->fb_location ||
1984                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1985                                 base = dev_priv->fb_location
1986                                         - dev_priv->gart_size;
1987                 }
1988                 dev_priv->gart_vm_start = base & 0xffc00000u;
1989                 if (dev_priv->gart_vm_start != base)
1990                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1991                                  base, dev_priv->gart_vm_start);
1992         }
1993
1994 #if __OS_HAS_AGP
1995         /* XXX */
1996         if (dev_priv->flags & RADEON_IS_AGP)
1997                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1998                                                  - dev->agp->base
1999                                                  + dev_priv->gart_vm_start);
2000         else
2001 #endif
2002                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2003                                                  - (unsigned long)dev->sg->virtual
2004                                                  + dev_priv->gart_vm_start);
2005
2006         DRM_DEBUG("fb 0x%08x size %d\n",
2007                   (unsigned int) dev_priv->fb_location,
2008                   (unsigned int) dev_priv->fb_size);
2009         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2010         DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2011                   (unsigned int) dev_priv->gart_vm_start);
2012         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2013                   dev_priv->gart_buffers_offset);
2014
2015         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2016         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2017                               + init->ring_size / sizeof(u32));
2018         dev_priv->ring.size = init->ring_size;
2019         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2020
2021         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2022         dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2023
2024         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2025         dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2026
2027         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2028
2029         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2030
2031 #if __OS_HAS_AGP
2032         if (dev_priv->flags & RADEON_IS_AGP) {
2033                 /* XXX turn off pcie gart */
2034         } else
2035 #endif
2036         {
2037                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2038                 /* if we have an offset set from userspace */
2039                 if (!dev_priv->pcigart_offset_set) {
2040                         DRM_ERROR("Need gart offset from userspace\n");
2041                         r600_do_cleanup_cp(dev);
2042                         return -EINVAL;
2043                 }
2044
2045                 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2046
2047                 dev_priv->gart_info.bus_addr =
2048                         dev_priv->pcigart_offset + dev_priv->fb_location;
2049                 dev_priv->gart_info.mapping.offset =
2050                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2051                 dev_priv->gart_info.mapping.size =
2052                         dev_priv->gart_info.table_size;
2053
2054                 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2055                 if (!dev_priv->gart_info.mapping.handle) {
2056                         DRM_ERROR("ioremap failed.\n");
2057                         r600_do_cleanup_cp(dev);
2058                         return -EINVAL;
2059                 }
2060
2061                 dev_priv->gart_info.addr =
2062                         dev_priv->gart_info.mapping.handle;
2063
2064                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2065                           dev_priv->gart_info.addr,
2066                           dev_priv->pcigart_offset);
2067
2068                 if (!r600_page_table_init(dev)) {
2069                         DRM_ERROR("Failed to init GART table\n");
2070                         r600_do_cleanup_cp(dev);
2071                         return -EINVAL;
2072                 }
2073
2074                 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2075                         r700_vm_init(dev);
2076                 else
2077                         r600_vm_init(dev);
2078         }
2079
2080         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2081                 r700_cp_load_microcode(dev_priv);
2082         else
2083                 r600_cp_load_microcode(dev_priv);
2084
2085         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2086
2087         dev_priv->last_buf = 0;
2088
2089         r600_do_engine_reset(dev);
2090         r600_test_writeback(dev_priv);
2091
2092         return 0;
2093 }
2094
2095 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2096 {
2097         drm_radeon_private_t *dev_priv = dev->dev_private;
2098
2099         DRM_DEBUG("\n");
2100         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2101                 r700_vm_init(dev);
2102                 r700_cp_load_microcode(dev_priv);
2103         } else {
2104                 r600_vm_init(dev);
2105                 r600_cp_load_microcode(dev_priv);
2106         }
2107         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2108         r600_do_engine_reset(dev);
2109
2110         return 0;
2111 }
2112
2113 /* Wait for the CP to go idle.
2114  */
2115 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2116 {
2117         RING_LOCALS;
2118         DRM_DEBUG("\n");
2119
2120         BEGIN_RING(5);
2121         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2122         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2123         /* wait for 3D idle clean */
2124         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2125         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2126         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2127
2128         ADVANCE_RING();
2129         COMMIT_RING();
2130
2131         return r600_do_wait_for_idle(dev_priv);
2132 }
2133
2134 /* Start the Command Processor.
2135  */
2136 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2137 {
2138         u32 cp_me;
2139         RING_LOCALS;
2140         DRM_DEBUG("\n");
2141
2142         BEGIN_RING(7);
2143         OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2144         OUT_RING(0x00000001);
2145         if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2146                 OUT_RING(0x00000003);
2147         else
2148                 OUT_RING(0x00000000);
2149         OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2150         OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2151         OUT_RING(0x00000000);
2152         OUT_RING(0x00000000);
2153         ADVANCE_RING();
2154         COMMIT_RING();
2155
2156         /* set the mux and reset the halt bit */
2157         cp_me = 0xff;
2158         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2159
2160         dev_priv->cp_running = 1;
2161
2162 }
2163
2164 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2165 {
2166         u32 cur_read_ptr;
2167         DRM_DEBUG("\n");
2168
2169         cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2170         RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2171         SET_RING_HEAD(dev_priv, cur_read_ptr);
2172         dev_priv->ring.tail = cur_read_ptr;
2173 }
2174
2175 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2176 {
2177         uint32_t cp_me;
2178
2179         DRM_DEBUG("\n");
2180
2181         cp_me = 0xff | R600_CP_ME_HALT;
2182
2183         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2184
2185         dev_priv->cp_running = 0;
2186 }
2187
2188 int r600_cp_dispatch_indirect(struct drm_device *dev,
2189                               struct drm_buf *buf, int start, int end)
2190 {
2191         drm_radeon_private_t *dev_priv = dev->dev_private;
2192         RING_LOCALS;
2193
2194         if (start != end) {
2195                 unsigned long offset = (dev_priv->gart_buffers_offset
2196                                         + buf->offset + start);
2197                 int dwords = (end - start + 3) / sizeof(u32);
2198
2199                 DRM_DEBUG("dwords:%d\n", dwords);
2200                 DRM_DEBUG("offset 0x%lx\n", offset);
2201
2202
2203                 /* Indirect buffer data must be a multiple of 16 dwords.
2204                  * pad the data with a Type-2 CP packet.
2205                  */
2206                 while (dwords & 0xf) {
2207                         u32 *data = (u32 *)
2208                             ((char *)dev->agp_buffer_map->handle
2209                              + buf->offset + start);
2210                         data[dwords++] = RADEON_CP_PACKET2;
2211                 }
2212
2213                 /* Fire off the indirect buffer */
2214                 BEGIN_RING(4);
2215                 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2216                 OUT_RING((offset & 0xfffffffc));
2217                 OUT_RING((upper_32_bits(offset) & 0xff));
2218                 OUT_RING(dwords);
2219                 ADVANCE_RING();
2220         }
2221
2222         return 0;
2223 }