1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.46 2008/10/28 07:30:49 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
60 #include <sys/param.h>
61 #include <sys/endian.h>
62 #include <sys/kernel.h>
64 #include <sys/interrupt.h>
67 #include <sys/serialize.h>
68 #include <sys/socket.h>
69 #include <sys/sockio.h>
70 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
75 #include <net/if_arp.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/ifq_var.h>
79 #include <net/if_types.h>
80 #include <net/if_var.h>
81 #include <net/vlan/if_vlan_var.h>
82 #include <net/vlan/if_vlan_ether.h>
84 #include <bus/pci/pcireg.h>
85 #include <bus/pci/pcivar.h>
86 #include <bus/pci/pcidevs.h>
88 #include <dev/netif/mii_layer/mii.h>
89 #include <dev/netif/mii_layer/miivar.h>
91 #include "miibus_if.h"
93 #include <dev/netif/nfe/if_nfereg.h>
94 #include <dev/netif/nfe/if_nfevar.h>
97 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
99 static int nfe_probe(device_t);
100 static int nfe_attach(device_t);
101 static int nfe_detach(device_t);
102 static void nfe_shutdown(device_t);
103 static int nfe_resume(device_t);
104 static int nfe_suspend(device_t);
106 static int nfe_miibus_readreg(device_t, int, int);
107 static void nfe_miibus_writereg(device_t, int, int, int);
108 static void nfe_miibus_statchg(device_t);
110 #ifdef DEVICE_POLLING
111 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
112 static void nfe_disable_intrs(struct nfe_softc *);
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static int nfe_rxeof(struct nfe_softc *);
117 static int nfe_txeof(struct nfe_softc *, int);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_powerup(device_t);
143 static void nfe_mac_reset(struct nfe_softc *);
144 static void nfe_tick(void *);
145 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
147 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
149 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
151 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
153 static void nfe_enable_intrs(struct nfe_softc *);
155 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
160 static int nfe_debug = 0;
161 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
162 static int nfe_tx_ring_count = NFE_TX_RING_DEF_COUNT;
164 * hw timer simulated interrupt moderation @4000Hz. Negative values
165 * disable the timer when the discrete interrupt rate falls below
166 * the moderation rate.
168 * XXX 8000Hz might be better but if the interrupt is shared it can
171 static int nfe_imtime = -250; /* uS */
173 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
174 TUNABLE_INT("hw.nfe.tx_ring_count", &nfe_tx_ring_count);
175 TUNABLE_INT("hw.nfe.imtimer", &nfe_imtime);
176 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
178 #define DPRINTF(sc, fmt, ...) do { \
179 if ((sc)->sc_debug) { \
180 if_printf(&(sc)->arpcom.ac_if, \
185 #define DPRINTFN(sc, lv, fmt, ...) do { \
186 if ((sc)->sc_debug >= (lv)) { \
187 if_printf(&(sc)->arpcom.ac_if, \
192 #else /* !NFE_DEBUG */
194 #define DPRINTF(sc, fmt, ...)
195 #define DPRINTFN(sc, lv, fmt, ...)
197 #endif /* NFE_DEBUG */
199 static const struct nfe_dev {
204 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
205 "NVIDIA nForce Fast Ethernet" },
207 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
208 "NVIDIA nForce2 Fast Ethernet" },
210 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
211 "NVIDIA nForce3 Gigabit Ethernet" },
213 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
214 chipset, and possibly also the 400R; it might be both nForce2- and
215 nForce3-based boards can use the same MCPs (= southbridges) */
216 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
217 "NVIDIA nForce3 Gigabit Ethernet" },
219 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
220 "NVIDIA nForce3 Gigabit Ethernet" },
222 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
223 "NVIDIA nForce3 Gigabit Ethernet" },
225 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
226 "NVIDIA nForce3 Gigabit Ethernet" },
228 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
229 "NVIDIA CK804 Gigabit Ethernet" },
231 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
232 "NVIDIA CK804 Gigabit Ethernet" },
234 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
235 "NVIDIA MCP04 Gigabit Ethernet" },
237 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
238 "NVIDIA MCP04 Gigabit Ethernet" },
240 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
241 "NVIDIA MCP51 Gigabit Ethernet" },
243 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
244 "NVIDIA MCP51 Gigabit Ethernet" },
246 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
247 "NVIDIA MCP55 Gigabit Ethernet" },
249 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
250 "NVIDIA MCP55 Gigabit Ethernet" },
252 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
253 "NVIDIA MCP61 Gigabit Ethernet" },
255 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
256 "NVIDIA MCP61 Gigabit Ethernet" },
258 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
259 "NVIDIA MCP61 Gigabit Ethernet" },
261 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
262 "NVIDIA MCP61 Gigabit Ethernet" },
264 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
265 "NVIDIA MCP65 Gigabit Ethernet" },
267 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
268 "NVIDIA MCP65 Gigabit Ethernet" },
270 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
271 "NVIDIA MCP65 Gigabit Ethernet" },
273 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
274 "NVIDIA MCP65 Gigabit Ethernet" },
276 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
277 "NVIDIA MCP67 Gigabit Ethernet" },
279 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
280 "NVIDIA MCP67 Gigabit Ethernet" },
282 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
283 "NVIDIA MCP67 Gigabit Ethernet" },
285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
286 "NVIDIA MCP67 Gigabit Ethernet" },
288 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
289 "NVIDIA MCP73 Gigabit Ethernet" },
291 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
292 "NVIDIA MCP73 Gigabit Ethernet" },
294 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
295 "NVIDIA MCP73 Gigabit Ethernet" },
297 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
298 "NVIDIA MCP73 Gigabit Ethernet" },
300 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
301 "NVIDIA MCP77 Gigabit Ethernet" },
303 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
304 "NVIDIA MCP77 Gigabit Ethernet" },
306 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
307 "NVIDIA MCP77 Gigabit Ethernet" },
309 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
310 "NVIDIA MCP77 Gigabit Ethernet" },
312 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
313 "NVIDIA MCP79 Gigabit Ethernet" },
315 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
316 "NVIDIA MCP79 Gigabit Ethernet" },
318 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
319 "NVIDIA MCP79 Gigabit Ethernet" },
321 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
322 "NVIDIA MCP79 Gigabit Ethernet" },
327 static device_method_t nfe_methods[] = {
328 /* Device interface */
329 DEVMETHOD(device_probe, nfe_probe),
330 DEVMETHOD(device_attach, nfe_attach),
331 DEVMETHOD(device_detach, nfe_detach),
332 DEVMETHOD(device_suspend, nfe_suspend),
333 DEVMETHOD(device_resume, nfe_resume),
334 DEVMETHOD(device_shutdown, nfe_shutdown),
337 DEVMETHOD(bus_print_child, bus_generic_print_child),
338 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
341 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
342 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
343 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
348 static driver_t nfe_driver = {
351 sizeof(struct nfe_softc)
354 static devclass_t nfe_devclass;
356 DECLARE_DUMMY_MODULE(if_nfe);
357 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
358 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
359 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
362 * NOTE: NFE_WORDALIGN support is guesswork right now.
365 nfe_probe(device_t dev)
367 const struct nfe_dev *n;
370 vid = pci_get_vendor(dev);
371 did = pci_get_device(dev);
372 for (n = nfe_devices; n->desc != NULL; ++n) {
373 if (vid == n->vid && did == n->did) {
374 struct nfe_softc *sc = device_get_softc(dev);
377 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
378 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
379 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
380 sc->sc_caps = NFE_NO_PWRCTL |
383 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
384 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
385 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
386 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
387 sc->sc_caps = NFE_JUMBO_SUP |
392 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
393 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
394 sc->sc_caps = NFE_FIX_EADDR;
396 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
397 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
398 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
399 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
400 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
401 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
402 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
403 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
404 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
405 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
406 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
407 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
408 sc->sc_caps |= NFE_40BIT_ADDR;
410 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
411 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
412 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
413 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
414 sc->sc_caps = NFE_JUMBO_SUP |
420 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
421 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
422 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
423 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
424 sc->sc_caps = NFE_JUMBO_SUP |
427 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
428 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
429 sc->sc_caps = NFE_JUMBO_SUP |
435 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
436 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
437 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
438 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
439 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
440 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
441 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
442 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
443 sc->sc_caps = NFE_40BIT_ADDR |
449 device_set_desc(dev, n->desc);
450 device_set_async_attach(dev, TRUE);
458 nfe_attach(device_t dev)
460 struct nfe_softc *sc = device_get_softc(dev);
461 struct ifnet *ifp = &sc->arpcom.ac_if;
462 uint8_t eaddr[ETHER_ADDR_LEN];
466 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
467 lwkt_serialize_init(&sc->sc_jbuf_serializer);
470 * Initialize sysctl variables
472 sc->sc_rx_ring_count = nfe_rx_ring_count;
473 sc->sc_tx_ring_count = nfe_tx_ring_count;
474 sc->sc_debug = nfe_debug;
475 if (nfe_imtime < 0) {
476 sc->sc_flags |= NFE_F_DYN_IM;
477 sc->sc_imtime = -nfe_imtime;
479 sc->sc_imtime = nfe_imtime;
481 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
483 sc->sc_mem_rid = PCIR_BAR(0);
485 if (sc->sc_caps & NFE_40BIT_ADDR)
486 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
487 else if (sc->sc_caps & NFE_JUMBO_SUP)
488 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
491 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
494 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
495 irq = pci_read_config(dev, PCIR_INTLINE, 4);
497 device_printf(dev, "chip is in D%d power mode "
498 "-- setting to D0\n", pci_get_powerstate(dev));
500 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
502 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
503 pci_write_config(dev, PCIR_INTLINE, irq, 4);
505 #endif /* !BURN_BRIDGE */
507 /* Enable bus mastering */
508 pci_enable_busmaster(dev);
510 /* Allocate IO memory */
511 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
512 &sc->sc_mem_rid, RF_ACTIVE);
513 if (sc->sc_mem_res == NULL) {
514 device_printf(dev, "could not allocate io memory\n");
517 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
518 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
522 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
524 RF_SHAREABLE | RF_ACTIVE);
525 if (sc->sc_irq_res == NULL) {
526 device_printf(dev, "could not allocate irq\n");
532 NFE_WRITE(sc, NFE_WOL_CTL, 0);
534 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
537 nfe_get_macaddr(sc, eaddr);
540 * Allocate top level DMA tag
542 if (sc->sc_caps & NFE_40BIT_ADDR)
543 lowaddr = NFE_BUS_SPACE_MAXADDR;
545 lowaddr = BUS_SPACE_MAXADDR_32BIT;
546 error = bus_dma_tag_create(NULL, /* parent */
547 1, 0, /* alignment, boundary */
548 lowaddr, /* lowaddr */
549 BUS_SPACE_MAXADDR, /* highaddr */
550 NULL, NULL, /* filter, filterarg */
551 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
553 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
557 device_printf(dev, "could not allocate parent dma tag\n");
562 * Allocate Tx and Rx rings.
564 error = nfe_alloc_tx_ring(sc, &sc->txq);
566 device_printf(dev, "could not allocate Tx ring\n");
570 error = nfe_alloc_rx_ring(sc, &sc->rxq);
572 device_printf(dev, "could not allocate Rx ring\n");
579 sysctl_ctx_init(&sc->sc_sysctl_ctx);
580 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
581 SYSCTL_STATIC_CHILDREN(_hw),
583 device_get_nameunit(dev),
585 if (sc->sc_sysctl_tree == NULL) {
586 device_printf(dev, "can't add sysctl node\n");
590 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
591 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
592 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
593 sc, 0, nfe_sysctl_imtime, "I",
594 "Interrupt moderation time (usec). "
595 "0 to disable interrupt moderation.");
596 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
597 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
598 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
600 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
601 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
602 "tx_ring_count", CTLFLAG_RD, &sc->sc_tx_ring_count,
604 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
605 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
606 "debug", CTLFLAG_RW, &sc->sc_debug,
607 0, "control debugging printfs");
609 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
612 device_printf(dev, "MII without any phy\n");
617 ifp->if_mtu = ETHERMTU;
618 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
619 ifp->if_ioctl = nfe_ioctl;
620 ifp->if_start = nfe_start;
621 #ifdef DEVICE_POLLING
622 ifp->if_poll = nfe_poll;
624 ifp->if_watchdog = nfe_watchdog;
625 ifp->if_init = nfe_init;
626 ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_ring_count);
627 ifq_set_ready(&ifp->if_snd);
629 ifp->if_capabilities = IFCAP_VLAN_MTU;
631 if (sc->sc_caps & NFE_HW_VLAN)
632 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
635 if (sc->sc_caps & NFE_HW_CSUM) {
636 ifp->if_capabilities |= IFCAP_HWCSUM;
637 ifp->if_hwassist = NFE_CSUM_FEATURES;
640 sc->sc_caps &= ~NFE_HW_CSUM;
642 ifp->if_capenable = ifp->if_capabilities;
644 callout_init(&sc->sc_tick_ch);
646 ether_ifattach(ifp, eaddr, NULL);
648 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
649 &sc->sc_ih, ifp->if_serializer);
651 device_printf(dev, "could not setup intr\n");
656 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
657 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
666 nfe_detach(device_t dev)
668 struct nfe_softc *sc = device_get_softc(dev);
670 if (device_is_attached(dev)) {
671 struct ifnet *ifp = &sc->arpcom.ac_if;
673 lwkt_serialize_enter(ifp->if_serializer);
675 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
676 lwkt_serialize_exit(ifp->if_serializer);
681 if (sc->sc_miibus != NULL)
682 device_delete_child(dev, sc->sc_miibus);
683 bus_generic_detach(dev);
685 if (sc->sc_sysctl_tree != NULL)
686 sysctl_ctx_free(&sc->sc_sysctl_ctx);
688 if (sc->sc_irq_res != NULL) {
689 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
693 if (sc->sc_mem_res != NULL) {
694 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
698 nfe_free_tx_ring(sc, &sc->txq);
699 nfe_free_rx_ring(sc, &sc->rxq);
700 if (sc->sc_dtag != NULL)
701 bus_dma_tag_destroy(sc->sc_dtag);
707 nfe_shutdown(device_t dev)
709 struct nfe_softc *sc = device_get_softc(dev);
710 struct ifnet *ifp = &sc->arpcom.ac_if;
712 lwkt_serialize_enter(ifp->if_serializer);
714 lwkt_serialize_exit(ifp->if_serializer);
718 nfe_suspend(device_t dev)
720 struct nfe_softc *sc = device_get_softc(dev);
721 struct ifnet *ifp = &sc->arpcom.ac_if;
723 lwkt_serialize_enter(ifp->if_serializer);
725 lwkt_serialize_exit(ifp->if_serializer);
731 nfe_resume(device_t dev)
733 struct nfe_softc *sc = device_get_softc(dev);
734 struct ifnet *ifp = &sc->arpcom.ac_if;
736 lwkt_serialize_enter(ifp->if_serializer);
737 if (ifp->if_flags & IFF_UP)
739 lwkt_serialize_exit(ifp->if_serializer);
745 nfe_miibus_statchg(device_t dev)
747 struct nfe_softc *sc = device_get_softc(dev);
748 struct mii_data *mii = device_get_softc(sc->sc_miibus);
749 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
751 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
753 phy = NFE_READ(sc, NFE_PHY_IFACE);
754 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
756 seed = NFE_READ(sc, NFE_RNDSEED);
757 seed &= ~NFE_SEED_MASK;
759 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
760 phy |= NFE_PHY_HDX; /* half-duplex */
761 misc |= NFE_MISC1_HDX;
764 switch (IFM_SUBTYPE(mii->mii_media_active)) {
765 case IFM_1000_T: /* full-duplex only */
766 link |= NFE_MEDIA_1000T;
767 seed |= NFE_SEED_1000T;
768 phy |= NFE_PHY_1000T;
771 link |= NFE_MEDIA_100TX;
772 seed |= NFE_SEED_100TX;
773 phy |= NFE_PHY_100TX;
776 link |= NFE_MEDIA_10T;
777 seed |= NFE_SEED_10T;
781 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
783 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
784 NFE_WRITE(sc, NFE_MISC1, misc);
785 NFE_WRITE(sc, NFE_LINKSPEED, link);
789 nfe_miibus_readreg(device_t dev, int phy, int reg)
791 struct nfe_softc *sc = device_get_softc(dev);
795 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
797 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
798 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
802 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
804 for (ntries = 0; ntries < 1000; ntries++) {
806 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
809 if (ntries == 1000) {
810 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
814 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
815 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
819 val = NFE_READ(sc, NFE_PHY_DATA);
820 if (val != 0xffffffff && val != 0)
821 sc->mii_phyaddr = phy;
823 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
829 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
831 struct nfe_softc *sc = device_get_softc(dev);
835 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
837 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
838 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
842 NFE_WRITE(sc, NFE_PHY_DATA, val);
843 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
844 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
846 for (ntries = 0; ntries < 1000; ntries++) {
848 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
854 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
858 #ifdef DEVICE_POLLING
861 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
863 struct nfe_softc *sc = ifp->if_softc;
865 ASSERT_SERIALIZED(ifp->if_serializer);
869 nfe_disable_intrs(sc);
872 case POLL_DEREGISTER:
873 nfe_enable_intrs(sc);
876 case POLL_AND_CHECK_STATUS:
879 if (ifp->if_flags & IFF_RUNNING) {
892 struct nfe_softc *sc = arg;
893 struct ifnet *ifp = &sc->arpcom.ac_if;
896 r = NFE_READ(sc, NFE_IRQ_STATUS);
898 return; /* not for us */
899 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
901 if (sc->sc_rate_second != time_second) {
903 * Calculate sc_rate_avg - interrupts per second.
905 sc->sc_rate_second = time_second;
906 if (sc->sc_rate_avg < sc->sc_rate_acc)
907 sc->sc_rate_avg = sc->sc_rate_acc;
909 sc->sc_rate_avg = (sc->sc_rate_avg * 3 +
910 sc->sc_rate_acc) / 4;
912 } else if (sc->sc_rate_avg < sc->sc_rate_acc) {
914 * Don't wait for a tick to roll over if we are taking
915 * a lot of interrupts.
917 sc->sc_rate_avg = sc->sc_rate_acc;
920 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
922 if (r & NFE_IRQ_LINK) {
923 NFE_READ(sc, NFE_PHY_STATUS);
924 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
925 DPRINTF(sc, "link state changed %s\n", "");
928 if (ifp->if_flags & IFF_RUNNING) {
936 ret |= nfe_txeof(sc, 1);
938 /* update the rate accumulator */
942 if (sc->sc_flags & NFE_F_DYN_IM) {
943 rate = 1000000 / sc->sc_imtime;
944 if ((sc->sc_flags & NFE_F_IRQ_TIMER) == 0 &&
945 sc->sc_rate_avg > rate) {
947 * Use the hardware timer to reduce the
948 * interrupt rate if the discrete interrupt
949 * rate has exceeded our threshold.
951 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_IMTIMER);
952 sc->sc_flags |= NFE_F_IRQ_TIMER;
953 } else if ((sc->sc_flags & NFE_F_IRQ_TIMER) &&
954 sc->sc_rate_avg <= rate) {
956 * Use discrete TX/RX interrupts if the rate
957 * has fallen below our threshold.
959 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_NOIMTIMER);
960 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
963 * Recollect, mainly to avoid the possible race
964 * introduced by changing interrupt masks.
974 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
976 struct nfe_softc *sc = ifp->if_softc;
977 struct ifreq *ifr = (struct ifreq *)data;
978 struct mii_data *mii;
979 int error = 0, mask, jumbo_cap;
981 ASSERT_SERIALIZED(ifp->if_serializer);
985 if ((sc->sc_caps & NFE_JUMBO_SUP) && sc->rxq.jbuf != NULL)
990 if ((jumbo_cap && ifr->ifr_mtu > NFE_JUMBO_MTU) ||
991 (!jumbo_cap && ifr->ifr_mtu > ETHERMTU)) {
993 } else if (ifp->if_mtu != ifr->ifr_mtu) {
994 ifp->if_mtu = ifr->ifr_mtu;
995 if (ifp->if_flags & IFF_RUNNING)
1000 if (ifp->if_flags & IFF_UP) {
1002 * If only the PROMISC or ALLMULTI flag changes, then
1003 * don't do a full re-init of the chip, just update
1006 if ((ifp->if_flags & IFF_RUNNING) &&
1007 ((ifp->if_flags ^ sc->sc_if_flags) &
1008 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
1011 if (!(ifp->if_flags & IFF_RUNNING))
1015 if (ifp->if_flags & IFF_RUNNING)
1018 sc->sc_if_flags = ifp->if_flags;
1022 if (ifp->if_flags & IFF_RUNNING)
1027 mii = device_get_softc(sc->sc_miibus);
1028 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1031 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
1032 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
1033 ifp->if_capenable ^= mask;
1034 if (IFCAP_TXCSUM & ifp->if_capenable)
1035 ifp->if_hwassist = NFE_CSUM_FEATURES;
1037 ifp->if_hwassist = 0;
1039 if (ifp->if_flags & IFF_RUNNING)
1044 error = ether_ioctl(ifp, cmd, data);
1051 nfe_rxeof(struct nfe_softc *sc)
1053 struct ifnet *ifp = &sc->arpcom.ac_if;
1054 struct nfe_rx_ring *ring = &sc->rxq;
1056 struct mbuf_chain chain[MAXCPU];
1059 ether_input_chain_init(chain);
1062 struct nfe_rx_data *data = &ring->data[ring->cur];
1067 if (sc->sc_caps & NFE_40BIT_ADDR) {
1068 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
1070 flags = le16toh(desc64->flags);
1071 len = le16toh(desc64->length) & 0x3fff;
1073 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
1075 flags = le16toh(desc32->flags);
1076 len = le16toh(desc32->length) & 0x3fff;
1079 if (flags & NFE_RX_READY)
1084 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1085 if (!(flags & NFE_RX_VALID_V1))
1088 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
1089 flags &= ~NFE_RX_ERROR;
1090 len--; /* fix buffer length */
1093 if (!(flags & NFE_RX_VALID_V2))
1096 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
1097 flags &= ~NFE_RX_ERROR;
1098 len--; /* fix buffer length */
1102 if (flags & NFE_RX_ERROR) {
1109 if (sc->sc_flags & NFE_F_USE_JUMBO)
1110 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1112 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1119 m->m_pkthdr.len = m->m_len = len;
1120 m->m_pkthdr.rcvif = ifp;
1122 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1123 (flags & NFE_RX_CSUMOK)) {
1124 if (flags & NFE_RX_IP_CSUMOK_V2) {
1125 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1130 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1131 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1133 CSUM_FRAG_NOT_CHECKED;
1134 m->m_pkthdr.csum_data = 0xffff;
1139 ether_input_chain(ifp, m, NULL, chain);
1141 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1142 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1146 ether_input_dispatch(chain);
1151 nfe_txeof(struct nfe_softc *sc, int start)
1153 struct ifnet *ifp = &sc->arpcom.ac_if;
1154 struct nfe_tx_ring *ring = &sc->txq;
1155 struct nfe_tx_data *data = NULL;
1157 while (ring->next != ring->cur) {
1160 if (sc->sc_caps & NFE_40BIT_ADDR)
1161 flags = le16toh(ring->desc64[ring->next].flags);
1163 flags = le16toh(ring->desc32[ring->next].flags);
1165 if (flags & NFE_TX_VALID)
1168 data = &ring->data[ring->next];
1170 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1171 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1174 if ((flags & NFE_TX_ERROR_V1) != 0) {
1175 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1182 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1185 if ((flags & NFE_TX_ERROR_V2) != 0) {
1186 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1194 if (data->m == NULL) { /* should not get there */
1196 "last fragment bit w/o associated mbuf!\n");
1200 /* last fragment of the mbuf chain transmitted */
1201 bus_dmamap_unload(ring->data_tag, data->map);
1206 KKASSERT(ring->queued >= 0);
1207 ring->next = (ring->next + 1) % sc->sc_tx_ring_count;
1210 if (sc->sc_tx_ring_count - ring->queued >=
1211 sc->sc_tx_spare + NFE_NSEG_RSVD)
1212 ifp->if_flags &= ~IFF_OACTIVE;
1214 if (ring->queued == 0)
1217 if (start && !ifq_is_empty(&ifp->if_snd))
1227 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1229 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1230 struct nfe_tx_data *data, *data_map;
1232 struct nfe_desc64 *desc64 = NULL;
1233 struct nfe_desc32 *desc32 = NULL;
1236 int error, i, j, maxsegs, nsegs;
1238 data = &ring->data[ring->cur];
1240 data_map = data; /* Remember who owns the DMA map */
1242 maxsegs = (sc->sc_tx_ring_count - ring->queued) - NFE_NSEG_RSVD;
1243 if (maxsegs > NFE_MAX_SCATTER)
1244 maxsegs = NFE_MAX_SCATTER;
1245 KASSERT(maxsegs >= sc->sc_tx_spare,
1246 ("no enough segments %d,%d\n", maxsegs, sc->sc_tx_spare));
1248 error = bus_dmamap_load_mbuf_defrag(ring->data_tag, map, &m0,
1249 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1252 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1256 /* setup h/w VLAN tagging */
1257 if (m0->m_flags & M_VLANTAG)
1258 vtag = m0->m_pkthdr.ether_vlantag;
1260 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1261 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1262 flags |= NFE_TX_IP_CSUM;
1263 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1264 flags |= NFE_TX_TCP_CSUM;
1268 * XXX urm. somebody is unaware of how hardware works. You
1269 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1270 * the ring until the entire chain is actually *VALID*. Otherwise
1271 * the hardware may encounter a partially initialized chain that
1272 * is marked as being ready to go when it in fact is not ready to
1276 for (i = 0; i < nsegs; i++) {
1277 j = (ring->cur + i) % sc->sc_tx_ring_count;
1278 data = &ring->data[j];
1280 if (sc->sc_caps & NFE_40BIT_ADDR) {
1281 desc64 = &ring->desc64[j];
1282 desc64->physaddr[0] =
1283 htole32(NFE_ADDR_HI(segs[i].ds_addr));
1284 desc64->physaddr[1] =
1285 htole32(NFE_ADDR_LO(segs[i].ds_addr));
1286 desc64->length = htole16(segs[i].ds_len - 1);
1287 desc64->vtag = htole32(vtag);
1288 desc64->flags = htole16(flags);
1290 desc32 = &ring->desc32[j];
1291 desc32->physaddr = htole32(segs[i].ds_addr);
1292 desc32->length = htole16(segs[i].ds_len - 1);
1293 desc32->flags = htole16(flags);
1296 /* csum flags and vtag belong to the first fragment only */
1297 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1301 KKASSERT(ring->queued <= sc->sc_tx_ring_count);
1304 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1305 if (sc->sc_caps & NFE_40BIT_ADDR) {
1306 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1308 if (sc->sc_caps & NFE_JUMBO_SUP)
1309 flags = NFE_TX_LASTFRAG_V2;
1311 flags = NFE_TX_LASTFRAG_V1;
1312 desc32->flags |= htole16(flags);
1316 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1317 * whole mess until the first descriptor in the map is flagged.
1319 for (i = nsegs - 1; i >= 0; --i) {
1320 j = (ring->cur + i) % sc->sc_tx_ring_count;
1321 if (sc->sc_caps & NFE_40BIT_ADDR) {
1322 desc64 = &ring->desc64[j];
1323 desc64->flags |= htole16(NFE_TX_VALID);
1325 desc32 = &ring->desc32[j];
1326 desc32->flags |= htole16(NFE_TX_VALID);
1329 ring->cur = (ring->cur + nsegs) % sc->sc_tx_ring_count;
1331 /* Exchange DMA map */
1332 data_map->map = data->map;
1342 nfe_start(struct ifnet *ifp)
1344 struct nfe_softc *sc = ifp->if_softc;
1345 struct nfe_tx_ring *ring = &sc->txq;
1346 int count = 0, oactive = 0;
1349 ASSERT_SERIALIZED(ifp->if_serializer);
1351 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1357 if (sc->sc_tx_ring_count - ring->queued <
1358 sc->sc_tx_spare + NFE_NSEG_RSVD) {
1360 ifp->if_flags |= IFF_OACTIVE;
1369 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1373 ETHER_BPF_MTAP(ifp, m0);
1375 error = nfe_encap(sc, ring, m0);
1378 if (error == EFBIG) {
1380 ifp->if_flags |= IFF_OACTIVE;
1394 * `m0' may be freed in nfe_encap(), so
1395 * it should not be touched any more.
1399 if (count == 0) /* nothing sent */
1403 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1406 * Set a timeout in case the chip goes out to lunch.
1412 nfe_watchdog(struct ifnet *ifp)
1414 struct nfe_softc *sc = ifp->if_softc;
1416 ASSERT_SERIALIZED(ifp->if_serializer);
1418 if (ifp->if_flags & IFF_RUNNING) {
1419 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1424 if_printf(ifp, "watchdog timeout\n");
1426 nfe_init(ifp->if_softc);
1434 struct nfe_softc *sc = xsc;
1435 struct ifnet *ifp = &sc->arpcom.ac_if;
1439 ASSERT_SERIALIZED(ifp->if_serializer);
1443 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
1448 * Switching between jumbo frames and normal frames should
1449 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1451 if (ifp->if_mtu > ETHERMTU) {
1452 sc->sc_flags |= NFE_F_USE_JUMBO;
1453 sc->rxq.bufsz = NFE_JBYTES;
1454 sc->sc_tx_spare = NFE_NSEG_SPARE_JUMBO;
1456 if_printf(ifp, "use jumbo frames\n");
1458 sc->sc_flags &= ~NFE_F_USE_JUMBO;
1459 sc->rxq.bufsz = MCLBYTES;
1460 sc->sc_tx_spare = NFE_NSEG_SPARE;
1462 if_printf(ifp, "use non-jumbo frames\n");
1465 error = nfe_init_tx_ring(sc, &sc->txq);
1471 error = nfe_init_rx_ring(sc, &sc->rxq);
1477 NFE_WRITE(sc, NFE_TX_POLL, 0);
1478 NFE_WRITE(sc, NFE_STATUS, 0);
1480 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1482 if (ifp->if_capenable & IFCAP_RXCSUM)
1483 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1486 * Although the adapter is capable of stripping VLAN tags from received
1487 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1488 * purpose. This will be done in software by our network stack.
1490 if (sc->sc_caps & NFE_HW_VLAN)
1491 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1493 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1495 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1497 if (sc->sc_caps & NFE_HW_VLAN)
1498 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1500 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1502 /* set MAC address */
1503 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1505 /* tell MAC where rings are in memory */
1506 if (sc->sc_caps & NFE_40BIT_ADDR) {
1507 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
1508 NFE_ADDR_HI(sc->rxq.physaddr));
1510 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, NFE_ADDR_LO(sc->rxq.physaddr));
1512 if (sc->sc_caps & NFE_40BIT_ADDR) {
1513 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI,
1514 NFE_ADDR_HI(sc->txq.physaddr));
1516 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr));
1518 NFE_WRITE(sc, NFE_RING_SIZE,
1519 (sc->sc_rx_ring_count - 1) << 16 |
1520 (sc->sc_tx_ring_count - 1));
1522 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1524 /* force MAC to wakeup */
1525 tmp = NFE_READ(sc, NFE_PWR_STATE);
1526 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1528 tmp = NFE_READ(sc, NFE_PWR_STATE);
1529 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1531 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1532 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1533 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1535 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1536 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1538 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1540 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1541 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1543 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1548 nfe_ifmedia_upd(ifp);
1551 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1554 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1556 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1558 #ifdef DEVICE_POLLING
1559 if ((ifp->if_flags & IFF_POLLING))
1560 nfe_disable_intrs(sc);
1563 nfe_enable_intrs(sc);
1565 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1567 ifp->if_flags |= IFF_RUNNING;
1568 ifp->if_flags &= ~IFF_OACTIVE;
1571 * If we had stuff in the tx ring before its all cleaned out now
1572 * so we are not going to get an interrupt, jump-start any pending
1575 if (!ifq_is_empty(&ifp->if_snd))
1580 nfe_stop(struct nfe_softc *sc)
1582 struct ifnet *ifp = &sc->arpcom.ac_if;
1583 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
1586 ASSERT_SERIALIZED(ifp->if_serializer);
1588 callout_stop(&sc->sc_tick_ch);
1591 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1592 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
1594 #define WAITMAX 50000
1599 NFE_WRITE(sc, NFE_TX_CTL, 0);
1600 for (i = 0; i < WAITMAX; ++i) {
1602 if ((NFE_READ(sc, NFE_TX_STATUS) & NFE_TX_STATUS_BUSY) == 0)
1606 if_printf(ifp, "can't stop TX\n");
1612 NFE_WRITE(sc, NFE_RX_CTL, 0);
1613 for (i = 0; i < WAITMAX; ++i) {
1615 if ((NFE_READ(sc, NFE_RX_STATUS) & NFE_RX_STATUS_BUSY) == 0)
1619 if_printf(ifp, "can't stop RX\n");
1624 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
1626 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
1628 /* Disable interrupts */
1629 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1631 /* Reset Tx and Rx rings */
1632 nfe_reset_tx_ring(sc, &sc->txq);
1633 nfe_reset_rx_ring(sc, &sc->rxq);
1637 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1639 int i, j, error, descsize;
1643 if (sc->sc_caps & NFE_40BIT_ADDR) {
1644 desc = (void **)&ring->desc64;
1645 descsize = sizeof(struct nfe_desc64);
1647 desc = (void **)&ring->desc32;
1648 descsize = sizeof(struct nfe_desc32);
1651 ring->bufsz = MCLBYTES;
1652 ring->cur = ring->next = 0;
1654 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1655 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1656 sc->sc_rx_ring_count * descsize,
1657 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1659 if_printf(&sc->arpcom.ac_if,
1660 "could not create RX desc ring\n");
1663 ring->tag = dmem.dmem_tag;
1664 ring->map = dmem.dmem_map;
1665 *desc = dmem.dmem_addr;
1666 ring->physaddr = dmem.dmem_busaddr;
1668 if (sc->sc_caps & NFE_JUMBO_SUP) {
1670 kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT(sc),
1671 M_DEVBUF, M_WAITOK | M_ZERO);
1673 error = nfe_jpool_alloc(sc, ring);
1675 if_printf(&sc->arpcom.ac_if,
1676 "could not allocate jumbo frames\n");
1677 kfree(ring->jbuf, M_DEVBUF);
1679 /* Allow jumbo frame allocation to fail */
1683 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1684 M_DEVBUF, M_WAITOK | M_ZERO);
1686 error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
1687 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1689 MCLBYTES, 1, MCLBYTES,
1690 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
1693 if_printf(&sc->arpcom.ac_if,
1694 "could not create RX mbuf DMA tag\n");
1698 /* Create a spare RX mbuf DMA map */
1699 error = bus_dmamap_create(ring->data_tag, BUS_DMA_WAITOK,
1700 &ring->data_tmpmap);
1702 if_printf(&sc->arpcom.ac_if,
1703 "could not create spare RX mbuf DMA map\n");
1704 bus_dma_tag_destroy(ring->data_tag);
1705 ring->data_tag = NULL;
1709 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1710 error = bus_dmamap_create(ring->data_tag, BUS_DMA_WAITOK,
1711 &ring->data[i].map);
1713 if_printf(&sc->arpcom.ac_if,
1714 "could not create %dth RX mbuf DMA mapn", i);
1720 for (j = 0; j < i; ++j)
1721 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1722 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1723 bus_dma_tag_destroy(ring->data_tag);
1724 ring->data_tag = NULL;
1729 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1733 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1734 struct nfe_rx_data *data = &ring->data[i];
1736 if (data->m != NULL) {
1737 if ((sc->sc_flags & NFE_F_USE_JUMBO) == 0)
1738 bus_dmamap_unload(ring->data_tag, data->map);
1744 ring->cur = ring->next = 0;
1748 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1752 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1755 /* XXX should use a function pointer */
1756 if (sc->sc_flags & NFE_F_USE_JUMBO)
1757 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1759 error = nfe_newbuf_std(sc, ring, i, 1);
1761 if_printf(&sc->arpcom.ac_if,
1762 "could not allocate RX buffer\n");
1765 nfe_set_ready_rxdesc(sc, ring, i);
1771 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1773 if (ring->data_tag != NULL) {
1774 struct nfe_rx_data *data;
1777 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1778 data = &ring->data[i];
1780 if (data->m != NULL) {
1781 bus_dmamap_unload(ring->data_tag, data->map);
1784 bus_dmamap_destroy(ring->data_tag, data->map);
1786 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1787 bus_dma_tag_destroy(ring->data_tag);
1790 nfe_jpool_free(sc, ring);
1792 if (ring->jbuf != NULL)
1793 kfree(ring->jbuf, M_DEVBUF);
1794 if (ring->data != NULL)
1795 kfree(ring->data, M_DEVBUF);
1797 if (ring->tag != NULL) {
1800 if (sc->sc_caps & NFE_40BIT_ADDR)
1801 desc = ring->desc64;
1803 desc = ring->desc32;
1805 bus_dmamap_unload(ring->tag, ring->map);
1806 bus_dmamem_free(ring->tag, desc, ring->map);
1807 bus_dma_tag_destroy(ring->tag);
1811 static struct nfe_jbuf *
1812 nfe_jalloc(struct nfe_softc *sc)
1814 struct ifnet *ifp = &sc->arpcom.ac_if;
1815 struct nfe_jbuf *jbuf;
1817 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1819 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1821 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1824 if_printf(ifp, "no free jumbo buffer\n");
1827 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1833 nfe_jfree(void *arg)
1835 struct nfe_jbuf *jbuf = arg;
1836 struct nfe_softc *sc = jbuf->sc;
1837 struct nfe_rx_ring *ring = jbuf->ring;
1839 if (&ring->jbuf[jbuf->slot] != jbuf)
1840 panic("%s: free wrong jumbo buffer\n", __func__);
1841 else if (jbuf->inuse == 0)
1842 panic("%s: jumbo buffer already freed\n", __func__);
1844 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1845 atomic_subtract_int(&jbuf->inuse, 1);
1846 if (jbuf->inuse == 0)
1847 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1848 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1854 struct nfe_jbuf *jbuf = arg;
1855 struct nfe_rx_ring *ring = jbuf->ring;
1857 if (&ring->jbuf[jbuf->slot] != jbuf)
1858 panic("%s: ref wrong jumbo buffer\n", __func__);
1859 else if (jbuf->inuse == 0)
1860 panic("%s: jumbo buffer already freed\n", __func__);
1862 atomic_add_int(&jbuf->inuse, 1);
1866 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1868 struct nfe_jbuf *jbuf;
1870 bus_addr_t physaddr;
1875 * Allocate a big chunk of DMA'able memory.
1877 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1878 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1880 BUS_DMA_WAITOK, &dmem);
1882 if_printf(&sc->arpcom.ac_if,
1883 "could not create jumbo buffer\n");
1886 ring->jtag = dmem.dmem_tag;
1887 ring->jmap = dmem.dmem_map;
1888 ring->jpool = dmem.dmem_addr;
1889 physaddr = dmem.dmem_busaddr;
1891 /* ..and split it into 9KB chunks */
1892 SLIST_INIT(&ring->jfreelist);
1895 for (i = 0; i < NFE_JPOOL_COUNT(sc); i++) {
1896 jbuf = &ring->jbuf[i];
1903 jbuf->physaddr = physaddr;
1905 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1908 physaddr += NFE_JBYTES;
1915 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1917 if (ring->jtag != NULL) {
1918 bus_dmamap_unload(ring->jtag, ring->jmap);
1919 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1920 bus_dma_tag_destroy(ring->jtag);
1925 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1927 int i, j, error, descsize;
1931 if (sc->sc_caps & NFE_40BIT_ADDR) {
1932 desc = (void **)&ring->desc64;
1933 descsize = sizeof(struct nfe_desc64);
1935 desc = (void **)&ring->desc32;
1936 descsize = sizeof(struct nfe_desc32);
1940 ring->cur = ring->next = 0;
1942 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1943 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1944 sc->sc_tx_ring_count * descsize,
1945 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1947 if_printf(&sc->arpcom.ac_if,
1948 "could not create TX desc ring\n");
1951 ring->tag = dmem.dmem_tag;
1952 ring->map = dmem.dmem_map;
1953 *desc = dmem.dmem_addr;
1954 ring->physaddr = dmem.dmem_busaddr;
1956 ring->data = kmalloc(sizeof(struct nfe_tx_data) * sc->sc_tx_ring_count,
1957 M_DEVBUF, M_WAITOK | M_ZERO);
1959 error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
1960 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1962 NFE_JBYTES, NFE_MAX_SCATTER, MCLBYTES,
1963 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1966 if_printf(&sc->arpcom.ac_if,
1967 "could not create TX buf DMA tag\n");
1971 for (i = 0; i < sc->sc_tx_ring_count; i++) {
1972 error = bus_dmamap_create(ring->data_tag,
1973 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1974 &ring->data[i].map);
1976 if_printf(&sc->arpcom.ac_if,
1977 "could not create %dth TX buf DMA map\n", i);
1984 for (j = 0; j < i; ++j)
1985 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1986 bus_dma_tag_destroy(ring->data_tag);
1987 ring->data_tag = NULL;
1992 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1996 for (i = 0; i < sc->sc_tx_ring_count; i++) {
1997 struct nfe_tx_data *data = &ring->data[i];
1999 if (sc->sc_caps & NFE_40BIT_ADDR)
2000 ring->desc64[i].flags = 0;
2002 ring->desc32[i].flags = 0;
2004 if (data->m != NULL) {
2005 bus_dmamap_unload(ring->data_tag, data->map);
2012 ring->cur = ring->next = 0;
2016 nfe_init_tx_ring(struct nfe_softc *sc __unused,
2017 struct nfe_tx_ring *ring __unused)
2023 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
2025 if (ring->data_tag != NULL) {
2026 struct nfe_tx_data *data;
2029 for (i = 0; i < sc->sc_tx_ring_count; ++i) {
2030 data = &ring->data[i];
2032 if (data->m != NULL) {
2033 bus_dmamap_unload(ring->data_tag, data->map);
2036 bus_dmamap_destroy(ring->data_tag, data->map);
2039 bus_dma_tag_destroy(ring->data_tag);
2042 if (ring->data != NULL)
2043 kfree(ring->data, M_DEVBUF);
2045 if (ring->tag != NULL) {
2048 if (sc->sc_caps & NFE_40BIT_ADDR)
2049 desc = ring->desc64;
2051 desc = ring->desc32;
2053 bus_dmamap_unload(ring->tag, ring->map);
2054 bus_dmamem_free(ring->tag, desc, ring->map);
2055 bus_dma_tag_destroy(ring->tag);
2060 nfe_ifmedia_upd(struct ifnet *ifp)
2062 struct nfe_softc *sc = ifp->if_softc;
2063 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2065 ASSERT_SERIALIZED(ifp->if_serializer);
2067 if (mii->mii_instance != 0) {
2068 struct mii_softc *miisc;
2070 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2071 mii_phy_reset(miisc);
2079 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2081 struct nfe_softc *sc = ifp->if_softc;
2082 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2084 ASSERT_SERIALIZED(ifp->if_serializer);
2087 ifmr->ifm_status = mii->mii_media_status;
2088 ifmr->ifm_active = mii->mii_media_active;
2092 nfe_setmulti(struct nfe_softc *sc)
2094 struct ifnet *ifp = &sc->arpcom.ac_if;
2095 struct ifmultiaddr *ifma;
2096 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2097 uint32_t filter = NFE_RXFILTER_MAGIC;
2100 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2101 bzero(addr, ETHER_ADDR_LEN);
2102 bzero(mask, ETHER_ADDR_LEN);
2106 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2107 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2109 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2112 if (ifma->ifma_addr->sa_family != AF_LINK)
2115 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2116 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2117 addr[i] &= maddr[i];
2118 mask[i] &= ~maddr[i];
2122 for (i = 0; i < ETHER_ADDR_LEN; i++)
2126 addr[0] |= 0x01; /* make sure multicast bit is set */
2128 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2129 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2130 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2131 addr[5] << 8 | addr[4]);
2132 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2133 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2134 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2135 mask[5] << 8 | mask[4]);
2137 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2138 NFE_WRITE(sc, NFE_RXFILTER, filter);
2142 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2146 lo = NFE_READ(sc, NFE_MACADDR_LO);
2147 hi = NFE_READ(sc, NFE_MACADDR_HI);
2148 if (sc->sc_caps & NFE_FIX_EADDR) {
2149 addr[0] = (lo >> 8) & 0xff;
2150 addr[1] = (lo & 0xff);
2152 addr[2] = (hi >> 24) & 0xff;
2153 addr[3] = (hi >> 16) & 0xff;
2154 addr[4] = (hi >> 8) & 0xff;
2155 addr[5] = (hi & 0xff);
2157 addr[0] = (hi & 0xff);
2158 addr[1] = (hi >> 8) & 0xff;
2159 addr[2] = (hi >> 16) & 0xff;
2160 addr[3] = (hi >> 24) & 0xff;
2162 addr[4] = (lo & 0xff);
2163 addr[5] = (lo >> 8) & 0xff;
2168 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2170 NFE_WRITE(sc, NFE_MACADDR_LO,
2171 addr[5] << 8 | addr[4]);
2172 NFE_WRITE(sc, NFE_MACADDR_HI,
2173 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2179 struct nfe_softc *sc = arg;
2180 struct ifnet *ifp = &sc->arpcom.ac_if;
2181 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2183 lwkt_serialize_enter(ifp->if_serializer);
2186 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2188 lwkt_serialize_exit(ifp->if_serializer);
2192 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2195 struct nfe_rx_data *data = &ring->data[idx];
2196 bus_dma_segment_t seg;
2201 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2204 m->m_len = m->m_pkthdr.len = MCLBYTES;
2207 * Aligning the payload improves access times.
2209 if (sc->sc_caps & NFE_WORDALIGN)
2210 m_adj(m, ETHER_ALIGN);
2212 error = bus_dmamap_load_mbuf_segment(ring->data_tag, ring->data_tmpmap,
2213 m, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
2217 if_printf(&sc->arpcom.ac_if,
2218 "could map RX mbuf %d\n", error);
2223 if (data->m != NULL) {
2224 /* Sync and unload originally mapped mbuf */
2225 bus_dmamap_sync(ring->data_tag, data->map,
2226 BUS_DMASYNC_POSTREAD);
2227 bus_dmamap_unload(ring->data_tag, data->map);
2230 /* Swap this DMA map with tmp DMA map */
2232 data->map = ring->data_tmpmap;
2233 ring->data_tmpmap = map;
2235 /* Caller is assumed to have collected the old mbuf */
2238 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2243 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2246 struct nfe_rx_data *data = &ring->data[idx];
2247 struct nfe_jbuf *jbuf;
2250 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2254 jbuf = nfe_jalloc(sc);
2257 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2258 "-- packet dropped!\n");
2262 m->m_ext.ext_arg = jbuf;
2263 m->m_ext.ext_buf = jbuf->buf;
2264 m->m_ext.ext_free = nfe_jfree;
2265 m->m_ext.ext_ref = nfe_jref;
2266 m->m_ext.ext_size = NFE_JBYTES;
2268 m->m_data = m->m_ext.ext_buf;
2269 m->m_flags |= M_EXT;
2270 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2273 * Aligning the payload improves access times.
2275 if (sc->sc_caps & NFE_WORDALIGN)
2276 m_adj(m, ETHER_ALIGN);
2278 /* Caller is assumed to have collected the old mbuf */
2281 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2286 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2287 bus_addr_t physaddr)
2289 if (sc->sc_caps & NFE_40BIT_ADDR) {
2290 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2292 desc64->physaddr[0] = htole32(NFE_ADDR_HI(physaddr));
2293 desc64->physaddr[1] = htole32(NFE_ADDR_LO(physaddr));
2295 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2297 desc32->physaddr = htole32(physaddr);
2302 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2304 if (sc->sc_caps & NFE_40BIT_ADDR) {
2305 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2307 desc64->length = htole16(ring->bufsz);
2308 desc64->flags = htole16(NFE_RX_READY);
2310 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2312 desc32->length = htole16(ring->bufsz);
2313 desc32->flags = htole16(NFE_RX_READY);
2318 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2320 struct nfe_softc *sc = arg1;
2321 struct ifnet *ifp = &sc->arpcom.ac_if;
2325 lwkt_serialize_enter(ifp->if_serializer);
2327 flags = sc->sc_flags & ~NFE_F_DYN_IM;
2329 if (sc->sc_flags & NFE_F_DYN_IM)
2332 error = sysctl_handle_int(oidp, &v, 0, req);
2333 if (error || req->newptr == NULL)
2337 flags |= NFE_F_DYN_IM;
2341 if (v != sc->sc_imtime || (flags ^ sc->sc_flags)) {
2342 if (NFE_IMTIME(v) == 0)
2345 sc->sc_flags = flags;
2346 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2348 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2350 nfe_enable_intrs(sc);
2354 lwkt_serialize_exit(ifp->if_serializer);
2359 nfe_powerup(device_t dev)
2361 struct nfe_softc *sc = device_get_softc(dev);
2366 * Bring MAC and PHY out of low power state
2369 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2371 did = pci_get_device(dev);
2372 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2373 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2374 pci_get_revid(dev) >= 0xa3)
2375 pwr_state |= NFE_PWRUP_REV_A3;
2377 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2381 nfe_mac_reset(struct nfe_softc *sc)
2383 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2384 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2386 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2388 /* Save several registers for later restoration */
2389 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2390 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2391 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2393 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2396 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2399 /* Restore saved registers */
2400 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2401 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2402 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2404 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
2408 nfe_enable_intrs(struct nfe_softc *sc)
2411 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
2412 * It is unclear how wide the timer is. Base programming does
2413 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
2414 * we don't get any interrupt moderation. TX moderation is
2415 * possible by using the timer interrupt instead of TX_DONE.
2417 * It is unclear whether there are other bits that can be
2418 * set to make the NFE device actually do interrupt moderation
2421 * For now set a 128uS interval as a placemark, but don't use
2424 if (sc->sc_imtime == 0)
2425 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
2427 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
2429 /* Enable interrupts */
2430 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
2432 if (sc->sc_irq_enable & NFE_IRQ_TIMER)
2433 sc->sc_flags |= NFE_F_IRQ_TIMER;
2435 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
2438 #ifdef DEVICE_POLLING
2440 nfe_disable_intrs(struct nfe_softc *sc)
2442 /* Disable interrupts */
2443 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
2444 sc->sc_flags &= ~NFE_F_IRQ_TIMER;