sys/dev/serial/rc/rc.c

   1 /*
   2  * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
   3  * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
  28  * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.23 2007/04/12 18:35:09 swildner Exp $
  29  *
  30  */
  31
  32 /*
  33  * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
  34  *
  35  */
  36
  37 #include "use_rc.h"
  38
  39 /*#define RCDEBUG*/
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/tty.h>
  44 #include <sys/proc.h>
  45 #include <sys/conf.h>
  46 #include <sys/dkstat.h>
  47 #include <sys/fcntl.h>
  48 #include <sys/interrupt.h>
  49 #include <sys/kernel.h>
  50 #include <sys/thread2.h>
  51 #include <machine/clock.h>
  52
  53 #include <bus/isa/i386/isa_device.h>
  54
  55 #include <machine_base/isa/ic/cd180.h>
  56 #include "rcreg.h"
  57
  58 /* Prototypes */
  59 static int     rcprobe         (struct isa_device *);
  60 static int     rcattach        (struct isa_device *);
  61
  62 #define rcin(port)      RC_IN  (nec, port)
  63 #define rcout(port,v)   RC_OUT (nec, port, v)
  64
  65 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
  66 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
  67
  68 #define RC_IBUFSIZE     256
  69 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
  70 #define RC_OBUFSIZE     512
  71 #define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
  72 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
  73 #define LOTS_OF_EVENTS  64
  74
  75 #define RC_FAKEID       0x10
  76
  77 #define RC_PROBED 1
  78 #define RC_ATTACHED 2
  79
  80 #define GET_UNIT(dev)   (minor(dev) & 0x3F)
  81 #define CALLOUT(dev)    (minor(dev) & 0x80)
  82
  83 /* For isa routines */
  84 struct isa_driver rcdriver = {
  85         rcprobe, rcattach, "rc"
  86 };
  87
  88 static  d_open_t        rcopen;
  89 static  d_close_t       rcclose;
  90 static  d_ioctl_t       rcioctl;
  91
  92 #define CDEV_MAJOR      63
  93 static struct dev_ops rc_ops = {
  94         { "rc", CDEV_MAJOR, D_TTY | D_KQFILTER },
  95         .d_open =       rcopen,
  96         .d_close =      rcclose,
  97         .d_read =       ttyread,
  98         .d_write =      ttywrite,
  99         .d_ioctl =      rcioctl,
 100         .d_poll =       ttypoll,
 101         .d_kqfilter =   ttykqfilter
 102 };
 103
 104 /* Per-board structure */
 105 static struct rc_softc {
 106         u_int           rcb_probed;     /* 1 - probed, 2 - attached */
 107         u_int           rcb_addr;       /* Base I/O addr        */
 108         u_int           rcb_unit;       /* unit #               */
 109         u_char          rcb_dtr;        /* DTR status           */
 110         struct rc_chans *rcb_baserc;    /* base rc ptr          */
 111 } rc_softc[NRC];
 112
 113 /* Per-channel structure */
 114 static struct rc_chans  {
 115         struct rc_softc *rc_rcb;                /* back ptr             */
 116         u_short          rc_flags;              /* Misc. flags          */
 117         int              rc_chan;               /* Channel #            */
 118         u_char           rc_ier;                /* intr. enable reg     */
 119         u_char           rc_msvr;               /* modem sig. status    */
 120         u_char           rc_cor2;               /* options reg          */
 121         u_char           rc_pendcmd;            /* special cmd pending  */
 122         u_int            rc_dtrwait;            /* dtr timeout          */
 123         u_int            rc_dcdwaits;           /* how many waits DCD in open */
 124         u_char           rc_hotchar;            /* end packed optimize */
 125         struct tty      *rc_tp;                 /* tty struct           */
 126         u_char          *rc_iptr;               /* Chars input buffer         */
 127         u_char          *rc_hiwat;              /* hi-water mark        */
 128         u_char          *rc_bufend;             /* end of buffer        */
 129         u_char          *rc_optr;               /* ptr in output buf    */
 130         u_char          *rc_obufend;            /* end of output buf    */
 131         struct callout   rc_dtr_ch;
 132         u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
 133         u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
 134 } rc_chans[NRC * CD180_NCHAN];
 135
 136 static int rc_scheduled_event = 0;
 137 static struct callout rc_wakeup_ch;
 138
 139 /* for pstat -t */
 140 static struct tty rc_tty[NRC * CD180_NCHAN];
 141 static const int  nrc_tty = NRC * CD180_NCHAN;
 142
 143 /* Flags */
 144 #define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
 145 #define RC_ACTOUT       0x0002          /* Dial-out port active         */
 146 #define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
 147 #define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
 148 #define RC_DORXFER      0x0010          /* RXFER event planned          */
 149 #define RC_DOXXFER      0x0020          /* XXFER event planned          */
 150 #define RC_MODCHG       0x0040          /* Modem status changed         */
 151 #define RC_OSUSP        0x0080          /* Output suspended             */
 152 #define RC_OSBUSY       0x0100          /* start() routine in progress  */
 153 #define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
 154 #define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
 155 #define RC_SEND_RDY     0x0800          /* ready to send */
 156
 157 /* Table for translation of RCSR status bits to internal form */
 158 static int rc_rcsrt[16] = {
 159         0,             TTY_OE,               TTY_FE,
 160         TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
 161         TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
 162         TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
 163         TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
 164         TTY_BI|TTY_PE|TTY_FE|TTY_OE
 165 };
 166
 167 /* Static prototypes */
 168 static inthand2_t rcintr;
 169 static void rc_hwreset          (int, int, unsigned int);
 170 static int  rc_test             (int, int);
 171 static void rc_discard_output   (struct rc_chans *);
 172 static void rc_hardclose        (struct rc_chans *);
 173 static int  rc_modctl           (struct rc_chans *, int, int);
 174 static void rc_start            (struct tty *);
 175 static void rc_stop              (struct tty *, int rw);
 176 static int  rc_param            (struct tty *, struct termios *);
 177 static inthand2_t rcpoll;
 178 static void rc_reinit           (struct rc_softc *);
 179 #ifdef RCDEBUG
 180 static void printrcflags();
 181 #endif
 182 static timeout_t rc_dtrwakeup;
 183 static timeout_t rc_wakeup;
 184 static void disc_optim          (struct tty     *tp, struct termios *t, struct rc_chans *);
 185 static void rc_wait0            (int nec, int unit, int chan, int line);
 186
 187 /**********************************************/
 188
 189 /* Quick device probing */
 190 static int
 191 rcprobe(struct isa_device *dvp)
 192 {
 193         int             irq = ffs(dvp->id_irq) - 1;
 194         int    nec = dvp->id_iobase;
 195
 196         if (dvp->id_unit > NRC)
 197                 return 0;
 198         if (!RC_VALIDADDR(nec)) {
 199                 kprintf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
 200                 return 0;
 201         }
 202         if (!RC_VALIDIRQ(irq)) {
 203                 kprintf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
 204                 return 0;
 205         }
 206         rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
 207         rcout(CD180_PPRH, 0x11);
 208         if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
 209                 return 0;
 210         /* Now, test the board more thoroughly, with diagnostic */
 211         if (rc_test(nec, dvp->id_unit))
 212                 return 0;
 213         rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
 214
 215         return 0xF;
 216 }
 217
 218 static int
 219 rcattach(struct isa_device *dvp)
 220 {
 221         int            chan, nec = dvp->id_iobase;
 222         struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
 223         struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
 224         static int              rc_started = 0;
 225         struct tty              *tp;
 226
 227         dvp->id_intr = rcintr;
 228
 229         /* Thorooughly test the device */
 230         if (rcb->rcb_probed != RC_PROBED)
 231                 return 0;
 232         rcb->rcb_addr   = nec;
 233         rcb->rcb_dtr    = 0;
 234         rcb->rcb_baserc = rc;
 235         rcb->rcb_unit   = dvp->id_unit;
 236         /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
 237         kprintf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
 238                 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
 239
 240         for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
 241                 callout_init(&rc->rc_dtr_ch);
 242                 rc->rc_rcb     = rcb;
 243                 rc->rc_chan    = chan;
 244                 rc->rc_iptr    = rc->rc_ibuf;
 245                 rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
 246                 rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
 247                 rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
 248                 rc->rc_cor2    = rc->rc_pendcmd = 0;
 249                 rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
 250                 rc->rc_dtrwait = 3 * hz;
 251                 rc->rc_dcdwaits= 0;
 252                 rc->rc_hotchar = 0;
 253                 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
 254                 ttychars(tp);
 255                 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
 256                 tp->t_cflag = TTYDEF_CFLAG;
 257                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
 258         }
 259         rcb->rcb_probed = RC_ATTACHED;
 260         if (!rc_started) {
 261                 dev_ops_add(&rc_ops, -1, rcb->rcb_unit);
 262                 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll", NULL);
 263                 callout_init(&rc_wakeup_ch);
 264                 rc_wakeup(NULL);
 265                 rc_started = 1;
 266         }
 267         return 1;
 268 }
 269
 270 /* RC interrupt handling */
 271 static void
 272 rcintr(void *arg, void *frame)
 273 {
 274         int unit = (int)arg;
 275         struct rc_softc        *rcb = &rc_softc[unit];
 276         struct rc_chans        *rc;
 277         int                    nec, resid;
 278         u_char                 val, iack, bsr, ucnt, *optr;
 279         int                             good_data, t_state;
 280
 281         if (rcb->rcb_probed != RC_ATTACHED) {
 282                 kprintf("rc%d: bogus interrupt\n", unit);
 283                 return;
 284         }
 285         nec = rcb->rcb_addr;
 286
 287         bsr = ~(rcin(RC_BSR));
 288
 289         if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
 290                 kprintf("rc%d: extra interrupt\n", unit);
 291                 rcout(CD180_EOIR, 0);
 292                 return;
 293         }
 294
 295         while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
 296 #ifdef RCDEBUG_DETAILED
 297                 kprintf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
 298                         (bsr & RC_BSR_TOUT)?"TOUT ":"",
 299                         (bsr & RC_BSR_RXINT)?"RXINT ":"",
 300                         (bsr & RC_BSR_TXINT)?"TXINT ":"",
 301                         (bsr & RC_BSR_MOINT)?"MOINT":"");
 302 #endif
 303                 if (bsr & RC_BSR_TOUT) {
 304                         kprintf("rc%d: hardware failure, reset board\n", unit);
 305                         rcout(RC_CTOUT, 0);
 306                         rc_reinit(rcb);
 307                         return;
 308                 }
 309                 if (bsr & RC_BSR_RXINT) {
 310                         iack = rcin(RC_PILR_RX);
 311                         good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
 312                         if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
 313                                 kprintf("rc%d: fake rxint: %02x\n", unit, iack);
 314                                 goto more_intrs;
 315                         }
 316                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 317                         t_state = rc->rc_tp->t_state;
 318                         /* Do RTS flow control stuff */
 319                         if (  (rc->rc_flags & RC_RTSFLOW)
 320                             || !(t_state & TS_ISOPEN)
 321                            ) {
 322                                 if (  (   !(t_state & TS_ISOPEN)
 323                                        || (t_state & TS_TBLOCK)
 324                                       )
 325                                     && (rc->rc_msvr & MSVR_RTS)
 326                                    )
 327                                         rcout(CD180_MSVR,
 328                                                 rc->rc_msvr &= ~MSVR_RTS);
 329                                 else if (!(rc->rc_msvr & MSVR_RTS))
 330                                         rcout(CD180_MSVR,
 331                                                 rc->rc_msvr |= MSVR_RTS);
 332                         }
 333                         ucnt  = rcin(CD180_RDCR) & 0xF;
 334                         resid = 0;
 335
 336                         if (t_state & TS_ISOPEN) {
 337                                 /* check for input buffer overflow */
 338                                 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
 339                                         resid  = ucnt;
 340                                         ucnt   = rc->rc_bufend - rc->rc_iptr;
 341                                         resid -= ucnt;
 342                                         if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
 343                                                 rc->rc_flags |= RC_WAS_BUFOVFL;
 344                                                 rc_scheduled_event++;
 345                                         }
 346                                 }
 347                                 optr = rc->rc_iptr;
 348                                 /* check foor good data */
 349                                 if (good_data) {
 350                                         while (ucnt-- > 0) {
 351                                                 val = rcin(CD180_RDR);
 352                                                 optr[0] = val;
 353                                                 optr[INPUT_FLAGS_SHIFT] = 0;
 354                                                 optr++;
 355                                                 rc_scheduled_event++;
 356                                                 if (val != 0 && val == rc->rc_hotchar)
 357                                                         setsofttty();
 358                                         }
 359                                 } else {
 360                                         /* Store also status data */
 361                                         while (ucnt-- > 0) {
 362                                                 iack = rcin(CD180_RCSR);
 363                                                 if (iack & RCSR_Timeout)
 364                                                         break;
 365                                                 if (   (iack & RCSR_OE)
 366                                                     && !(rc->rc_flags & RC_WAS_SILOVFL)) {
 367                                                         rc->rc_flags |= RC_WAS_SILOVFL;
 368                                                         rc_scheduled_event++;
 369                                                 }
 370                                                 val = rcin(CD180_RDR);
 371                                                 /*
 372                                                   Don't store PE if IGNPAR and BREAK if IGNBRK,
 373                                                   this hack allows "raw" tty optimization
 374                                                   works even if IGN* is set.
 375                                                 */
 376                                                 if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
 377                                                     || ((!(iack & (RCSR_PE|RCSR_FE))
 378                                                     ||  !(rc->rc_tp->t_iflag & IGNPAR))
 379                                                     && (!(iack & RCSR_Break)
 380                                                     ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
 381                                                         if (   (iack & (RCSR_PE|RCSR_FE))
 382                                                             && (t_state & TS_CAN_BYPASS_L_RINT)
 383                                                             && ((iack & RCSR_FE)
 384                                                             ||  ((iack & RCSR_PE)
 385                                                             &&  (rc->rc_tp->t_iflag & INPCK))))
 386                                                                 val = 0;
 387                                                         else if (val != 0 && val == rc->rc_hotchar)
 388                                                                 setsofttty();
 389                                                         optr[0] = val;
 390                                                         optr[INPUT_FLAGS_SHIFT] = iack;
 391                                                         optr++;
 392                                                         rc_scheduled_event++;
 393                                                 }
 394                                         }
 395                                 }
 396                                 rc->rc_iptr = optr;
 397                                 rc->rc_flags |= RC_DORXFER;
 398                         } else
 399                                 resid = ucnt;
 400                         /* Clear FIFO if necessary */
 401                         while (resid-- > 0) {
 402                                 if (!good_data)
 403                                         iack = rcin(CD180_RCSR);
 404                                 else
 405                                         iack = 0;
 406                                 if (iack & RCSR_Timeout)
 407                                         break;
 408                                 (void) rcin(CD180_RDR);
 409                         }
 410                         goto more_intrs;
 411                 }
 412                 if (bsr & RC_BSR_MOINT) {
 413                         iack = rcin(RC_PILR_MODEM);
 414                         if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
 415                                 kprintf("rc%d: fake moint: %02x\n", unit, iack);
 416                                 goto more_intrs;
 417                         }
 418                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 419                         iack = rcin(CD180_MCR);
 420                         rc->rc_msvr = rcin(CD180_MSVR);
 421                         rcout(CD180_MCR, 0);
 422 #ifdef RCDEBUG
 423                         printrcflags(rc, "moint");
 424 #endif
 425                         if (rc->rc_flags & RC_CTSFLOW) {
 426                                 if (rc->rc_msvr & MSVR_CTS)
 427                                         rc->rc_flags |= RC_SEND_RDY;
 428                                 else
 429                                         rc->rc_flags &= ~RC_SEND_RDY;
 430                         } else
 431                                 rc->rc_flags |= RC_SEND_RDY;
 432                         if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
 433                                 rc_scheduled_event += LOTS_OF_EVENTS;
 434                                 rc->rc_flags |= RC_MODCHG;
 435                                 setsofttty();
 436                         }
 437                         goto more_intrs;
 438                 }
 439                 if (bsr & RC_BSR_TXINT) {
 440                         iack = rcin(RC_PILR_TX);
 441                         if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
 442                                 kprintf("rc%d: fake txint: %02x\n", unit, iack);
 443                                 goto more_intrs;
 444                         }
 445                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 446                         if (    (rc->rc_flags & RC_OSUSP)
 447                             || !(rc->rc_flags & RC_SEND_RDY)
 448                            )
 449                                 goto more_intrs;
 450                         /* Handle breaks and other stuff */
 451                         if (rc->rc_pendcmd) {
 452                                 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
 453                                 rcout(CD180_TDR,  CD180_C_ESC);
 454                                 rcout(CD180_TDR,  rc->rc_pendcmd);
 455                                 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
 456                                 rc->rc_pendcmd = 0;
 457                                 goto more_intrs;
 458                         }
 459                         optr = rc->rc_optr;
 460                         resid = rc->rc_obufend - optr;
 461                         if (resid > CD180_NFIFO)
 462                                 resid = CD180_NFIFO;
 463                         while (resid-- > 0)
 464                                 rcout(CD180_TDR, *optr++);
 465                         rc->rc_optr = optr;
 466
 467                         /* output completed? */
 468                         if (optr >= rc->rc_obufend) {
 469                                 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
 470 #ifdef RCDEBUG
 471                                 kprintf("rc%d/%d: output completed\n", unit, rc->rc_chan);
 472 #endif
 473                                 if (!(rc->rc_flags & RC_DOXXFER)) {
 474                                         rc_scheduled_event += LOTS_OF_EVENTS;
 475                                         rc->rc_flags |= RC_DOXXFER;
 476                                         setsofttty();
 477                                 }
 478                         }
 479                 }
 480         more_intrs:
 481                 rcout(CD180_EOIR, 0);   /* end of interrupt */
 482                 rcout(RC_CTOUT, 0);
 483                 bsr = ~(rcin(RC_BSR));
 484         }
 485 }
 486
 487 /* Feed characters to output buffer */
 488 static void
 489 rc_start(struct tty *tp)
 490 {
 491         struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 492         int                    nec = rc->rc_rcb->rcb_addr;
 493
 494         if (rc->rc_flags & RC_OSBUSY)
 495                 return;
 496         crit_enter();
 497         rc->rc_flags |= RC_OSBUSY;
 498         cpu_disable_intr();
 499         if (tp->t_state & TS_TTSTOP)
 500                 rc->rc_flags |= RC_OSUSP;
 501         else
 502                 rc->rc_flags &= ~RC_OSUSP;
 503         /* Do RTS flow control stuff */
 504         if (   (rc->rc_flags & RC_RTSFLOW)
 505             && (tp->t_state & TS_TBLOCK)
 506             && (rc->rc_msvr & MSVR_RTS)
 507            ) {
 508                 rcout(CD180_CAR, rc->rc_chan);
 509                 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
 510         } else if (!(rc->rc_msvr & MSVR_RTS)) {
 511                 rcout(CD180_CAR, rc->rc_chan);
 512                 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
 513         }
 514         cpu_enable_intr();
 515         if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
 516                 goto out;
 517 #ifdef RCDEBUG
 518         printrcflags(rc, "rcstart");
 519 #endif
 520         ttwwakeup(tp);
 521 #ifdef RCDEBUG
 522         kprintf("rcstart: outq = %d obuf = %d\n",
 523                 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
 524 #endif
 525         if (tp->t_state & TS_BUSY)
 526                 goto    out;    /* output still in progress ... */
 527
 528         if (tp->t_outq.c_cc > 0) {
 529                 u_int   ocnt;
 530
 531                 tp->t_state |= TS_BUSY;
 532                 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
 533                 cpu_disable_intr();
 534                 rc->rc_optr = rc->rc_obuf;
 535                 rc->rc_obufend = rc->rc_optr + ocnt;
 536                 cpu_enable_intr();
 537                 if (!(rc->rc_ier & IER_TxRdy)) {
 538 #ifdef RCDEBUG
 539                         kprintf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
 540 #endif
 541                         rcout(CD180_CAR, rc->rc_chan);
 542                         rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
 543                 }
 544         }
 545 out:
 546         rc->rc_flags &= ~RC_OSBUSY;
 547         crit_exit();
 548 }
 549
 550 /* Handle delayed events. */
 551 void
 552 rcpoll(void *dummy, void *frame)
 553 {
 554         struct rc_chans *rc;
 555         struct rc_softc *rcb;
 556         u_char        *tptr, *eptr;
 557         struct tty    *tp;
 558         int            chan, icnt, nec, unit;
 559
 560         if (rc_scheduled_event == 0)
 561                 return;
 562 repeat:
 563         for (unit = 0; unit < NRC; unit++) {
 564                 rcb = &rc_softc[unit];
 565                 rc = rcb->rcb_baserc;
 566                 nec = rc->rc_rcb->rcb_addr;
 567                 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
 568                         tp = rc->rc_tp;
 569 #ifdef RCDEBUG
 570                         if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
 571                             RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
 572                                 printrcflags(rc, "rcevent");
 573 #endif
 574                         if (rc->rc_flags & RC_WAS_BUFOVFL) {
 575                                 cpu_disable_intr();
 576                                 rc->rc_flags &= ~RC_WAS_BUFOVFL;
 577                                 rc_scheduled_event--;
 578                                 cpu_enable_intr();
 579                                 kprintf("rc%d/%d: interrupt-level buffer overflow\n",
 580                                         unit, chan);
 581                         }
 582                         if (rc->rc_flags & RC_WAS_SILOVFL) {
 583                                 cpu_disable_intr();
 584                                 rc->rc_flags &= ~RC_WAS_SILOVFL;
 585                                 rc_scheduled_event--;
 586                                 cpu_enable_intr();
 587                                 kprintf("rc%d/%d: silo overflow\n",
 588                                         unit, chan);
 589                         }
 590                         if (rc->rc_flags & RC_MODCHG) {
 591                                 cpu_disable_intr();
 592                                 rc->rc_flags &= ~RC_MODCHG;
 593                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 594                                 cpu_enable_intr();
 595                                 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
 596                         }
 597                         if (rc->rc_flags & RC_DORXFER) {
 598                                 cpu_disable_intr();
 599                                 rc->rc_flags &= ~RC_DORXFER;
 600                                 eptr = rc->rc_iptr;
 601                                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
 602                                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 603                                 else
 604                                         tptr = rc->rc_ibuf;
 605                                 icnt = eptr - tptr;
 606                                 if (icnt > 0) {
 607                                         if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 608                                                 rc->rc_iptr   = rc->rc_ibuf;
 609                                                 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
 610                                                 rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
 611                                         } else {
 612                                                 rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
 613                                                 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
 614                                                 rc->rc_hiwat  =
 615                                                         &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
 616                                         }
 617                                         if (   (rc->rc_flags & RC_RTSFLOW)
 618                                             && (tp->t_state & TS_ISOPEN)
 619                                             && !(tp->t_state & TS_TBLOCK)
 620                                             && !(rc->rc_msvr & MSVR_RTS)
 621                                             ) {
 622                                                 rcout(CD180_CAR, chan);
 623                                                 rcout(CD180_MSVR,
 624                                                         rc->rc_msvr |= MSVR_RTS);
 625                                         }
 626                                         rc_scheduled_event -= icnt;
 627                                 }
 628                                 cpu_enable_intr();
 629
 630                                 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
 631                                         goto done1;
 632
 633                                 if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
 634                                     && !(tp->t_state & TS_LOCAL)) {
 635                                         if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
 636                                             && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
 637                                             && !(tp->t_state & TS_TBLOCK))
 638                                                 ttyblock(tp);
 639                                         tk_nin += icnt;
 640                                         tk_rawcc += icnt;
 641                                         tp->t_rawcc += icnt;
 642                                         if (b_to_q(tptr, icnt, &tp->t_rawq))
 643                                                 kprintf("rc%d/%d: tty-level buffer overflow\n",
 644                                                         unit, chan);
 645                                         ttwakeup(tp);
 646                                         if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
 647                                             || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
 648                                                 tp->t_state &= ~TS_TTSTOP;
 649                                                 tp->t_lflag &= ~FLUSHO;
 650                                                 rc_start(tp);
 651                                         }
 652                                 } else {
 653                                         for (; tptr < eptr; tptr++)
 654                                                 (*linesw[tp->t_line].l_rint)
 655                                                     (tptr[0] |
 656                                                     rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
 657                                 }
 658 done1: ;
 659                         }
 660                         if (rc->rc_flags & RC_DOXXFER) {
 661                                 cpu_disable_intr();
 662                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 663                                 rc->rc_flags &= ~RC_DOXXFER;
 664                                 rc->rc_tp->t_state &= ~TS_BUSY;
 665                                 cpu_enable_intr();
 666                                 (*linesw[tp->t_line].l_start)(tp);
 667                         }
 668                 }
 669                 if (rc_scheduled_event == 0)
 670                         break;
 671         }
 672         if (rc_scheduled_event >= LOTS_OF_EVENTS)
 673                 goto repeat;
 674 }
 675
 676 static  void
 677 rc_stop(struct tty *tp, int rw)
 678 {
 679         struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 680         u_char *tptr, *eptr;
 681
 682 #ifdef RCDEBUG
 683         kprintf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
 684                 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
 685 #endif
 686         if (rw & FWRITE)
 687                 rc_discard_output(rc);
 688         cpu_disable_intr();
 689         if (rw & FREAD) {
 690                 rc->rc_flags &= ~RC_DORXFER;
 691                 eptr = rc->rc_iptr;
 692                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 693                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 694                         rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
 695                 } else {
 696                         tptr = rc->rc_ibuf;
 697                         rc->rc_iptr = rc->rc_ibuf;
 698                 }
 699                 rc_scheduled_event -= eptr - tptr;
 700         }
 701         if (tp->t_state & TS_TTSTOP)
 702                 rc->rc_flags |= RC_OSUSP;
 703         else
 704                 rc->rc_flags &= ~RC_OSUSP;
 705         cpu_enable_intr();
 706 }
 707
 708 static  int
 709 rcopen(struct dev_open_args *ap)
 710 {
 711         cdev_t dev = ap->a_head.a_dev;
 712         struct rc_chans *rc;
 713         struct tty      *tp;
 714         int             unit, nec, error = 0;
 715
 716         unit = GET_UNIT(dev);
 717         if (unit >= NRC * CD180_NCHAN)
 718                 return ENXIO;
 719         if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
 720                 return ENXIO;
 721         rc  = &rc_chans[unit];
 722         tp  = rc->rc_tp;
 723         dev->si_tty = tp;
 724         nec = rc->rc_rcb->rcb_addr;
 725 #ifdef RCDEBUG
 726         kprintf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 727 #endif
 728         crit_enter();
 729
 730 again:
 731         while (rc->rc_flags & RC_DTR_OFF) {
 732                 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
 733                 if (error != 0)
 734                         goto out;
 735         }
 736         if (tp->t_state & TS_ISOPEN) {
 737                 if (CALLOUT(dev)) {
 738                         if (!(rc->rc_flags & RC_ACTOUT)) {
 739                                 error = EBUSY;
 740                                 goto out;
 741                         }
 742                 } else {
 743                         if (rc->rc_flags & RC_ACTOUT) {
 744                                 if (ap->a_oflags & O_NONBLOCK) {
 745                                         error = EBUSY;
 746                                         goto out;
 747                                 }
 748                                 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
 749                                 if (error)
 750                                         goto out;
 751                                 goto again;
 752                         }
 753                 }
 754                 if (tp->t_state & TS_XCLUDE &&
 755                     suser_cred(ap->a_cred, 0)) {
 756                         error = EBUSY;
 757                         goto out;
 758                 }
 759         } else {
 760                 tp->t_oproc   = rc_start;
 761                 tp->t_param   = rc_param;
 762                 tp->t_stop    = rc_stop;
 763                 tp->t_dev     = dev;
 764
 765                 if (CALLOUT(dev))
 766                         tp->t_cflag |= CLOCAL;
 767                 else
 768                         tp->t_cflag &= ~CLOCAL;
 769
 770                 error = rc_param(tp, &tp->t_termios);
 771                 if (error)
 772                         goto out;
 773                 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
 774
 775                 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
 776                         (*linesw[tp->t_line].l_modem)(tp, 1);
 777         }
 778         if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
 779             && !(tp->t_cflag & CLOCAL) && !(ap->a_oflags & O_NONBLOCK)) {
 780                 rc->rc_dcdwaits++;
 781                 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
 782                 rc->rc_dcdwaits--;
 783                 if (error != 0)
 784                         goto out;
 785                 goto again;
 786         }
 787         error = (*linesw[tp->t_line].l_open)(dev, tp);
 788         disc_optim(tp, &tp->t_termios, rc);
 789         if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
 790                 rc->rc_flags |= RC_ACTOUT;
 791 out:
 792         crit_exit();
 793
 794         if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
 795                 rc_hardclose(rc);
 796
 797         return error;
 798 }
 799
 800 static int
 801 rcclose(struct dev_close_args *ap)
 802 {
 803         cdev_t dev = ap->a_head.a_dev;
 804         struct rc_chans *rc;
 805         struct tty      *tp;
 806         int unit = GET_UNIT(dev);
 807
 808         if (unit >= NRC * CD180_NCHAN)
 809                 return ENXIO;
 810         rc  = &rc_chans[unit];
 811         tp  = rc->rc_tp;
 812 #ifdef RCDEBUG
 813         kprintf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 814 #endif
 815         crit_enter();
 816         (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
 817         disc_optim(tp, &tp->t_termios, rc);
 818         rc_stop(tp, FREAD | FWRITE);
 819         rc_hardclose(rc);
 820         ttyclose(tp);
 821         crit_exit();
 822         return 0;
 823 }
 824
 825 static void
 826 rc_hardclose(struct rc_chans *rc)
 827 {
 828         int nec = rc->rc_rcb->rcb_addr;
 829         struct tty *tp = rc->rc_tp;
 830
 831         crit_enter();
 832         rcout(CD180_CAR, rc->rc_chan);
 833
 834         /* Disable rx/tx intrs */
 835         rcout(CD180_IER, rc->rc_ier = 0);
 836         if (   (tp->t_cflag & HUPCL)
 837             || (!(rc->rc_flags & RC_ACTOUT)
 838                && !(rc->rc_msvr & MSVR_CD)
 839                && !(tp->t_cflag & CLOCAL))
 840             || !(tp->t_state & TS_ISOPEN)
 841            ) {
 842                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 843                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 844                 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
 845                 if (rc->rc_dtrwait) {
 846                         callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
 847                                 rc_dtrwakeup, rc);
 848                         rc->rc_flags |= RC_DTR_OFF;
 849                 }
 850         }
 851         rc->rc_flags &= ~RC_ACTOUT;
 852         wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
 853         wakeup(TSA_CARR_ON(tp));
 854         crit_exit();
 855 }
 856
 857 /* Reset the bastard */
 858 static void
 859 rc_hwreset(int unit, int nec, unsigned int chipid)
 860 {
 861         CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
 862         DELAY(20000);
 863         WAITFORCCR(unit, -1);
 864
 865         rcout(RC_CTOUT, 0);             /* Clear timeout  */
 866         rcout(CD180_GIVR,  chipid);
 867         rcout(CD180_GICR,  0);
 868
 869         /* Set Prescaler Registers (1 msec) */
 870         rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
 871         rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
 872
 873         /* Initialize Priority Interrupt Level Registers */
 874         rcout(CD180_PILR1, RC_PILR_MODEM);
 875         rcout(CD180_PILR2, RC_PILR_TX);
 876         rcout(CD180_PILR3, RC_PILR_RX);
 877
 878         /* Reset DTR */
 879         rcout(RC_DTREG, ~0);
 880 }
 881
 882 /* Set channel parameters */
 883 static int
 884 rc_param(struct tty *tp, struct termios *ts)
 885 {
 886         struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 887         int    nec = rc->rc_rcb->rcb_addr;
 888         int      idivs, odivs, val, cflag, iflag, lflag, inpflow;
 889
 890         if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
 891             || ts->c_ispeed < 0 || ts->c_ispeed > 76800
 892            )
 893                 return (EINVAL);
 894         if (ts->c_ispeed == 0)
 895                 ts->c_ispeed = ts->c_ospeed;
 896         odivs = RC_BRD(ts->c_ospeed);
 897         idivs = RC_BRD(ts->c_ispeed);
 898
 899         crit_enter();
 900
 901         /* Select channel */
 902         rcout(CD180_CAR, rc->rc_chan);
 903
 904         /* If speed == 0, hangup line */
 905         if (ts->c_ospeed == 0) {
 906                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 907                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 908                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
 909         }
 910
 911         tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
 912         cflag = ts->c_cflag;
 913         iflag = ts->c_iflag;
 914         lflag = ts->c_lflag;
 915
 916         if (idivs > 0) {
 917                 rcout(CD180_RBPRL, idivs & 0xFF);
 918                 rcout(CD180_RBPRH, idivs >> 8);
 919         }
 920         if (odivs > 0) {
 921                 rcout(CD180_TBPRL, odivs & 0xFF);
 922                 rcout(CD180_TBPRH, odivs >> 8);
 923         }
 924
 925         /* set timeout value */
 926         if (ts->c_ispeed > 0) {
 927                 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
 928
 929                 if (   !(lflag & ICANON)
 930                     && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
 931                     && ts->c_cc[VTIME] * 10 > itm)
 932                         itm = ts->c_cc[VTIME] * 10;
 933
 934                 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
 935         }
 936
 937         switch (cflag & CSIZE) {
 938                 case CS5:       val = COR1_5BITS;      break;
 939                 case CS6:       val = COR1_6BITS;      break;
 940                 case CS7:       val = COR1_7BITS;      break;
 941                 default:
 942                 case CS8:       val = COR1_8BITS;      break;
 943         }
 944         if (cflag & PARENB) {
 945                 val |= COR1_NORMPAR;
 946                 if (cflag & PARODD)
 947                         val |= COR1_ODDP;
 948                 if (!(cflag & INPCK))
 949                         val |= COR1_Ignore;
 950         } else
 951                 val |= COR1_Ignore;
 952         if (cflag & CSTOPB)
 953                 val |= COR1_2SB;
 954         rcout(CD180_COR1, val);
 955
 956         /* Set FIFO threshold */
 957         val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
 958         inpflow = 0;
 959         if (   (iflag & IXOFF)
 960             && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
 961                 && (   ts->c_cc[VSTART] != _POSIX_VDISABLE
 962                     || (iflag & IXANY)
 963                    )
 964                )
 965            ) {
 966                 inpflow = 1;
 967                 val |= COR3_SCDE|COR3_FCT;
 968         }
 969         rcout(CD180_COR3, val);
 970
 971         /* Initialize on-chip automatic flow control */
 972         val = 0;
 973         rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
 974         if (cflag & CCTS_OFLOW) {
 975                 rc->rc_flags |= RC_CTSFLOW;
 976                 val |= COR2_CtsAE;
 977         } else
 978                 rc->rc_flags |= RC_SEND_RDY;
 979         if (tp->t_state & TS_TTSTOP)
 980                 rc->rc_flags |= RC_OSUSP;
 981         else
 982                 rc->rc_flags &= ~RC_OSUSP;
 983         if (cflag & CRTS_IFLOW)
 984                 rc->rc_flags |= RC_RTSFLOW;
 985         else
 986                 rc->rc_flags &= ~RC_RTSFLOW;
 987
 988         if (inpflow) {
 989                 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
 990                         rcout(CD180_SCHR1, ts->c_cc[VSTART]);
 991                 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
 992                 val |= COR2_TxIBE;
 993                 if (iflag & IXANY)
 994                         val |= COR2_IXM;
 995         }
 996
 997         rcout(CD180_COR2, rc->rc_cor2 = val);
 998
 999         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1000                 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1001
1002         disc_optim(tp, ts, rc);
1003
1004         /* modem ctl */
1005         val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1006         if (cflag & CCTS_OFLOW)
1007                 val |= MCOR1_CTSzd;
1008         rcout(CD180_MCOR1, val);
1009
1010         val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1011         if (cflag & CCTS_OFLOW)
1012                 val |= MCOR2_CTSod;
1013         rcout(CD180_MCOR2, val);
1014
1015         /* enable i/o and interrupts */
1016         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1017                 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1018         WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1019
1020         rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1021         if (cflag & CCTS_OFLOW)
1022                 rc->rc_ier |= IER_CTS;
1023         if (cflag & CREAD)
1024                 rc->rc_ier |= IER_RxData;
1025         if (tp->t_state & TS_BUSY)
1026                 rc->rc_ier |= IER_TxRdy;
1027         if (ts->c_ospeed != 0)
1028                 rc_modctl(rc, TIOCM_DTR, DMBIS);
1029         if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1030                 rc->rc_flags |= RC_SEND_RDY;
1031         rcout(CD180_IER, rc->rc_ier);
1032         crit_exit();
1033         return 0;
1034 }
1035
1036 /* Re-initialize board after bogus interrupts */
1037 static void
1038 rc_reinit(struct rc_softc *rcb)
1039 {
1040         struct rc_chans       *rc, *rce;
1041         int                    nec;
1042
1043         nec = rcb->rcb_addr;
1044         rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1045         rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1046         rce = rc + CD180_NCHAN;
1047         for (; rc < rce; rc++)
1048                 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1049 }
1050
1051 static  int
1052 rcioctl(struct dev_ioctl_args *ap)
1053 {
1054         cdev_t dev = ap->a_head.a_dev;
1055         struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1056         int                   error;
1057         struct tty                     *tp = rc->rc_tp;
1058
1059         error = (*linesw[tp->t_line].l_ioctl)(tp, ap->a_cmd, ap->a_data,
1060                                               ap->a_fflag, ap->a_cred);
1061         if (error != ENOIOCTL)
1062                 return (error);
1063         error = ttioctl(tp, ap->a_cmd, ap->a_data, ap->a_fflag);
1064         disc_optim(tp, &tp->t_termios, rc);
1065         if (error != ENOIOCTL)
1066                 return (error);
1067         crit_enter();
1068
1069         switch (ap->a_cmd) {
1070             case TIOCSBRK:
1071                 rc->rc_pendcmd = CD180_C_SBRK;
1072                 break;
1073
1074             case TIOCCBRK:
1075                 rc->rc_pendcmd = CD180_C_EBRK;
1076                 break;
1077
1078             case TIOCSDTR:
1079                 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1080                 break;
1081
1082             case TIOCCDTR:
1083                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1084                 break;
1085
1086             case TIOCMGET:
1087                 *(int *) ap->a_data = rc_modctl(rc, 0, DMGET);
1088                 break;
1089
1090             case TIOCMSET:
1091                 (void) rc_modctl(rc, *(int *) ap->a_data, DMSET);
1092                 break;
1093
1094             case TIOCMBIC:
1095                 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIC);
1096                 break;
1097
1098             case TIOCMBIS:
1099                 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIS);
1100                 break;
1101
1102             case TIOCMSDTRWAIT:
1103                 error = suser_cred(ap->a_cred, 0);
1104                 if (error != 0) {
1105                         crit_exit();
1106                         return (error);
1107                 }
1108                 rc->rc_dtrwait = *(int *)ap->a_data * hz / 100;
1109                 break;
1110
1111             case TIOCMGDTRWAIT:
1112                 *(int *)ap->a_data = rc->rc_dtrwait * 100 / hz;
1113                 break;
1114
1115             default:
1116                 crit_exit();
1117                 return ENOTTY;
1118         }
1119         crit_exit();
1120         return 0;
1121 }
1122
1123
1124 /* Modem control routines */
1125
1126 static int
1127 rc_modctl(struct rc_chans *rc, int bits, int cmd)
1128 {
1129         int    nec = rc->rc_rcb->rcb_addr;
1130         u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1131
1132         rcout(CD180_CAR, rc->rc_chan);
1133
1134         switch (cmd) {
1135             case DMSET:
1136                 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1137                                 ~(*dtr |= 1 << rc->rc_chan) :
1138                                 ~(*dtr &= ~(1 << rc->rc_chan)));
1139                 msvr = rcin(CD180_MSVR);
1140                 if (bits & TIOCM_RTS)
1141                         msvr |= MSVR_RTS;
1142                 else
1143                         msvr &= ~MSVR_RTS;
1144                 if (bits & TIOCM_DTR)
1145                         msvr |= MSVR_DTR;
1146                 else
1147                         msvr &= ~MSVR_DTR;
1148                 rcout(CD180_MSVR, msvr);
1149                 break;
1150
1151             case DMBIS:
1152                 if (bits & TIOCM_DTR)
1153                         rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1154                 msvr = rcin(CD180_MSVR);
1155                 if (bits & TIOCM_RTS)
1156                         msvr |= MSVR_RTS;
1157                 if (bits & TIOCM_DTR)
1158                         msvr |= MSVR_DTR;
1159                 rcout(CD180_MSVR, msvr);
1160                 break;
1161
1162             case DMGET:
1163                 bits = TIOCM_LE;
1164                 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1165
1166                 if (msvr & MSVR_RTS)
1167                         bits |= TIOCM_RTS;
1168                 if (msvr & MSVR_CTS)
1169                         bits |= TIOCM_CTS;
1170                 if (msvr & MSVR_DSR)
1171                         bits |= TIOCM_DSR;
1172                 if (msvr & MSVR_DTR)
1173                         bits |= TIOCM_DTR;
1174                 if (msvr & MSVR_CD)
1175                         bits |= TIOCM_CD;
1176                 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1177                         bits |= TIOCM_RI;
1178                 return bits;
1179
1180             case DMBIC:
1181                 if (bits & TIOCM_DTR)
1182                         rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1183                 msvr = rcin(CD180_MSVR);
1184                 if (bits & TIOCM_RTS)
1185                         msvr &= ~MSVR_RTS;
1186                 if (bits & TIOCM_DTR)
1187                         msvr &= ~MSVR_DTR;
1188                 rcout(CD180_MSVR, msvr);
1189                 break;
1190         }
1191         rc->rc_msvr = rcin(CD180_MSVR);
1192         return 0;
1193 }
1194
1195 /* Test the board. */
1196 int
1197 rc_test(int nec, int unit)
1198 {
1199         int     chan = 0;
1200         int     i = 0, rcnt;
1201         unsigned int    iack, chipid;
1202         unsigned short  divs;
1203         static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1204 #define CTLEN   8
1205 #define ERR(s)  { \
1206                 kprintf("rc%d: ", unit); kprintf s ; kprintf("\n"); \
1207                 crit_exit(); return 1; }
1208
1209         struct rtest {
1210                 u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1211                 u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1212                 int     rxptr;                  /* RX pointer */
1213                 int     txptr;                  /* TX pointer */
1214         } tchans[CD180_NCHAN];
1215
1216         crit_enter();
1217
1218         chipid = RC_FAKEID;
1219
1220         /* First, reset board to inital state */
1221         rc_hwreset(unit, nec, chipid);
1222
1223         divs = RC_BRD(19200);
1224
1225         /* Initialize channels */
1226         for (chan = 0; chan < CD180_NCHAN; chan++) {
1227
1228                 /* Select and reset channel */
1229                 rcout(CD180_CAR, chan);
1230                 CCRCMD(unit, chan, CCR_ResetChan);
1231                 WAITFORCCR(unit, chan);
1232
1233                 /* Set speed */
1234                 rcout(CD180_RBPRL, divs & 0xFF);
1235                 rcout(CD180_RBPRH, divs >> 8);
1236                 rcout(CD180_TBPRL, divs & 0xFF);
1237                 rcout(CD180_TBPRH, divs >> 8);
1238
1239                 /* set timeout value */
1240                 rcout(CD180_RTPR,  0);
1241
1242                 /* Establish local loopback */
1243                 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1244                 rcout(CD180_COR2, COR2_LLM);
1245                 rcout(CD180_COR3, CD180_NFIFO);
1246                 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1247                 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1248                 WAITFORCCR(unit, chan);
1249                 rcout(CD180_MSVR, MSVR_RTS);
1250
1251                 /* Fill TXBUF with test data */
1252                 for (i = 0; i < CD180_NFIFO; i++) {
1253                         tchans[chan].txbuf[i] = ctest[i];
1254                         tchans[chan].rxbuf[i] = 0;
1255                 }
1256                 tchans[chan].txptr = tchans[chan].rxptr = 0;
1257
1258                 /* Now, start transmit */
1259                 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1260         }
1261         /* Pseudo-interrupt poll stuff */
1262         for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1263                 i = ~(rcin(RC_BSR));
1264                 if (i & RC_BSR_TOUT)
1265                         ERR(("BSR timeout bit set\n"))
1266                 else if (i & RC_BSR_TXINT) {
1267                         iack = rcin(RC_PILR_TX);
1268                         if (iack != (GIVR_IT_TDI | chipid))
1269                                 ERR(("Bad TX intr ack (%02x != %02x)\n",
1270                                         iack, GIVR_IT_TDI | chipid));
1271                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1272                         /* If no more data to transmit, disable TX intr */
1273                         if (tchans[chan].txptr >= CD180_NFIFO) {
1274                                 iack = rcin(CD180_IER);
1275                                 rcout(CD180_IER, iack & ~IER_TxMpty);
1276                         } else {
1277                                 for (iack = tchans[chan].txptr;
1278                                     iack < CD180_NFIFO; iack++)
1279                                         rcout(CD180_TDR,
1280                                             tchans[chan].txbuf[iack]);
1281                                 tchans[chan].txptr = iack;
1282                         }
1283                         rcout(CD180_EOIR, 0);
1284                 } else if (i & RC_BSR_RXINT) {
1285                         u_char ucnt;
1286
1287                         iack = rcin(RC_PILR_RX);
1288                         if (iack != (GIVR_IT_RGDI | chipid) &&
1289                             iack != (GIVR_IT_REI  | chipid))
1290                                 ERR(("Bad RX intr ack (%02x != %02x)\n",
1291                                         iack, GIVR_IT_RGDI | chipid))
1292                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1293                         ucnt = rcin(CD180_RDCR) & 0xF;
1294                         while (ucnt-- > 0) {
1295                                 iack = rcin(CD180_RCSR);
1296                                 if (iack & RCSR_Timeout)
1297                                         break;
1298                                 if (iack & 0xF)
1299                                         ERR(("Bad char chan %d (RCSR = %02X)\n",
1300                                             chan, iack))
1301                                 if (tchans[chan].rxptr > CD180_NFIFO)
1302                                         ERR(("Got extra chars chan %d\n",
1303                                             chan))
1304                                 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1305                                         rcin(CD180_RDR);
1306                         }
1307                         rcout(CD180_EOIR, 0);
1308                 }
1309                 rcout(RC_CTOUT, 0);
1310                 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1311                         if (tchans[chan].rxptr >= CD180_NFIFO)
1312                                 iack++;
1313                 if (iack == CD180_NCHAN)
1314                         break;
1315         }
1316         for (chan = 0; chan < CD180_NCHAN; chan++) {
1317                 /* Select and reset channel */
1318                 rcout(CD180_CAR, chan);
1319                 CCRCMD(unit, chan, CCR_ResetChan);
1320         }
1321
1322         if (!rcnt)
1323                 ERR(("looses characters during local loopback\n"))
1324         /* Now, check data */
1325         for (chan = 0; chan < CD180_NCHAN; chan++)
1326                 for (i = 0; i < CD180_NFIFO; i++)
1327                         if (ctest[i] != tchans[chan].rxbuf[i])
1328                                 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1329                                     chan, i, ctest[i], tchans[chan].rxbuf[i]))
1330         crit_exit();
1331         return 0;
1332 }
1333
1334 #ifdef RCDEBUG
1335 static void
1336 printrcflags(struct rc_chans *rc, char *comment)
1337 {
1338         u_short f = rc->rc_flags;
1339         int    nec = rc->rc_rcb->rcb_addr;
1340
1341         kprintf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1342                 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1343                 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1344                 (f & RC_ACTOUT) ?"ACTOUT " :"",
1345                 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1346                 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1347                 (f & RC_DORXFER)?"DORXFER " :"",
1348                 (f & RC_DOXXFER)?"DOXXFER " :"",
1349                 (f & RC_MODCHG) ?"MODCHG "  :"",
1350                 (f & RC_OSUSP)  ?"OSUSP " :"",
1351                 (f & RC_OSBUSY) ?"OSBUSY " :"",
1352                 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1353                 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1354                 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1355
1356         rcout(CD180_CAR, rc->rc_chan);
1357
1358         kprintf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1359                 rc->rc_rcb->rcb_unit, rc->rc_chan,
1360                 rcin(CD180_MSVR),
1361                 rcin(CD180_IER),
1362                 rcin(CD180_CCSR));
1363 }
1364 #endif /* RCDEBUG */
1365
1366 static void
1367 rc_dtrwakeup(void *chan)
1368 {
1369         struct rc_chans  *rc;
1370
1371         rc = (struct rc_chans *)chan;
1372         rc->rc_flags &= ~RC_DTR_OFF;
1373         wakeup(&rc->rc_dtrwait);
1374 }
1375
1376 static void
1377 rc_discard_output(struct rc_chans *rc)
1378 {
1379         cpu_disable_intr();
1380         if (rc->rc_flags & RC_DOXXFER) {
1381                 rc_scheduled_event -= LOTS_OF_EVENTS;
1382                 rc->rc_flags &= ~RC_DOXXFER;
1383         }
1384         rc->rc_optr = rc->rc_obufend;
1385         rc->rc_tp->t_state &= ~TS_BUSY;
1386         cpu_enable_intr();
1387         ttwwakeup(rc->rc_tp);
1388 }
1389
1390 static void
1391 rc_wakeup(void *chan)
1392 {
1393         if (rc_scheduled_event != 0) {
1394                 crit_enter();
1395                 rcpoll(NULL, NULL);
1396                 crit_exit();
1397         }
1398         callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
1399 }
1400
1401 static void
1402 disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc)
1403 {
1404
1405         if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1406             && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1407             && (!(t->c_iflag & PARMRK)
1408                 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1409             && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1410             && linesw[tp->t_line].l_rint == ttyinput)
1411                 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1412         else
1413                 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1414         rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1415 }
1416
1417 static void
1418 rc_wait0(int nec, int unit, int chan, int line)
1419 {
1420         int rcnt;
1421
1422         for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1423                 DELAY(30);
1424         if (rcnt == 0)
1425                 kprintf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1426                       unit, chan, line);
1427 }