kernel: Add descriptions to the intrhooks that miss them.
[dragonfly.git] / sys / dev / sound / pci / hda / hdac.c
1 /*-
2  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3  * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.8 2007/11/30 15:11:42 ariff Exp $
28  */
29
30 /*
31  * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
32  * that this driver still in its early stage, and possible of rewrite are
33  * pretty much guaranteed. There are supposedly several distinct parent/child
34  * busses to make this "perfect", but as for now and for the sake of
35  * simplicity, everything is gobble up within single source.
36  *
37  * List of subsys:
38  *     1) HDA Controller support
39  *     2) HDA Codecs support, which may include
40  *        - HDA
41  *        - Modem
42  *        - HDMI
43  *     3) Widget parser - the real magic of why this driver works on so
44  *        many hardwares with minimal vendor specific quirk. The original
45  *        parser was written using Ruby and can be found at
46  *        http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
47  *        ruby parser take the verbose dmesg dump as its input. Refer to
48  *        http://www.microsoft.com/whdc/device/audio/default.mspx for various
49  *        interesting documents, especially UAA (Universal Audio Architecture).
50  *     4) Possible vendor specific support.
51  *        (snd_hda_intel, snd_hda_ati, etc..)
52  *
53  * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
54  * Compaq V3000 with Conexant HDA.
55  *
56  *    * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
57  *    *                                                                 *
58  *    *        This driver is a collaborative effort made by:           *
59  *    *                                                                 *
60  *    *          Stephane E. Potvin <sepotvin@videotron.ca>             *
61  *    *               Andrea Bittau <a.bittau@cs.ucl.ac.uk>             *
62  *    *               Wesley Morgan <morganw@chemikals.org>             *
63  *    *              Daniel Eischen <deischen@FreeBSD.org>              *
64  *    *             Maxime Guillaud <bsd-ports@mguillaud.net>           *
65  *    *              Ariff Abdullah <ariff@FreeBSD.org>                 *
66  *    *                                                                 *
67  *    *   ....and various people from freebsd-multimedia@FreeBSD.org    *
68  *    *                                                                 *
69  *    * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
70  */
71
72 #include <dev/sound/pcm/sound.h>
73 #include <bus/pci/pcireg.h>
74 #include <bus/pci/pcivar.h>
75
76 #include <sys/ctype.h>
77 #include <sys/taskqueue.h>
78
79 #include <dev/sound/pci/hda/hdac_private.h>
80 #include <dev/sound/pci/hda/hdac_reg.h>
81 #include <dev/sound/pci/hda/hda_reg.h>
82 #include <dev/sound/pci/hda/hdac.h>
83
84 #include "mixer_if.h"
85
86 #define HDA_DRV_TEST_REV        "20071129_0050"
87 #define HDA_WIDGET_PARSER_REV   1
88
89 static int hda_debug
90 #ifdef HDA_DEBUG
91         = 1
92 #endif
93         ;
94 #define HDA_BOOTVERBOSE(stmt)   do {                    \
95         if (hda_debug && bootverbose != 0) {            \
96                 stmt                                    \
97         }                                               \
98 } while(0)
99
100 #if 1
101 #undef HDAC_INTR_EXTRA
102 #define HDAC_INTR_EXTRA         1
103 #endif
104
105 #define hdac_lock(sc)           snd_mtxlock((sc)->lock)
106 #define hdac_unlock(sc)         snd_mtxunlock((sc)->lock)
107 #define hdac_lockassert(sc)     snd_mtxassert((sc)->lock)
108 #define hdac_lockowned(sc)      (1)/* mtx_owned((sc)->lock) */
109
110 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
111 #include <machine/specialreg.h>
112 #define HDAC_DMA_ATTR(sc, v, s, attr)   do {                            \
113         vm_offset_t va = (vm_offset_t)(v);                              \
114         vm_size_t sz = (vm_size_t)(s);                                  \
115         if ((sc) != NULL && ((sc)->flags & HDAC_F_DMA_NOCACHE) &&       \
116             va != 0 && sz != 0)                                         \
117                 (void)pmap_change_attr(va, sz, (attr));                 \
118 } while(0)
119 #else
120 #define HDAC_DMA_ATTR(...)
121 #endif
122
123 #define HDA_FLAG_MATCH(fl, v)   (((fl) & (v)) == (v))
124 #define HDA_DEV_MATCH(fl, v)    ((fl) == (v) || \
125                                 (fl) == 0xffffffff || \
126                                 (((fl) & 0xffff0000) == 0xffff0000 && \
127                                 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
128                                 (((fl) & 0x0000ffff) == 0x0000ffff && \
129                                 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
130 #define HDA_MATCH_ALL           0xffffffff
131 #define HDAC_INVALID            0xffffffff
132
133 /* Default controller / jack sense poll: 250ms */
134 #define HDAC_POLL_INTERVAL      max(hz >> 2, 1)
135
136 /*
137  * Make room for possible 4096 playback/record channels, in 100 years to come.
138  */
139 #define HDAC_TRIGGER_NONE       0x00000000
140 #define HDAC_TRIGGER_PLAY       0x00000fff
141 #define HDAC_TRIGGER_REC        0x00fff000
142 #define HDAC_TRIGGER_UNSOL      0x80000000
143
144 #define HDA_MODEL_CONSTRUCT(vendor, model)      \
145                 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
146
147 /* Controller models */
148
149 /* Intel */
150 #define INTEL_VENDORID          0x8086
151 #define HDA_INTEL_82801F        HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
152 #define HDA_INTEL_63XXESB       HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
153 #define HDA_INTEL_82801G        HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
154 #define HDA_INTEL_82801H        HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
155 #define HDA_INTEL_82801I        HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
156 #define HDA_INTEL_ALL           HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
157
158 /* Nvidia */
159 #define NVIDIA_VENDORID         0x10de
160 #define HDA_NVIDIA_MCP51        HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
161 #define HDA_NVIDIA_MCP55        HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
162 #define HDA_NVIDIA_MCP61_1      HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
163 #define HDA_NVIDIA_MCP61_2      HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
164 #define HDA_NVIDIA_MCP65_1      HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
165 #define HDA_NVIDIA_MCP65_2      HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
166 #define HDA_NVIDIA_MCP67_1      HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)
167 #define HDA_NVIDIA_MCP67_2      HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)
168 #define HDA_NVIDIA_ALL          HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
169
170 /* ATI */
171 #define ATI_VENDORID            0x1002
172 #define HDA_ATI_SB450           HDA_MODEL_CONSTRUCT(ATI, 0x437b)
173 #define HDA_ATI_SB600           HDA_MODEL_CONSTRUCT(ATI, 0x4383)
174 #define HDA_ATI_ALL             HDA_MODEL_CONSTRUCT(ATI, 0xffff)
175
176 /* VIA */
177 #define VIA_VENDORID            0x1106
178 #define HDA_VIA_VT82XX          HDA_MODEL_CONSTRUCT(VIA, 0x3288)
179 #define HDA_VIA_ALL             HDA_MODEL_CONSTRUCT(VIA, 0xffff)
180
181 /* SiS */
182 #define SIS_VENDORID            0x1039
183 #define HDA_SIS_966             HDA_MODEL_CONSTRUCT(SIS, 0x7502)
184 #define HDA_SIS_ALL             HDA_MODEL_CONSTRUCT(SIS, 0xffff)
185
186 /* OEM/subvendors */
187
188 /* Intel */
189 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
190
191 /* HP/Compaq */
192 #define HP_VENDORID             0x103c
193 #define HP_V3000_SUBVENDOR      HDA_MODEL_CONSTRUCT(HP, 0x30b5)
194 #define HP_NX7400_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x30a2)
195 #define HP_NX6310_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x30aa)
196 #define HP_NX6325_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x30b0)
197 #define HP_XW4300_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x3013)
198 #define HP_3010_SUBVENDOR       HDA_MODEL_CONSTRUCT(HP, 0x3010)
199 #define HP_DV5000_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x30a5)
200 #define HP_DC7700_SUBVENDOR     HDA_MODEL_CONSTRUCT(HP, 0x2802)
201 #define HP_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(HP, 0xffff)
202 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
203 #define HP_NX6325_SUBVENDORX    0x103c30b0
204
205 /* Dell */
206 #define DELL_VENDORID           0x1028
207 #define DELL_D820_SUBVENDOR     HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
208 #define DELL_I1300_SUBVENDOR    HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
209 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
210 #define DELL_OPLX745_SUBVENDOR  HDA_MODEL_CONSTRUCT(DELL, 0x01da)
211 #define DELL_ALL_SUBVENDOR      HDA_MODEL_CONSTRUCT(DELL, 0xffff)
212
213 /* Clevo */
214 #define CLEVO_VENDORID          0x1558
215 #define CLEVO_D900T_SUBVENDOR   HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
216 #define CLEVO_ALL_SUBVENDOR     HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
217
218 /* Acer */
219 #define ACER_VENDORID           0x1025
220 #define ACER_A5050_SUBVENDOR    HDA_MODEL_CONSTRUCT(ACER, 0x010f)
221 #define ACER_A4520_SUBVENDOR    HDA_MODEL_CONSTRUCT(ACER, 0x0127)
222 #define ACER_3681WXM_SUBVENDOR  HDA_MODEL_CONSTRUCT(ACER, 0x0110)
223 #define ACER_ALL_SUBVENDOR      HDA_MODEL_CONSTRUCT(ACER, 0xffff)
224
225 /* Asus */
226 #define ASUS_VENDORID           0x1043
227 #define ASUS_M5200_SUBVENDOR    HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
228 #define ASUS_U5F_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
229 #define ASUS_A8JC_SUBVENDOR     HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
230 #define ASUS_P1AH2_SUBVENDOR    HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
231 #define ASUS_A7M_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
232 #define ASUS_A7T_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
233 #define ASUS_W6F_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
234 #define ASUS_W2J_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
235 #define ASUS_F3JC_SUBVENDOR     HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
236 #define ASUS_M2V_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
237 #define ASUS_M2N_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
238 #define ASUS_M2NPVMX_SUBVENDOR  HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
239 #define ASUS_P5BWD_SUBVENDOR    HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
240 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
241 #define ASUS_ALL_SUBVENDOR      HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
242
243 /* IBM / Lenovo */
244 #define IBM_VENDORID            0x1014
245 #define IBM_M52_SUBVENDOR       HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
246 #define IBM_ALL_SUBVENDOR       HDA_MODEL_CONSTRUCT(IBM, 0xffff)
247
248 /* Lenovo */
249 #define LENOVO_VENDORID         0x17aa
250 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
251 #define LENOVO_TCA55_SUBVENDOR  HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)
252 #define LENOVO_ALL_SUBVENDOR    HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
253
254 /* Samsung */
255 #define SAMSUNG_VENDORID        0x144d
256 #define SAMSUNG_Q1_SUBVENDOR    HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
257 #define SAMSUNG_ALL_SUBVENDOR   HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
258
259 /* Medion ? */
260 #define MEDION_VENDORID                 0x161f
261 #define MEDION_MD95257_SUBVENDOR        HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
262 #define MEDION_ALL_SUBVENDOR            HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
263
264 /* Apple Computer Inc. */
265 #define APPLE_VENDORID          0x106b
266 #define APPLE_MB3_SUBVENDOR     HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)
267
268 /*
269  * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
270  * instead of their own, which is beyond my comprehension
271  * (see HDA_CODEC_STAC9221 below).
272  */
273 #define APPLE_INTEL_MAC         0x76808384
274
275 /* LG Electronics */
276 #define LG_VENDORID             0x1854
277 #define LG_LW20_SUBVENDOR       HDA_MODEL_CONSTRUCT(LG, 0x0018)
278 #define LG_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(LG, 0xffff)
279
280 /* Fujitsu Siemens */
281 #define FS_VENDORID             0x1734
282 #define FS_PA1510_SUBVENDOR     HDA_MODEL_CONSTRUCT(FS, 0x10b8)
283 #define FS_SI1848_SUBVENDOR     HDA_MODEL_CONSTRUCT(FS, 0x10cd)
284 #define FS_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(FS, 0xffff)
285
286 /* Fujitsu Limited */
287 #define FL_VENDORID             0x10cf
288 #define FL_S7020D_SUBVENDOR     HDA_MODEL_CONSTRUCT(FL, 0x1326)
289 #define FL_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(FL, 0xffff)
290
291 /* Toshiba */
292 #define TOSHIBA_VENDORID        0x1179
293 #define TOSHIBA_U200_SUBVENDOR  HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
294 #define TOSHIBA_A135_SUBVENDOR  HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)
295 #define TOSHIBA_ALL_SUBVENDOR   HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
296
297 /* Micro-Star International (MSI) */
298 #define MSI_VENDORID            0x1462
299 #define MSI_MS1034_SUBVENDOR    HDA_MODEL_CONSTRUCT(MSI, 0x0349)
300 #define MSI_MS034A_SUBVENDOR    HDA_MODEL_CONSTRUCT(MSI, 0x034a)
301 #define MSI_ALL_SUBVENDOR       HDA_MODEL_CONSTRUCT(MSI, 0xffff)
302
303 /* Giga-Byte Technology */
304 #define GB_VENDORID             0x1458
305 #define GB_G33S2H_SUBVENDOR     HDA_MODEL_CONSTRUCT(GB, 0xa022)
306 #define GP_ALL_SUBVENDOR        HDA_MODEL_CONSTRUCT(GB, 0xffff)
307
308 /* Uniwill ? */
309 #define UNIWILL_VENDORID        0x1584
310 #define UNIWILL_9075_SUBVENDOR  HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
311 #define UNIWILL_9080_SUBVENDOR  HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
312
313
314 /* Misc constants.. */
315 #define HDA_AMP_MUTE_DEFAULT    (0xffffffff)
316 #define HDA_AMP_MUTE_NONE       (0)
317 #define HDA_AMP_MUTE_LEFT       (1 << 0)
318 #define HDA_AMP_MUTE_RIGHT      (1 << 1)
319 #define HDA_AMP_MUTE_ALL        (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
320
321 #define HDA_AMP_LEFT_MUTED(v)   ((v) & (HDA_AMP_MUTE_LEFT))
322 #define HDA_AMP_RIGHT_MUTED(v)  (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
323
324 #define HDA_DAC_PATH    (1 << 0)
325 #define HDA_ADC_PATH    (1 << 1)
326 #define HDA_ADC_RECSEL  (1 << 2)
327
328 #define HDA_DAC_LOCKED  (1 << 3)
329 #define HDA_ADC_LOCKED  (1 << 4)
330
331 #define HDA_CTL_OUT     (1 << 0)
332 #define HDA_CTL_IN      (1 << 1)
333 #define HDA_CTL_BOTH    (HDA_CTL_IN | HDA_CTL_OUT)
334
335 #define HDA_GPIO_MAX            8
336 /* 0 - 7 = GPIO , 8 = Flush */
337 #define HDA_QUIRK_GPIO0         (1 << 0)
338 #define HDA_QUIRK_GPIO1         (1 << 1)
339 #define HDA_QUIRK_GPIO2         (1 << 2)
340 #define HDA_QUIRK_GPIO3         (1 << 3)
341 #define HDA_QUIRK_GPIO4         (1 << 4)
342 #define HDA_QUIRK_GPIO5         (1 << 5)
343 #define HDA_QUIRK_GPIO6         (1 << 6)
344 #define HDA_QUIRK_GPIO7         (1 << 7)
345 #define HDA_QUIRK_GPIOFLUSH     (1 << 8)
346
347 /* 9 - 25 = anything else */
348 #define HDA_QUIRK_SOFTPCMVOL    (1 << 9)
349 #define HDA_QUIRK_FIXEDRATE     (1 << 10)
350 #define HDA_QUIRK_FORCESTEREO   (1 << 11)
351 #define HDA_QUIRK_EAPDINV       (1 << 12)
352 #define HDA_QUIRK_DMAPOS        (1 << 13)
353
354 /* 26 - 31 = vrefs */
355 #define HDA_QUIRK_IVREF50       (1 << 26)
356 #define HDA_QUIRK_IVREF80       (1 << 27)
357 #define HDA_QUIRK_IVREF100      (1 << 28)
358 #define HDA_QUIRK_OVREF50       (1 << 29)
359 #define HDA_QUIRK_OVREF80       (1 << 30)
360 #define HDA_QUIRK_OVREF100      (1 << 31)
361
362 #define HDA_QUIRK_IVREF         (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
363                                                         HDA_QUIRK_IVREF100)
364 #define HDA_QUIRK_OVREF         (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
365                                                         HDA_QUIRK_OVREF100)
366 #define HDA_QUIRK_VREF          (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
367
368 #define SOUND_MASK_SKIP         (1 << 30)
369 #define SOUND_MASK_DISABLE      (1 << 31)
370
371 static const struct {
372         char *key;
373         uint32_t value;
374 } hdac_quirks_tab[] = {
375         { "gpio0", HDA_QUIRK_GPIO0 },
376         { "gpio1", HDA_QUIRK_GPIO1 },
377         { "gpio2", HDA_QUIRK_GPIO2 },
378         { "gpio3", HDA_QUIRK_GPIO3 },
379         { "gpio4", HDA_QUIRK_GPIO4 },
380         { "gpio5", HDA_QUIRK_GPIO5 },
381         { "gpio6", HDA_QUIRK_GPIO6 },
382         { "gpio7", HDA_QUIRK_GPIO7 },
383         { "gpioflush", HDA_QUIRK_GPIOFLUSH },
384         { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
385         { "fixedrate", HDA_QUIRK_FIXEDRATE },
386         { "forcestereo", HDA_QUIRK_FORCESTEREO },
387         { "eapdinv", HDA_QUIRK_EAPDINV },
388         { "dmapos", HDA_QUIRK_DMAPOS },
389         { "ivref50", HDA_QUIRK_IVREF50 },
390         { "ivref80", HDA_QUIRK_IVREF80 },
391         { "ivref100", HDA_QUIRK_IVREF100 },
392         { "ovref50", HDA_QUIRK_OVREF50 },
393         { "ovref80", HDA_QUIRK_OVREF80 },
394         { "ovref100", HDA_QUIRK_OVREF100 },
395         { "ivref", HDA_QUIRK_IVREF },
396         { "ovref", HDA_QUIRK_OVREF },
397         { "vref", HDA_QUIRK_VREF },
398 };
399 #define HDAC_QUIRKS_TAB_LEN NELEM(hdac_quirks_tab)
400
401 #define HDA_BDL_MIN     2
402 #define HDA_BDL_MAX     256
403 #define HDA_BDL_DEFAULT HDA_BDL_MIN
404
405 #define HDA_BLK_MIN     HDAC_DMA_ALIGNMENT
406 #define HDA_BLK_ALIGN   (~(HDA_BLK_MIN - 1))
407
408 #define HDA_BUFSZ_MIN           4096
409 #define HDA_BUFSZ_MAX           65536
410 #define HDA_BUFSZ_DEFAULT       16384
411
412 #define HDA_PARSE_MAXDEPTH      10
413
414 #define HDAC_UNSOLTAG_EVENT_HP          0x00
415 #define HDAC_UNSOLTAG_EVENT_TEST        0x01
416
417 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
418
419 static int hdac_msi_enable = 1;
420 TUNABLE_INT("hw.snd.hdac.msi.enable", &hdac_msi_enable);
421
422 enum {
423         HDA_PARSE_MIXER,
424         HDA_PARSE_DIRECT
425 };
426
427 /* Default */
428 static uint32_t hdac_fmt[] = {
429         AFMT_STEREO | AFMT_S16_LE,
430         0
431 };
432
433 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
434
435 static const struct {
436         uint32_t        model;
437         char            *desc;
438 } hdac_devices[] = {
439         { HDA_INTEL_82801F,  "Intel 82801F" },
440         { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
441         { HDA_INTEL_82801G,  "Intel 82801G" },
442         { HDA_INTEL_82801H,  "Intel 82801H" },
443         { HDA_INTEL_82801I,  "Intel 82801I" },
444         { HDA_NVIDIA_MCP51,  "NVidia MCP51" },
445         { HDA_NVIDIA_MCP55,  "NVidia MCP55" },
446         { HDA_NVIDIA_MCP61_1, "NVidia MCP61" },
447         { HDA_NVIDIA_MCP61_2, "NVidia MCP61" },
448         { HDA_NVIDIA_MCP65_1, "NVidia MCP65" },
449         { HDA_NVIDIA_MCP65_2, "NVidia MCP65" },
450         { HDA_NVIDIA_MCP67_1, "NVidia MCP67" },
451         { HDA_NVIDIA_MCP67_2, "NVidia MCP67" },
452         { HDA_ATI_SB450,     "ATI SB450"    },
453         { HDA_ATI_SB600,     "ATI SB600"    },
454         { HDA_VIA_VT82XX,    "VIA VT8251/8237A" },
455         { HDA_SIS_966,       "SiS 966" },
456         /* Unknown */
457         { HDA_INTEL_ALL,  "Intel (Unknown)"  },
458         { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
459         { HDA_ATI_ALL,    "ATI (Unknown)"    },
460         { HDA_VIA_ALL,    "VIA (Unknown)"    },
461         { HDA_SIS_ALL,    "SiS (Unknown)"    },
462 };
463 #define HDAC_DEVICES_LEN NELEM(hdac_devices)
464
465 static const struct {
466         uint16_t vendor;
467         uint8_t reg;
468         uint8_t mask;
469         uint8_t enable;
470 } hdac_pcie_snoop[] = {
471         {  INTEL_VENDORID, 0x00, 0x00, 0x00 },
472         {    ATI_VENDORID, 0x42, 0xf8, 0x02 },
473         { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
474 };
475 #define HDAC_PCIESNOOP_LEN NELEM(hdac_pcie_snoop)
476
477 static const struct {
478         uint32_t        rate;
479         int             valid;
480         uint16_t        base;
481         uint16_t        mul;
482         uint16_t        div;
483 } hda_rate_tab[] = {
484         {   8000, 1, 0x0000, 0x0000, 0x0500 },  /* (48000 * 1) / 6 */
485         {   9600, 0, 0x0000, 0x0000, 0x0400 },  /* (48000 * 1) / 5 */
486         {  12000, 0, 0x0000, 0x0000, 0x0300 },  /* (48000 * 1) / 4 */
487         {  16000, 1, 0x0000, 0x0000, 0x0200 },  /* (48000 * 1) / 3 */
488         {  18000, 0, 0x0000, 0x1000, 0x0700 },  /* (48000 * 3) / 8 */
489         {  19200, 0, 0x0000, 0x0800, 0x0400 },  /* (48000 * 2) / 5 */
490         {  24000, 0, 0x0000, 0x0000, 0x0100 },  /* (48000 * 1) / 2 */
491         {  28800, 0, 0x0000, 0x1000, 0x0400 },  /* (48000 * 3) / 5 */
492         {  32000, 1, 0x0000, 0x0800, 0x0200 },  /* (48000 * 2) / 3 */
493         {  36000, 0, 0x0000, 0x1000, 0x0300 },  /* (48000 * 3) / 4 */
494         {  38400, 0, 0x0000, 0x1800, 0x0400 },  /* (48000 * 4) / 5 */
495         {  48000, 1, 0x0000, 0x0000, 0x0000 },  /* (48000 * 1) / 1 */
496         {  64000, 0, 0x0000, 0x1800, 0x0200 },  /* (48000 * 4) / 3 */
497         {  72000, 0, 0x0000, 0x1000, 0x0100 },  /* (48000 * 3) / 2 */
498         {  96000, 1, 0x0000, 0x0800, 0x0000 },  /* (48000 * 2) / 1 */
499         { 144000, 0, 0x0000, 0x1000, 0x0000 },  /* (48000 * 3) / 1 */
500         { 192000, 1, 0x0000, 0x1800, 0x0000 },  /* (48000 * 4) / 1 */
501         {   8820, 0, 0x4000, 0x0000, 0x0400 },  /* (44100 * 1) / 5 */
502         {  11025, 1, 0x4000, 0x0000, 0x0300 },  /* (44100 * 1) / 4 */
503         {  12600, 0, 0x4000, 0x0800, 0x0600 },  /* (44100 * 2) / 7 */
504         {  14700, 0, 0x4000, 0x0000, 0x0200 },  /* (44100 * 1) / 3 */
505         {  17640, 0, 0x4000, 0x0800, 0x0400 },  /* (44100 * 2) / 5 */
506         {  18900, 0, 0x4000, 0x1000, 0x0600 },  /* (44100 * 3) / 7 */
507         {  22050, 1, 0x4000, 0x0000, 0x0100 },  /* (44100 * 1) / 2 */
508         {  25200, 0, 0x4000, 0x1800, 0x0600 },  /* (44100 * 4) / 7 */
509         {  26460, 0, 0x4000, 0x1000, 0x0400 },  /* (44100 * 3) / 5 */
510         {  29400, 0, 0x4000, 0x0800, 0x0200 },  /* (44100 * 2) / 3 */
511         {  33075, 0, 0x4000, 0x1000, 0x0300 },  /* (44100 * 3) / 4 */
512         {  35280, 0, 0x4000, 0x1800, 0x0400 },  /* (44100 * 4) / 5 */
513         {  44100, 1, 0x4000, 0x0000, 0x0000 },  /* (44100 * 1) / 1 */
514         {  58800, 0, 0x4000, 0x1800, 0x0200 },  /* (44100 * 4) / 3 */
515         {  66150, 0, 0x4000, 0x1000, 0x0100 },  /* (44100 * 3) / 2 */
516         {  88200, 1, 0x4000, 0x0800, 0x0000 },  /* (44100 * 2) / 1 */
517         { 132300, 0, 0x4000, 0x1000, 0x0000 },  /* (44100 * 3) / 1 */
518         { 176400, 1, 0x4000, 0x1800, 0x0000 },  /* (44100 * 4) / 1 */
519 };
520 #define HDA_RATE_TAB_LEN NELEM(hda_rate_tab)
521
522 /* All codecs you can eat... */
523 #define HDA_CODEC_CONSTRUCT(vendor, id) \
524                 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
525
526 /* Realtek */
527 #define REALTEK_VENDORID        0x10ec
528 #define HDA_CODEC_ALC260        HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
529 #define HDA_CODEC_ALC262        HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
530 #define HDA_CODEC_ALC268        HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
531 #define HDA_CODEC_ALC660        HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
532 #define HDA_CODEC_ALC861        HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
533 #define HDA_CODEC_ALC861VD      HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
534 #define HDA_CODEC_ALC880        HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
535 #define HDA_CODEC_ALC882        HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
536 #define HDA_CODEC_ALC883        HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
537 #define HDA_CODEC_ALC885        HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
538 #define HDA_CODEC_ALC888        HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
539 #define HDA_CODEC_ALCXXXX       HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
540
541 /* Analog Devices */
542 #define ANALOGDEVICES_VENDORID  0x11d4
543 #define HDA_CODEC_AD1981HD      HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
544 #define HDA_CODEC_AD1983        HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
545 #define HDA_CODEC_AD1984        HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984)
546 #define HDA_CODEC_AD1986A       HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
547 #define HDA_CODEC_AD1988        HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
548 #define HDA_CODEC_AD1988B       HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
549 #define HDA_CODEC_ADXXXX        HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
550
551 /* CMedia */
552 #define CMEDIA_VENDORID         0x434d
553 #define HDA_CODEC_CMI9880       HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
554 #define HDA_CODEC_CMIXXXX       HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
555
556 /* Sigmatel */
557 #define SIGMATEL_VENDORID       0x8384
558 #define HDA_CODEC_STAC9221      HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
559 #define HDA_CODEC_STAC9221D     HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
560 #define HDA_CODEC_STAC9220      HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
561 #define HDA_CODEC_STAC922XD     HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
562 #define HDA_CODEC_STAC9227      HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
563 #define HDA_CODEC_STAC9271D     HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
564 #define HDA_CODEC_STACXXXX      HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
565
566 /*
567  * Conexant
568  *
569  * Ok, the truth is, I don't have any idea at all whether
570  * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
571  * place that tell me it is "Venice" is from its Windows driver INF.
572  *
573  *  Venice - CX?????
574  * Waikiki - CX20551-22
575  */
576 #define CONEXANT_VENDORID       0x14f1
577 #define HDA_CODEC_CXVENICE      HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
578 #define HDA_CODEC_CXWAIKIKI     HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
579 #define HDA_CODEC_CXXXXX        HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
580
581 /* VIA */
582 #define HDA_CODEC_VT1708_8      HDA_CODEC_CONSTRUCT(VIA, 0x1708)
583 #define HDA_CODEC_VT1708_9      HDA_CODEC_CONSTRUCT(VIA, 0x1709)
584 #define HDA_CODEC_VT1708_A      HDA_CODEC_CONSTRUCT(VIA, 0x170a)
585 #define HDA_CODEC_VT1708_B      HDA_CODEC_CONSTRUCT(VIA, 0x170b)
586 #define HDA_CODEC_VT1709_0      HDA_CODEC_CONSTRUCT(VIA, 0xe710)
587 #define HDA_CODEC_VT1709_1      HDA_CODEC_CONSTRUCT(VIA, 0xe711)
588 #define HDA_CODEC_VT1709_2      HDA_CODEC_CONSTRUCT(VIA, 0xe712)
589 #define HDA_CODEC_VT1709_3      HDA_CODEC_CONSTRUCT(VIA, 0xe713)
590 #define HDA_CODEC_VT1709_4      HDA_CODEC_CONSTRUCT(VIA, 0xe714)
591 #define HDA_CODEC_VT1709_5      HDA_CODEC_CONSTRUCT(VIA, 0xe715)
592 #define HDA_CODEC_VT1709_6      HDA_CODEC_CONSTRUCT(VIA, 0xe716)
593 #define HDA_CODEC_VT1709_7      HDA_CODEC_CONSTRUCT(VIA, 0xe717)
594 #define HDA_CODEC_VTXXXX        HDA_CODEC_CONSTRUCT(VIA, 0xffff)
595
596
597 /* Codecs */
598 static const struct {
599         uint32_t id;
600         char *name;
601 } hdac_codecs[] = {
602         { HDA_CODEC_ALC260,    "Realtek ALC260" },
603         { HDA_CODEC_ALC262,    "Realtek ALC262" },
604         { HDA_CODEC_ALC268,    "Realtek ALC268" },
605         { HDA_CODEC_ALC660,    "Realtek ALC660" },
606         { HDA_CODEC_ALC861,    "Realtek ALC861" },
607         { HDA_CODEC_ALC861VD,  "Realtek ALC861-VD" },
608         { HDA_CODEC_ALC880,    "Realtek ALC880" },
609         { HDA_CODEC_ALC882,    "Realtek ALC882" },
610         { HDA_CODEC_ALC883,    "Realtek ALC883" },
611         { HDA_CODEC_ALC885,    "Realtek ALC885" },
612         { HDA_CODEC_ALC888,    "Realtek ALC888" },
613         { HDA_CODEC_AD1981HD,  "Analog Devices AD1981HD" },
614         { HDA_CODEC_AD1983,    "Analog Devices AD1983" },
615         { HDA_CODEC_AD1984,    "Analog Devices AD1984" },
616         { HDA_CODEC_AD1986A,   "Analog Devices AD1986A" },
617         { HDA_CODEC_AD1988,    "Analog Devices AD1988" },
618         { HDA_CODEC_AD1988B,   "Analog Devices AD1988B" },
619         { HDA_CODEC_CMI9880,   "CMedia CMI9880" },
620         { HDA_CODEC_STAC9221,  "Sigmatel STAC9221" },
621         { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
622         { HDA_CODEC_STAC9220,  "Sigmatel STAC9220" },
623         { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
624         { HDA_CODEC_STAC9227,  "Sigmatel STAC9227" },
625         { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
626         { HDA_CODEC_CXVENICE,  "Conexant Venice" },
627         { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
628         { HDA_CODEC_VT1708_8,  "VIA VT1708_8" },
629         { HDA_CODEC_VT1708_9,  "VIA VT1708_9" },
630         { HDA_CODEC_VT1708_A,  "VIA VT1708_A" },
631         { HDA_CODEC_VT1708_B,  "VIA VT1708_B" },
632         { HDA_CODEC_VT1709_0,  "VIA VT1709_0" },
633         { HDA_CODEC_VT1709_1,  "VIA VT1709_1" },
634         { HDA_CODEC_VT1709_2,  "VIA VT1709_2" },
635         { HDA_CODEC_VT1709_3,  "VIA VT1709_3" },
636         { HDA_CODEC_VT1709_4,  "VIA VT1709_4" },
637         { HDA_CODEC_VT1709_5,  "VIA VT1709_5" },
638         { HDA_CODEC_VT1709_6,  "VIA VT1709_6" },
639         { HDA_CODEC_VT1709_7,  "VIA VT1709_7" },
640         /* Unknown codec */
641         { HDA_CODEC_ALCXXXX,   "Realtek (Unknown)" },
642         { HDA_CODEC_ADXXXX,    "Analog Devices (Unknown)" },
643         { HDA_CODEC_CMIXXXX,   "CMedia (Unknown)" },
644         { HDA_CODEC_STACXXXX,  "Sigmatel (Unknown)" },
645         { HDA_CODEC_CXXXXX,    "Conexant (Unknown)" },
646         { HDA_CODEC_VTXXXX,    "VIA (Unknown)" },
647 };
648 #define HDAC_CODECS_LEN NELEM(hdac_codecs)
649
650 enum {
651         HDAC_HP_SWITCH_CTL,
652         HDAC_HP_SWITCH_CTRL,
653         HDAC_HP_SWITCH_DEBUG
654 };
655
656 static const struct {
657         uint32_t model;
658         uint32_t id;
659         int type;
660         int inverted;
661         int polling;
662         int execsense;
663         nid_t hpnid;
664         nid_t spkrnid[8];
665         nid_t eapdnid;
666 } hdac_hp_switch[] = {
667         /* Specific OEM models */
668         { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
669             0, 0, -1, 17, { 16, -1 }, 16 },
670         /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
671             0, 0, -1, 21, { 16, 17, -1 }, -1 } */
672         /* { HP_3010_SUBVENDOR,  HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
673             0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */
674         { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
675             0, 0, -1, 6, { 5, -1 }, 5 },
676         { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
677             0, 0, -1, 6, { 5, -1 }, 5 },
678         { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
679             0, 0, -1, 6, { 5, -1 }, 5 },
680         /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL,
681             0, 0, -1, 21, { 22, 27, -1 }, -1 }, */
682         { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
683             0, 0, -1, 6, { 5, -1 }, -1 },
684         { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL,
685             0, 0, -1, 27, { 20, -1 }, -1 },
686         { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
687             0, 0, -1, 13, { 14, -1 }, -1 },
688         { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
689             0, 0, -1, 13, { 14, -1 }, -1 },
690         { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
691             0, 0, -1, 6, { 5, 7, -1 }, -1 },
692         { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL,
693             0, 0, -1, 21, { 20, 22, -1 }, -1 },
694         { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
695             0, 0, -1, 10, { 13, -1 }, -1 },
696         { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
697             1, 0, -1, 26, { 27, -1 }, -1 },
698         /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
699             0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */
700         { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
701             0, 0, -1, 27, { 20, -1 }, -1 },
702         { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
703             0, 0, -1, 20, { 21, -1 }, -1 },
704         { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
705             0, 0, -1, 20, { 21, -1 }, -1 },
706         { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL,
707             0, 0, -1, 20, { 21, -1 }, -1 },
708         { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
709             0, 0, -1, 20, { 21, -1 }, -1 },
710         { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
711             0, 0, -1, 20, { 27, -1 }, -1 },
712         { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
713             0, 0, -1, 20, { 27, -1 }, -1 },
714         { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
715             0, 0, -1, 20, { 21, -1 }, -1 },
716         { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
717             0, 0, -1, 20, { 16, -1 }, -1 },
718         /*
719          * All models that at least come from the same vendor with
720          * simmilar codec.
721          */
722         { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
723             0, 0, -1, 17, { 16, -1 }, 16 },
724         { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
725             0, 0, -1, 6, { 5, -1 }, 5 },
726         { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
727             0, 0, -1, 6, { 5, -1 }, -1 },
728         { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
729             0, 0, -1, 13, { 14, -1 }, -1 },
730 #if 0
731         { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
732             1, 0, -1, 26, { 27, -1 }, -1 },
733         { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
734             0, 0, -1, 20, { 21, -1 }, -1 },
735 #endif
736 };
737 #define HDAC_HP_SWITCH_LEN NELEM(hdac_hp_switch)
738
739 static const struct {
740         uint32_t model;
741         uint32_t id;
742         nid_t eapdnid;
743         int hp_switch;
744 } hdac_eapd_switch[] = {
745         { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
746         { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
747         { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
748 };
749 #define HDAC_EAPD_SWITCH_LEN NELEM(hdac_eapd_switch)
750
751 /****************************************************************************
752  * Function prototypes
753  ****************************************************************************/
754 static void     hdac_intr_handler(void *);
755 static int      hdac_reset(struct hdac_softc *);
756 static int      hdac_get_capabilities(struct hdac_softc *);
757 static void     hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
758 static int      hdac_dma_alloc(struct hdac_softc *,
759                                         struct hdac_dma *, bus_size_t);
760 static void     hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
761 static int      hdac_mem_alloc(struct hdac_softc *);
762 static void     hdac_mem_free(struct hdac_softc *);
763 static int      hdac_irq_alloc(struct hdac_softc *);
764 static void     hdac_irq_free(struct hdac_softc *);
765 static void     hdac_corb_init(struct hdac_softc *);
766 static void     hdac_rirb_init(struct hdac_softc *);
767 static void     hdac_corb_start(struct hdac_softc *);
768 static void     hdac_rirb_start(struct hdac_softc *);
769 static void     hdac_scan_codecs(struct hdac_softc *, int);
770 static int      hdac_probe_codec(struct hdac_codec *);
771 static struct   hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
772 static void     hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
773
774 static void     hdac_attach2(void *);
775
776 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
777                                                         uint32_t, int);
778 static void     hdac_command_send_internal(struct hdac_softc *,
779                                         struct hdac_command_list *, int);
780
781 static int      hdac_probe(device_t);
782 static int      hdac_attach(device_t);
783 static int      hdac_detach(device_t);
784 static void     hdac_widget_connection_select(struct hdac_widget *, uint8_t);
785 static void     hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
786                                                 uint32_t, int, int);
787 static struct   hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
788                                                         nid_t, int, int);
789 static void     hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
790                                 nid_t, nid_t, int, int, int, int, int, int);
791 static int      hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
792 static struct   hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
793
794 static int      hdac_rirb_flush(struct hdac_softc *sc);
795 static int      hdac_unsolq_flush(struct hdac_softc *sc);
796
797 #define hdac_command(a1, a2, a3)        \
798                 hdac_command_sendone_internal(a1, a2, a3)
799
800 #define hdac_codec_id(d)                                                \
801                 ((uint32_t)((d == NULL) ? 0x00000000 :                  \
802                 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) |      \
803                 ((uint32_t)(d)->device_id & 0x0000ffff))))
804
805 static char *
806 hdac_codec_name(struct hdac_devinfo *devinfo)
807 {
808         uint32_t id;
809         int i;
810
811         id = hdac_codec_id(devinfo);
812
813         for (i = 0; i < HDAC_CODECS_LEN; i++) {
814                 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
815                         return (hdac_codecs[i].name);
816         }
817
818         return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
819 }
820
821 static char *
822 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
823 {
824         static char *ossname[] = SOUND_DEVICE_NAMES;
825         static char *unknown = "???";
826         int i;
827
828         for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
829                 if (devmask & (1 << i))
830                         return (ossname[i]);
831         }
832         return (unknown);
833 }
834
835 static void
836 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
837 {
838         static char *ossname[] = SOUND_DEVICE_NAMES;
839         int i, first = 1;
840
841         bzero(buf, len);
842         for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
843                 if (mask & (1 << i)) {
844                         if (first == 0)
845                                 strlcat(buf, ", ", len);
846                         strlcat(buf, ossname[i], len);
847                         first = 0;
848                 }
849         }
850 }
851
852 static struct hdac_audio_ctl *
853 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
854 {
855         if (devinfo == NULL ||
856             devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
857             index == NULL || devinfo->function.audio.ctl == NULL ||
858             devinfo->function.audio.ctlcnt < 1 ||
859             *index < 0 || *index >= devinfo->function.audio.ctlcnt)
860                 return (NULL);
861         return (&devinfo->function.audio.ctl[(*index)++]);
862 }
863
864 static struct hdac_audio_ctl *
865 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
866                                                 int index, int cnt)
867 {
868         struct hdac_audio_ctl *ctl, *retctl = NULL;
869         int i, at, atindex, found = 0;
870
871         if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
872                 return (NULL);
873
874         at = cnt;
875         if (at == 0)
876                 at = 1;
877         else if (at < 0)
878                 at = -1;
879         atindex = index;
880         if (atindex < 0)
881                 atindex = -1;
882
883         i = 0;
884         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
885                 if (ctl->enable == 0 || ctl->widget == NULL)
886                         continue;
887                 if (!(ctl->widget->nid == nid && (atindex == -1 ||
888                     ctl->index == atindex)))
889                         continue;
890                 found++;
891                 if (found == cnt)
892                         return (ctl);
893                 retctl = ctl;
894         }
895
896         return ((at == -1) ? retctl : NULL);
897 }
898
899 static void
900 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
901 {
902         struct hdac_softc *sc;
903         struct hdac_widget *w;
904         struct hdac_audio_ctl *ctl;
905         uint32_t val, id, res;
906         int i = 0, j, timeout, forcemute;
907         nid_t cad;
908
909         if (devinfo == NULL || devinfo->codec == NULL ||
910             devinfo->codec->sc == NULL)
911                 return;
912
913         sc = devinfo->codec->sc;
914         cad = devinfo->codec->cad;
915         id = hdac_codec_id(devinfo);
916         for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
917                 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
918                     sc->pci_subvendor) &&
919                     hdac_hp_switch[i].id == id)
920                         break;
921         }
922
923         if (i >= HDAC_HP_SWITCH_LEN)
924                 return;
925
926         forcemute = 0;
927         if (hdac_hp_switch[i].eapdnid != -1) {
928                 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
929                 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
930                         forcemute = (w->param.eapdbtl &
931                             HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
932         }
933
934         if (hdac_hp_switch[i].execsense != -1)
935                 hdac_command(sc,
936                     HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
937                     hdac_hp_switch[i].execsense), cad);
938
939         timeout = 10000;
940         do {
941                 res = hdac_command(sc,
942                     HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid),
943                     cad);
944                 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff)
945                         break;
946                 DELAY(10);
947         } while (--timeout != 0);
948
949         HDA_BOOTVERBOSE(
950                 device_printf(sc->dev,
951                     "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n",
952                     hdac_hp_switch[i].hpnid, timeout, res);
953         );
954
955         res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
956         res ^= hdac_hp_switch[i].inverted;
957
958         switch (hdac_hp_switch[i].type) {
959         case HDAC_HP_SWITCH_CTL:
960                 ctl = hdac_audio_ctl_amp_get(devinfo,
961                     hdac_hp_switch[i].hpnid, 0, 1);
962                 if (ctl != NULL) {
963                         val = (res != 0 && forcemute == 0) ?
964                             HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
965                         if (val != ctl->muted) {
966                                 ctl->muted = val;
967                                 hdac_audio_ctl_amp_set(ctl,
968                                     HDA_AMP_MUTE_DEFAULT, ctl->left,
969                                     ctl->right);
970                         }
971                 }
972                 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
973                         ctl = hdac_audio_ctl_amp_get(devinfo,
974                             hdac_hp_switch[i].spkrnid[j], 0, 1);
975                         if (ctl == NULL)
976                                 continue;
977                         val = (res != 0 || forcemute == 1) ?
978                             HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
979                         if (val == ctl->muted)
980                                 continue;
981                         ctl->muted = val;
982                         hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
983                             ctl->left, ctl->right);
984                 }
985                 break;
986         case HDAC_HP_SWITCH_CTRL:
987                 if (res != 0) {
988                         /* HP in */
989                         w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
990                         if (w != NULL && w->type ==
991                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
992                                 if (forcemute == 0)
993                                         val = w->wclass.pin.ctrl |
994                                             HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
995                                 else
996                                         val = w->wclass.pin.ctrl &
997                                             ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
998                                 if (val != w->wclass.pin.ctrl) {
999                                         w->wclass.pin.ctrl = val;
1000                                         hdac_command(sc,
1001                                             HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1002                                             w->nid, w->wclass.pin.ctrl), cad);
1003                                 }
1004                         }
1005                         for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1006                                 w = hdac_widget_get(devinfo,
1007                                     hdac_hp_switch[i].spkrnid[j]);
1008                                 if (w == NULL || w->type !=
1009                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1010                                         continue;
1011                                 val = w->wclass.pin.ctrl &
1012                                     ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1013                                 if (val == w->wclass.pin.ctrl)
1014                                         continue;
1015                                 w->wclass.pin.ctrl = val;
1016                                 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1017                                     cad, w->nid, w->wclass.pin.ctrl), cad);
1018                         }
1019                 } else {
1020                         /* HP out */
1021                         w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
1022                         if (w != NULL && w->type ==
1023                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1024                                 val = w->wclass.pin.ctrl &
1025                                     ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1026                                 if (val != w->wclass.pin.ctrl) {
1027                                         w->wclass.pin.ctrl = val;
1028                                         hdac_command(sc,
1029                                             HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1030                                             w->nid, w->wclass.pin.ctrl), cad);
1031                                 }
1032                         }
1033                         for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1034                                 w = hdac_widget_get(devinfo,
1035                                     hdac_hp_switch[i].spkrnid[j]);
1036                                 if (w == NULL || w->type !=
1037                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1038                                         continue;
1039                                 if (forcemute == 0)
1040                                         val = w->wclass.pin.ctrl |
1041                                             HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1042                                 else
1043                                         val = w->wclass.pin.ctrl &
1044                                             ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1045                                 if (val == w->wclass.pin.ctrl)
1046                                         continue;
1047                                 w->wclass.pin.ctrl = val;
1048                                 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
1049                                     cad, w->nid, w->wclass.pin.ctrl), cad);
1050                         }
1051                 }
1052                 break;
1053         case HDAC_HP_SWITCH_DEBUG:
1054                 if (hdac_hp_switch[i].execsense != -1)
1055                         hdac_command(sc,
1056                             HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
1057                             hdac_hp_switch[i].execsense), cad);
1058                 res = hdac_command(sc,
1059                     HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
1060                 device_printf(sc->dev,
1061                     "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1062                     hdac_hp_switch[i].hpnid, res);
1063                 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
1064                         w = hdac_widget_get(devinfo,
1065                             hdac_hp_switch[i].spkrnid[j]);
1066                         if (w == NULL || w->type !=
1067                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1068                                 continue;
1069                         if (hdac_hp_switch[i].execsense != -1)
1070                                 hdac_command(sc,
1071                                     HDA_CMD_SET_PIN_SENSE(cad, w->nid,
1072                                     hdac_hp_switch[i].execsense), cad);
1073                         res = hdac_command(sc,
1074                             HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
1075                         device_printf(sc->dev,
1076                             "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1077                             j + 1, w->nid, res);
1078                 }
1079                 break;
1080         default:
1081                 break;
1082         }
1083 }
1084
1085 static void
1086 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1087 {
1088         struct hdac_softc *sc;
1089         struct hdac_devinfo *devinfo = NULL;
1090         device_t *devlist = NULL;
1091         int devcount, i;
1092
1093         if (codec == NULL || codec->sc == NULL)
1094                 return;
1095
1096         sc = codec->sc;
1097
1098         HDA_BOOTVERBOSE(
1099                 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1100         );
1101
1102         device_get_children(sc->dev, &devlist, &devcount);
1103         for (i = 0; devlist != NULL && i < devcount; i++) {
1104                 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1105                 if (devinfo != NULL && devinfo->node_type ==
1106                     HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1107                     devinfo->codec != NULL &&
1108                     devinfo->codec->cad == codec->cad) {
1109                         break;
1110                 } else
1111                         devinfo = NULL;
1112         }
1113         if (devlist != NULL)
1114                 kfree(devlist, M_TEMP);
1115
1116         if (devinfo == NULL)
1117                 return;
1118
1119         switch (tag) {
1120         case HDAC_UNSOLTAG_EVENT_HP:
1121                 hdac_hp_switch_handler(devinfo);
1122                 break;
1123         case HDAC_UNSOLTAG_EVENT_TEST:
1124                 device_printf(sc->dev, "Unsol Test!\n");
1125                 break;
1126         default:
1127                 break;
1128         }
1129 }
1130
1131 static int
1132 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1133 {
1134         /* XXX to be removed */
1135 #ifdef HDAC_INTR_EXTRA
1136         uint32_t res;
1137 #endif
1138
1139         if (!(ch->flags & HDAC_CHN_RUNNING))
1140                 return (0);
1141
1142         /* XXX to be removed */
1143 #ifdef HDAC_INTR_EXTRA
1144         res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1145 #endif
1146
1147         /* XXX to be removed */
1148 #ifdef HDAC_INTR_EXTRA
1149         HDA_BOOTVERBOSE(
1150                 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1151                         device_printf(sc->dev,
1152                             "PCMDIR_%s intr triggered beyond stream boundary:"
1153                             "%08x\n",
1154                             (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1155         );
1156 #endif
1157
1158         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1159             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1160
1161         /* XXX to be removed */
1162 #ifdef HDAC_INTR_EXTRA
1163         if (res & HDAC_SDSTS_BCIS) {
1164 #endif
1165                 return (1);
1166         /* XXX to be removed */
1167 #ifdef HDAC_INTR_EXTRA
1168         }
1169 #endif
1170
1171         return (0);
1172 }
1173
1174 /****************************************************************************
1175  * void hdac_intr_handler(void *)
1176  *
1177  * Interrupt handler. Processes interrupts received from the hdac.
1178  ****************************************************************************/
1179 static void
1180 hdac_intr_handler(void *context)
1181 {
1182         struct hdac_softc *sc;
1183         uint32_t intsts;
1184         uint8_t rirbsts;
1185         struct hdac_rirb *rirb_base;
1186         uint32_t trigger;
1187
1188         sc = (struct hdac_softc *)context;
1189
1190         hdac_lock(sc);
1191         if (sc->polling != 0) {
1192                 hdac_unlock(sc);
1193                 return;
1194         }
1195
1196         /* Do we have anything to do? */
1197         intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1198         if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1199                 hdac_unlock(sc);
1200                 return;
1201         }
1202
1203         trigger = 0;
1204
1205         /* Was this a controller interrupt? */
1206         if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1207                 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1208                 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1209                 /* Get as many responses that we can */
1210                 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1211                         HDAC_WRITE_1(&sc->mem,
1212                             HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1213                         if (hdac_rirb_flush(sc) != 0)
1214                                 trigger |= HDAC_TRIGGER_UNSOL;
1215                         rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1216                 }
1217                 /* XXX to be removed */
1218                 /* Clear interrupt and exit */
1219 #ifdef HDAC_INTR_EXTRA
1220                 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1221 #endif
1222         }
1223
1224         if (intsts & HDAC_INTSTS_SIS_MASK) {
1225                 if ((intsts & (1 << sc->num_iss)) &&
1226                     hdac_stream_intr(sc, &sc->play) != 0)
1227                         trigger |= HDAC_TRIGGER_PLAY;
1228                 if ((intsts & (1 << 0)) &&
1229                     hdac_stream_intr(sc, &sc->rec) != 0)
1230                         trigger |= HDAC_TRIGGER_REC;
1231                 /* XXX to be removed */
1232 #ifdef HDAC_INTR_EXTRA
1233                 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1234                     HDAC_INTSTS_SIS_MASK);
1235 #endif
1236         }
1237
1238         hdac_unlock(sc);
1239
1240         if (trigger & HDAC_TRIGGER_PLAY)
1241                 chn_intr(sc->play.c);
1242         if (trigger & HDAC_TRIGGER_REC)
1243                 chn_intr(sc->rec.c);
1244         if (trigger & HDAC_TRIGGER_UNSOL)
1245                 taskqueue_enqueue(taskqueue_swi, &sc->unsolq_task);
1246 }
1247
1248 /****************************************************************************
1249  * int hdac_reset(hdac_softc *)
1250  *
1251  * Reset the hdac to a quiescent and known state.
1252  ****************************************************************************/
1253 static int
1254 hdac_reset(struct hdac_softc *sc)
1255 {
1256         uint32_t gctl;
1257         int count, i;
1258
1259         /*
1260          * Stop all Streams DMA engine
1261          */
1262         for (i = 0; i < sc->num_iss; i++)
1263                 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1264         for (i = 0; i < sc->num_oss; i++)
1265                 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1266         for (i = 0; i < sc->num_bss; i++)
1267                 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1268
1269         /*
1270          * Stop Control DMA engines.
1271          */
1272         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1273         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1274
1275         /*
1276          * Reset DMA position buffer.
1277          */
1278         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1279         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1280
1281         /*
1282          * Reset the controller. The reset must remain asserted for
1283          * a minimum of 100us.
1284          */
1285         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1286         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1287         count = 10000;
1288         do {
1289                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1290                 if (!(gctl & HDAC_GCTL_CRST))
1291                         break;
1292                 DELAY(10);
1293         } while (--count);
1294         if (gctl & HDAC_GCTL_CRST) {
1295                 device_printf(sc->dev, "Unable to put hdac in reset\n");
1296                 return (ENXIO);
1297         }
1298         DELAY(100);
1299         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1300         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1301         count = 10000;
1302         do {
1303                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1304                 if (gctl & HDAC_GCTL_CRST)
1305                         break;
1306                 DELAY(10);
1307         } while (--count);
1308         if (!(gctl & HDAC_GCTL_CRST)) {
1309                 device_printf(sc->dev, "Device stuck in reset\n");
1310                 return (ENXIO);
1311         }
1312
1313         /*
1314          * Wait for codecs to finish their own reset sequence. The delay here
1315          * should be of 250us but for some reasons, on it's not enough on my
1316          * computer. Let's use twice as much as necessary to make sure that
1317          * it's reset properly.
1318          */
1319         DELAY(1000);
1320
1321         return (0);
1322 }
1323
1324
1325 /****************************************************************************
1326  * int hdac_get_capabilities(struct hdac_softc *);
1327  *
1328  * Retreive the general capabilities of the hdac;
1329  *      Number of Input Streams
1330  *      Number of Output Streams
1331  *      Number of bidirectional Streams
1332  *      64bit ready
1333  *      CORB and RIRB sizes
1334  ****************************************************************************/
1335 static int
1336 hdac_get_capabilities(struct hdac_softc *sc)
1337 {
1338         uint16_t gcap;
1339         uint8_t corbsize, rirbsize;
1340
1341         gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1342         sc->num_iss = HDAC_GCAP_ISS(gcap);
1343         sc->num_oss = HDAC_GCAP_OSS(gcap);
1344         sc->num_bss = HDAC_GCAP_BSS(gcap);
1345
1346         sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1347
1348         corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1349         if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1350             HDAC_CORBSIZE_CORBSZCAP_256)
1351                 sc->corb_size = 256;
1352         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1353             HDAC_CORBSIZE_CORBSZCAP_16)
1354                 sc->corb_size = 16;
1355         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1356             HDAC_CORBSIZE_CORBSZCAP_2)
1357                 sc->corb_size = 2;
1358         else {
1359                 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1360                     __func__, corbsize);
1361                 return (ENXIO);
1362         }
1363
1364         rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1365         if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1366             HDAC_RIRBSIZE_RIRBSZCAP_256)
1367                 sc->rirb_size = 256;
1368         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1369             HDAC_RIRBSIZE_RIRBSZCAP_16)
1370                 sc->rirb_size = 16;
1371         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1372             HDAC_RIRBSIZE_RIRBSZCAP_2)
1373                 sc->rirb_size = 2;
1374         else {
1375                 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1376                     __func__, rirbsize);
1377                 return (ENXIO);
1378         }
1379
1380         return (0);
1381 }
1382
1383
1384 /****************************************************************************
1385  * void hdac_dma_cb
1386  *
1387  * This function is called by bus_dmamap_load when the mapping has been
1388  * established. We just record the physical address of the mapping into
1389  * the struct hdac_dma passed in.
1390  ****************************************************************************/
1391 static void
1392 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1393 {
1394         struct hdac_dma *dma;
1395
1396         if (error == 0) {
1397                 dma = (struct hdac_dma *)callback_arg;
1398                 dma->dma_paddr = segs[0].ds_addr;
1399         }
1400 }
1401
1402
1403 /****************************************************************************
1404  * int hdac_dma_alloc
1405  *
1406  * This function allocate and setup a dma region (struct hdac_dma).
1407  * It must be freed by a corresponding hdac_dma_free.
1408  ****************************************************************************/
1409 static int
1410 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1411 {
1412         bus_size_t roundsz;
1413         int result;
1414         bus_addr_t lowaddr;
1415
1416         roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1417         lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1418             BUS_SPACE_MAXADDR_32BIT;
1419         bzero(dma, sizeof(*dma));
1420
1421         /*
1422          * Create a DMA tag
1423          */
1424         result = bus_dma_tag_create(NULL,       /* parent */
1425             HDAC_DMA_ALIGNMENT,                 /* alignment */
1426             0,                                  /* boundary */
1427             lowaddr,                            /* lowaddr */
1428             BUS_SPACE_MAXADDR,                  /* highaddr */
1429             NULL,                               /* filtfunc */
1430             NULL,                               /* fistfuncarg */
1431             roundsz,                            /* maxsize */
1432             1,                                  /* nsegments */
1433             roundsz,                            /* maxsegsz */
1434             0,                                  /* flags */
1435             &dma->dma_tag);                     /* dmat */
1436         if (result != 0) {
1437                 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1438                     __func__, result);
1439                 goto hdac_dma_alloc_fail;
1440         }
1441
1442         /*
1443          * Allocate DMA memory
1444          */
1445 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1446         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1447             BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1448             ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1449             &dma->dma_map);
1450 #else
1451         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1452             BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map);
1453 #endif
1454         if (result != 0) {
1455                 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1456                     __func__, result);
1457                 goto hdac_dma_alloc_fail;
1458         }
1459
1460         dma->dma_size = roundsz;
1461
1462         /*
1463          * Map the memory
1464          */
1465         result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1466             (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1467         if (result != 0 || dma->dma_paddr == 0) {
1468                 if (result == 0)
1469                         result = ENOMEM;
1470                 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1471                     __func__, result);
1472                 goto hdac_dma_alloc_fail;
1473         }
1474
1475         HDA_BOOTVERBOSE(
1476                 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1477                     __func__, (uintmax_t)size, (uintmax_t)roundsz);
1478         );
1479
1480         return (0);
1481
1482 hdac_dma_alloc_fail:
1483         hdac_dma_free(sc, dma);
1484
1485         return (result);
1486 }
1487
1488
1489 /****************************************************************************
1490  * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1491  *
1492  * Free a struct dhac_dma that has been previously allocated via the
1493  * hdac_dma_alloc function.
1494  ****************************************************************************/
1495 static void
1496 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1497 {
1498         if (dma->dma_map != NULL) {
1499 #if 0
1500                 /* Flush caches */
1501                 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1502                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1503 #endif
1504                 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1505         }
1506         if (dma->dma_vaddr != NULL) {
1507                 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1508                 dma->dma_vaddr = NULL;
1509         }
1510         dma->dma_map = NULL;
1511         if (dma->dma_tag != NULL) {
1512                 bus_dma_tag_destroy(dma->dma_tag);
1513                 dma->dma_tag = NULL;
1514         }
1515         dma->dma_size = 0;
1516 }
1517
1518 /****************************************************************************
1519  * int hdac_mem_alloc(struct hdac_softc *)
1520  *
1521  * Allocate all the bus resources necessary to speak with the physical
1522  * controller.
1523  ****************************************************************************/
1524 static int
1525 hdac_mem_alloc(struct hdac_softc *sc)
1526 {
1527         struct hdac_mem *mem;
1528
1529         mem = &sc->mem;
1530         mem->mem_rid = PCIR_BAR(0);
1531         mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1532             &mem->mem_rid, RF_ACTIVE);
1533         if (mem->mem_res == NULL) {
1534                 device_printf(sc->dev,
1535                     "%s: Unable to allocate memory resource\n", __func__);
1536                 return (ENOMEM);
1537         }
1538         mem->mem_tag = rman_get_bustag(mem->mem_res);
1539         mem->mem_handle = rman_get_bushandle(mem->mem_res);
1540
1541         return (0);
1542 }
1543
1544 /****************************************************************************
1545  * void hdac_mem_free(struct hdac_softc *)
1546  *
1547  * Free up resources previously allocated by hdac_mem_alloc.
1548  ****************************************************************************/
1549 static void
1550 hdac_mem_free(struct hdac_softc *sc)
1551 {
1552         struct hdac_mem *mem;
1553
1554         mem = &sc->mem;
1555         if (mem->mem_res != NULL)
1556                 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1557                     mem->mem_res);
1558         mem->mem_res = NULL;
1559 }
1560
1561 /****************************************************************************
1562  * int hdac_irq_alloc(struct hdac_softc *)
1563  *
1564  * Allocate and setup the resources necessary for interrupt handling.
1565  ****************************************************************************/
1566 static int
1567 hdac_irq_alloc(struct hdac_softc *sc)
1568 {
1569         struct hdac_irq *irq;
1570         int result;
1571         u_int irq_flags;
1572
1573         irq = &sc->irq;
1574         irq->irq_rid = 0x0;
1575         irq->irq_type = pci_alloc_1intr(sc->dev, hdac_msi_enable,
1576             &irq->irq_rid, &irq_flags);
1577         irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1578             &irq->irq_rid, irq_flags);
1579         if (irq->irq_res == NULL) {
1580                 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1581                     __func__);
1582                 goto hdac_irq_alloc_fail;
1583         }
1584         result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1585             hdac_intr_handler, sc, &irq->irq_handle);
1586         if (result != 0) {
1587                 device_printf(sc->dev,
1588                     "%s: Unable to setup interrupt handler (%x)\n",
1589                     __func__, result);
1590                 goto hdac_irq_alloc_fail;
1591         }
1592
1593         return (0);
1594
1595 hdac_irq_alloc_fail:
1596         hdac_irq_free(sc);
1597
1598         return (ENXIO);
1599 }
1600
1601 /****************************************************************************
1602  * void hdac_irq_free(struct hdac_softc *)
1603  *
1604  * Free up resources previously allocated by hdac_irq_alloc.
1605  ****************************************************************************/
1606 static void
1607 hdac_irq_free(struct hdac_softc *sc)
1608 {
1609         struct hdac_irq *irq;
1610
1611         irq = &sc->irq;
1612         if (irq->irq_res != NULL && irq->irq_handle != NULL)
1613                 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1614         if (irq->irq_res != NULL)
1615                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1616                     irq->irq_res);
1617         if (irq->irq_type == PCI_INTR_TYPE_MSI)
1618                 pci_release_msi(sc->dev);
1619         irq->irq_handle = NULL;
1620         irq->irq_res = NULL;
1621         irq->irq_rid = 0x0;
1622 }
1623
1624 /****************************************************************************
1625  * void hdac_corb_init(struct hdac_softc *)
1626  *
1627  * Initialize the corb registers for operations but do not start it up yet.
1628  * The CORB engine must not be running when this function is called.
1629  ****************************************************************************/
1630 static void
1631 hdac_corb_init(struct hdac_softc *sc)
1632 {
1633         uint8_t corbsize;
1634         uint64_t corbpaddr;
1635
1636         /* Setup the CORB size. */
1637         switch (sc->corb_size) {
1638         case 256:
1639                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1640                 break;
1641         case 16:
1642                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1643                 break;
1644         case 2:
1645                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1646                 break;
1647         default:
1648                 panic("%s: Invalid CORB size (%x)", __func__, sc->corb_size);
1649         }
1650         HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1651
1652         /* Setup the CORB Address in the hdac */
1653         corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1654         HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1655         HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1656
1657         /* Set the WP and RP */
1658         sc->corb_wp = 0;
1659         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1660         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1661         /*
1662          * The HDA specification indicates that the CORBRPRST bit will always
1663          * read as zero. Unfortunately, it seems that at least the 82801G
1664          * doesn't reset the bit to zero, which stalls the corb engine.
1665          * manually reset the bit to zero before continuing.
1666          */
1667         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1668
1669         /* Enable CORB error reporting */
1670 #if 0
1671         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1672 #endif
1673 }
1674
1675 /****************************************************************************
1676  * void hdac_rirb_init(struct hdac_softc *)
1677  *
1678  * Initialize the rirb registers for operations but do not start it up yet.
1679  * The RIRB engine must not be running when this function is called.
1680  ****************************************************************************/
1681 static void
1682 hdac_rirb_init(struct hdac_softc *sc)
1683 {
1684         uint8_t rirbsize;
1685         uint64_t rirbpaddr;
1686
1687         /* Setup the RIRB size. */
1688         switch (sc->rirb_size) {
1689         case 256:
1690                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1691                 break;
1692         case 16:
1693                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1694                 break;
1695         case 2:
1696                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1697                 break;
1698         default:
1699                 panic("%s: Invalid RIRB size (%x)", __func__, sc->rirb_size);
1700         }
1701         HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1702
1703         /* Setup the RIRB Address in the hdac */
1704         rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1705         HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1706         HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1707
1708         /* Setup the WP and RP */
1709         sc->rirb_rp = 0;
1710         HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1711
1712         if (sc->polling == 0) {
1713                 /* Setup the interrupt threshold */
1714                 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1715
1716                 /* Enable Overrun and response received reporting */
1717 #if 0
1718                 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1719                     HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1720 #else
1721                 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1722 #endif
1723         }
1724
1725 #if 0
1726         /*
1727          * Make sure that the Host CPU cache doesn't contain any dirty
1728          * cache lines that falls in the rirb. If I understood correctly, it
1729          * should be sufficient to do this only once as the rirb is purely
1730          * read-only from now on.
1731          */
1732         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1733             BUS_DMASYNC_PREREAD);
1734 #endif
1735 }
1736
1737 /****************************************************************************
1738  * void hdac_corb_start(hdac_softc *)
1739  *
1740  * Startup the corb DMA engine
1741  ****************************************************************************/
1742 static void
1743 hdac_corb_start(struct hdac_softc *sc)
1744 {
1745         uint32_t corbctl;
1746
1747         corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1748         corbctl |= HDAC_CORBCTL_CORBRUN;
1749         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1750 }
1751
1752 /****************************************************************************
1753  * void hdac_rirb_start(hdac_softc *)
1754  *
1755  * Startup the rirb DMA engine
1756  ****************************************************************************/
1757 static void
1758 hdac_rirb_start(struct hdac_softc *sc)
1759 {
1760         uint32_t rirbctl;
1761
1762         rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1763         rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1764         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1765 }
1766
1767
1768 /****************************************************************************
1769  * void hdac_scan_codecs(struct hdac_softc *, int)
1770  *
1771  * Scan the bus for available codecs, starting with num.
1772  ****************************************************************************/
1773 static void
1774 hdac_scan_codecs(struct hdac_softc *sc, int num)
1775 {
1776         struct hdac_codec *codec;
1777         int i;
1778         uint16_t statests;
1779
1780         if (num < 0)
1781                 num = 0;
1782         if (num >= HDAC_CODEC_MAX)
1783                 num = HDAC_CODEC_MAX - 1;
1784
1785         statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1786         for (i = num; i < HDAC_CODEC_MAX; i++) {
1787                 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1788                         /* We have found a codec. */
1789                         codec = kmalloc(sizeof(*codec), M_HDAC,
1790                                         M_ZERO | M_WAITOK);
1791                         codec->commands = NULL;
1792                         codec->responses_received = 0;
1793                         codec->verbs_sent = 0;
1794                         codec->sc = sc;
1795                         codec->cad = i;
1796                         sc->codecs[i] = codec;
1797                         if (hdac_probe_codec(codec) != 0)
1798                                 break;
1799                 }
1800         }
1801         /* All codecs have been probed, now try to attach drivers to them */
1802         /* bus_generic_attach(sc->dev); */
1803 }
1804
1805 /****************************************************************************
1806  * void hdac_probe_codec(struct hdac_softc *, int)
1807  *
1808  * Probe a the given codec_id for available function groups.
1809  ****************************************************************************/
1810 static int
1811 hdac_probe_codec(struct hdac_codec *codec)
1812 {
1813         struct hdac_softc *sc = codec->sc;
1814         struct hdac_devinfo *devinfo;
1815         uint32_t vendorid, revisionid, subnode;
1816         int startnode;
1817         int endnode;
1818         int i;
1819         nid_t cad = codec->cad;
1820
1821         HDA_BOOTVERBOSE(
1822                 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1823         );
1824         vendorid = hdac_command(sc,
1825             HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1826             cad);
1827         revisionid = hdac_command(sc,
1828             HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1829             cad);
1830         subnode = hdac_command(sc,
1831             HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1832             cad);
1833         startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1834         endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1835
1836         HDA_BOOTVERBOSE(
1837                 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1838                     startnode, endnode);
1839         );
1840         for (i = startnode; i < endnode; i++) {
1841                 devinfo = hdac_probe_function(codec, i);
1842                 if (devinfo != NULL) {
1843                         /* XXX Ignore other FG. */
1844                         devinfo->vendor_id =
1845                             HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1846                         devinfo->device_id =
1847                             HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1848                         devinfo->revision_id =
1849                             HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1850                         devinfo->stepping_id =
1851                             HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1852                         HDA_BOOTVERBOSE(
1853                                 device_printf(sc->dev,
1854                                     "HDA_DEBUG: \tFound AFG nid=%d "
1855                                     "[startnode=%d endnode=%d]\n",
1856                                     devinfo->nid, startnode, endnode);
1857                         );
1858                         return (1);
1859                 }
1860         }
1861
1862         HDA_BOOTVERBOSE(
1863                 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1864         );
1865         return (0);
1866 }
1867
1868 static struct hdac_devinfo *
1869 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1870 {
1871         struct hdac_softc *sc = codec->sc;
1872         struct hdac_devinfo *devinfo;
1873         uint32_t fctgrptype;
1874         nid_t cad = codec->cad;
1875
1876         fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1877             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1878
1879         /* XXX For now, ignore other FG. */
1880         if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1881                 return (NULL);
1882
1883         devinfo = kmalloc(sizeof(*devinfo), M_HDAC, M_WAITOK | M_ZERO);
1884         devinfo->nid = nid;
1885         devinfo->node_type = fctgrptype;
1886         devinfo->codec = codec;
1887
1888         hdac_add_child(sc, devinfo);
1889
1890         return (devinfo);
1891 }
1892
1893 static void
1894 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1895 {
1896         devinfo->dev = device_add_child(sc->dev, NULL, -1);
1897         device_set_ivars(devinfo->dev, (void *)devinfo);
1898         /* XXX - Print more information when booting verbose??? */
1899 }
1900
1901 static void
1902 hdac_widget_connection_parse(struct hdac_widget *w)
1903 {
1904         struct hdac_softc *sc = w->devinfo->codec->sc;
1905         uint32_t res;
1906         int i, j, max, ents, entnum;
1907         nid_t cad = w->devinfo->codec->cad;
1908         nid_t nid = w->nid;
1909         nid_t cnid, addcnid, prevcnid;
1910
1911         w->nconns = 0;
1912
1913         res = hdac_command(sc,
1914             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1915
1916         ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1917
1918         if (ents < 1)
1919                 return;
1920
1921         entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1922         max = NELEM(w->conns) - 1;
1923         prevcnid = 0;
1924
1925 #define CONN_RMASK(e)           (1 << ((32 / (e)) - 1))
1926 #define CONN_NMASK(e)           (CONN_RMASK(e) - 1)
1927 #define CONN_RESVAL(r, e, n)    ((r) >> ((32 / (e)) * (n)))
1928 #define CONN_RANGE(r, e, n)     (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1929 #define CONN_CNID(r, e, n)      (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
1930
1931         for (i = 0; i < ents; i += entnum) {
1932                 res = hdac_command(sc,
1933                     HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1934                 for (j = 0; j < entnum; j++) {
1935                         cnid = CONN_CNID(res, entnum, j);
1936                         if (cnid == 0) {
1937                                 if (w->nconns < ents)
1938                                         device_printf(sc->dev,
1939                                             "%s: nid=%d WARNING: zero cnid "
1940                                             "entnum=%d j=%d index=%d "
1941                                             "entries=%d found=%d res=0x%08x\n",
1942                                             __func__, nid, entnum, j, i,
1943                                             ents, w->nconns, res);
1944                                 else
1945                                         goto getconns_out;
1946                         }
1947                         if (cnid < w->devinfo->startnode ||
1948                             cnid >= w->devinfo->endnode) {
1949                                 HDA_BOOTVERBOSE(
1950                                         device_printf(sc->dev,
1951                                             "%s: GHOST: nid=%d j=%d "
1952                                             "entnum=%d index=%d res=0x%08x\n",
1953                                             __func__, nid, j, entnum, i, res);
1954                                 );
1955                         }
1956                         if (CONN_RANGE(res, entnum, j) == 0)
1957                                 addcnid = cnid;
1958                         else if (prevcnid == 0 || prevcnid >= cnid) {
1959                                 device_printf(sc->dev,
1960                                     "%s: WARNING: Invalid child range "
1961                                     "nid=%d index=%d j=%d entnum=%d "
1962                                     "prevcnid=%d cnid=%d res=0x%08x\n",
1963                                     __func__, nid, i, j, entnum, prevcnid,
1964                                     cnid, res);
1965                                 addcnid = cnid;
1966                         } else
1967                                 addcnid = prevcnid + 1;
1968                         while (addcnid <= cnid) {
1969                                 if (w->nconns > max) {
1970                                         device_printf(sc->dev,
1971                                             "%s: nid=%d: Adding %d: "
1972                                             "Max connection reached! max=%d\n",
1973                                             __func__, nid, addcnid, max + 1);
1974                                         goto getconns_out;
1975                                 }
1976                                 w->conns[w->nconns++] = addcnid++;
1977                         }
1978                         prevcnid = cnid;
1979                 }
1980         }
1981
1982 getconns_out:
1983         HDA_BOOTVERBOSE(
1984                 device_printf(sc->dev,
1985                     "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
1986                     __func__, nid, ents, w->nconns);
1987         );
1988         return;
1989 }
1990
1991 static uint32_t
1992 hdac_widget_pin_getconfig(struct hdac_widget *w)
1993 {
1994         struct hdac_softc *sc;
1995         uint32_t config, orig, id;
1996         nid_t cad, nid;
1997
1998         sc = w->devinfo->codec->sc;
1999         cad = w->devinfo->codec->cad;
2000         nid = w->nid;
2001         id = hdac_codec_id(w->devinfo);
2002
2003         config = hdac_command(sc,
2004             HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
2005             cad);
2006         orig = config;
2007
2008         /*
2009          * XXX REWRITE!!!! Don't argue!
2010          */
2011         if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
2012                 switch (nid) {
2013                 case 26:
2014                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2015                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2016                         break;
2017                 case 27:
2018                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2019                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
2020                         break;
2021                 default:
2022                         break;
2023                 }
2024         } else if (id == HDA_CODEC_ALC880 &&
2025             (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
2026             sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
2027                 /*
2028                  * Super broken BIOS
2029                  */
2030                 switch (nid) {
2031                 case 20:
2032                         break;
2033                 case 21:
2034                         break;
2035                 case 22:
2036                         break;
2037                 case 23:
2038                         break;
2039                 case 24:        /* MIC1 */
2040                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2041                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2042                         break;
2043                 case 25:        /* XXX MIC2 */
2044                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2045                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2046                         break;
2047                 case 26:        /* LINE1 */
2048                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2049                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2050                         break;
2051                 case 27:        /* XXX LINE2 */
2052                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2053                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2054                         break;
2055                 case 28:        /* CD */
2056                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2057                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2058                         break;
2059                 case 30:
2060                         break;
2061                 case 31:
2062                         break;
2063                 default:
2064                         break;
2065                 }
2066         } else if (id == HDA_CODEC_ALC883 &&
2067             (sc->pci_subvendor == MSI_MS034A_SUBVENDOR ||
2068             HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) {
2069                 switch (nid) {
2070                 case 25:
2071                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2072                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2073                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2074                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2075                         break;
2076                 case 28:
2077                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2078                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2079                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2080                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2081                         break;
2082                 default:
2083                         break;
2084                 }
2085         } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
2086             HP_V3000_SUBVENDOR) {
2087                 switch (nid) {
2088                 case 18:
2089                         config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2090                         config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2091                         break;
2092                 case 20:
2093                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2094                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2095                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2096                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2097                         break;
2098                 case 21:
2099                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2100                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2101                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2102                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2103                         break;
2104                 default:
2105                         break;
2106                 }
2107         } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2108             HP_DV5000_SUBVENDOR) {
2109                 switch (nid) {
2110                 case 20:
2111                 case 21:
2112                         config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2113                         config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2114                         break;
2115                 default:
2116                         break;
2117                 }
2118         } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2119             ASUS_W6F_SUBVENDOR) {
2120                 switch (nid) {
2121                 case 11:
2122                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2123                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2124                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2125                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2126                         break;
2127                 case 15:
2128                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2129                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2130                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2131                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2132                         break;
2133                 default:
2134                         break;
2135                 }
2136         } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2137             UNIWILL_9075_SUBVENDOR) {
2138                 switch (nid) {
2139                 case 15:
2140                         config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2141                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2142                         config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2143                             HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2144                         break;
2145                 default:
2146                         break;
2147                 }
2148         } else if (id == HDA_CODEC_AD1986A &&
2149             (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2150             sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) {
2151                 switch (nid) {
2152                 case 28:        /* LINE */
2153                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2154                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2155                         break;
2156                 case 29:        /* MIC */
2157                         config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2158                         config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2159                         break;
2160                 default:
2161                         break;
2162                 }
2163         }
2164
2165         HDA_BOOTVERBOSE(
2166                 if (config != orig)
2167                         device_printf(sc->dev,
2168                             "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2169                             nid, orig, config);
2170         );
2171
2172         return (config);
2173 }
2174
2175 static uint32_t
2176 hdac_widget_pin_getcaps(struct hdac_widget *w)
2177 {
2178         struct hdac_softc *sc;
2179         uint32_t caps, orig, id;
2180         nid_t cad, nid;
2181
2182         sc = w->devinfo->codec->sc;
2183         cad = w->devinfo->codec->cad;
2184         nid = w->nid;
2185         id = hdac_codec_id(w->devinfo);
2186
2187         caps = hdac_command(sc,
2188             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2189         orig = caps;
2190
2191         HDA_BOOTVERBOSE(
2192                 if (caps != orig)
2193                         device_printf(sc->dev,
2194                             "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2195                             nid, orig, caps);
2196         );
2197
2198         return (caps);
2199 }
2200
2201 static void
2202 hdac_widget_pin_parse(struct hdac_widget *w)
2203 {
2204         struct hdac_softc *sc = w->devinfo->codec->sc;
2205         uint32_t config, pincap;
2206         char *devstr, *connstr;
2207         nid_t cad = w->devinfo->codec->cad;
2208         nid_t nid = w->nid;
2209
2210         config = hdac_widget_pin_getconfig(w);
2211         w->wclass.pin.config = config;
2212
2213         pincap = hdac_widget_pin_getcaps(w);
2214         w->wclass.pin.cap = pincap;
2215
2216         w->wclass.pin.ctrl = hdac_command(sc,
2217             HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2218             ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2219             HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2220             HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2221             HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
2222
2223         if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2224                 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2225         if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2226                 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2227         if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2228                 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2229         if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2230                 w->param.eapdbtl = hdac_command(sc,
2231                     HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2232                 w->param.eapdbtl &= 0x7;
2233                 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2234         } else
2235                 w->param.eapdbtl = HDAC_INVALID;
2236
2237         switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2238         case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2239                 devstr = "line out";
2240                 break;
2241         case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2242                 devstr = "speaker";
2243                 break;
2244         case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2245                 devstr = "headphones out";
2246                 break;
2247         case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2248                 devstr = "CD";
2249                 break;
2250         case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2251                 devstr = "SPDIF out";
2252                 break;
2253         case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2254                 devstr = "digital (other) out";
2255                 break;
2256         case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2257                 devstr = "modem, line side";
2258                 break;
2259         case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2260                 devstr = "modem, handset side";
2261                 break;
2262         case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2263                 devstr = "line in";
2264                 break;
2265         case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2266                 devstr = "AUX";
2267                 break;
2268         case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2269                 devstr = "Mic in";
2270                 break;
2271         case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2272                 devstr = "telephony";
2273                 break;
2274         case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2275                 devstr = "SPDIF in";
2276                 break;
2277         case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2278                 devstr = "digital (other) in";
2279                 break;
2280         case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2281                 devstr = "other";
2282                 break;
2283         default:
2284                 devstr = "unknown";
2285                 break;
2286         }
2287
2288         switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2289         case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2290                 connstr = "jack";
2291                 break;
2292         case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2293                 connstr = "none";
2294                 break;
2295         case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2296                 connstr = "fixed";
2297                 break;
2298         case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2299                 connstr = "jack / fixed";
2300                 break;
2301         default:
2302                 connstr = "unknown";
2303                 break;
2304         }
2305
2306         strlcat(w->name, ": ", sizeof(w->name));
2307         strlcat(w->name, devstr, sizeof(w->name));
2308         strlcat(w->name, " (", sizeof(w->name));
2309         strlcat(w->name, connstr, sizeof(w->name));
2310         strlcat(w->name, ")", sizeof(w->name));
2311 }
2312
2313 static void
2314 hdac_widget_parse(struct hdac_widget *w)
2315 {
2316         struct hdac_softc *sc = w->devinfo->codec->sc;
2317         uint32_t wcap, cap;
2318         char *typestr;
2319         nid_t cad = w->devinfo->codec->cad;
2320         nid_t nid = w->nid;
2321
2322         wcap = hdac_command(sc,
2323             HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2324             cad);
2325         w->param.widget_cap = wcap;
2326         w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2327
2328         switch (w->type) {
2329         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2330                 typestr = "audio output";
2331                 break;
2332         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2333                 typestr = "audio input";
2334                 break;
2335         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2336                 typestr = "audio mixer";
2337                 break;
2338         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2339                 typestr = "audio selector";
2340                 break;
2341         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2342                 typestr = "pin";
2343                 break;
2344         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2345                 typestr = "power widget";
2346                 break;
2347         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2348                 typestr = "volume widget";
2349                 break;
2350         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2351                 typestr = "beep widget";
2352                 break;
2353         case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2354                 typestr = "vendor widget";
2355                 break;
2356         default:
2357                 typestr = "unknown type";
2358                 break;
2359         }
2360
2361         strlcpy(w->name, typestr, sizeof(w->name));
2362
2363         if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2364                 hdac_command(sc,
2365                     HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2366                     cad);
2367                 DELAY(1000);
2368         }
2369
2370         hdac_widget_connection_parse(w);
2371
2372         if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2373                 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2374                         w->param.outamp_cap =
2375                             hdac_command(sc,
2376                             HDA_CMD_GET_PARAMETER(cad, nid,
2377                             HDA_PARAM_OUTPUT_AMP_CAP), cad);
2378                 else
2379                         w->param.outamp_cap =
2380                             w->devinfo->function.audio.outamp_cap;
2381         } else
2382                 w->param.outamp_cap = 0;
2383
2384         if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2385                 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2386                         w->param.inamp_cap =
2387                             hdac_command(sc,
2388                             HDA_CMD_GET_PARAMETER(cad, nid,
2389                             HDA_PARAM_INPUT_AMP_CAP), cad);
2390                 else
2391                         w->param.inamp_cap =
2392                             w->devinfo->function.audio.inamp_cap;
2393         } else
2394                 w->param.inamp_cap = 0;
2395
2396         if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2397             w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2398                 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2399                         cap = hdac_command(sc,
2400                             HDA_CMD_GET_PARAMETER(cad, nid,
2401                             HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2402                         w->param.supp_stream_formats = (cap != 0) ? cap :
2403                             w->devinfo->function.audio.supp_stream_formats;
2404                         cap = hdac_command(sc,
2405                             HDA_CMD_GET_PARAMETER(cad, nid,
2406                             HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2407                         w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2408                             w->devinfo->function.audio.supp_pcm_size_rate;
2409                 } else {
2410                         w->param.supp_stream_formats =
2411                             w->devinfo->function.audio.supp_stream_formats;
2412                         w->param.supp_pcm_size_rate =
2413                             w->devinfo->function.audio.supp_pcm_size_rate;
2414                 }
2415         } else {
2416                 w->param.supp_stream_formats = 0;
2417                 w->param.supp_pcm_size_rate = 0;
2418         }
2419
2420         if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2421                 hdac_widget_pin_parse(w);
2422 }
2423
2424 static struct hdac_widget *
2425 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2426 {
2427         if (devinfo == NULL || devinfo->widget == NULL ||
2428                     nid < devinfo->startnode || nid >= devinfo->endnode)
2429                 return (NULL);
2430         return (&devinfo->widget[nid - devinfo->startnode]);
2431 }
2432
2433 static __inline int
2434 hda_poll_channel(struct hdac_chan *ch)
2435 {
2436         uint32_t sz, delta;
2437         volatile uint32_t ptr;
2438
2439         if (!(ch->flags & HDAC_CHN_RUNNING))
2440                 return (0);
2441
2442         sz = ch->blksz * ch->blkcnt;
2443         if (ch->dmapos != NULL)
2444                 ptr = *(ch->dmapos);
2445         else
2446                 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2447                     ch->off + HDAC_SDLPIB);
2448         ch->ptr = ptr;
2449         ptr %= sz;
2450         ptr &= ~(ch->blksz - 1);
2451         delta = (sz + ptr - ch->prevptr) % sz;
2452
2453         if (delta < ch->blksz)
2454                 return (0);
2455
2456         ch->prevptr = ptr;
2457
2458         return (1);
2459 }
2460
2461 #define hda_chan_active(sc)    (((sc)->play.flags | (sc)->rec.flags) & \
2462                                 HDAC_CHN_RUNNING)
2463
2464 static void
2465 hda_poll_callback(void *arg)
2466 {
2467         struct hdac_softc *sc = arg;
2468         uint32_t trigger;
2469
2470         if (sc == NULL)
2471                 return;
2472
2473         hdac_lock(sc);
2474         if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2475                 hdac_unlock(sc);
2476                 return;
2477         }
2478
2479         trigger = 0;
2480         trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0;
2481         trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0;
2482
2483         /* XXX */
2484         callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2485             hda_poll_callback, sc);
2486
2487         hdac_unlock(sc);
2488
2489         if (trigger & HDAC_TRIGGER_PLAY)
2490                 chn_intr(sc->play.c);
2491         if (trigger & HDAC_TRIGGER_REC)
2492                 chn_intr(sc->rec.c);
2493 }
2494
2495 static int
2496 hdac_rirb_flush(struct hdac_softc *sc)
2497 {
2498         struct hdac_rirb *rirb_base, *rirb;
2499         struct hdac_codec *codec;
2500         struct hdac_command_list *commands;
2501         nid_t cad;
2502         uint32_t resp;
2503         uint8_t rirbwp;
2504         int ret;
2505
2506         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2507         rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2508 #if 0
2509         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2510             BUS_DMASYNC_POSTREAD);
2511 #endif
2512         ret = 0;
2513
2514         while (sc->rirb_rp != rirbwp) {
2515                 sc->rirb_rp++;
2516                 sc->rirb_rp %= sc->rirb_size;
2517                 rirb = &rirb_base[sc->rirb_rp];
2518                 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2519                 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2520                     sc->codecs[cad] == NULL)
2521                         continue;
2522                 resp = rirb->response;
2523                 codec = sc->codecs[cad];
2524                 commands = codec->commands;
2525                 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2526                         sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2527                             ((resp >> 26) & 0xffff);
2528                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2529                 } else if (commands != NULL && commands->num_commands > 0 &&
2530                     codec->responses_received < commands->num_commands)
2531                         commands->responses[codec->responses_received++] =
2532                             resp;
2533                 ret++;
2534         }
2535
2536         return (ret);
2537 }
2538
2539 static int
2540 hdac_unsolq_flush(struct hdac_softc *sc)
2541 {
2542         nid_t cad;
2543         uint32_t tag;
2544         int ret = 0;
2545
2546         if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2547                 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2548                 while (sc->unsolq_rp != sc->unsolq_wp) {
2549                         cad = sc->unsolq[sc->unsolq_rp] >> 16;
2550                         tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2551                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2552                         hdac_unsolicited_handler(sc->codecs[cad], tag);
2553                         ret++;
2554                 }
2555                 sc->unsolq_st = HDAC_UNSOLQ_READY;
2556         }
2557
2558         return (ret);
2559 }
2560
2561 static void
2562 hdac_poll_callback(void *arg)
2563 {
2564         struct hdac_softc *sc = arg;
2565         if (sc == NULL)
2566                 return;
2567
2568         hdac_lock(sc);
2569         if (sc->polling == 0 || sc->poll_ival == 0) {
2570                 hdac_unlock(sc);
2571                 return;
2572         }
2573         if (hdac_rirb_flush(sc) != 0)
2574                 hdac_unsolq_flush(sc);
2575         callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2576         hdac_unlock(sc);
2577 }
2578
2579 static void
2580 hdac_stream_stop(struct hdac_chan *ch)
2581 {
2582         struct hdac_softc *sc = ch->devinfo->codec->sc;
2583         uint32_t ctl;
2584
2585         ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2586         ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2587             HDAC_SDCTL_RUN);
2588         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2589
2590         ch->flags &= ~HDAC_CHN_RUNNING;
2591
2592         if (sc->polling != 0) {
2593                 int pollticks;
2594
2595                 if (hda_chan_active(sc) == 0) {
2596                         callout_stop(&sc->poll_hda);
2597                         sc->poll_ticks = 1;
2598                 } else {
2599                         if (sc->play.flags & HDAC_CHN_RUNNING)
2600                                 ch = &sc->play;
2601                         else
2602                                 ch = &sc->rec;
2603                         pollticks = ((uint64_t)hz * ch->blksz) /
2604                             ((uint64_t)sndbuf_getbps(ch->b) *
2605                             sndbuf_getspd(ch->b));
2606                         pollticks >>= 2;
2607                         if (pollticks > hz)
2608                                 pollticks = hz;
2609                         if (pollticks < 1) {
2610                                 HDA_BOOTVERBOSE(
2611                                         device_printf(sc->dev,
2612                                             "%s: pollticks=%d < 1 !\n",
2613                                             __func__, pollticks);
2614                                 );
2615                                 pollticks = 1;
2616                         }
2617                         if (pollticks > sc->poll_ticks) {
2618                                 HDA_BOOTVERBOSE(
2619                                         device_printf(sc->dev,
2620                                             "%s: pollticks %d -> %d\n",
2621                                             __func__, sc->poll_ticks,
2622                                             pollticks);
2623                                 );
2624                                 sc->poll_ticks = pollticks;
2625                                 callout_reset(&sc->poll_hda, 1,
2626                                     hda_poll_callback, sc);
2627                         }
2628                 }
2629         } else {
2630                 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2631                 ctl &= ~(1 << (ch->off >> 5));
2632                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2633         }
2634 }
2635
2636 static void
2637 hdac_stream_start(struct hdac_chan *ch)
2638 {
2639         struct hdac_softc *sc = ch->devinfo->codec->sc;
2640         uint32_t ctl;
2641
2642         if (sc->polling != 0) {
2643                 int pollticks;
2644
2645                 pollticks = ((uint64_t)hz * ch->blksz) /
2646                     ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2647                 pollticks >>= 2;
2648                 if (pollticks > hz)
2649                         pollticks = hz;
2650                 if (pollticks < 1) {
2651                         HDA_BOOTVERBOSE(
2652                                 device_printf(sc->dev,
2653                                     "%s: pollticks=%d < 1 !\n",
2654                                     __func__, pollticks);
2655                         );
2656                         pollticks = 1;
2657                 }
2658                 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2659                         HDA_BOOTVERBOSE(
2660                                 if (hda_chan_active(sc) == 0) {
2661                                         device_printf(sc->dev,
2662                                             "%s: pollticks=%d\n",
2663                                             __func__, pollticks);
2664                                 } else {
2665                                         device_printf(sc->dev,
2666                                             "%s: pollticks %d -> %d\n",
2667                                             __func__, sc->poll_ticks,
2668                                             pollticks);
2669                                 }
2670                         );
2671                         sc->poll_ticks = pollticks;
2672                         callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2673                             sc);
2674                 }
2675                 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2676                 ctl |= HDAC_SDCTL_RUN;
2677         } else {
2678                 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2679                 ctl |= 1 << (ch->off >> 5);
2680                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2681                 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2682                 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2683                     HDAC_SDCTL_RUN;
2684         } 
2685         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2686
2687         ch->flags |= HDAC_CHN_RUNNING;
2688 }
2689
2690 static void
2691 hdac_stream_reset(struct hdac_chan *ch)
2692 {
2693         struct hdac_softc *sc = ch->devinfo->codec->sc;
2694         int timeout = 1000;
2695         int to = timeout;
2696         uint32_t ctl;
2697
2698         ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2699         ctl |= HDAC_SDCTL_SRST;
2700         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2701         do {
2702                 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2703                 if (ctl & HDAC_SDCTL_SRST)
2704                         break;
2705                 DELAY(10);
2706         } while (--to);
2707         if (!(ctl & HDAC_SDCTL_SRST)) {
2708                 device_printf(sc->dev, "timeout in reset\n");
2709         }
2710         ctl &= ~HDAC_SDCTL_SRST;
2711         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2712         to = timeout;
2713         do {
2714                 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2715                 if (!(ctl & HDAC_SDCTL_SRST))
2716                         break;
2717                 DELAY(10);
2718         } while (--to);
2719         if (ctl & HDAC_SDCTL_SRST)
2720                 device_printf(sc->dev, "can't reset!\n");
2721 }
2722
2723 static void
2724 hdac_stream_setid(struct hdac_chan *ch)
2725 {
2726         struct hdac_softc *sc = ch->devinfo->codec->sc;
2727         uint32_t ctl;
2728
2729         ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2730         ctl &= ~HDAC_SDCTL2_STRM_MASK;
2731         ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2732         HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2733 }
2734
2735 static void
2736 hdac_bdl_setup(struct hdac_chan *ch)
2737 {
2738         struct hdac_softc *sc = ch->devinfo->codec->sc;
2739         struct hdac_bdle *bdle;
2740         uint64_t addr;
2741         uint32_t blksz, blkcnt;
2742         int i;
2743
2744         addr = (uint64_t)sndbuf_getbufaddr(ch->b);
2745         bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2746
2747         if (sc->polling != 0) {
2748                 blksz = ch->blksz * ch->blkcnt;
2749                 blkcnt = 1;
2750         } else {
2751                 blksz = ch->blksz;
2752                 blkcnt = ch->blkcnt;
2753         }
2754
2755         for (i = 0; i < blkcnt; i++, bdle++) {
2756                 bdle->addrl = (uint32_t)addr;
2757                 bdle->addrh = (uint32_t)(addr >> 32);
2758                 bdle->len = blksz;
2759                 bdle->ioc = 1 ^ sc->polling;
2760                 addr += blksz;
2761         }
2762
2763         HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2764         HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
2765         addr = ch->bdl_dma.dma_paddr;
2766         HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2767         HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2768         if (ch->dmapos != NULL &&
2769             !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2770                 addr = sc->pos_dma.dma_paddr;
2771                 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2772                     ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2773                 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2774         }
2775 }
2776
2777 static int
2778 hdac_bdl_alloc(struct hdac_chan *ch)
2779 {
2780         struct hdac_softc *sc = ch->devinfo->codec->sc;
2781         int rc;
2782
2783         rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2784             sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2785         if (rc) {
2786                 device_printf(sc->dev, "can't alloc bdl\n");
2787                 return (rc);
2788         }
2789
2790         return (0);
2791 }
2792
2793 static void
2794 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2795                                         int index, int lmute, int rmute,
2796                                         int left, int right, int dir)
2797 {
2798         uint16_t v = 0;
2799
2800         if (sc == NULL)
2801                 return;
2802
2803         if (left != right || lmute != rmute) {
2804                 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2805                     (lmute << 7) | left;
2806                 hdac_command(sc,
2807                     HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2808                 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2809                     (rmute << 7) | right;
2810         } else
2811                 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2812                     (lmute << 7) | left;
2813
2814         hdac_command(sc,
2815             HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2816 }
2817
2818 static void
2819 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2820                                                 int left, int right)
2821 {
2822         struct hdac_softc *sc;
2823         nid_t nid, cad;
2824         int lmute, rmute;
2825
2826         if (ctl == NULL || ctl->widget == NULL ||
2827             ctl->widget->devinfo == NULL ||
2828             ctl->widget->devinfo->codec == NULL ||
2829             ctl->widget->devinfo->codec->sc == NULL)
2830                 return;
2831
2832         sc = ctl->widget->devinfo->codec->sc;
2833         cad = ctl->widget->devinfo->codec->cad;
2834         nid = ctl->widget->nid;
2835
2836         if (mute == HDA_AMP_MUTE_DEFAULT) {
2837                 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2838                 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2839         } else {
2840                 lmute = HDA_AMP_LEFT_MUTED(mute);
2841                 rmute = HDA_AMP_RIGHT_MUTED(mute);
2842         }
2843
2844         if (ctl->dir & HDA_CTL_OUT)
2845                 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2846                     lmute, rmute, left, right, 0);
2847         if (ctl->dir & HDA_CTL_IN)
2848                 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2849                     lmute, rmute, left, right, 1);
2850         ctl->left = left;
2851         ctl->right = right;
2852 }
2853
2854 static void
2855 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2856 {
2857         if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2858                 return;
2859         hdac_command(w->devinfo->codec->sc,
2860             HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2861             w->nid, index), w->devinfo->codec->cad);
2862         w->selconn = index;
2863 }
2864
2865
2866 /****************************************************************************
2867  * uint32_t hdac_command_sendone_internal
2868  *
2869  * Wrapper function that sends only one command to a given codec
2870  ****************************************************************************/
2871 static uint32_t
2872 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2873 {
2874         struct hdac_command_list cl;
2875         uint32_t response = HDAC_INVALID;
2876
2877         if (!hdac_lockowned(sc))
2878                 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2879         cl.num_commands = 1;
2880         cl.verbs = &verb;
2881         cl.responses = &response;
2882
2883         hdac_command_send_internal(sc, &cl, cad);
2884
2885         return (response);
2886 }
2887
2888 /****************************************************************************
2889  * hdac_command_send_internal
2890  *
2891  * Send a command list to the codec via the corb. We queue as much verbs as
2892  * we can and sleep on the codec. When the interrupt get the responses
2893  * back from the rirb, it will wake us up so we can queue the remaining verbs
2894  * if any.
2895  ****************************************************************************/
2896 static void
2897 hdac_command_send_internal(struct hdac_softc *sc,
2898                         struct hdac_command_list *commands, nid_t cad)
2899 {
2900         struct hdac_codec *codec;
2901         int corbrp;
2902         uint32_t *corb;
2903         int timeout;
2904         int retry = 10;
2905         struct hdac_rirb *rirb_base;
2906
2907         if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2908             commands->num_commands < 1)
2909                 return;
2910
2911         codec = sc->codecs[cad];
2912         codec->commands = commands;
2913         codec->responses_received = 0;
2914         codec->verbs_sent = 0;
2915         corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2916         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2917
2918         do {
2919                 if (codec->verbs_sent != commands->num_commands) {
2920                         /* Queue as many verbs as possible */
2921                         corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2922 #if 0
2923                         bus_dmamap_sync(sc->corb_dma.dma_tag,
2924                             sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2925 #endif
2926                         while (codec->verbs_sent != commands->num_commands &&
2927                             ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2928                                 sc->corb_wp++;
2929                                 sc->corb_wp %= sc->corb_size;
2930                                 corb[sc->corb_wp] =
2931                                     commands->verbs[codec->verbs_sent++];
2932                         }
2933
2934                         /* Send the verbs to the codecs */
2935 #if 0
2936                         bus_dmamap_sync(sc->corb_dma.dma_tag,
2937                             sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2938 #endif
2939                         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2940                 }
2941
2942                 timeout = 1000;
2943                 while (hdac_rirb_flush(sc) == 0 && --timeout)
2944                         DELAY(10);
2945         } while ((codec->verbs_sent != commands->num_commands ||
2946             codec->responses_received != commands->num_commands) && --retry);
2947
2948         if (retry == 0)
2949                 device_printf(sc->dev,
2950                     "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2951                     __func__, commands->num_commands, codec->verbs_sent,
2952                     codec->responses_received);
2953
2954         codec->commands = NULL;
2955         codec->responses_received = 0;
2956         codec->verbs_sent = 0;
2957
2958         hdac_unsolq_flush(sc);
2959 }
2960
2961
2962 /****************************************************************************
2963  * Device Methods
2964  ****************************************************************************/
2965
2966 /****************************************************************************
2967  * int hdac_probe(device_t)
2968  *
2969  * Probe for the presence of an hdac. If none is found, check for a generic
2970  * match using the subclass of the device.
2971  ****************************************************************************/
2972 static int
2973 hdac_probe(device_t dev)
2974 {
2975         int i, result;
2976         uint32_t model;
2977         uint16_t class, subclass;
2978         char desc[64];
2979
2980         model = (uint32_t)pci_get_device(dev) << 16;
2981         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2982         class = pci_get_class(dev);
2983         subclass = pci_get_subclass(dev);
2984
2985         bzero(desc, sizeof(desc));
2986         result = ENXIO;
2987         for (i = 0; i < HDAC_DEVICES_LEN; i++) {
2988                 if (hdac_devices[i].model == model) {
2989                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2990                         result = BUS_PROBE_DEFAULT;
2991                         break;
2992                 }
2993                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
2994                     class == PCIC_MULTIMEDIA &&
2995                     subclass == PCIS_MULTIMEDIA_HDA) {
2996                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2997                         result = BUS_PROBE_GENERIC;
2998                         break;
2999                 }
3000         }
3001         if (result == ENXIO && class == PCIC_MULTIMEDIA &&
3002             subclass == PCIS_MULTIMEDIA_HDA) {
3003                 strlcpy(desc, "Generic", sizeof(desc));
3004                 result = BUS_PROBE_GENERIC;
3005         }
3006         if (result != ENXIO) {
3007                 strlcat(desc, " High Definition Audio Controller",
3008                     sizeof(desc));
3009                 device_set_desc_copy(dev, desc);
3010         }
3011
3012         return (result);
3013 }
3014
3015 static void *
3016 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
3017                                         struct pcm_channel *c, int dir)
3018 {
3019         struct hdac_devinfo *devinfo = data;
3020         struct hdac_softc *sc = devinfo->codec->sc;
3021         struct hdac_chan *ch;
3022
3023         hdac_lock(sc);
3024         if (dir == PCMDIR_PLAY) {
3025                 ch = &sc->play;
3026                 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
3027                 devinfo->function.audio.playcnt++;
3028         } else {
3029                 ch = &sc->rec;
3030                 ch->off = devinfo->function.audio.reccnt << 5;
3031                 devinfo->function.audio.reccnt++;
3032         }
3033         if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
3034                 ch->caps.minspeed = ch->caps.maxspeed = 48000;
3035                 ch->pcmrates[0] = 48000;
3036                 ch->pcmrates[1] = 0;
3037         }
3038         if (sc->pos_dma.dma_vaddr != NULL)
3039                 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
3040                     (sc->streamcnt * 8));
3041         else
3042                 ch->dmapos = NULL;
3043         ch->sid = ++sc->streamcnt;
3044         ch->dir = dir;
3045         ch->b = b;
3046         ch->c = c;
3047         ch->devinfo = devinfo;
3048         ch->blksz = sc->chan_size / sc->chan_blkcnt;
3049         ch->blkcnt = sc->chan_blkcnt;
3050         hdac_unlock(sc);
3051
3052         if (hdac_bdl_alloc(ch) != 0) {
3053                 ch->blkcnt = 0;
3054                 return (NULL);
3055         }
3056
3057         if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
3058                 return (NULL);
3059
3060         HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b),
3061             PAT_UNCACHEABLE);
3062
3063         return (ch);
3064 }
3065
3066 static int
3067 hdac_channel_free(kobj_t obj, void *data)
3068 {
3069         struct hdac_softc *sc;
3070         struct hdac_chan *ch;
3071
3072         ch = (struct hdac_chan *)data;
3073         sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ?
3074             ch->devinfo->codec->sc : NULL;
3075         if (ch != NULL && sc != NULL) {
3076                 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b),
3077                     sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK);
3078         }
3079
3080         return (1);
3081 }
3082
3083 static int
3084 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3085 {
3086         struct hdac_chan *ch = data;
3087         int i;
3088
3089         for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3090                 if (format == ch->caps.fmtlist[i]) {
3091                         ch->fmt = format;
3092                         return (0);
3093                 }
3094         }
3095
3096         return (EINVAL);
3097 }
3098
3099 static int
3100 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3101 {
3102         struct hdac_chan *ch = data;
3103         uint32_t spd = 0, threshold;
3104         int i;
3105
3106         for (i = 0; ch->pcmrates[i] != 0; i++) {
3107                 spd = ch->pcmrates[i];
3108                 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3109                     ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3110                 if (speed < threshold)
3111                         break;
3112         }
3113
3114         if (spd == 0)   /* impossible */
3115                 ch->spd = 48000;
3116         else
3117                 ch->spd = spd;
3118
3119         return (ch->spd);
3120 }
3121
3122 static void
3123 hdac_stream_setup(struct hdac_chan *ch)
3124 {
3125         struct hdac_softc *sc = ch->devinfo->codec->sc;
3126         struct hdac_widget *w;
3127         int i, chn, totalchn;
3128         nid_t cad = ch->devinfo->codec->cad;
3129         uint16_t fmt;
3130
3131         fmt = 0;
3132         if (ch->fmt & AFMT_S16_LE)
3133                 fmt |= ch->bit16 << 4;
3134         else if (ch->fmt & AFMT_S32_LE)
3135                 fmt |= ch->bit32 << 4;
3136         else
3137                 fmt |= 1 << 4;
3138
3139         for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3140                 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3141                         fmt |= hda_rate_tab[i].base;
3142                         fmt |= hda_rate_tab[i].mul;
3143                         fmt |= hda_rate_tab[i].div;
3144                         break;
3145                 }
3146         }
3147
3148         if (ch->fmt & AFMT_STEREO) {
3149                 fmt |= 1;
3150                 totalchn = 2;
3151         } else
3152                 totalchn = 1;
3153
3154         HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3155
3156         chn = 0;
3157         for (i = 0; ch->io[i] != -1; i++) {
3158                 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3159                 if (w == NULL)
3160                         continue;
3161                 HDA_BOOTVERBOSE(
3162                         device_printf(sc->dev,
3163                             "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3164                             "fmt=0x%08x\n",
3165                             (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3166                             ch->io[i], fmt);
3167                 );
3168                 hdac_command(sc,
3169                     HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3170                 if (ch->dir == PCMDIR_REC)
3171                         hdac_command(sc,
3172                             HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3173                             (chn < totalchn) ? ((ch->sid << 4) | chn) : 0),
3174                             cad);
3175                 else
3176                         hdac_command(sc,
3177                             HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3178                             ch->sid << 4), cad);
3179                 chn +=
3180                     HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ?
3181                     2 : 1;
3182         }
3183 }
3184
3185 static int
3186 hdac_channel_setfragments(kobj_t obj, void *data,
3187                                         uint32_t blksz, uint32_t blkcnt)
3188 {
3189         struct hdac_chan *ch = data;
3190         struct hdac_softc *sc = ch->devinfo->codec->sc;
3191
3192         blksz &= HDA_BLK_ALIGN;
3193
3194         if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3195                 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3196         if (blksz < HDA_BLK_MIN)
3197                 blksz = HDA_BLK_MIN;
3198         if (blkcnt > HDA_BDL_MAX)
3199                 blkcnt = HDA_BDL_MAX;
3200         if (blkcnt < HDA_BDL_MIN)
3201                 blkcnt = HDA_BDL_MIN;
3202
3203         while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3204                 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3205                         blkcnt >>= 1;
3206                 else if ((blksz >> 1) >= HDA_BLK_MIN)
3207                         blksz >>= 1;
3208                 else
3209                         break;
3210         }
3211
3212         if ((sndbuf_getblksz(ch->b) != blksz ||
3213             sndbuf_getblkcnt(ch->b) != blkcnt) &&
3214             sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3215                 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3216                     __func__, blksz, blkcnt);
3217
3218         ch->blksz = sndbuf_getblksz(ch->b);
3219         ch->blkcnt = sndbuf_getblkcnt(ch->b);
3220
3221         return (1);
3222 }
3223
3224 static int
3225 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3226 {
3227         struct hdac_chan *ch = data;
3228         struct hdac_softc *sc = ch->devinfo->codec->sc;
3229
3230         hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
3231
3232         return (ch->blksz);
3233 }
3234
3235 static void
3236 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3237 {
3238         struct hdac_devinfo *devinfo = ch->devinfo;
3239         nid_t cad = devinfo->codec->cad;
3240         int i;
3241
3242         hdac_stream_stop(ch);
3243
3244         for (i = 0; ch->io[i] != -1; i++) {
3245                 hdac_command(sc,
3246                     HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3247                     0), cad);
3248         }
3249 }
3250
3251 static void
3252 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3253 {
3254         ch->ptr = 0;
3255         ch->prevptr = 0;
3256         hdac_stream_stop(ch);
3257         hdac_stream_reset(ch);
3258         hdac_bdl_setup(ch);
3259         hdac_stream_setid(ch);
3260         hdac_stream_setup(ch);
3261         hdac_stream_start(ch);
3262 }
3263
3264 static int
3265 hdac_channel_trigger(kobj_t obj, void *data, int go)
3266 {
3267         struct hdac_chan *ch = data;
3268         struct hdac_softc *sc = ch->devinfo->codec->sc;
3269
3270         if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT))
3271                 return (0);
3272
3273         hdac_lock(sc);
3274         switch (go) {
3275         case PCMTRIG_START:
3276                 hdac_channel_start(sc, ch);
3277                 break;
3278         case PCMTRIG_STOP:
3279         case PCMTRIG_ABORT:
3280                 hdac_channel_stop(sc, ch);
3281                 break;
3282         default:
3283                 break;
3284         }
3285         hdac_unlock(sc);
3286
3287         return (0);
3288 }
3289
3290 static int
3291 hdac_channel_getptr(kobj_t obj, void *data)
3292 {
3293         struct hdac_chan *ch = data;
3294         struct hdac_softc *sc = ch->devinfo->codec->sc;
3295         uint32_t ptr;
3296
3297         hdac_lock(sc);
3298         if (sc->polling != 0)
3299                 ptr = ch->ptr;
3300         else if (ch->dmapos != NULL)
3301                 ptr = *(ch->dmapos);
3302         else
3303                 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3304         hdac_unlock(sc);
3305
3306         /*
3307          * Round to available space and force 128 bytes aligment.
3308          */
3309         ptr %= ch->blksz * ch->blkcnt;
3310         ptr &= HDA_BLK_ALIGN;
3311
3312         return (ptr);
3313 }
3314
3315 static struct pcmchan_caps *
3316 hdac_channel_getcaps(kobj_t obj, void *data)
3317 {
3318         return (&((struct hdac_chan *)data)->caps);
3319 }
3320
3321 static kobj_method_t hdac_channel_methods[] = {
3322         KOBJMETHOD(channel_init,                hdac_channel_init),
3323         KOBJMETHOD(channel_free,                hdac_channel_free),
3324         KOBJMETHOD(channel_setformat,           hdac_channel_setformat),
3325         KOBJMETHOD(channel_setspeed,            hdac_channel_setspeed),
3326         KOBJMETHOD(channel_setblocksize,        hdac_channel_setblocksize),
3327         KOBJMETHOD(channel_trigger,             hdac_channel_trigger),
3328         KOBJMETHOD(channel_getptr,              hdac_channel_getptr),
3329         KOBJMETHOD(channel_getcaps,             hdac_channel_getcaps),
3330         { 0, 0 }
3331 };
3332 CHANNEL_DECLARE(hdac_channel);
3333
3334 static void
3335 hdac_jack_poll_callback(void *arg)
3336 {
3337         struct hdac_devinfo *devinfo = arg;
3338         struct hdac_softc *sc;
3339
3340         if (devinfo == NULL || devinfo->codec == NULL ||
3341             devinfo->codec->sc == NULL)
3342                 return;
3343         sc = devinfo->codec->sc;
3344         hdac_lock(sc);
3345         if (sc->poll_ival == 0) {
3346                 hdac_unlock(sc);
3347                 return;
3348         }
3349         hdac_hp_switch_handler(devinfo);
3350         callout_reset(&sc->poll_jack, sc->poll_ival,
3351             hdac_jack_poll_callback, devinfo);
3352         hdac_unlock(sc);
3353 }
3354
3355 static int
3356 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3357 {
3358         struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3359         struct hdac_softc *sc = devinfo->codec->sc;
3360         struct hdac_widget *w, *cw;
3361         struct hdac_audio_ctl *ctl;
3362         uint32_t mask, recmask, id;
3363         int i, j, softpcmvol;
3364         nid_t cad;
3365
3366         hdac_lock(sc);
3367
3368         mask = 0;
3369         recmask = 0;
3370
3371         id = hdac_codec_id(devinfo);
3372         cad = devinfo->codec->cad;
3373         for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3374                 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
3375                     sc->pci_subvendor) && hdac_hp_switch[i].id == id))
3376                         continue;
3377                 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
3378                 if (w == NULL || w->enable == 0 || w->type !=
3379                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3380                         continue;
3381                 if (hdac_hp_switch[i].polling != 0)
3382                         callout_reset(&sc->poll_jack, 1,
3383                             hdac_jack_poll_callback, devinfo);
3384                 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
3385                         hdac_command(sc,
3386                             HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3387                             HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
3388                             HDAC_UNSOLTAG_EVENT_HP), cad);
3389                 else
3390                         continue;
3391                 hdac_hp_switch_handler(devinfo);
3392                 HDA_BOOTVERBOSE(
3393                         device_printf(sc->dev,
3394                             "HDA_DEBUG: Enabling headphone/speaker "
3395                             "audio routing switching:\n");
3396                         device_printf(sc->dev,
3397                             "HDA_DEBUG: \tindex=%d nid=%d "
3398                             "pci_subvendor=0x%08x "
3399                             "codec=0x%08x [%s]\n",
3400                             i, w->nid, sc->pci_subvendor, id,
3401                             (hdac_hp_switch[i].polling != 0) ? "POLL" :
3402                             "UNSOL");
3403                 );
3404                 break;
3405         }
3406         for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3407                 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3408                     sc->pci_subvendor) &&
3409                     hdac_eapd_switch[i].id == id))
3410                         continue;
3411                 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3412                 if (w == NULL || w->enable == 0)
3413                         break;
3414                 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3415                     w->param.eapdbtl == HDAC_INVALID)
3416                         break;
3417                 mask |= SOUND_MASK_OGAIN;
3418                 break;
3419         }
3420
3421         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3422                 w = hdac_widget_get(devinfo, i);
3423                 if (w == NULL || w->enable == 0)
3424                         continue;
3425                 mask |= w->ctlflags;
3426                 if (!(w->pflags & HDA_ADC_RECSEL))
3427                         continue;
3428                 for (j = 0; j < w->nconns; j++) {
3429                         cw = hdac_widget_get(devinfo, w->conns[j]);
3430                         if (cw == NULL || cw->enable == 0)
3431                                 continue;
3432                         recmask |= cw->ctlflags;
3433                 }
3434         }
3435
3436         if (!(mask & SOUND_MASK_PCM)) {
3437                 softpcmvol = 1;
3438                 mask |= SOUND_MASK_PCM;
3439         } else
3440                 softpcmvol = (devinfo->function.audio.quirks &
3441                     HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3442
3443         i = 0;
3444         ctl = NULL;
3445         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3446                 if (ctl->widget == NULL || ctl->enable == 0)
3447                         continue;
3448                 if (!(ctl->ossmask & SOUND_MASK_PCM))
3449                         continue;
3450                 if (ctl->step > 0)
3451                         break;
3452         }
3453
3454         if (softpcmvol == 1 || ctl == NULL) {
3455                 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3456                 HDA_BOOTVERBOSE(
3457                         device_printf(sc->dev,
3458                             "HDA_DEBUG: %s Soft PCM volume\n",
3459                             (softpcmvol == 1) ?
3460                             "Forcing" : "Enabling");
3461                 );
3462                 i = 0;
3463                 /*
3464                  * XXX Temporary quirk for STAC9220, until the parser
3465                  *     become smarter.
3466                  */
3467                 if (id == HDA_CODEC_STAC9220) {
3468                         mask |= SOUND_MASK_VOLUME;
3469                         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3470                             NULL) {
3471                                 if (ctl->widget == NULL || ctl->enable == 0)
3472                                         continue;
3473                                 if (ctl->widget->nid == 11 && ctl->index == 0) {
3474                                         ctl->ossmask = SOUND_MASK_VOLUME;
3475                                         ctl->ossval = 100 | (100 << 8);
3476                                 } else
3477                                         ctl->ossmask &= ~SOUND_MASK_VOLUME;
3478                         }
3479                 } else if (id == HDA_CODEC_STAC9221) {
3480                         mask |= SOUND_MASK_VOLUME;
3481                         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3482                             NULL) {
3483                                 if (ctl->widget == NULL)
3484                                         continue;
3485                                 if (ctl->widget->type ==
3486                                     HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3487                                     ctl->index == 0 && (ctl->widget->nid == 2 ||
3488                                     ctl->widget->enable != 0)) {
3489                                         ctl->enable = 1;
3490                                         ctl->ossmask = SOUND_MASK_VOLUME;
3491                                         ctl->ossval = 100 | (100 << 8);
3492                                 } else if (ctl->enable == 0)
3493                                         continue;
3494                                 else
3495                                         ctl->ossmask &= ~SOUND_MASK_VOLUME;
3496                         }
3497                 } else {
3498                         mix_setparentchild(m, SOUND_MIXER_VOLUME,
3499                             SOUND_MASK_PCM);
3500                         if (!(mask & SOUND_MASK_VOLUME))
3501                                 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3502                                     SOUND_MIXER_NONE);
3503                         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3504                             NULL) {
3505                                 if (ctl->widget == NULL || ctl->enable == 0)
3506                                         continue;
3507                                 if (!HDA_FLAG_MATCH(ctl->ossmask,
3508                                     SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3509                                         continue;
3510                                 if (!(ctl->mute == 1 && ctl->step == 0))
3511                                         ctl->enable = 0;
3512                         }
3513                 }
3514         }
3515
3516         recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3517             SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3518             SOUND_MASK_OGAIN);
3519         recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3520         mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3521
3522         mix_setrecdevs(m, recmask);
3523         mix_setdevs(m, mask);
3524
3525         hdac_unlock(sc);
3526
3527         return (0);
3528 }
3529
3530 static int
3531 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3532                                         unsigned left, unsigned right)
3533 {
3534         struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3535         struct hdac_softc *sc = devinfo->codec->sc;
3536         struct hdac_widget *w;
3537         struct hdac_audio_ctl *ctl;
3538         uint32_t id, mute;
3539         int lvol, rvol, mlvol, mrvol;
3540         int i = 0;
3541
3542         hdac_lock(sc);
3543         if (dev == SOUND_MIXER_OGAIN) {
3544                 uint32_t orig;
3545                 /*if (left != right || !(left == 0 || left == 1)) {
3546                         hdac_unlock(sc);
3547                         return (-1);
3548                 }*/
3549                 id = hdac_codec_id(devinfo);
3550                 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3551                         if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3552                             sc->pci_subvendor) &&
3553                             hdac_eapd_switch[i].id == id)
3554                                 break;
3555                 }
3556                 if (i >= HDAC_EAPD_SWITCH_LEN) {
3557                         hdac_unlock(sc);
3558                         return (-1);
3559                 }
3560                 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3561                 if (w == NULL ||
3562                     w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3563                     w->param.eapdbtl == HDAC_INVALID) {
3564                         hdac_unlock(sc);
3565                         return (-1);
3566                 }
3567                 orig = w->param.eapdbtl;
3568                 if (left == 0)
3569                         w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3570                 else
3571                         w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3572                 if (orig != w->param.eapdbtl) {
3573                         uint32_t val;
3574
3575                         if (hdac_eapd_switch[i].hp_switch != 0)
3576                                 hdac_hp_switch_handler(devinfo);
3577                         val = w->param.eapdbtl;
3578                         if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3579                                 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3580                         hdac_command(sc,
3581                             HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3582                             w->nid, val), devinfo->codec->cad);
3583                 }
3584                 hdac_unlock(sc);
3585                 return (left | (left << 8));
3586         }
3587         if (dev == SOUND_MIXER_VOLUME)
3588                 devinfo->function.audio.mvol = left | (right << 8);
3589
3590         mlvol = devinfo->function.audio.mvol & 0x7f;
3591         mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3592         lvol = 0;
3593         rvol = 0;
3594
3595         i = 0;
3596         while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3597                 if (ctl->widget == NULL || ctl->enable == 0 ||
3598                     !(ctl->ossmask & (1 << dev)))
3599                         continue;
3600                 switch (dev) {
3601                 case SOUND_MIXER_VOLUME:
3602                         lvol = ((ctl->ossval & 0x7f) * left) / 100;
3603                         lvol = (lvol * ctl->step) / 100;
3604                         rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3605                         rvol = (rvol * ctl->step) / 100;
3606                         break;
3607                 default:
3608                         if (ctl->ossmask & SOUND_MASK_VOLUME) {
3609                                 lvol = (left * mlvol) / 100;
3610                                 lvol = (lvol * ctl->step) / 100;
3611                                 rvol = (right * mrvol) / 100;
3612                                 rvol = (rvol * ctl->step) / 100;
3613                         } else {
3614                                 lvol = (left * ctl->step) / 100;
3615                                 rvol = (right * ctl->step) / 100;
3616                         }
3617                         ctl->ossval = left | (right << 8);
3618                         break;
3619                 }
3620                 mute = 0;
3621                 if (ctl->step < 1) {
3622                         mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3623                             (ctl->muted & HDA_AMP_MUTE_LEFT);
3624                         mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3625                             (ctl->muted & HDA_AMP_MUTE_RIGHT);
3626                 } else {
3627                         mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3628                             (ctl->muted & HDA_AMP_MUTE_LEFT);
3629                         mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3630                             (ctl->muted & HDA_AMP_MUTE_RIGHT);
3631                 }
3632                 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3633         }
3634         hdac_unlock(sc);
3635
3636         return (left | (right << 8));
3637 }
3638
3639 static int
3640 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3641 {
3642         struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3643         struct hdac_widget *w, *cw;
3644         struct hdac_softc *sc = devinfo->codec->sc;
3645         uint32_t ret = src, target;
3646         int i, j;
3647
3648         target = 0;
3649         for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3650                 if (src & (1 << i)) {
3651                         target = 1 << i;
3652                         break;
3653                 }
3654         }
3655
3656         hdac_lock(sc);
3657
3658         for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3659                 w = hdac_widget_get(devinfo, i);
3660                 if (w == NULL || w->enable == 0)
3661                         continue;
3662                 if (!(w->pflags & HDA_ADC_RECSEL))
3663                         continue;
3664                 for (j = 0; j < w->nconns; j++) {
3665                         cw = hdac_widget_get(devinfo, w->conns[j]);
3666                         if (cw == NULL || cw->enable == 0)
3667                                 continue;
3668                         if ((target == SOUND_MASK_VOLUME &&
3669                             cw->type !=
3670                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3671                             (target != SOUND_MASK_VOLUME &&
3672                             cw->type ==
3673                             HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3674                                 continue;
3675                         if (cw->ctlflags & target) {
3676                                 if (!(w->pflags & HDA_ADC_LOCKED))
3677                                         hdac_widget_connection_select(w, j);
3678                                 ret = target;
3679                                 j += w->nconns;
3680                         }
3681                 }
3682         }
3683
3684         hdac_unlock(sc);
3685
3686         return (ret);
3687 }
3688
3689 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3690         KOBJMETHOD(mixer_init,          hdac_audio_ctl_ossmixer_init),
3691         KOBJMETHOD(mixer_set,           hdac_audio_ctl_ossmixer_set),
3692         KOBJMETHOD(mixer_setrecsrc,     hdac_audio_ctl_ossmixer_setrecsrc),
3693         { 0, 0 }
3694 };
3695 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3696
3697 static void
3698 hdac_unsolq_task(void *context, int pending)
3699 {
3700         struct hdac_softc *sc;
3701
3702         sc = (struct hdac_softc *)context;
3703
3704         hdac_lock(sc);
3705         hdac_unsolq_flush(sc);
3706         hdac_unlock(sc);
3707 }
3708
3709 /****************************************************************************
3710  * int hdac_attach(device_t)
3711  *
3712  * Attach the device into the kernel. Interrupts usually won't be enabled
3713  * when this function is called. Setup everything that doesn't require
3714  * interrupts and defer probing of codecs until interrupts are enabled.
3715  ****************************************************************************/
3716 static int
3717 hdac_attach(device_t dev)
3718 {
3719         struct hdac_softc *sc;
3720         int result;
3721         int i;
3722         uint16_t vendor;
3723         uint8_t v;
3724
3725         sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
3726         sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
3727         sc->dev = dev;
3728         sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3729         sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
3730         vendor = pci_get_vendor(dev);
3731
3732         if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3733                 /* Screw nx6325 - subdevice/subvendor swapped */
3734                 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3735         }
3736
3737         callout_init(&sc->poll_hda);
3738         callout_init(&sc->poll_hdac);
3739         callout_init(&sc->poll_jack);
3740
3741         TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
3742
3743         sc->poll_ticks = 1;
3744         sc->poll_ival = HDAC_POLL_INTERVAL;
3745         if (resource_int_value(device_get_name(dev),
3746             device_get_unit(dev), "polling", &i) == 0 && i != 0)
3747                 sc->polling = 1;
3748         else
3749                 sc->polling = 0;
3750
3751         sc->chan_size = pcm_getbuffersize(dev,
3752             HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3753
3754         if (resource_int_value(device_get_name(dev),
3755             device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3756                 i &= HDA_BLK_ALIGN;
3757                 if (i < HDA_BLK_MIN)
3758                         i = HDA_BLK_MIN;
3759                 sc->chan_blkcnt = sc->chan_size / i;
3760                 i = 0;
3761                 while (sc->chan_blkcnt >> i)
3762                         i++;
3763                 sc->chan_blkcnt = 1 << (i - 1);
3764                 if (sc->chan_blkcnt < HDA_BDL_MIN)
3765                         sc->chan_blkcnt = HDA_BDL_MIN;
3766                 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3767                         sc->chan_blkcnt = HDA_BDL_MAX;
3768         } else
3769                 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3770
3771         result = bus_dma_tag_create(NULL,       /* parent */
3772             HDAC_DMA_ALIGNMENT,                 /* alignment */
3773             0,                                  /* boundary */
3774             BUS_SPACE_MAXADDR_32BIT,            /* lowaddr */
3775             BUS_SPACE_MAXADDR,                  /* highaddr */
3776             NULL,                               /* filtfunc */
3777             NULL,                               /* fistfuncarg */
3778             sc->chan_size,                      /* maxsize */
3779             1,                                  /* nsegments */
3780             sc->chan_size,                      /* maxsegsz */
3781             0,                                  /* flags */
3782             &sc->chan_dmat);                    /* dmat */
3783         if (result != 0) {
3784                 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
3785                      __func__, result);
3786                 snd_mtxfree(sc->lock);
3787                 kfree(sc, M_DEVBUF);
3788                 return (ENXIO);
3789         }
3790
3791
3792         sc->hdabus = NULL;
3793         for (i = 0; i < HDAC_CODEC_MAX; i++)
3794                 sc->codecs[i] = NULL;
3795
3796         pci_enable_busmaster(dev);
3797
3798         if (vendor == INTEL_VENDORID) {
3799                 /* TCSEL -> TC0 */
3800                 v = pci_read_config(dev, 0x44, 1);
3801                 pci_write_config(dev, 0x44, v & 0xf8, 1);
3802                 HDA_BOOTVERBOSE(
3803                         device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3804                             pci_read_config(dev, 0x44, 1));
3805                 );
3806         }
3807
3808 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3809         sc->flags |= HDAC_F_DMA_NOCACHE;
3810
3811         if (resource_int_value(device_get_name(dev),
3812             device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3813 #else
3814         sc->flags &= ~HDAC_F_DMA_NOCACHE;
3815 #endif
3816                 /*
3817                  * Try to enable PCIe snoop to avoid messing around with
3818                  * uncacheable DMA attribute. Since PCIe snoop register
3819                  * config is pretty much vendor specific, there are no
3820                  * general solutions on how to enable it, forcing us (even
3821                  * Microsoft) to enable uncacheable or write combined DMA
3822                  * by default.
3823                  *
3824                  * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3825                  */
3826                 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3827                         if (hdac_pcie_snoop[i].vendor != vendor)
3828                                 continue;
3829                         sc->flags &= ~HDAC_F_DMA_NOCACHE;
3830                         if (hdac_pcie_snoop[i].reg == 0x00)
3831                                 break;
3832                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3833                         if ((v & hdac_pcie_snoop[i].enable) ==
3834                             hdac_pcie_snoop[i].enable)
3835                                 break;
3836                         v &= hdac_pcie_snoop[i].mask;
3837                         v |= hdac_pcie_snoop[i].enable;
3838                         pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
3839    &