1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
38 * Driver for the Broadcom BCR5400 1000baseT PHY. Speed is always
39 * 1000mbps; all we need to negotiate here is full or half duplex.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/socket.h>
47 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_media.h>
52 #include <net/if_arp.h>
57 #include "brgphyreg.h"
59 #include "miibus_if.h"
61 static int brgphy_probe(device_t);
62 static int brgphy_attach(device_t);
64 static const struct mii_phydesc brgphys[] = {
65 MII_PHYDESC(xxBROADCOM, BCM5400),
66 MII_PHYDESC(xxBROADCOM, BCM5401),
67 MII_PHYDESC(xxBROADCOM, BCM5411),
68 MII_PHYDESC(xxBROADCOM, BCM5421),
69 MII_PHYDESC(xxBROADCOM, BCM54K2),
70 MII_PHYDESC(xxBROADCOM, BCM5461),
71 MII_PHYDESC(xxBROADCOM, BCM5462),
72 MII_PHYDESC(xxBROADCOM, BCM5464),
74 MII_PHYDESC(xxBROADCOM, BCM5701),
75 MII_PHYDESC(xxBROADCOM, BCM5703),
76 MII_PHYDESC(xxBROADCOM, BCM5704),
77 MII_PHYDESC(xxBROADCOM, BCM5705),
78 MII_PHYDESC(xxBROADCOM, BCM5714),
79 MII_PHYDESC(xxBROADCOM, BCM5750),
80 MII_PHYDESC(xxBROADCOM, BCM5752),
81 MII_PHYDESC(xxBROADCOM, BCM5780),
83 MII_PHYDESC(xxBROADCOM2,BCM54XX),
84 MII_PHYDESC(xxBROADCOM2,BCM5481),
85 MII_PHYDESC(xxBROADCOM2,BCM5482),
86 MII_PHYDESC(xxBROADCOM2,BCM5722),
87 MII_PHYDESC(xxBROADCOM2,BCM5755),
88 MII_PHYDESC(xxBROADCOM2,BCM5761),
89 MII_PHYDESC(xxBROADCOM2,BCM5784),
90 MII_PHYDESC(xxBROADCOM2,BCM5787),
92 MII_PHYDESC(xxBROADCOM, BCM5706C),
93 MII_PHYDESC(xxBROADCOM, BCM5708C),
94 MII_PHYDESC(xxBROADCOM2, BCM5709CAX),
95 MII_PHYDESC(xxBROADCOM2, BCM5709C),
97 MII_PHYDESC(xxBROADCOM3, BCM54640),
98 MII_PHYDESC(xxBROADCOM3, BCM54680),
99 MII_PHYDESC(xxBROADCOM3, BCM54685),
100 MII_PHYDESC(xxBROADCOM3, BCM54880),
101 MII_PHYDESC(xxBROADCOM3, BCM54881),
102 MII_PHYDESC(xxBROADCOM3, BCM5719C),
103 MII_PHYDESC(xxBROADCOM3, BCM5718C),
104 MII_PHYDESC(xxBROADCOM3, BCM5720C),
105 MII_PHYDESC(xxBROADCOM3, BCM57765),
106 MII_PHYDESC(xxBROADCOM3, BCM57780),
108 MII_PHYDESC(BROADCOM2, BCM5906),
113 static device_method_t brgphy_methods[] = {
114 /* device interface */
115 DEVMETHOD(device_probe, brgphy_probe),
116 DEVMETHOD(device_attach, brgphy_attach),
117 DEVMETHOD(device_detach, ukphy_detach),
118 DEVMETHOD(device_shutdown, bus_generic_shutdown),
122 static devclass_t brgphy_devclass;
124 static driver_t brgphy_driver = {
127 sizeof(struct mii_softc)
130 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, NULL, NULL);
132 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
133 static void brgphy_status(struct mii_softc *);
134 static void brgphy_mii_phy_auto(struct mii_softc *);
135 static void brgphy_reset(struct mii_softc *);
136 static void brgphy_loop(struct mii_softc *);
138 static void brgphy_bcm5401_dspcode(struct mii_softc *);
139 static void brgphy_bcm5411_dspcode(struct mii_softc *);
140 static void brgphy_bcm5421_dspcode(struct mii_softc *);
141 static void brgphy_bcm54k2_dspcode(struct mii_softc *);
143 static void brgphy_adc_bug(struct mii_softc *);
144 static void brgphy_5704_a0_bug(struct mii_softc *);
145 static void brgphy_ber_bug(struct mii_softc *);
146 static void brgphy_crc_bug(struct mii_softc *);
148 static void brgphy_disable_early_dac(struct mii_softc *);
149 static void brgphy_jumbo_settings(struct mii_softc *, u_long);
150 static void brgphy_eth_wirespeed(struct mii_softc *);
153 brgphy_probe(device_t dev)
155 struct mii_attach_args *ma = device_get_ivars(dev);
156 const struct mii_phydesc *mpd;
158 mpd = mii_phy_match(ma, brgphys);
160 device_set_desc(dev, mpd->mpd_name);
167 brgphy_attach(device_t dev)
169 struct mii_softc *sc;
170 struct mii_attach_args *ma;
171 struct mii_data *mii;
173 sc = device_get_softc(dev);
174 ma = device_get_ivars(dev);
175 mii_softc_init(sc, ma);
176 sc->mii_dev = device_get_parent(dev);
177 mii = device_get_softc(sc->mii_dev);
178 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
180 sc->mii_inst = mii->mii_instance;
181 sc->mii_service = brgphy_service;
182 sc->mii_reset = brgphy_reset;
185 sc->mii_flags |= MIIF_NOISOLATE;
190 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
192 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
195 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
201 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
202 if (sc->mii_capabilities & BMSR_EXTSTAT)
203 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
205 device_printf(dev, " ");
206 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
207 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
208 mii_phy_add_media(sc);
210 kprintf("no media present");
213 MIIBUS_MEDIAINIT(sc->mii_dev);
218 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
220 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
226 * If we're not polling our PHY instance, just return.
228 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
234 * If the media indicates a different PHY instance,
237 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
238 reg = PHY_READ(sc, MII_BMCR);
239 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
244 * If the interface is not up, don't do anything.
246 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
249 brgphy_reset(sc); /* XXX hardware bug work-around */
251 switch (IFM_SUBTYPE(ife->ifm_media)) {
255 * If we're already in auto mode, just return.
257 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
260 brgphy_mii_phy_auto(sc);
263 speed = BRGPHY_S1000;
272 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
273 speed |= BRGPHY_BMCR_FDX;
274 gig = BRGPHY_1000CTL_AFD;
276 gig = BRGPHY_1000CTL_AHD;
279 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
280 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
281 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
283 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
286 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
287 PHY_WRITE(sc, BRGPHY_MII_BMCR,
288 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
290 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
294 * When settning the link manually, one side must
295 * be the master and the other the slave. However
296 * ifmedia doesn't give us a good way to specify
297 * this, so we fake it by using one of the LINK
298 * flags. If LINK0 is set, we program the PHY to
299 * be a master, otherwise it's a slave.
301 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
302 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
303 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
305 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
306 gig|BRGPHY_1000CTL_MSE);
311 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
322 * If we're not currently selected, just return.
324 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
328 * Is the interface even up?
330 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
334 * Only used for autonegotiation.
336 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
340 * Check to see if we have link. If we do, we don't
341 * need to restart the autonegotiation process. Read
342 * the BMSR twice in case it's latched.
344 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
345 if (reg & BMSR_LINK) {
351 * Only retry autonegotiation every 5 seconds.
353 if (++sc->mii_ticks <= sc->mii_anegticks)
357 brgphy_mii_phy_auto(sc);
361 /* Update the media status. */
365 * Callback if something changed. Note that we need to poke
366 * the DSP on the Broadcom PHYs if the media changes.
368 if (sc->mii_media_active != mii->mii_media_active ||
369 sc->mii_media_status != mii->mii_media_status ||
370 cmd == MII_MEDIACHG) {
371 switch (sc->mii_model) {
372 case MII_MODEL_xxBROADCOM_BCM5400:
373 brgphy_bcm5401_dspcode(sc);
375 case MII_MODEL_xxBROADCOM_BCM5401:
376 if (sc->mii_rev == 1 || sc->mii_rev == 3)
377 brgphy_bcm5401_dspcode(sc);
379 case MII_MODEL_xxBROADCOM_BCM5411:
380 brgphy_bcm5411_dspcode(sc);
384 mii_phy_update(sc, cmd);
389 brgphy_status(struct mii_softc *sc)
391 struct mii_data *mii = sc->mii_pdata;
394 mii->mii_media_status = IFM_AVALID;
395 mii->mii_media_active = IFM_ETHER;
397 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
398 if (bmsr & BRGPHY_BMSR_LINK)
399 mii->mii_media_status |= IFM_ACTIVE;
401 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
402 if (bmcr & BRGPHY_BMCR_LOOP)
403 mii->mii_media_active |= IFM_LOOP;
405 if (bmcr & BRGPHY_BMCR_AUTOEN) {
408 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
409 /* Erg, still trying, I guess... */
410 mii->mii_media_active |= IFM_NONE;
414 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS);
416 switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
417 case BRGPHY_RES_1000FD:
418 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
420 case BRGPHY_RES_1000HD:
421 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
423 case BRGPHY_RES_100FD:
424 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
426 case BRGPHY_RES_100T4:
427 mii->mii_media_active |= IFM_100_T4;
429 case BRGPHY_RES_100HD:
430 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
432 case BRGPHY_RES_10FD:
433 mii->mii_media_active |= IFM_10_T | IFM_FDX;
435 case BRGPHY_RES_10HD:
436 mii->mii_media_active |= IFM_10_T | IFM_HDX;
439 if (sc->mii_model == MII_MODEL_BROADCOM2_BCM5906) {
440 mii->mii_media_active |= (auxsts &
441 BRGPHY_RES_100) ? IFM_100_TX : IFM_10_T;
442 mii->mii_media_active |= (auxsts &
443 BRGPHY_RES_FULL) ? IFM_FDX : IFM_HDX;
446 mii->mii_media_active |= IFM_NONE;
450 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media;
456 brgphy_mii_phy_auto(struct mii_softc *sc)
462 PHY_WRITE(sc, BRGPHY_MII_ANAR,
463 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
466 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
467 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
468 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
469 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
470 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
473 PHY_WRITE(sc, BRGPHY_MII_BMCR,
474 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
475 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
479 brgphy_loop(struct mii_softc *sc)
484 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
485 for (i = 0; i < 15000; i++) {
486 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
487 if (!(bmsr & BRGPHY_BMSR_LINK))
494 brgphy_reset(struct mii_softc *sc)
498 switch (sc->mii_model) {
499 case MII_MODEL_xxBROADCOM_BCM5400:
500 brgphy_bcm5401_dspcode(sc);
502 case MII_MODEL_xxBROADCOM_BCM5401:
503 if (sc->mii_rev == 1 || sc->mii_rev == 3)
504 brgphy_bcm5401_dspcode(sc);
506 case MII_MODEL_xxBROADCOM_BCM5411:
507 brgphy_bcm5411_dspcode(sc);
509 case MII_MODEL_xxBROADCOM_BCM5421:
510 brgphy_bcm5421_dspcode(sc);
512 case MII_MODEL_xxBROADCOM_BCM54K2:
513 brgphy_bcm54k2_dspcode(sc);
517 if (sc->mii_privtag != MII_PRIVTAG_BRGPHY)
520 if (sc->mii_priv & BRGPHY_FLAG_ADC_BUG)
522 if (sc->mii_priv & BRGPHY_FLAG_5704_A0)
523 brgphy_5704_a0_bug(sc);
524 if (sc->mii_priv & BRGPHY_FLAG_BER_BUG) {
526 } else if (sc->mii_priv & BRGPHY_FLAG_JITTER_BUG) {
527 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
528 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
530 if (sc->mii_priv & BRGPHY_FLAG_ADJUST_TRIM) {
531 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
532 PHY_WRITE(sc, BRGPHY_TEST1,
533 BRGPHY_TEST1_TRIM_EN | 0x4);
535 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
538 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
540 if (sc->mii_priv & BRGPHY_FLAG_CRC_BUG)
542 if (sc->mii_priv & BRGPHY_FLAG_NO_EARLYDAC)
543 brgphy_disable_early_dac(sc);
545 /* Set Jumbo frame settings in the PHY. */
546 brgphy_jumbo_settings(sc, sc->mii_pdata->mii_ifp->if_mtu);
548 /* Adjust output voltage */
549 if (sc->mii_priv & BRGPHY_FLAG_5906)
550 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
552 /* Enable Ethernet@Wirespeed */
553 if (sc->mii_priv & BRGPHY_FLAG_WIRESPEED)
554 brgphy_eth_wirespeed(sc);
556 /* Enable Link LED on Dell boxes */
557 if (sc->mii_priv & BRGPHY_FLAG_NO_3LED) {
558 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
559 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
560 ~BRGPHY_PHY_EXTCTL_3_LED);
564 /* Turn off tap power management on 5401. */
566 brgphy_bcm5401_dspcode(struct mii_softc *sc)
568 static const struct {
572 { BRGPHY_MII_AUXCTL, 0x0c20 },
573 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
574 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
575 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
576 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
577 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
578 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
579 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
580 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
581 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
582 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
587 for (i = 0; dspcode[i].reg != 0; i++)
588 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
592 /* Setting some undocumented voltage */
594 brgphy_bcm5411_dspcode(struct mii_softc *sc)
596 static const struct {
607 for (i = 0; dspcode[i].reg != 0; i++)
608 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
612 brgphy_bcm5421_dspcode(struct mii_softc *sc)
616 /* Set Class A mode */
617 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
618 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
619 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
621 /* Set FFE gamma override to -0.125 */
622 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
623 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
624 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
625 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
626 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
627 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
631 brgphy_bcm54k2_dspcode(struct mii_softc *sc)
633 static const struct {
643 for (i = 0; dspcode[i].reg != 0; i++)
644 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
648 brgphy_adc_bug(struct mii_softc *sc)
650 static const struct {
654 { BRGPHY_MII_AUXCTL, 0x0c00 },
655 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
656 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
657 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
658 { BRGPHY_MII_DSP_RW_PORT, 0x0323 },
659 { BRGPHY_MII_AUXCTL, 0x0400 },
664 for (i = 0; dspcode[i].reg != 0; i++)
665 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
669 brgphy_5704_a0_bug(struct mii_softc *sc)
671 static const struct {
681 for (i = 0; dspcode[i].reg != 0; i++)
682 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
686 brgphy_ber_bug(struct mii_softc *sc)
688 static const struct {
692 { BRGPHY_MII_AUXCTL, 0x0c00 },
693 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
694 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
695 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
696 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
697 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
698 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
699 { BRGPHY_MII_AUXCTL, 0x0400 },
704 for (i = 0; dspcode[i].reg != 0; i++)
705 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
709 brgphy_crc_bug(struct mii_softc *sc)
711 static const struct {
715 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
723 for (i = 0; dspcode[i].reg != 0; i++)
724 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
728 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
732 /* Set or clear jumbo frame settings in the PHY. */
733 if (mtu > ETHER_MAX_LEN) {
734 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
735 /* BCM5401 PHY cannot read-modify-write. */
736 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
738 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
739 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
740 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
741 val | BRGPHY_AUXCTL_LONG_PKT);
744 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
745 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
746 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
748 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
749 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
750 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
751 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
753 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
754 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
755 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
760 brgphy_eth_wirespeed(struct mii_softc *sc)
764 /* Enable Ethernet@Wirespeed */
765 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
766 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
767 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4)));
771 brgphy_disable_early_dac(struct mii_softc *sc)
775 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
776 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
778 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);