2 **********************************************************************
3 * emu10k1.h, derived from 8010.h
4 * Copyright 1999, 2000 Creative Labs, Inc.
6 **********************************************************************
8 * Date Author Summary of changes
9 * ---- ------ ------------------
10 * October 20, 1999 Bertrand Lee base code release
11 * November 2, 1999 Alan Cox Cleaned of 8bit chars, DOS
13 * December 8, 1999 Jon Taylor Added lots of new register info
14 * February 10, 2003 Orlando Bassotto Added Audigy registers
15 * and opcode macros from
16 * ALSA project emu10k1.h.
19 **********************************************************************
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public
32 * License along with this program; if not, write to the Free
33 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
37 **********************************************************************
38 * $FreeBSD: src/sys/gnu/dev/sound/pci/emu10k1.h,v 1.2.2.3 2001/08/01 03:41:09 cg Exp $
39 * $DragonFly: src/sys/dev/sound/pci/gnu/emu10k1.h,v 1.3 2004/01/06 16:07:41 asmodai Exp $
46 /* ------------------- DEFINES -------------------- */
48 #define EMUPAGESIZE 4096 /* don't change */
49 #define MAXREQVOICES 8
50 #define MAXPAGES (32768 * 64 / EMUPAGESIZE) /* WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE */
53 #define NUM_G 64 /* use all channels */
57 #define TMEMSIZE 256*1024
60 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
62 /************************************************************************************************/
63 /* PCI function 0 registers, address = <val> + PCIBASE0 */
64 /************************************************************************************************/
66 #define PTR 0x00 /* Indexed register set pointer register */
67 /* NOTE: The CHANNELNUM and ADDRESS words can */
68 /* be modified independently of each other. */
69 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
70 /* channel number of the register to be */
71 /* accessed. For non per-channel registers the */
72 /* value should be set to zero. */
73 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
74 #define A_PTR_ADDRESS_MASK 0x0fff0000 /* Audigy register index */
76 #define DATA 0x04 /* Indexed register set data register */
78 #define IPR 0x08 /* Global interrupt pending register */
79 /* Clear pending interrupts by writing a 1 to */
80 /* the relevant bits and zero to the other bits */
82 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
83 #define A_IPR_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
84 #define A_IPR_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
86 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
87 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
88 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
89 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
90 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
91 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
92 #define IPR_MUTE 0x00040000 /* Mute button pressed */
93 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
94 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
95 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
96 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
97 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
98 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
99 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
100 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
101 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
102 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
103 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
104 #define IPR_CHANNELLOOP 0x00000040 /* One or more channel loop interrupts pending */
105 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
106 /* Highest set channel in CLIPL or CLIPH. When */
107 /* IP is written with CL set, the bit in CLIPL */
108 /* or CLIPH corresponding to the CIN value */
109 /* written will be cleared. */
110 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU2) */
111 #define A_IPR_MIDITRANSBUFEMPTY1 IPR_MIDITRANSBUFEMPTY /* MIDI UART transmit buffer empty */
112 #define A_IPR_MIDIRECVBUFEMPTY1 IPR_MIDIRECVBUFEMPTY /* MIDI UART receive buffer empty */
115 #define INTE 0x0c /* Interrupt enable register */
116 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
117 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
118 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
119 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
120 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
121 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
122 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
123 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
124 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
125 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
126 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
127 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
128 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
129 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
130 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
131 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
132 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
133 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
135 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
136 /* NOTE: There is no reason to use this under */
137 /* Linux, and it will cause odd hardware */
138 /* behavior and possibly random segfaults and */
139 /* lockups if enabled. */
141 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
142 #define A_INTE_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
143 #define A_INTE_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
146 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
147 /* NOTE: This bit must always be enabled */
148 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
149 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
150 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
151 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
152 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
153 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
154 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
155 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
156 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
157 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
158 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
159 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
160 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
162 /* The next two interrupts are for the midi port on the Audigy (A_MPU2) */
163 #define A_INTE_MIDITXENABLE1 INTE_MIDITXENABLE
164 #define A_INTE_MIDIRXENABLE1 INTE_MIDIRXENABLE
166 #define WC 0x10 /* Wall Clock register */
167 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
168 #define WC_SAMPLECOUNTER 0x14060010
169 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
170 /* NOTE: Each channel takes 1/64th of a sample */
171 /* period to be serviced. */
173 #define HCFG 0x14 /* Hardware config register */
174 /* NOTE: There is no reason to use the legacy */
175 /* SoundBlaster emulation stuff described below */
176 /* under Linux, and all kinds of weird hardware */
177 /* behavior can result if you try. Don't. */
178 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
179 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
180 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
181 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
182 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
183 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
184 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
185 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
186 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
187 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
188 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
189 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
190 /* NOTE: The rest of the bits in this register */
191 /* _are_ relevant under Linux. */
192 #define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
193 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
194 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
195 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
196 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
198 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
199 #define HCFG_GPOUT0 0x00001000 /* set to enable digital out on 5.1 cards */
200 #define HCFG_GPOUT1 0x00000800 /* External pin (IR) */
201 #define HCFG_GPOUT2 0x00000400 /* External pin (IR) */
203 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
204 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
205 /* 1 = Force all 3 async digital inputs to use */
206 /* the same async sample rate tracker (ZVIDEO) */
207 #define HCFG_AC3ENABLE_MASK 0x0x0000e0 /* AC3 async input control - Not implemented */
208 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
209 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
210 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
211 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
212 /* will automatically mute their output when */
213 /* they are not rate-locked to the external */
214 /* async audio source */
215 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
216 /* NOTE: This should generally never be used. */
217 #define HCFG_LOCKTANKCACHE 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
218 /* NOTE: This should generally never be used. */
219 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
220 /* NOTE: This is a 'cheap' way to implement a */
221 /* master mute function on the mute button, and */
222 /* in general should not be used unless a more */
223 /* sophisticated master mute function has not */
225 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
226 /* Should be set to 1 when the EMU10K1 is */
227 /* completely initialized. */
229 /* For Audigy, MPU port move to 0x70-0x74 ptr register */
231 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
233 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
234 #define MUCMD_RESET 0xff /* RESET command */
235 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
236 /* NOTE: All other commands are ignored */
238 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
239 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
240 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
242 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
243 #define A_IOCFG_GPOUT_MASK 0x00ff
244 #define A_IOCFG_GPOUT_D 0x04 /* Digital Output */
245 #define A_IOCFG_GPOUT_A 0x40 /* Analog Output */
246 #define A_IOCFG_GPOUT_AD (A_IOCFG_GPOUT_A|A_IOCFG_GPOUT_D)
247 #define A_IOCFG_GPINPUT_MASK 0xff00
249 #define TIMER 0x1a /* Timer terminal count register (16-bit) */
250 /* NOTE: After the rate is changed, a maximum */
251 /* of 1024 sample periods should be allowed */
252 /* before the new rate is guaranteed accurate. */
253 #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
254 /* 0 == 1024 periods, [1..4] are not useful */
255 #define TIMER_RATE 0x0a00001a
257 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
259 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
260 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
261 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
263 /************************************************************************************************/
264 /* PCI function 1 registers, address = <val> + PCIBASE1 */
265 /************************************************************************************************/
267 #define JOYSTICK1 0x00 /* Analog joystick port register */
268 #define JOYSTICK2 0x01 /* Analog joystick port register */
269 #define JOYSTICK3 0x02 /* Analog joystick port register */
270 #define JOYSTICK4 0x03 /* Analog joystick port register */
271 #define JOYSTICK5 0x04 /* Analog joystick port register */
272 #define JOYSTICK6 0x05 /* Analog joystick port register */
273 #define JOYSTICK7 0x06 /* Analog joystick port register */
274 #define JOYSTICK8 0x07 /* Analog joystick port register */
276 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
277 /* When reading, use these bitfields: */
278 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
279 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
282 /********************************************************************************************************/
283 /* AC97 pointer-offset register set, accessed through the AC97ADDRESS and AC97DATA registers */
284 /********************************************************************************************************/
286 #define AC97_RESET 0x00
287 #define AC97_MASTERVOLUME 0x02 /* Master volume */
288 #define AC97_HEADPHONEVOLUME 0x04 /* Headphone volume */
289 #define AC97_MASTERVOLUMEMONO 0x06 /* Mast volume mono */
290 #define AC97_MASTERTONE 0x08
291 #define AC97_PCBEEPVOLUME 0x0a /* PC speaker system beep volume */
292 #define AC97_PHONEVOLUME 0x0c
293 #define AC97_MICVOLUME 0x0e
294 #define AC97_LINEINVOLUME 0x10
295 #define AC97_CDVOLUME 0x12
296 #define AC97_VIDEOVOLUME 0x14
297 #define AC97_AUXVOLUME 0x16
298 #define AC97_PCMOUTVOLUME 0x18
299 #define AC97_RECORDSELECT 0x1a
300 #define AC97_RECORDGAIN 0x1c
301 #define AC97_RECORDGAINMIC 0x1e
302 #define AC97_GENERALPUPOSE 0x20
303 #define AC97_3DCONTROL 0x22
304 #define AC97_MODEMRATE 0x24
305 #define AC97_POWERDOWN 0x26
306 #define AC97_VENDORID1 0x7c
307 #define AC97_VENDORID2 0x7e
308 #define AC97_ZVIDEOVOLUME 0xec
309 #define AC97_AC3VOLUME 0xed
311 /********************************************************************************************************/
312 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
313 /********************************************************************************************************/
315 #define CPF 0x00 /* Current pitch and fraction register */
316 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
317 #define CPF_CURRENTPITCH 0x10100000
318 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
319 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
320 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
322 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
323 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
324 #define PTRX_PITCHTARGET 0x10100001
325 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
326 #define PTRX_FXSENDAMOUNT_A 0x08080001
327 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
328 #define PTRX_FXSENDAMOUNT_B 0x08000001
330 #define CVCF 0x02 /* Current volume and filter cutoff register */
331 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
332 #define CVCF_CURRENTVOL 0x10100002
333 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
334 #define CVCF_CURRENTFILTER 0x10000002
336 #define VTFT 0x03 /* Volume target and filter cutoff target register */
337 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
338 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
340 #define Z1 0x05 /* Filter delay memory 1 register */
342 #define Z2 0x04 /* Filter delay memory 2 register */
344 #define PSST 0x06 /* Send C amount and loop start address register */
345 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
347 #define PSST_FXSENDAMOUNT_C 0x08180006
349 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
350 #define PSST_LOOPSTARTADDR 0x18000006
352 #define DSL 0x07 /* Send D amount and loop start address register */
353 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
355 #define DSL_FXSENDAMOUNT_D 0x08180007
357 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
358 #define DSL_LOOPENDADDR 0x18000007
360 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
361 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
362 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
363 /* 1 == full band, 7 == lowpass */
364 /* ROM 0 is used when pitch shifting downward or less */
365 /* then 3 semitones upward. Increasingly higher ROM */
366 /* numbers are used, typically in steps of 3 semitones, */
367 /* as upward pitch shifting is performed. */
368 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
369 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
370 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
371 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
372 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
373 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
374 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
375 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
376 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
377 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
378 #define CCCA_CURRADDR 0x18000008
380 #define CCR 0x09 /* Cache control register */
381 #define CCR_CACHEINVALIDSIZE 0x07190009
382 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
383 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
384 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
385 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
386 #define CCR_READADDRESS 0x06100009
387 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
388 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
389 /* NOTE: This is valid only if CACHELOOPFLAG is set */
390 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
391 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
393 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
394 /* NOTE: This register is normally not used */
395 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
397 #define FXRT 0x0b /* Effects send routing register */
398 /* NOTE: It is illegal to assign the same routing to */
399 /* two effects sends. */
400 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
401 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
402 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
403 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
405 #define MAPA 0x0c /* Cache map A */
407 #define MAPB 0x0d /* Cache map B */
409 #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
410 #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
412 #define ENVVOL 0x10 /* Volume envelope register */
413 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
414 /* 0x8000-n == 666*n usec delay */
416 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
417 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
418 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
419 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
420 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
422 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
423 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
424 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
425 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
426 /* this channel and from writing to pitch, filter and */
427 /* volume targets. */
428 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
429 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
431 #define LFOVAL1 0x13 /* Modulation LFO value */
432 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
433 /* 0x8000-n == 666*n usec delay */
435 #define ENVVAL 0x14 /* Modulation envelope register */
436 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
437 /* 0x8000-n == 666*n usec delay */
439 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
440 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
441 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
442 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
443 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
445 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
446 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
447 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
448 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
449 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
451 #define LFOVAL2 0x17 /* Vibrato LFO register */
452 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
453 /* 0x8000-n == 666*n usec delay */
455 #define IP 0x18 /* Initial pitch register */
456 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
457 /* 4 bits of octave, 12 bits of fractional octave */
458 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
460 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
461 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
462 /* 6 most significant bits are semitones */
463 /* 2 least significant bits are fractions */
464 #define IFATN_FILTERCUTOFF 0x08080019
465 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
466 #define IFATN_ATTENUATION 0x08000019
469 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
470 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
471 /* Signed 2's complement, +/- one octave peak extremes */
472 #define PEFE_PITCHAMOUNT 0x0808001a
473 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
474 /* Signed 2's complement, +/- six octaves peak extremes */
475 #define PEFE_FILTERAMOUNT 0x0800001a
476 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
477 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
478 /* Signed 2's complement, +/- one octave extremes */
479 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
480 /* Signed 2's complement, +/- three octave extremes */
483 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
484 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
485 /* Signed 2's complement, with +/- 12dB extremes */
487 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
488 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
489 /* Signed 2's complement, +/- one octave extremes */
490 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
491 /* 0.039Hz steps, maximum of 9.85 Hz. */
493 #define TEMPENV 0x1e /* Tempory envelope register */
494 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
495 /* NOTE: All channels contain internal variables; do */
496 /* not write to these locations. */
498 #define CD0 0x20 /* Cache data 0 register */
499 #define CD1 0x21 /* Cache data 1 register */
500 #define CD2 0x22 /* Cache data 2 register */
501 #define CD3 0x23 /* Cache data 3 register */
502 #define CD4 0x24 /* Cache data 4 register */
503 #define CD5 0x25 /* Cache data 5 register */
504 #define CD6 0x26 /* Cache data 6 register */
505 #define CD7 0x27 /* Cache data 7 register */
506 #define CD8 0x28 /* Cache data 8 register */
507 #define CD9 0x29 /* Cache data 9 register */
508 #define CDA 0x2a /* Cache data A register */
509 #define CDB 0x2b /* Cache data B register */
510 #define CDC 0x2c /* Cache data C register */
511 #define CDD 0x2d /* Cache data D register */
512 #define CDE 0x2e /* Cache data E register */
513 #define CDF 0x2f /* Cache data F register */
515 #define PTB 0x40 /* Page table base register */
516 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
518 #define TCB 0x41 /* Tank cache base register */
519 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
521 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
522 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
523 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
524 /* NOTE: To guarantee phase coherency, both channels */
525 /* must be disabled prior to enabling both channels. */
526 #define A_ADCCR_RCHANENABLE 0x00000020
527 #define A_ADCCR_LCHANENABLE 0x00000010
529 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
530 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
532 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
533 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
534 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
535 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
536 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
537 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
538 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
539 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
541 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
542 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
543 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
545 #define FXWC 0x43 /* FX output write channels register */
546 /* When set, each bit enables the writing of the */
547 /* corresponding FX output channel (internal registers */
548 /* 0x20-0x3f) into host memory. This mode of recording */
549 /* is 16bit, 48kHz only. All 32 channels can be enabled */
550 /* simultaneously. */
551 #define TCBS 0x44 /* Tank cache buffer size register */
552 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
553 #define TCBS_BUFFSIZE_16K 0x00000000
554 #define TCBS_BUFFSIZE_32K 0x00000001
555 #define TCBS_BUFFSIZE_64K 0x00000002
556 #define TCBS_BUFFSIZE_128K 0x00000003
557 #define TCBS_BUFFSIZE_256K 0x00000004
558 #define TCBS_BUFFSIZE_512K 0x00000005
559 #define TCBS_BUFFSIZE_1024K 0x00000006
560 #define TCBS_BUFFSIZE_2048K 0x00000007
562 #define MICBA 0x45 /* AC97 microphone buffer address register */
563 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
565 #define ADCBA 0x46 /* ADC buffer address register */
566 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
568 #define FXBA 0x47 /* FX Buffer Address */
569 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
571 #define MICBS 0x49 /* Microphone buffer size register */
573 #define ADCBS 0x4a /* ADC buffer size register */
575 #define FXBS 0x4b /* FX buffer size register */
577 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
578 #define ADCBS_BUFSIZE_NONE 0x00000000
579 #define ADCBS_BUFSIZE_384 0x00000001
580 #define ADCBS_BUFSIZE_448 0x00000002
581 #define ADCBS_BUFSIZE_512 0x00000003
582 #define ADCBS_BUFSIZE_640 0x00000004
583 #define ADCBS_BUFSIZE_768 0x00000005
584 #define ADCBS_BUFSIZE_896 0x00000006
585 #define ADCBS_BUFSIZE_1024 0x00000007
586 #define ADCBS_BUFSIZE_1280 0x00000008
587 #define ADCBS_BUFSIZE_1536 0x00000009
588 #define ADCBS_BUFSIZE_1792 0x0000000a
589 #define ADCBS_BUFSIZE_2048 0x0000000b
590 #define ADCBS_BUFSIZE_2560 0x0000000c
591 #define ADCBS_BUFSIZE_3072 0x0000000d
592 #define ADCBS_BUFSIZE_3584 0x0000000e
593 #define ADCBS_BUFSIZE_4096 0x0000000f
594 #define ADCBS_BUFSIZE_5120 0x00000010
595 #define ADCBS_BUFSIZE_6144 0x00000011
596 #define ADCBS_BUFSIZE_7168 0x00000012
597 #define ADCBS_BUFSIZE_8192 0x00000013
598 #define ADCBS_BUFSIZE_10240 0x00000014
599 #define ADCBS_BUFSIZE_12288 0x00000015
600 #define ADCBS_BUFSIZE_14366 0x00000016
601 #define ADCBS_BUFSIZE_16384 0x00000017
602 #define ADCBS_BUFSIZE_20480 0x00000018
603 #define ADCBS_BUFSIZE_24576 0x00000019
604 #define ADCBS_BUFSIZE_28672 0x0000001a
605 #define ADCBS_BUFSIZE_32768 0x0000001b
606 #define ADCBS_BUFSIZE_40960 0x0000001c
607 #define ADCBS_BUFSIZE_49152 0x0000001d
608 #define ADCBS_BUFSIZE_57344 0x0000001e
609 #define ADCBS_BUFSIZE_65536 0x0000001f
612 #define CDCS 0x50 /* CD-ROM digital channel status register */
614 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
616 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
618 /* definitions for debug register - taken from the alsa drivers */
619 #define DBG_ZC 0x80000000 /* zero tram counter */
620 #define DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
621 #define DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
622 #define DBG_SINGLE_STEP 0x00008000 /* single step mode */
623 #define DBG_STEP 0x00004000 /* start single step */
624 #define DBG_CONDITION_CODE 0x00003e00 /* condition code */
625 #define DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
628 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
631 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
632 #define A_DBG_ZC 0x40000000 /* zero tram counter */
633 #define A_DBG_STEP_ADDR 0x000003ff
634 #define A_DBG_SATURATION_OCCURED 0x20000000
635 #define A_DBG_SATURATION_ADDR 0x0ffc0000
637 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
639 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
641 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
643 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
644 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
645 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
646 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
647 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
648 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
649 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
650 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
651 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
652 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
653 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
654 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
655 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
656 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
657 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
658 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
659 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
660 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
661 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
662 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
663 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
664 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
665 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
667 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
668 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
670 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
672 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
674 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
676 #define SOLEL 0x5c /* Stop on loop enable low register */
678 #define SOLEH 0x5d /* Stop on loop enable high register */
680 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
681 #define SPBYPASS_ENABLE 0x00000001 /* Enable SPDIF bypass mode */
683 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
684 #define AC97SLOT_CNTR 0x10 /* Center enable */
685 #define AC97SLOT_LFE 0x20 /* LFE enable */
687 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
689 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
691 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
692 /* NOTE: This one has no SPDIFLOCKED field */
693 /* Assumes sample lock */
695 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
696 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
697 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
698 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
701 /* Note that these values can vary +/- by a small amount */
702 #define SRCS_SPDIFRATE_44 0x0003acd9
703 #define SRCS_SPDIFRATE_48 0x00040000
704 #define SRCS_SPDIFRATE_96 0x00080000
706 #define MICIDX 0x63 /* Microphone recording buffer index register */
707 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
708 #define MICIDX_IDX 0x10000063
710 #define A_ADCIDX 0x63
711 #define A_ADCIDX_IDX 0x10000063
713 #define ADCIDX 0x64 /* ADC recording buffer index register */
714 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
715 #define ADCIDX_IDX 0x10000064
717 #define FXIDX 0x65 /* FX recording buffer index register */
718 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
719 #define FXIDX_IDX 0x10000065
721 /* This is the MPU port on the card (via the game port) */
722 #define A_MUDATA1 0x70
723 #define A_MUCMD1 0x71
724 #define A_MUSTAT1 A_MUCMD1
726 /* This is the MPU port on the Audigy Drive */
727 #define A_MUDATA2 0x72
728 #define A_MUCMD2 0x73
729 #define A_MUSTAT2 A_MUCMD2
731 /* The next two are the Audigy equivalent of FXWC */
732 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
733 /* Each bit selects a channel for recording */
734 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
735 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
737 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
738 #define A_SPDIF_48000 0x00000080
739 #define A_SPDIF_44100 0x00000000
740 #define A_SPDIF_96000 0x00000040
743 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
744 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
745 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
746 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
748 #define A_SENDAMOUNTS 0x7d
749 #define A_FXSENDAMOUNT_E_MASK 0xff000000
750 #define A_FXSENDAMOUNT_F_MASK 0x00ff0000
751 #define A_FXSENDAMOUNT_G_MASK 0x0000ff00
752 #define A_FXSENDAMOUNT_H_MASK 0x000000ff
754 /* The send amounts for this one are the same as used with the emu10k1 */
756 #define A_FXRT_CHANNELA 0x0000003f
757 #define A_FXRT_CHANNELB 0x00003f00
758 #define A_FXRT_CHANNELC 0x003f0000
759 #define A_FXRT_CHANNELD 0x3f000000
762 /* Each FX general purpose register is 32 bits in length, all bits are used */
763 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
764 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
765 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
766 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
767 /* locations are for external TRAM. */
768 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
769 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
771 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
772 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
773 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
774 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
775 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
776 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
777 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
779 #define MICROCODEBASE 0x400 /* Microcode data base address */
781 /* Each DSP microcode instruction is mapped into 2 doublewords */
782 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
783 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
784 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
785 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
786 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
787 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
790 /* Audigy Soundcard have a different instruction format */
791 #define AUDIGY_CODEBASE 0x600
792 #define A_LOWORD_OPY_MASK 0x000007ff
793 #define A_LOWORD_OPX_MASK 0x007ff000
794 #define A_HIWORD_OPCODE_MASK 0x0f000000
795 #define A_HIWORD_RESULT_MASK 0x007ff000
796 #define A_HIWORD_OPA_MASK 0x000007ff
798 /* Opcodes macros -- Based on ALSA emu10k1.h */
800 /* FX8010/EMU10K1/EMU10K2 Instruction set */
801 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
802 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
803 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
804 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
805 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
806 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
807 #define iACC3 0x06 /* R = A + X + Y ; saturation */
808 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
809 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
810 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
811 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
812 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
813 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
814 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
815 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
816 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
818 /* FX8010 opcode macros */
819 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
820 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
821 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f */
822 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
823 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
824 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
825 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
826 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
828 /* FX8010 Constants */
829 #define C_00000000 0x40
830 #define C_00000001 0x41
831 #define C_00000002 0x42
832 #define C_00000003 0x43
833 #define C_00000004 0x44
834 #define C_00000008 0x45
835 #define C_00000010 0x46
836 #define C_00000020 0x47
837 #define C_00000100 0x48
838 #define C_00010000 0x49
839 #define C_00080000 0x4a
840 #define C_10000000 0x4b
841 #define C_20000000 0x4c
842 #define C_40000000 0x4d
843 #define C_80000000 0x4e
844 #define C_7fffffff 0x4f
845 #define C_ffffffff 0x50
846 #define C_fffffffe 0x51
847 #define C_c0000000 0x52
848 #define C_4f1bbcdc 0x53
849 #define C_5a7ef9db 0x54
850 #define C_00100000 0x55 /* ?? */
852 /* FX8010 FX Send Bus Registers */
853 #define FXBUS_PCM_LEFT 0x00
854 #define FXBUS_PCM_RIGHT 0x01
855 #define FXBUS_PCM_LEFT_REAR 0x02
856 #define FXBUS_PCM_RIGHT_REAR 0x03
857 #define FXBUS_MIDI_LEFT 0x04
858 #define FXBUS_MIDI_RIGHT 0x05
859 #define FXBUS_PCM_CENTER 0x06
860 #define FXBUS_PCM_LFE 0x07
861 #define FXBUS_MIDI_REVERB 0x0c
862 #define FXBUS_MIDI_CHORUS 0x0d
865 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
866 #define GPR_COND 0x57 /* CCR, condition register */
867 #define GPR_NOISE0 0x58 /* noise source */
868 #define GPR_NOISE1 0x59 /* noise source */
869 #define GPR_IRQ 0x5a /* IRQ register */
870 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
873 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
874 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
875 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
876 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
877 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
878 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
879 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
880 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
881 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
882 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
883 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
884 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
885 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
886 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
889 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
890 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
891 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
892 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
893 #define EXTOUT_CENTER 0x04 /* SB Live 5.1 - center */
894 #define EXTOUT_LFE 0x05 /* SB Live 5.1 - LFE */
895 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
896 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
897 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
898 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
899 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
900 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
901 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
902 #define EXTOUT_ACENTER 0x11 /* Analog Center */
903 #define EXTOUT_ALFE 0x12 /* Analog LFE */
905 /* Audigy opcode macros */
906 #define A_FXBUS(x) ((x) + 0x00)
907 #define A_EXTIN(x) ((x) + 0x40)
908 #define A_EXTOUT(x) ((x) + 0x60)
909 #define A_GPR(x) ((x) + A_FXGPREGBASE)
911 /* Audigy constants */
912 #define A_C_00000000 0xc0
913 #define A_C_00000001 0xc1
914 #define A_C_00000002 0xc2
915 #define A_C_00000003 0xc3
916 #define A_C_00000004 0xc4
917 #define A_C_00000008 0xc5
918 #define A_C_00000010 0xc6
919 #define A_C_00000020 0xc7
920 #define A_C_00000100 0xc8
921 #define A_C_00010000 0xc9
922 #define A_C_00000800 0xca
923 #define A_C_10000000 0xcb
924 #define A_C_20000000 0xcc
925 #define A_C_40000000 0xcd
926 #define A_C_80000000 0xce
927 #define A_C_7fffffff 0xcf
928 #define A_C_ffffffff 0xd0
929 #define A_C_fffffffe 0xd1
930 #define A_C_c0000000 0xd2
931 #define A_C_4f1bbcdc 0xd3
932 #define A_C_5a7ef9db 0xd4
933 #define A_C_00100000 0xd5
935 /* Audigy FX Send Bus Registers */
936 #define A_FXBUS_PCM_LEFT FXBUS_PCM_LEFT
937 #define A_FXBUS_PCM_RIGHT FXBUS_PCM_RIGHT
938 #define A_FXBUS_PCM_LEFT_REAR FXBUS_PCM_LEFT_REAR
939 #define A_FXBUS_PCM_RIGHT_REAR FXBUS_PCM_RIGHT_REAR
940 #define A_FXBUS_MIDI_LEFT FXBUS_MIDI_LEFT
941 #define A_FXBUS_MIDI_RIGHT FXBUS_MIDI_RIGHT
942 #define A_FXBUS_PCM_CENTER FXBUS_PCM_CENTER
943 #define A_FXBUS_PCM_LFE FXBUS_PCM_LFE
944 #define A_FXBUS_MIDI_REVERB FXBUS_MIDI_REVERB
945 #define A_FXBUS_MIDI_CHORUS FXBUS_MIDI_CHORUS
947 #define A_GPR_ACCU 0xd6 /* 0xd6 = 0x7fffffff (?) ACCUM? */
948 #define A_GPR_COND 0xd7 /* 0xd7 = 0x0000000 CCR */
949 #define A_GPR_NOISE0 0xd8 /* 0xd8 = noise1 */
950 #define A_GPR_NOISE1 0xd9 /* 0xd9 = noise2 */
951 #define A_GPR_IRQ 0xda /* IRQ register */
952 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter */
955 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
956 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
957 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
958 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
959 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
960 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
961 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
962 #define A_EXTIN_LINE2_R 0x09 /* right */
963 #define A_EXTIN_RCA_SPDIF_L 0x0a /* audigy drive RCA SPDIF - left */
964 #define A_EXTIN_RCA_SPDIF_R 0x0b /* right */
965 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
966 #define A_EXTIN_AUX2_R 0x0d /* - right */
969 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
970 #define A_EXTOUT_FRONT_R 0x01 /* right */
971 #define A_EXTOUT_CENTER 0x02 /* digital front center */
972 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
973 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
974 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
975 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
976 #define A_EXTOUT_REAR_R 0x07 /* right */
977 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
978 #define A_EXTOUT_AFRONT_R 0x09 /* right */
979 #define A_EXTOUT_ACENTER 0x0a /* analog center */
980 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
983 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
984 #define A_EXTOUT_AREAR_R 0x0f /* right */
985 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
986 #define A_EXTOUT_AC97_R 0x11 /* right */
987 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
988 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
991 #define ENABLE 0xffffffff
992 #define DISABLE 0x00000000
997 #endif /* EMU10K1_H */
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