2 * Copyright (c) 2002-2004 M. Warner Losh.
3 * Copyright (c) 2000-2001 Jonathan Chen.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/pccbb/pccbb_pci.c,v 1.15 2005/10/08 06:58:51 imp Exp $
28 * $DragonFly: src/sys/dev/pccard/pccbb/pccbb_pci.c,v 1.2 2007/08/14 14:58:44 sephe Exp $
32 * Copyright (c) 1998, 1999 and 2000
33 * HAYAKAWA Koichi. All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 * 3. All advertising materials mentioning features or use of this software
44 * must display the following acknowledgement:
45 * This product includes software developed by HAYAKAWA Koichi.
46 * 4. The name of the author may not be used to endorse or promote products
47 * derived from this software without specific prior written permission.
49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 * Driver for PCI to CardBus Bridge chips
66 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
68 * Written by Jonathan Chen <jon@freebsd.org>
69 * The author would like to acknowledge:
70 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing
71 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things
72 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver
73 * * David Cross: Author of the initial ugly hack for a specific cardbus card
76 #include <sys/param.h>
77 #include <sys/systm.h>
79 #include <sys/errno.h>
80 #include <sys/kernel.h>
82 #include <sys/malloc.h>
83 #include <sys/sysctl.h>
84 #include <sys/kthread.h>
87 #include <sys/module.h>
89 #include <bus/pci/pcireg.h>
90 #include <bus/pci/pcivar.h>
91 #include <machine/clock.h>
93 #include <bus/pccard/pccardreg.h>
94 #include <bus/pccard/pccardvar.h>
96 #include <dev/pccard/exca/excareg.h>
97 #include <dev/pccard/exca/excavar.h>
99 #include <dev/pccard/pccbb/pccbbreg.h>
100 #include <dev/pccard/pccbb/pccbbvar.h>
102 #include "power_if.h"
106 #define DPRINTF(x) do { if (cbb_debug) kprintf x; } while (0)
107 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
109 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
110 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
111 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \
112 pci_write_config(DEV, REG, ( \
113 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)
115 static void cbb_chipinit(struct cbb_softc *sc);
117 static struct yenta_chipinfo {
122 /* Texas Instruments chips */
123 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X},
124 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X},
125 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X},
127 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX},
128 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX},
129 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX},
130 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX},
131 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX},
132 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X},
133 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X},
134 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X},
135 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX},
136 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX},
137 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX},
138 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX},
139 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX},
140 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/
141 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX},
142 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX},
143 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX},
144 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX},
145 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX},
146 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX},
147 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX},
148 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX},
149 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
150 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
151 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX},
152 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX},
153 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
154 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
155 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
156 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
159 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX},
160 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX},
161 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX},
162 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX},
163 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX},
164 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX},
167 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X},
168 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X},
169 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X},
170 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X},
171 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X},
172 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X},
174 /* Toshiba products */
175 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95},
176 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95},
177 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97},
178 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97},
181 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS},
182 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS},
183 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
186 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
187 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
188 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
189 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
190 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
191 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
192 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO},
193 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO},
194 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO},
195 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO},
196 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO},
197 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO},
200 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS},
203 {0 /* null id */, "unknown", CB_UNKNOWN},
206 /************************************************************************/
208 /************************************************************************/
211 cbb_chipset(uint32_t pci_id, const char **namep)
213 struct yenta_chipinfo *ycp;
215 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp)
218 *namep = ycp->yc_name;
219 return (ycp->yc_chiptype);
223 cbb_pci_probe(device_t brdev)
226 uint8_t progif, subclass, class;
229 * Do we know that we support the chipset? If so, then we
232 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) {
233 device_set_desc(brdev, name);
238 * We do support generic CardBus bridges. All that we've seen
239 * to date have progif 0 (the Yenta spec, and successors mandate
242 class = pci_get_class(brdev);
243 subclass = pci_get_subclass(brdev);
244 progif = pci_get_progif(brdev);
245 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_CARDBUS &&
247 device_set_desc(brdev, "PCI-CardBus Bridge");
254 * Still need this because the pci code only does power for type 0
258 cbb_powerstate_d0(device_t dev)
260 u_int32_t membase, irq;
262 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
263 /* Save important PCI config data. */
264 membase = pci_read_config(dev, CBBR_SOCKBASE, 4);
265 irq = pci_read_config(dev, PCIR_INTLINE, 4);
267 /* Reset the power state. */
268 device_printf(dev, "chip is in D%d power mode "
269 "-- setting to D0\n", pci_get_powerstate(dev));
271 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
273 /* Restore PCI config data. */
274 pci_write_config(dev, CBBR_SOCKBASE, membase, 4);
275 pci_write_config(dev, PCIR_INTLINE, irq, 4);
280 * Print out the config space
283 cbb_print_config(device_t dev)
287 device_printf(dev, "PCI Configuration space:");
288 for (i = 0; i < 256; i += 4) {
290 kprintf("\n 0x%02x: ", i);
291 kprintf("0x%08x ", pci_read_config(dev, i, 4));
297 cbb_pci_attach(device_t brdev)
299 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */
301 struct cbb_softc *sc = device_get_softc(brdev);
305 parent = device_get_parent(brdev);
307 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
310 sc->exca[0].pccarddev = NULL;
311 sc->domain = pci_get_domain(brdev);
312 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1);
313 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1);
314 sc->pribus = pcib_get_bus(parent);
316 cbb_powerstate_d0(brdev);
319 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
322 device_printf(brdev, "Could not grab register memory\n");
325 DEVPRINTF((brdev, "Found memory at %08lx\n",
326 rman_get_start(sc->base_res)));
329 sc->bst = rman_get_bustag(sc->base_res);
330 sc->bsh = rman_get_bushandle(sc->base_res);
331 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
332 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN;
333 sc->exca[0].chipset = EXCA_CARDBUS;
334 sc->chipinit = cbb_chipinit;
338 * This is a gross hack. We should be scanning the entire pci
339 * tree, assigning bus numbers in a way such that we (1) can
340 * reserve 1 extra bus just in case and (2) all sub busses
341 * are in an appropriate range.
343 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->secbus));
344 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1);
345 if (sc->secbus == 0 || sc->pribus != pribus) {
346 if (curr_bus_number <= sc->pribus)
347 curr_bus_number = sc->pribus + 1;
348 if (pribus != sc->pribus) {
349 DEVPRINTF((brdev, "Setting primary bus to %d\n",
351 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
353 sc->secbus = curr_bus_number++;
354 sc->subbus = curr_bus_number++;
355 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n",
356 sc->secbus, sc->subbus));
357 pci_write_config(brdev, PCIR_SECBUS_2, sc->secbus, 1);
358 pci_write_config(brdev, PCIR_SUBBUS_2, sc->subbus, 1);
361 /* attach children */
362 sc->cbdev = device_add_child(brdev, "cardbus", -1);
363 if (sc->cbdev == NULL)
364 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n"));
365 else if (device_probe_and_attach(sc->cbdev) != 0)
366 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n"));
368 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1);
369 if (sc->exca[0].pccarddev == NULL)
370 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n"));
371 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0)
372 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n"));
374 /* Map and establish the interrupt. */
376 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
377 RF_SHAREABLE | RF_ACTIVE);
378 if (sc->irq_res == NULL) {
379 kprintf("cbb: Unable to map IRQ...\n");
383 if (bus_setup_intr(brdev, sc->irq_res, INTR_MPSAFE, cbb_intr, sc,
384 &sc->intrhand, NULL)) {
385 device_printf(brdev, "couldn't establish interrupt");
389 /* reset 16-bit pcmcia bus */
390 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
393 cbb_power(brdev, CARD_OFF);
395 /* CSC Interrupt: Card detect interrupt on */
396 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
398 /* reset interrupt */
399 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
402 cbb_print_config(brdev);
404 /* Start the thread */
405 if (kthread_create(cbb_event_thread, sc, &sc->event_thread,
406 "%s", device_get_nameunit(brdev))) {
407 device_printf(brdev, "unable to create event thread.\n");
408 panic("cbb_create_event_thread");
413 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
415 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE,
422 cbb_chipinit(struct cbb_softc *sc)
424 uint32_t mux, sysctrl, reg;
426 /* Set CardBus latency timer */
427 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20)
428 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1);
430 /* Set PCI latency timer */
431 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
432 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
434 /* Enable memory access */
435 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND,
438 | PCIM_CMD_BUSMASTEREN, 2);
440 /* disable Legacy IO */
441 switch (sc->chipset) {
443 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL,
444 & ~(CBBM_BRIDGECTRL_RL_3E0_EN |
445 CBBM_BRIDGECTRL_RL_3E2_EN), 2);
448 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4);
452 /* Use PCI interrupt for interrupt routing */
453 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL,
454 & ~(CBBM_BRIDGECTRL_MASTER_ABORT |
455 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN),
456 | CBBM_BRIDGECTRL_WRITE_POST_EN,
460 * XXX this should be a function table, ala OLDCARD. This means
461 * that we could more easily support ISA interrupts for pccard
462 * cards if we had to.
464 switch (sc->chipset) {
467 * The TI 1031, TI 1130 and TI 1131 all require another bit
468 * be set to enable PCI routing of interrupts, and then
469 * a bit for each of the CSC and Function interrupts we
472 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL,
473 | CBBM_CBCTRL_113X_PCI_INTR |
474 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN,
476 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL,
477 & ~(CBBM_DEVCTRL_INT_SERIAL |
478 CBBM_DEVCTRL_INT_PCI), 1);
482 * Some TI 12xx (and [14][45]xx) based pci cards
483 * sometimes have issues with the MFUNC register not
484 * being initialized due to a bad EEPROM on board.
485 * Laptops that this matters on have this register
486 * properly initialized.
488 * The TI125X parts have a different register.
490 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4);
491 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4);
493 mux = (mux & ~CBBM_MFUNC_PIN0) |
494 CBBM_MFUNC_PIN0_INTA;
495 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0)
496 mux = (mux & ~CBBM_MFUNC_PIN1) |
497 CBBM_MFUNC_PIN1_INTB;
498 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4);
503 * Disable zoom video. Some machines initialize this
504 * improperly and exerpience has shown that this helps
505 * prevent strange behavior.
507 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
511 * Issue #1: INT# generated at the same time as
512 * selected ISA IRQ. When IREQ# or STSCHG# is active,
513 * in addition to the ISA IRQ being generated, INT#
514 * will also be generated at the same time.
516 * Some of the older controllers have an issue in
517 * which the slot's PCI INT# will be asserted whenever
518 * IREQ# or STSCGH# is asserted even if ExCA registers
519 * 03h or 05h have an ISA IRQ selected.
521 * The fix for this issue, which will work for any
522 * controller (old or new), is to set ExCA registers
523 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
524 * These bits are undocumented. By setting this
525 * register (of each slot) to '1010xxxxb' a routing of
526 * IREQ# to INTC# and STSCHG# to INTC# is selected.
527 * Since INTC# isn't connected there will be no
528 * unexpected PCI INT when IREQ# or STSCHG# is active.
529 * However, INTA# (slot 0) or INTB# (slot 1) will
530 * still be correctly generated if NO ISA IRQ is
531 * selected (ExCA regs 03h or 05h are cleared).
533 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C);
535 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC;
536 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg);
541 * Disable Zoom Video, ToPIC 97, 100.
543 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1);
546 * At offset 0xa1: INTERRUPT CONTROL register
547 * 0x1: Turn on INT interrupts.
549 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL,
550 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1);
554 * SOCKETCTRL appears to be TOPIC 95/B specific
556 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL,
557 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4);
561 * At offset 0xa0: SLOT CONTROL
562 * 0x80 Enable CardBus Functionality
563 * 0x40 Enable CardBus and PC Card registers
564 * 0x20 Lock ID in exca regs
565 * 0x10 Write protect ID in config regs
566 * Clear the rest of the bits, which defaults the slot
567 * in legacy mode to 0x3e0 and offset 0. (legacy
568 * mode is determined elsewhere)
570 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL,
571 CBBM_TOPIC_SLOTCTRL_SLOTON |
572 CBBM_TOPIC_SLOTCTRL_SLOTEN |
573 CBBM_TOPIC_SLOTCTRL_ID_LOCK |
574 CBBM_TOPIC_SLOTCTRL_ID_WP, 1);
577 * At offset 0xa3 Card Detect Control Register
578 * 0x80 CARDBUS enbale
579 * 0x01 Cleared for hardware change detect
581 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC,
582 | CBBM_TOPIC_CDC_CARDBUS,
583 & ~CBBM_TOPIC_CDC_SWDETECT, 4);
588 * Need to tell ExCA registers to CSC interrupts route via PCI
589 * interrupts. There are two ways to do this. Once is to set
590 * INTR_ENABLE and the other is to set CSC to 0. Since both
591 * methods are mutually compatible, we do both.
593 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE);
594 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0);
596 cbb_disable_func_intr(sc);
598 /* close all memory and io windows */
599 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4);
600 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4);
601 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4);
602 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4);
603 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4);
604 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4);
605 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4);
606 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
610 cbb_route_interrupt(device_t pcib, device_t dev, int pin)
612 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib);
614 return (rman_get_start(sc->irq_res));
617 static device_method_t cbb_methods[] = {
618 /* Device interface */
619 DEVMETHOD(device_probe, cbb_pci_probe),
620 DEVMETHOD(device_attach, cbb_pci_attach),
621 DEVMETHOD(device_detach, cbb_detach),
622 DEVMETHOD(device_shutdown, cbb_shutdown),
623 DEVMETHOD(device_suspend, cbb_suspend),
624 DEVMETHOD(device_resume, cbb_resume),
627 DEVMETHOD(bus_print_child, bus_generic_print_child),
628 DEVMETHOD(bus_read_ivar, cbb_read_ivar),
629 DEVMETHOD(bus_write_ivar, cbb_write_ivar),
630 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource),
631 DEVMETHOD(bus_release_resource, cbb_release_resource),
632 DEVMETHOD(bus_activate_resource, cbb_activate_resource),
633 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource),
634 DEVMETHOD(bus_driver_added, cbb_driver_added),
635 DEVMETHOD(bus_child_detached, cbb_child_detached),
636 DEVMETHOD(bus_setup_intr, cbb_setup_intr),
637 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr),
638 DEVMETHOD(bus_child_present, cbb_child_present),
640 /* 16-bit card interface */
641 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags),
642 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset),
644 /* power interface */
645 DEVMETHOD(power_enable_socket, cbb_power_enable_socket),
646 DEVMETHOD(power_disable_socket, cbb_power_disable_socket),
648 /* pcib compatibility interface */
649 DEVMETHOD(pcib_maxslots, cbb_maxslots),
650 DEVMETHOD(pcib_read_config, cbb_read_config),
651 DEVMETHOD(pcib_write_config, cbb_write_config),
652 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt),
657 static driver_t cbb_driver = {
660 sizeof(struct cbb_softc)
663 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0);
664 MODULE_DEPEND(cbb, exca, 1, 1, 1);