55cff363f7b6ee65df3670bb02cf86af5209112d
[dragonfly.git] / sys / platform / pc32 / apic / ioapic_abi.c
1 /*
2  * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
4  * Copyright (c) 1991 The Regents of the University of California.
5  * All rights reserved.
6  * 
7  * This code is derived from software contributed to The DragonFly Project
8  * by Matthew Dillon <dillon@backplane.com>
9  *
10  * This code is derived from software contributed to Berkeley by
11  * William Jolitz.
12  * 
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  * 3. Neither the name of The DragonFly Project nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific, prior written permission.
26  * 
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.12 2007/04/30 16:45:55 dillon Exp $
41  */
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
48 #include <sys/bus.h>
49 #include <sys/rman.h>
50 #include <sys/thread2.h>
51
52 #include <machine/smp.h>
53 #include <machine/segments.h>
54 #include <machine/md_var.h>
55 #include <machine/intr_machdep.h>
56 #include <machine/globaldata.h>
57
58 #include <machine_base/isa/isa_intr.h>
59 #include <machine_base/icu/icu.h>
60 #include <machine_base/icu/icu_var.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine_base/apic/ioapic_abi.h>
63 #include <machine_base/apic/ioapic_ipl.h>
64 #include <machine_base/apic/apicreg.h>
65
66 #include <dev/acpica5/acpi_sci_var.h>
67
68 #define IOAPIC_HWI_VECTORS      IDT_HWI_VECTORS
69
70 extern inthand_t
71         IDTVEC(ioapic_intr0),
72         IDTVEC(ioapic_intr1),
73         IDTVEC(ioapic_intr2),
74         IDTVEC(ioapic_intr3),
75         IDTVEC(ioapic_intr4),
76         IDTVEC(ioapic_intr5),
77         IDTVEC(ioapic_intr6),
78         IDTVEC(ioapic_intr7),
79         IDTVEC(ioapic_intr8),
80         IDTVEC(ioapic_intr9),
81         IDTVEC(ioapic_intr10),
82         IDTVEC(ioapic_intr11),
83         IDTVEC(ioapic_intr12),
84         IDTVEC(ioapic_intr13),
85         IDTVEC(ioapic_intr14),
86         IDTVEC(ioapic_intr15),
87         IDTVEC(ioapic_intr16),
88         IDTVEC(ioapic_intr17),
89         IDTVEC(ioapic_intr18),
90         IDTVEC(ioapic_intr19),
91         IDTVEC(ioapic_intr20),
92         IDTVEC(ioapic_intr21),
93         IDTVEC(ioapic_intr22),
94         IDTVEC(ioapic_intr23),
95         IDTVEC(ioapic_intr24),
96         IDTVEC(ioapic_intr25),
97         IDTVEC(ioapic_intr26),
98         IDTVEC(ioapic_intr27),
99         IDTVEC(ioapic_intr28),
100         IDTVEC(ioapic_intr29),
101         IDTVEC(ioapic_intr30),
102         IDTVEC(ioapic_intr31),
103         IDTVEC(ioapic_intr32),
104         IDTVEC(ioapic_intr33),
105         IDTVEC(ioapic_intr34),
106         IDTVEC(ioapic_intr35),
107         IDTVEC(ioapic_intr36),
108         IDTVEC(ioapic_intr37),
109         IDTVEC(ioapic_intr38),
110         IDTVEC(ioapic_intr39),
111         IDTVEC(ioapic_intr40),
112         IDTVEC(ioapic_intr41),
113         IDTVEC(ioapic_intr42),
114         IDTVEC(ioapic_intr43),
115         IDTVEC(ioapic_intr44),
116         IDTVEC(ioapic_intr45),
117         IDTVEC(ioapic_intr46),
118         IDTVEC(ioapic_intr47),
119         IDTVEC(ioapic_intr48),
120         IDTVEC(ioapic_intr49),
121         IDTVEC(ioapic_intr50),
122         IDTVEC(ioapic_intr51),
123         IDTVEC(ioapic_intr52),
124         IDTVEC(ioapic_intr53),
125         IDTVEC(ioapic_intr54),
126         IDTVEC(ioapic_intr55),
127         IDTVEC(ioapic_intr56),
128         IDTVEC(ioapic_intr57),
129         IDTVEC(ioapic_intr58),
130         IDTVEC(ioapic_intr59),
131         IDTVEC(ioapic_intr60),
132         IDTVEC(ioapic_intr61),
133         IDTVEC(ioapic_intr62),
134         IDTVEC(ioapic_intr63),
135         IDTVEC(ioapic_intr64),
136         IDTVEC(ioapic_intr65),
137         IDTVEC(ioapic_intr66),
138         IDTVEC(ioapic_intr67),
139         IDTVEC(ioapic_intr68),
140         IDTVEC(ioapic_intr69),
141         IDTVEC(ioapic_intr70),
142         IDTVEC(ioapic_intr71),
143         IDTVEC(ioapic_intr72),
144         IDTVEC(ioapic_intr73),
145         IDTVEC(ioapic_intr74),
146         IDTVEC(ioapic_intr75),
147         IDTVEC(ioapic_intr76),
148         IDTVEC(ioapic_intr77),
149         IDTVEC(ioapic_intr78),
150         IDTVEC(ioapic_intr79),
151         IDTVEC(ioapic_intr80),
152         IDTVEC(ioapic_intr81),
153         IDTVEC(ioapic_intr82),
154         IDTVEC(ioapic_intr83),
155         IDTVEC(ioapic_intr84),
156         IDTVEC(ioapic_intr85),
157         IDTVEC(ioapic_intr86),
158         IDTVEC(ioapic_intr87),
159         IDTVEC(ioapic_intr88),
160         IDTVEC(ioapic_intr89),
161         IDTVEC(ioapic_intr90),
162         IDTVEC(ioapic_intr91),
163         IDTVEC(ioapic_intr92),
164         IDTVEC(ioapic_intr93),
165         IDTVEC(ioapic_intr94),
166         IDTVEC(ioapic_intr95),
167         IDTVEC(ioapic_intr96),
168         IDTVEC(ioapic_intr97),
169         IDTVEC(ioapic_intr98),
170         IDTVEC(ioapic_intr99),
171         IDTVEC(ioapic_intr100),
172         IDTVEC(ioapic_intr101),
173         IDTVEC(ioapic_intr102),
174         IDTVEC(ioapic_intr103),
175         IDTVEC(ioapic_intr104),
176         IDTVEC(ioapic_intr105),
177         IDTVEC(ioapic_intr106),
178         IDTVEC(ioapic_intr107),
179         IDTVEC(ioapic_intr108),
180         IDTVEC(ioapic_intr109),
181         IDTVEC(ioapic_intr110),
182         IDTVEC(ioapic_intr111),
183         IDTVEC(ioapic_intr112),
184         IDTVEC(ioapic_intr113),
185         IDTVEC(ioapic_intr114),
186         IDTVEC(ioapic_intr115),
187         IDTVEC(ioapic_intr116),
188         IDTVEC(ioapic_intr117),
189         IDTVEC(ioapic_intr118),
190         IDTVEC(ioapic_intr119),
191         IDTVEC(ioapic_intr120),
192         IDTVEC(ioapic_intr121),
193         IDTVEC(ioapic_intr122),
194         IDTVEC(ioapic_intr123),
195         IDTVEC(ioapic_intr124),
196         IDTVEC(ioapic_intr125),
197         IDTVEC(ioapic_intr126),
198         IDTVEC(ioapic_intr127),
199         IDTVEC(ioapic_intr128),
200         IDTVEC(ioapic_intr129),
201         IDTVEC(ioapic_intr130),
202         IDTVEC(ioapic_intr131),
203         IDTVEC(ioapic_intr132),
204         IDTVEC(ioapic_intr133),
205         IDTVEC(ioapic_intr134),
206         IDTVEC(ioapic_intr135),
207         IDTVEC(ioapic_intr136),
208         IDTVEC(ioapic_intr137),
209         IDTVEC(ioapic_intr138),
210         IDTVEC(ioapic_intr139),
211         IDTVEC(ioapic_intr140),
212         IDTVEC(ioapic_intr141),
213         IDTVEC(ioapic_intr142),
214         IDTVEC(ioapic_intr143),
215         IDTVEC(ioapic_intr144),
216         IDTVEC(ioapic_intr145),
217         IDTVEC(ioapic_intr146),
218         IDTVEC(ioapic_intr147),
219         IDTVEC(ioapic_intr148),
220         IDTVEC(ioapic_intr149),
221         IDTVEC(ioapic_intr150),
222         IDTVEC(ioapic_intr151),
223         IDTVEC(ioapic_intr152),
224         IDTVEC(ioapic_intr153),
225         IDTVEC(ioapic_intr154),
226         IDTVEC(ioapic_intr155),
227         IDTVEC(ioapic_intr156),
228         IDTVEC(ioapic_intr157),
229         IDTVEC(ioapic_intr158),
230         IDTVEC(ioapic_intr159),
231         IDTVEC(ioapic_intr160),
232         IDTVEC(ioapic_intr161),
233         IDTVEC(ioapic_intr162),
234         IDTVEC(ioapic_intr163),
235         IDTVEC(ioapic_intr164),
236         IDTVEC(ioapic_intr165),
237         IDTVEC(ioapic_intr166),
238         IDTVEC(ioapic_intr167),
239         IDTVEC(ioapic_intr168),
240         IDTVEC(ioapic_intr169),
241         IDTVEC(ioapic_intr170),
242         IDTVEC(ioapic_intr171),
243         IDTVEC(ioapic_intr172),
244         IDTVEC(ioapic_intr173),
245         IDTVEC(ioapic_intr174),
246         IDTVEC(ioapic_intr175),
247         IDTVEC(ioapic_intr176),
248         IDTVEC(ioapic_intr177),
249         IDTVEC(ioapic_intr178),
250         IDTVEC(ioapic_intr179),
251         IDTVEC(ioapic_intr180),
252         IDTVEC(ioapic_intr181),
253         IDTVEC(ioapic_intr182),
254         IDTVEC(ioapic_intr183),
255         IDTVEC(ioapic_intr184),
256         IDTVEC(ioapic_intr185),
257         IDTVEC(ioapic_intr186),
258         IDTVEC(ioapic_intr187),
259         IDTVEC(ioapic_intr188),
260         IDTVEC(ioapic_intr189),
261         IDTVEC(ioapic_intr190),
262         IDTVEC(ioapic_intr191);
263
264 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
265         &IDTVEC(ioapic_intr0),
266         &IDTVEC(ioapic_intr1),
267         &IDTVEC(ioapic_intr2),
268         &IDTVEC(ioapic_intr3),
269         &IDTVEC(ioapic_intr4),
270         &IDTVEC(ioapic_intr5),
271         &IDTVEC(ioapic_intr6),
272         &IDTVEC(ioapic_intr7),
273         &IDTVEC(ioapic_intr8),
274         &IDTVEC(ioapic_intr9),
275         &IDTVEC(ioapic_intr10),
276         &IDTVEC(ioapic_intr11),
277         &IDTVEC(ioapic_intr12),
278         &IDTVEC(ioapic_intr13),
279         &IDTVEC(ioapic_intr14),
280         &IDTVEC(ioapic_intr15),
281         &IDTVEC(ioapic_intr16),
282         &IDTVEC(ioapic_intr17),
283         &IDTVEC(ioapic_intr18),
284         &IDTVEC(ioapic_intr19),
285         &IDTVEC(ioapic_intr20),
286         &IDTVEC(ioapic_intr21),
287         &IDTVEC(ioapic_intr22),
288         &IDTVEC(ioapic_intr23),
289         &IDTVEC(ioapic_intr24),
290         &IDTVEC(ioapic_intr25),
291         &IDTVEC(ioapic_intr26),
292         &IDTVEC(ioapic_intr27),
293         &IDTVEC(ioapic_intr28),
294         &IDTVEC(ioapic_intr29),
295         &IDTVEC(ioapic_intr30),
296         &IDTVEC(ioapic_intr31),
297         &IDTVEC(ioapic_intr32),
298         &IDTVEC(ioapic_intr33),
299         &IDTVEC(ioapic_intr34),
300         &IDTVEC(ioapic_intr35),
301         &IDTVEC(ioapic_intr36),
302         &IDTVEC(ioapic_intr37),
303         &IDTVEC(ioapic_intr38),
304         &IDTVEC(ioapic_intr39),
305         &IDTVEC(ioapic_intr40),
306         &IDTVEC(ioapic_intr41),
307         &IDTVEC(ioapic_intr42),
308         &IDTVEC(ioapic_intr43),
309         &IDTVEC(ioapic_intr44),
310         &IDTVEC(ioapic_intr45),
311         &IDTVEC(ioapic_intr46),
312         &IDTVEC(ioapic_intr47),
313         &IDTVEC(ioapic_intr48),
314         &IDTVEC(ioapic_intr49),
315         &IDTVEC(ioapic_intr50),
316         &IDTVEC(ioapic_intr51),
317         &IDTVEC(ioapic_intr52),
318         &IDTVEC(ioapic_intr53),
319         &IDTVEC(ioapic_intr54),
320         &IDTVEC(ioapic_intr55),
321         &IDTVEC(ioapic_intr56),
322         &IDTVEC(ioapic_intr57),
323         &IDTVEC(ioapic_intr58),
324         &IDTVEC(ioapic_intr59),
325         &IDTVEC(ioapic_intr60),
326         &IDTVEC(ioapic_intr61),
327         &IDTVEC(ioapic_intr62),
328         &IDTVEC(ioapic_intr63),
329         &IDTVEC(ioapic_intr64),
330         &IDTVEC(ioapic_intr65),
331         &IDTVEC(ioapic_intr66),
332         &IDTVEC(ioapic_intr67),
333         &IDTVEC(ioapic_intr68),
334         &IDTVEC(ioapic_intr69),
335         &IDTVEC(ioapic_intr70),
336         &IDTVEC(ioapic_intr71),
337         &IDTVEC(ioapic_intr72),
338         &IDTVEC(ioapic_intr73),
339         &IDTVEC(ioapic_intr74),
340         &IDTVEC(ioapic_intr75),
341         &IDTVEC(ioapic_intr76),
342         &IDTVEC(ioapic_intr77),
343         &IDTVEC(ioapic_intr78),
344         &IDTVEC(ioapic_intr79),
345         &IDTVEC(ioapic_intr80),
346         &IDTVEC(ioapic_intr81),
347         &IDTVEC(ioapic_intr82),
348         &IDTVEC(ioapic_intr83),
349         &IDTVEC(ioapic_intr84),
350         &IDTVEC(ioapic_intr85),
351         &IDTVEC(ioapic_intr86),
352         &IDTVEC(ioapic_intr87),
353         &IDTVEC(ioapic_intr88),
354         &IDTVEC(ioapic_intr89),
355         &IDTVEC(ioapic_intr90),
356         &IDTVEC(ioapic_intr91),
357         &IDTVEC(ioapic_intr92),
358         &IDTVEC(ioapic_intr93),
359         &IDTVEC(ioapic_intr94),
360         &IDTVEC(ioapic_intr95),
361         &IDTVEC(ioapic_intr96),
362         &IDTVEC(ioapic_intr97),
363         &IDTVEC(ioapic_intr98),
364         &IDTVEC(ioapic_intr99),
365         &IDTVEC(ioapic_intr100),
366         &IDTVEC(ioapic_intr101),
367         &IDTVEC(ioapic_intr102),
368         &IDTVEC(ioapic_intr103),
369         &IDTVEC(ioapic_intr104),
370         &IDTVEC(ioapic_intr105),
371         &IDTVEC(ioapic_intr106),
372         &IDTVEC(ioapic_intr107),
373         &IDTVEC(ioapic_intr108),
374         &IDTVEC(ioapic_intr109),
375         &IDTVEC(ioapic_intr110),
376         &IDTVEC(ioapic_intr111),
377         &IDTVEC(ioapic_intr112),
378         &IDTVEC(ioapic_intr113),
379         &IDTVEC(ioapic_intr114),
380         &IDTVEC(ioapic_intr115),
381         &IDTVEC(ioapic_intr116),
382         &IDTVEC(ioapic_intr117),
383         &IDTVEC(ioapic_intr118),
384         &IDTVEC(ioapic_intr119),
385         &IDTVEC(ioapic_intr120),
386         &IDTVEC(ioapic_intr121),
387         &IDTVEC(ioapic_intr122),
388         &IDTVEC(ioapic_intr123),
389         &IDTVEC(ioapic_intr124),
390         &IDTVEC(ioapic_intr125),
391         &IDTVEC(ioapic_intr126),
392         &IDTVEC(ioapic_intr127),
393         &IDTVEC(ioapic_intr128),
394         &IDTVEC(ioapic_intr129),
395         &IDTVEC(ioapic_intr130),
396         &IDTVEC(ioapic_intr131),
397         &IDTVEC(ioapic_intr132),
398         &IDTVEC(ioapic_intr133),
399         &IDTVEC(ioapic_intr134),
400         &IDTVEC(ioapic_intr135),
401         &IDTVEC(ioapic_intr136),
402         &IDTVEC(ioapic_intr137),
403         &IDTVEC(ioapic_intr138),
404         &IDTVEC(ioapic_intr139),
405         &IDTVEC(ioapic_intr140),
406         &IDTVEC(ioapic_intr141),
407         &IDTVEC(ioapic_intr142),
408         &IDTVEC(ioapic_intr143),
409         &IDTVEC(ioapic_intr144),
410         &IDTVEC(ioapic_intr145),
411         &IDTVEC(ioapic_intr146),
412         &IDTVEC(ioapic_intr147),
413         &IDTVEC(ioapic_intr148),
414         &IDTVEC(ioapic_intr149),
415         &IDTVEC(ioapic_intr150),
416         &IDTVEC(ioapic_intr151),
417         &IDTVEC(ioapic_intr152),
418         &IDTVEC(ioapic_intr153),
419         &IDTVEC(ioapic_intr154),
420         &IDTVEC(ioapic_intr155),
421         &IDTVEC(ioapic_intr156),
422         &IDTVEC(ioapic_intr157),
423         &IDTVEC(ioapic_intr158),
424         &IDTVEC(ioapic_intr159),
425         &IDTVEC(ioapic_intr160),
426         &IDTVEC(ioapic_intr161),
427         &IDTVEC(ioapic_intr162),
428         &IDTVEC(ioapic_intr163),
429         &IDTVEC(ioapic_intr164),
430         &IDTVEC(ioapic_intr165),
431         &IDTVEC(ioapic_intr166),
432         &IDTVEC(ioapic_intr167),
433         &IDTVEC(ioapic_intr168),
434         &IDTVEC(ioapic_intr169),
435         &IDTVEC(ioapic_intr170),
436         &IDTVEC(ioapic_intr171),
437         &IDTVEC(ioapic_intr172),
438         &IDTVEC(ioapic_intr173),
439         &IDTVEC(ioapic_intr174),
440         &IDTVEC(ioapic_intr175),
441         &IDTVEC(ioapic_intr176),
442         &IDTVEC(ioapic_intr177),
443         &IDTVEC(ioapic_intr178),
444         &IDTVEC(ioapic_intr179),
445         &IDTVEC(ioapic_intr180),
446         &IDTVEC(ioapic_intr181),
447         &IDTVEC(ioapic_intr182),
448         &IDTVEC(ioapic_intr183),
449         &IDTVEC(ioapic_intr184),
450         &IDTVEC(ioapic_intr185),
451         &IDTVEC(ioapic_intr186),
452         &IDTVEC(ioapic_intr187),
453         &IDTVEC(ioapic_intr188),
454         &IDTVEC(ioapic_intr189),
455         &IDTVEC(ioapic_intr190),
456         &IDTVEC(ioapic_intr191)
457 };
458
459 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
460
461 static struct ioapic_irqmap {
462         int                     im_type;        /* IOAPIC_IMT_ */
463         enum intr_trigger       im_trig;
464         enum intr_polarity      im_pola;
465         int                     im_gsi;
466         uint32_t                im_flags;       /* IOAPIC_IMF_ */
467 } ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
468
469 #define IOAPIC_IMT_UNUSED       0
470 #define IOAPIC_IMT_RESERVED     1
471 #define IOAPIC_IMT_LINE         2
472 #define IOAPIC_IMT_SYSCALL      3
473
474 #define IOAPIC_IMT_ISHWI(map)   ((map)->im_type != IOAPIC_IMT_RESERVED && \
475                                  (map)->im_type != IOAPIC_IMT_SYSCALL)
476
477 #define IOAPIC_IMF_CONF         0x1
478
479 extern void     IOAPIC_INTREN(int);
480 extern void     IOAPIC_INTRDIS(int);
481
482 extern int      imcr_present;
483
484 static void     ioapic_abi_intr_enable(int);
485 static void     ioapic_abi_intr_disable(int);
486 static void     ioapic_abi_intr_setup(int, int);
487 static void     ioapic_abi_intr_teardown(int);
488 static void     ioapic_abi_intr_config(int,
489                     enum intr_trigger, enum intr_polarity);
490 static int      ioapic_abi_intr_cpuid(int);
491
492 static void     ioapic_abi_finalize(void);
493 static void     ioapic_abi_cleanup(void);
494 static void     ioapic_abi_setdefault(void);
495 static void     ioapic_abi_stabilize(void);
496 static void     ioapic_abi_initmap(void);
497 static void     ioapic_abi_rman_setup(struct rman *);
498
499 static int      ioapic_abi_gsi_cpuid(int, int);
500
501 struct machintr_abi MachIntrABI_IOAPIC = {
502         MACHINTR_IOAPIC,
503
504         .intr_disable   = ioapic_abi_intr_disable,
505         .intr_enable    = ioapic_abi_intr_enable,
506         .intr_setup     = ioapic_abi_intr_setup,
507         .intr_teardown  = ioapic_abi_intr_teardown,
508         .intr_config    = ioapic_abi_intr_config,
509         .intr_cpuid     = ioapic_abi_intr_cpuid,
510
511         .finalize       = ioapic_abi_finalize,
512         .cleanup        = ioapic_abi_cleanup,
513         .setdefault     = ioapic_abi_setdefault,
514         .stabilize      = ioapic_abi_stabilize,
515         .initmap        = ioapic_abi_initmap,
516         .rman_setup     = ioapic_abi_rman_setup
517 };
518
519 static int      ioapic_abi_extint_irq = -1;
520 static int      ioapic_abi_line_irq_max;
521 static int      ioapic_abi_gsi_balance;
522
523 struct ioapic_irqinfo   ioapic_irqs[IOAPIC_HWI_VECTORS];
524
525 static void
526 ioapic_abi_intr_enable(int irq)
527 {
528         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
529                 kprintf("ioapic_abi_intr_enable invalid irq %d\n", irq);
530                 return;
531         }
532         IOAPIC_INTREN(irq);
533 }
534
535 static void
536 ioapic_abi_intr_disable(int irq)
537 {
538         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
539                 kprintf("ioapic_abi_intr_disable invalid irq %d\n", irq);
540                 return;
541         }
542         IOAPIC_INTRDIS(irq);
543 }
544
545 static void
546 ioapic_abi_finalize(void)
547 {
548         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
549         KKASSERT(ioapic_enable);
550
551         /*
552          * If an IMCR is present, program bit 0 to disconnect the 8259
553          * from the BSP.
554          */
555         if (imcr_present) {
556                 outb(0x22, 0x70);       /* select IMCR */
557                 outb(0x23, 0x01);       /* disconnect 8259 */
558         }
559 }
560
561 /*
562  * This routine is called after physical interrupts are enabled but before
563  * the critical section is released.  We need to clean out any interrupts
564  * that had already been posted to the cpu.
565  */
566 static void
567 ioapic_abi_cleanup(void)
568 {
569         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
570 }
571
572 /* Must never be called */
573 static void
574 ioapic_abi_stabilize(void)
575 {
576         panic("ioapic_stabilize() is called\n");
577 }
578
579 static void
580 ioapic_abi_intr_setup(int intr, int flags)
581 {
582         int vector, select;
583         uint32_t value;
584         u_long ef;
585
586         KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
587             intr != IOAPIC_HWI_SYSCALL);
588         KKASSERT(ioapic_irqs[intr].io_addr != NULL);
589
590         ef = read_eflags();
591         cpu_disable_intr();
592
593         vector = IDT_OFFSET + intr;
594
595         /*
596          * Now reprogram the vector in the IO APIC.  In order to avoid
597          * losing an EOI for a level interrupt, which is vector based,
598          * make sure that the IO APIC is programmed for edge-triggering
599          * first, then reprogrammed with the new vector.  This should
600          * clear the IRR bit.
601          */
602         imen_lock();
603
604         select = ioapic_irqs[intr].io_idx;
605         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
606         value |= IOART_INTMSET;
607
608         ioapic_write(ioapic_irqs[intr].io_addr, select,
609             (value & ~APIC_TRIGMOD_MASK));
610         ioapic_write(ioapic_irqs[intr].io_addr, select,
611             (value & ~IOART_INTVEC) | vector);
612
613         imen_unlock();
614
615         machintr_intr_enable(intr);
616
617         write_eflags(ef);
618 }
619
620 static void
621 ioapic_abi_intr_teardown(int intr)
622 {
623         int vector, select;
624         uint32_t value;
625         u_long ef;
626
627         KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
628             intr != IOAPIC_HWI_SYSCALL);
629         KKASSERT(ioapic_irqs[intr].io_addr != NULL);
630
631         ef = read_eflags();
632         cpu_disable_intr();
633
634         /*
635          * Teardown an interrupt vector.  The vector should already be
636          * installed in the cpu's IDT, but make sure.
637          */
638         machintr_intr_disable(intr);
639
640         vector = IDT_OFFSET + intr;
641
642         /*
643          * In order to avoid losing an EOI for a level interrupt, which
644          * is vector based, make sure that the IO APIC is programmed for
645          * edge-triggering first, then reprogrammed with the new vector.
646          * This should clear the IRR bit.
647          */
648         imen_lock();
649
650         select = ioapic_irqs[intr].io_idx;
651         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
652
653         ioapic_write(ioapic_irqs[intr].io_addr, select,
654             (value & ~APIC_TRIGMOD_MASK));
655         ioapic_write(ioapic_irqs[intr].io_addr, select,
656             (value & ~IOART_INTVEC) | vector);
657
658         imen_unlock();
659
660         write_eflags(ef);
661 }
662
663 static void
664 ioapic_abi_setdefault(void)
665 {
666         int intr;
667
668         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
669                 if (intr == IOAPIC_HWI_SYSCALL)
670                         continue;
671                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
672                        SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
673         }
674 }
675
676 static void
677 ioapic_abi_initmap(void)
678 {
679         int cpu;
680
681         kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
682
683         /*
684          * NOTE: ncpus is not ready yet
685          */
686         for (cpu = 0; cpu < MAXCPU; ++cpu) {
687                 int i;
688
689                 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
690                         ioapic_irqmaps[cpu][i].im_gsi = -1;
691                 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
692                     IOAPIC_IMT_SYSCALL;
693         }
694 }
695
696 void
697 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
698     enum intr_polarity pola)
699 {
700         struct ioapic_irqinfo *info;
701         struct ioapic_irqmap *map;
702         void *ioaddr;
703         int pin, cpuid;
704
705         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
706         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
707
708         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
709         if (irq > ioapic_abi_line_irq_max)
710                 ioapic_abi_line_irq_max = irq;
711
712         cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
713
714         map = &ioapic_irqmaps[cpuid][irq];
715
716         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
717         map->im_type = IOAPIC_IMT_LINE;
718
719         map->im_gsi = gsi;
720         map->im_trig = trig;
721         map->im_pola = pola;
722
723         if (bootverbose) {
724                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
725                         irq, map->im_gsi,
726                         intr_str_trigger(map->im_trig),
727                         intr_str_polarity(map->im_pola));
728         }
729
730         pin = ioapic_gsi_pin(map->im_gsi);
731         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
732
733         info = &ioapic_irqs[irq];
734
735         imen_lock();
736
737         info->io_addr = ioaddr;
738         info->io_idx = IOAPIC_REDTBL + (2 * pin);
739         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
740         if (map->im_trig == INTR_TRIGGER_LEVEL)
741                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
742
743         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
744             map->im_trig, map->im_pola, cpuid);
745
746         imen_unlock();
747 }
748
749 void
750 ioapic_abi_fixup_irqmap(void)
751 {
752         int cpu;
753
754         for (cpu = 0; cpu < ncpus; ++cpu) {
755                 int i;
756
757                 for (i = 0; i < ISA_IRQ_CNT; ++i) {
758                         struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
759
760                         if (map->im_type == IOAPIC_IMT_UNUSED) {
761                                 map->im_type = IOAPIC_IMT_RESERVED;
762                                 if (bootverbose) {
763                                         kprintf("IOAPIC: "
764                                             "cpu%d irq %d reserved\n", cpu, i);
765                                 }
766                         }
767                 }
768         }
769
770         ioapic_abi_line_irq_max += 1;
771         if (bootverbose)
772                 kprintf("IOAPIC: line irq max %d\n", ioapic_abi_line_irq_max);
773 }
774
775 int
776 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
777 {
778         int cpu;
779
780         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
781         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
782
783         for (cpu = 0; cpu < ncpus; ++cpu) {
784                 int irq;
785
786                 for (irq = 0; irq < ioapic_abi_line_irq_max; ++irq) {
787                         const struct ioapic_irqmap *map =
788                             &ioapic_irqmaps[cpu][irq];
789
790                         if (map->im_gsi == gsi) {
791                                 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
792
793                                 if (map->im_flags & IOAPIC_IMF_CONF) {
794                                         if (map->im_trig != trig ||
795                                             map->im_pola != pola)
796                                                 return -1;
797                                 }
798                                 return irq;
799                         }
800                 }
801         }
802         return -1;
803 }
804
805 int
806 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
807 {
808         int cpu;
809
810         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
811         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
812
813         if (irq < 0 || irq >= ioapic_abi_line_irq_max)
814                 return -1;
815
816         for (cpu = 0; cpu < ncpus; ++cpu) {
817                 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
818
819                 if (map->im_type == IOAPIC_IMT_LINE) {
820                         if (map->im_flags & IOAPIC_IMF_CONF) {
821                                 if (map->im_trig != trig ||
822                                     map->im_pola != pola)
823                                         return -1;
824                         }
825                         return irq;
826                 }
827         }
828         return -1;
829 }
830
831 static void
832 ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
833 {
834         struct ioapic_irqinfo *info;
835         struct ioapic_irqmap *map = NULL;
836         void *ioaddr;
837         int pin, cpuid;
838
839         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
840         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
841
842         KKASSERT(irq >= 0 && irq < ioapic_abi_line_irq_max);
843         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
844                 map = &ioapic_irqmaps[cpuid][irq];
845                 if (map->im_type == IOAPIC_IMT_LINE)
846                         break;
847         }
848         KKASSERT(cpuid < ncpus);
849
850 #ifdef notyet
851         if (map->im_flags & IOAPIC_IMF_CONF) {
852                 if (trig != map->im_trig) {
853                         panic("ioapic_intr_config: trig %s -> %s\n",
854                               intr_str_trigger(map->im_trig),
855                               intr_str_trigger(trig));
856                 }
857                 if (pola != map->im_pola) {
858                         panic("ioapic_intr_config: pola %s -> %s\n",
859                               intr_str_polarity(map->im_pola),
860                               intr_str_polarity(pola));
861                 }
862                 return;
863         }
864 #endif
865         map->im_flags |= IOAPIC_IMF_CONF;
866
867         if (trig == map->im_trig && pola == map->im_pola)
868                 return;
869
870         if (bootverbose) {
871                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
872                         irq, map->im_gsi,
873                         intr_str_trigger(map->im_trig),
874                         intr_str_polarity(map->im_pola),
875                         intr_str_trigger(trig),
876                         intr_str_polarity(pola));
877         }
878         map->im_trig = trig;
879         map->im_pola = pola;
880
881         pin = ioapic_gsi_pin(map->im_gsi);
882         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
883
884         info = &ioapic_irqs[irq];
885
886         imen_lock();
887
888         info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
889         if (map->im_trig == INTR_TRIGGER_LEVEL)
890                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
891
892         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
893             map->im_trig, map->im_pola, cpuid);
894
895         imen_unlock();
896 }
897
898 int
899 ioapic_abi_extint_irqmap(int irq)
900 {
901         struct ioapic_irqinfo *info;
902         struct ioapic_irqmap *map;
903         void *ioaddr;
904         int pin, error, vec;
905
906         /* XXX only irq0 is allowed */
907         KKASSERT(irq == 0);
908
909         vec = IDT_OFFSET + irq;
910
911         if (ioapic_abi_extint_irq == irq)
912                 return 0;
913         else if (ioapic_abi_extint_irq >= 0)
914                 return EEXIST;
915
916         error = icu_ioapic_extint(irq, vec);
917         if (error)
918                 return error;
919
920         /* ExtINT is always targeted to cpu0 */
921         map = &ioapic_irqmaps[0][irq];
922
923         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
924                  map->im_type == IOAPIC_IMT_LINE);
925         if (map->im_type == IOAPIC_IMT_LINE) {
926                 if (map->im_flags & IOAPIC_IMF_CONF)
927                         return EEXIST;
928         }
929         ioapic_abi_extint_irq = irq;
930
931         map->im_type = IOAPIC_IMT_LINE;
932         map->im_trig = INTR_TRIGGER_EDGE;
933         map->im_pola = INTR_POLARITY_HIGH;
934         map->im_flags = IOAPIC_IMF_CONF;
935
936         map->im_gsi = ioapic_extpin_gsi();
937         KKASSERT(map->im_gsi >= 0);
938
939         if (bootverbose) {
940                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
941                         irq, map->im_gsi,
942                         intr_str_trigger(map->im_trig),
943                         intr_str_polarity(map->im_pola));
944         }
945
946         pin = ioapic_gsi_pin(map->im_gsi);
947         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
948
949         info = &ioapic_irqs[irq];
950
951         imen_lock();
952
953         info->io_addr = ioaddr;
954         info->io_idx = IOAPIC_REDTBL + (2 * pin);
955         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
956
957         ioapic_extpin_setup(ioaddr, pin, vec);
958
959         imen_unlock();
960
961         return 0;
962 }
963
964 static int
965 ioapic_abi_intr_cpuid(int irq)
966 {
967         const struct ioapic_irqmap *map = NULL;
968         int cpuid;
969
970         KKASSERT(irq >= 0 && irq < ioapic_abi_line_irq_max);
971
972         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
973                 map = &ioapic_irqmaps[cpuid][irq];
974                 if (map->im_type == IOAPIC_IMT_LINE)
975                         return cpuid;
976         }
977
978         /* XXX some drivers tries to peek at reserved IRQs */
979         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
980                 map = &ioapic_irqmaps[cpuid][irq];
981                 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
982         }
983         return 0;
984 }
985
986 static int
987 ioapic_abi_gsi_cpuid(int irq, int gsi)
988 {
989         char envpath[32];
990         int cpuid = -1;
991
992         KKASSERT(gsi >= 0);
993
994         if (!ioapic_abi_gsi_balance)
995                 return 0;
996
997         if (irq == 0 || gsi == 0) {
998                 if (bootverbose) {
999                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1000                             irq, gsi);
1001                 }
1002                 return 0;
1003         }
1004
1005         if (irq == acpi_sci_irqno()) {
1006                 if (bootverbose) {
1007                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1008                             irq, gsi);
1009                 }
1010                 return 0;
1011         }
1012
1013         ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1014         kgetenv_int(envpath, &cpuid);
1015
1016         if (cpuid < 0) {
1017                 cpuid = gsi % ncpus;
1018                 if (bootverbose) {
1019                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1020                             irq, gsi, cpuid);
1021                 }
1022         } else if (cpuid >= ncpus) {
1023                 cpuid = ncpus - 1;
1024                 if (bootverbose) {
1025                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1026                             irq, gsi, cpuid);
1027                 }
1028         } else {
1029                 if (bootverbose) {
1030                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1031                             irq, gsi, cpuid);
1032                 }
1033         }
1034         return cpuid;
1035 }
1036
1037 static void
1038 ioapic_abi_rman_setup(struct rman *rm)
1039 {
1040         int start, end, i;
1041
1042         KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1043             ("invalid rman cpuid %d", rm->rm_cpuid));
1044
1045         start = end = -1;
1046         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1047                 const struct ioapic_irqmap *map =
1048                     &ioapic_irqmaps[rm->rm_cpuid][i];
1049
1050                 if (start < 0) {
1051                         if (IOAPIC_IMT_ISHWI(map))
1052                                 start = end = i;
1053                 } else {
1054                         if (IOAPIC_IMT_ISHWI(map)) {
1055                                 end = i;
1056                         } else {
1057                                 KKASSERT(end >= 0);
1058                                 if (bootverbose) {
1059                                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1060                                             rm->rm_cpuid, start, end);
1061                                 }
1062                                 if (rman_manage_region(rm, start, end)) {
1063                                         panic("rman_manage_region"
1064                                             "(cpu%d %d - %d)", rm->rm_cpuid,
1065                                             start, end);
1066                                 }
1067                                 start = end = -1;
1068                         }
1069                 }
1070         }
1071         if (start >= 0) {
1072                 KKASSERT(end >= 0);
1073                 if (bootverbose) {
1074                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1075                             rm->rm_cpuid, start, end);
1076                 }
1077                 if (rman_manage_region(rm, start, end)) {
1078                         panic("rman_manage_region(cpu%d %d - %d)",
1079                             rm->rm_cpuid, start, end);
1080                 }
1081         }
1082 }