2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ar5212/ar5212.h"
25 #include "ar5212/ar5212reg.h"
26 #include "ar5212/ar5212desc.h"
29 * Return the hardware NextTBTT in TSF
32 ar5212GetNextTBTT(struct ath_hal *ah)
34 #define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10)
35 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
40 * Initialize all of the hardware registers used to
41 * send beacons. Note that for station operation the
42 * driver calls ar5212SetStaBeaconTimers instead.
45 ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
47 struct ath_hal_5212 *ahp = AH5212(ah);
50 * Limit the timers to their specific resolutions:
52 * + Timer 0 - 0..15 0xffff TU
53 * + Timer 1 - 0..18 0x7ffff TU/8
54 * + Timer 2 - 0..24 0x1ffffff TU/8
55 * + Timer 3 - 0..15 0xffff TU
57 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt & 0xffff);
58 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba & 0x7ffff);
59 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba & 0x1ffffff);
60 /* XXX force nextatim to be non-zero? */
61 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim & 0xffff);
63 * Set the Beacon register after setting all timers.
65 if (bt->bt_intval & AR_BEACON_RESET_TSF) {
67 * When resetting the TSF,
68 * write twice to the corresponding register; each
69 * write to the RESET_TSF bit toggles the internal
70 * signal to cause a reset of the TSF - but if the signal
71 * is left high, it will reset the TSF on the next
72 * chip reset also! writing the bit an even number
73 * of times fixes this issue
75 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
77 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
78 ahp->ah_beaconInterval = (bt->bt_intval & HAL_BEACON_PERIOD);
82 * Old api for setting up beacon timer registers when
83 * operating in !station mode. Note the fixed constants
84 * adjusting the DBA and SWBA timers and the fixed ATIM
88 ar5212BeaconInit(struct ath_hal *ah,
89 uint32_t next_beacon, uint32_t beacon_period)
93 bzero(&bt, sizeof(bt));
94 bt.bt_nexttbtt = next_beacon;
96 * TIMER1: in AP/adhoc mode this controls the DMA beacon
97 * alert timer; otherwise it controls the next wakeup time.
98 * TIMER2: in AP mode, it controls the SBA beacon alert
99 * interrupt; otherwise it sets the start of the next CFP.
101 switch (AH_PRIVATE(ah)->ah_opmode) {
104 bt.bt_nextdba = 0xffff;
105 bt.bt_nextswba = 0x7ffff;
109 bt.bt_nextdba = (next_beacon -
110 ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */
111 bt.bt_nextswba = (next_beacon -
112 ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */
116 * Set the ATIM window
117 * Our hardware does not support an ATIM window of 0
118 * (beacons will not work). If the ATIM windows is 0,
121 bt.bt_nextatim = next_beacon + 1;
122 bt.bt_intval = beacon_period &
123 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
124 ar5212SetBeaconTimers(ah, &bt);
128 ar5212ResetStaBeaconTimers(struct ath_hal *ah)
132 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
133 val = OS_REG_READ(ah, AR_STA_ID1);
134 val |= AR_STA_ID1_PWR_SAV; /* XXX */
135 /* tell the h/w that the associated AP is not PCF capable */
136 OS_REG_WRITE(ah, AR_STA_ID1,
137 val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
138 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
142 * Set all the beacon related bits on the h/w for stations
143 * i.e. initializes the corresponding h/w timers;
144 * also tells the h/w whether to anticipate PCF beacons
147 ar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
149 struct ath_hal_5212 *ahp = AH5212(ah);
150 uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
152 HALASSERT(bs->bs_intval != 0);
153 /* if the AP will do PCF */
154 if (bs->bs_cfpmaxduration != 0) {
155 /* tell the h/w that the associated AP is PCF capable */
156 OS_REG_WRITE(ah, AR_STA_ID1,
157 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
159 /* set CFP_PERIOD(1.024ms) register */
160 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
162 /* set CFP_DUR(1.024ms) register to max cfp duration */
163 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
165 /* set TIMER2(128us) to anticipated time of next CFP */
166 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
168 /* tell the h/w that the associated AP is not PCF capable */
169 OS_REG_WRITE(ah, AR_STA_ID1,
170 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
174 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
176 OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
179 * Start the beacon timers by setting the BEACON register
180 * to the beacon interval; also write the tim offset which
181 * we should know by now. The code, in ar5211WriteAssocid,
182 * also sets the tim offset once the AID is known which can
183 * be left as such for now.
185 OS_REG_WRITE(ah, AR_BEACON,
186 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
187 | SM(bs->bs_intval, AR_BEACON_PERIOD)
188 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
192 * Configure the BMISS interrupt. Note that we
193 * assume the caller blocks interrupts while enabling
196 HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
197 ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
198 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
199 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
202 * Program the sleep registers to correlate with the beacon setup.
206 * Oahu beacons timers on the station were used for power
207 * save operation (waking up in anticipation of a beacon)
208 * and any CFP function; Venice does sleep/power-save timers
209 * differently - so this is the right place to set them up;
210 * don't think the beacon timers are used by venice sta hw
211 * for any useful purpose anymore
212 * Setup venice's sleep related timers
213 * Current implementation assumes sw processing of beacons -
214 * assuming an interrupt is generated every beacon which
215 * causes the hardware to become awake until the sw tells
216 * it to go to sleep again; beacon timeout is to allow for
217 * beacon jitter; cab timeout is max time to wait for cab
218 * after seeing the last DTIM or MORE CAB bit
220 #define CAB_TIMEOUT_VAL 10 /* in TU */
221 #define BEACON_TIMEOUT_VAL 10 /* in TU */
222 #define SLEEP_SLOP 3 /* in TU */
225 * For max powersave mode we may want to sleep for longer than a
226 * beacon period and not want to receive all beacons; modify the
227 * timers accordingly; make sure to align the next TIM to the
228 * next DTIM if we decide to wake for DTIMs only
230 beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
231 HALASSERT(beaconintval != 0);
232 if (bs->bs_sleepduration > beaconintval) {
233 HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
234 bs->bs_sleepduration);
235 beaconintval = bs->bs_sleepduration;
237 dtimperiod = bs->bs_dtimperiod;
238 if (bs->bs_sleepduration > dtimperiod) {
239 HALASSERT(dtimperiod == 0 ||
240 roundup(bs->bs_sleepduration, dtimperiod) ==
241 bs->bs_sleepduration);
242 dtimperiod = bs->bs_sleepduration;
244 HALASSERT(beaconintval <= dtimperiod);
245 if (beaconintval == dtimperiod)
246 nextTbtt = bs->bs_nextdtim;
248 nextTbtt = bs->bs_nexttbtt;
249 nextdtim = bs->bs_nextdtim;
251 OS_REG_WRITE(ah, AR_SLEEP1,
252 SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM)
253 | SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT)
254 | AR_SLEEP1_ASSUME_DTIM
255 | AR_SLEEP1_ENH_SLEEP_ENA
257 OS_REG_WRITE(ah, AR_SLEEP2,
258 SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM)
259 | SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT)
261 OS_REG_WRITE(ah, AR_SLEEP3,
262 SM(beaconintval, AR_SLEEP3_TIM_PERIOD)
263 | SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD)
265 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
266 __func__, bs->bs_nextdtim);
267 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
269 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
270 __func__, beaconintval);
271 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
272 __func__, dtimperiod);
273 #undef CAB_TIMEOUT_VAL
274 #undef BEACON_TIMEOUT_VAL