2 * from: vector.s, 386BSD 0.1 unknown origin
3 * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.47.2.5 2001/09/01 22:33:38 tegge Exp $
7 #include "opt_auto_eoi.h"
10 #include <machine/asmacros.h>
11 #include <machine/lock.h>
12 #include <machine/psl.h>
13 #include <machine/trap.h>
14 #include <machine/segments.h>
16 #include <machine_base/icu/icu.h>
17 #include <bus/isa/isa.h>
22 #include <machine_base/apic/ioapic_ipl.h>
23 #include <machine/intr_machdep.h>
26 /* convert an absolute IRQ# into bitmask */
27 #define IRQ_LBIT(irq_num) (1UL << (irq_num & 0x3f))
30 #define IRQ_SBITS(irq_num) ((irq_num) & 0x3f)
32 /* convert an absolute IRQ# into gd_ipending index */
33 #define IRQ_LIDX(irq_num) ((irq_num) >> 6)
36 #define MPLOCKED lock ;
41 #define APIC_PUSH_FRAME \
42 PUSH_FRAME ; /* 15 regs + space for 5 extras */ \
43 movq $0,TF_XFLAGS(%rsp) ; \
44 movq $0,TF_TRAPNO(%rsp) ; \
45 movq $0,TF_ADDR(%rsp) ; \
46 movq $0,TF_FLAGS(%rsp) ; \
47 movq $0,TF_ERR(%rsp) ; \
51 * JG stale? Warning: POP_FRAME can only be used if there is no chance of a
52 * segment register being changed (e.g. by procfs), which is why syscalls
55 #define APIC_POP_FRAME POP_FRAME
57 #define IOAPICADDR(irq_num) \
58 CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_ADDR
59 #define REDIRIDX(irq_num) \
60 CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_ENTIDX
61 #define IOAPICFLAGS(irq_num) \
62 CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_FLAGS
64 #define MASK_IRQ(irq_num) \
65 IOAPIC_IMASK_LOCK ; /* into critical reg */ \
66 testl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
67 jne 7f ; /* masked, don't mask */ \
68 orl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
69 /* set the mask bit */ \
70 movq IOAPICADDR(irq_num), %rcx ; /* ioapic addr */ \
71 movl REDIRIDX(irq_num), %eax ; /* get the index */ \
72 movl %eax, (%rcx) ; /* write the index */ \
73 orl $IOART_INTMASK,IOAPIC_WINDOW(%rcx) ;/* set the mask */ \
74 7: ; /* already masked */ \
75 IOAPIC_IMASK_UNLOCK ; \
78 * Test to see whether we are handling an edge or level triggered INT.
79 * Level-triggered INTs must still be masked as we don't clear the source,
80 * and the EOI cycle would cause redundant INTs to occur.
82 #define MASK_LEVEL_IRQ(irq_num) \
83 testl $IOAPIC_IM_FLAG_LEVEL, IOAPICFLAGS(irq_num) ; \
84 jz 9f ; /* edge, don't mask */ \
89 * Test to see if the source is currntly masked, clear if so.
91 #define UNMASK_IRQ(irq_num) \
94 IOAPIC_IMASK_LOCK ; /* into critical reg */ \
95 testl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
96 je 7f ; /* bit clear, not masked */ \
97 andl $~IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
98 /* clear mask bit */ \
99 movq IOAPICADDR(irq_num),%rcx ; /* ioapic addr */ \
100 movl REDIRIDX(irq_num), %eax ; /* get the index */ \
101 movl %eax,(%rcx) ; /* write the index */ \
102 andl $~IOART_INTMASK,IOAPIC_WINDOW(%rcx) ;/* clear the mask */ \
104 IOAPIC_IMASK_UNLOCK ; \
108 * Interrupt call handlers run in the following sequence:
110 * - Push the trap frame required by doreti
111 * - Mask the interrupt and reenable its source
112 * - If we cannot take the interrupt set its ipending bit and
114 * - If we can take the interrupt clear its ipending bit,
115 * call the handler, then unmask and doreti.
117 * YYY can cache gd base opitner instead of using hidden %fs prefixes.
120 #define INTR_HANDLER(irq_num) \
123 IDTVEC(ioapic_intr##irq_num) ; \
125 FAKE_MCOUNT(TF_RIP(%rsp)) ; \
126 MASK_LEVEL_IRQ(irq_num) ; \
128 movl $0, LA_EOI(%rax) ; \
129 movq PCPU(curthread),%rbx ; \
130 testl $-1,TD_NEST_COUNT(%rbx) ; \
132 testl $-1,TD_CRITCOUNT(%rbx) ; \
135 /* in critical section, make interrupt pending */ \
136 /* set the pending bit and return, leave interrupt masked */ \
138 shlq $IRQ_SBITS(irq_num),%rcx ; \
139 movq $IRQ_LIDX(irq_num),%rdx ; \
140 orq %rcx,PCPU_E8(ipending,%rdx) ; \
141 orl $RQF_INTPEND,PCPU(reqflags) ; \
144 /* clear pending bit, run handler */ \
146 shlq $IRQ_SBITS(irq_num),%rcx ; \
148 movq $IRQ_LIDX(irq_num),%rdx ; \
149 andq %rcx,PCPU_E8(ipending,%rdx) ; \
150 pushq $irq_num ; /* trapframe -> intrframe */ \
151 movq %rsp, %rdi ; /* pass frame by reference */ \
152 incl TD_CRITCOUNT(%rbx) ; \
154 call ithread_fast_handler ; /* returns 0 to unmask */ \
155 decl TD_CRITCOUNT(%rbx) ; \
156 addq $8, %rsp ; /* intrframe -> trapframe */ \
157 UNMASK_IRQ(irq_num) ; \
163 * Handle "spurious INTerrupts".
165 * This is different than the "spurious INTerrupt" generated by an
166 * 8259 PIC for missing INTs. See the APIC documentation for details.
167 * This routine should NOT do an 'EOI' cycle.
174 /* No EOI cycle used here */
181 * Handle TLB shootdowns.
183 * NOTE: interrupts are left disabled.
191 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
192 FAKE_MCOUNT(TF_RIP(%rsp))
193 subq $8,%rsp /* make same as interrupt frame */
194 movq %rsp,%rdi /* pass frame by reference */
195 call smp_invltlb_intr
196 addq $8,%rsp /* turn into trapframe */
202 * Executed by a CPU when it receives an Xcpustop IPI from another CPU,
204 * - We cannot call doreti
205 * - Signals its receipt.
206 * - Waits for permission to restart.
207 * - Processing pending IPIQ events while waiting.
208 * - Signals its restart.
217 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
219 movl PCPU(cpuid), %eax
220 imull $PCB_SIZE, %eax
221 leaq CNAME(stoppcbs), %rdi
223 call CNAME(savectx) /* Save process context */
225 movslq PCPU(cpuid), %rax
228 * Indicate that we have stopped and loop waiting for permission
229 * to start again. We must still process IPI events while in a
232 * Interrupts must remain enabled for non-IPI'd per-cpu interrupts
233 * (e.g. Xtimer, Xinvltlb).
236 btsq %rax, stopped_cpus /* stopped_cpus |= (1<<id) */
239 andl $~RQF_IPIQ,PCPU(reqflags)
241 call lwkt_smp_stopped
244 btq %rax, started_cpus /* while (!(started_cpus & (1<<id))) */
248 btrq %rax, started_cpus /* started_cpus &= ~(1<<id) */
250 btrq %rax, stopped_cpus /* stopped_cpus &= ~(1<<id) */
255 movq CNAME(cpustop_restartfunc), %rax
258 movq $0, CNAME(cpustop_restartfunc) /* One-shot */
267 * For now just have one ipiq IPI, but what we really want is
268 * to have one for each source cpu to the APICs don't get stalled
269 * backlogging the requests.
277 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
278 FAKE_MCOUNT(TF_RIP(%rsp))
280 incl PCPU(cnt) + V_IPI
281 movq PCPU(curthread),%rbx
282 testl $-1,TD_CRITCOUNT(%rbx)
284 subq $8,%rsp /* make same as interrupt frame */
285 movq %rsp,%rdi /* pass frame by reference */
286 incl PCPU(intr_nesting_level)
287 incl TD_CRITCOUNT(%rbx)
289 call lwkt_process_ipiq_frame
290 decl TD_CRITCOUNT(%rbx)
291 decl PCPU(intr_nesting_level)
292 addq $8,%rsp /* turn into trapframe */
296 orl $RQF_IPIQ,PCPU(reqflags)
309 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */
310 FAKE_MCOUNT(TF_RIP(%rsp))
312 subq $8,%rsp /* make same as interrupt frame */
313 movq %rsp,%rdi /* pass frame by reference */
314 call lapic_timer_always
315 addq $8,%rsp /* turn into trapframe */
317 incl PCPU(cnt) + V_TIMER
318 movq PCPU(curthread),%rbx
319 testl $-1,TD_CRITCOUNT(%rbx)
321 testl $-1,TD_NEST_COUNT(%rbx)
323 subq $8,%rsp /* make same as interrupt frame */
324 movq %rsp,%rdi /* pass frame by reference */
325 incl PCPU(intr_nesting_level)
326 incl TD_CRITCOUNT(%rbx)
328 call lapic_timer_process_frame
329 decl TD_CRITCOUNT(%rbx)
330 decl PCPU(intr_nesting_level)
331 addq $8,%rsp /* turn into trapframe */
335 orl $RQF_TIMER,PCPU(reqflags)
537 /* variables used by stop_cpus()/restart_cpus()/Xcpustop */
538 .globl stopped_cpus, started_cpus
544 .globl CNAME(cpustop_restartfunc)
545 CNAME(cpustop_restartfunc):