2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
37 * Functions to provide access to special i386 instructions.
40 #ifndef _CPU_CPUFUNC_H_
41 #define _CPU_CPUFUNC_H_
44 #include <sys/types.h>
47 #include <sys/cdefs.h>
51 #define readb(va) (*(volatile u_int8_t *) (va))
52 #define readw(va) (*(volatile u_int16_t *) (va))
53 #define readl(va) (*(volatile u_int32_t *) (va))
55 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
56 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
57 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #include <machine/lock.h> /* XXX */
65 #ifdef SWTCH_OPTIM_STATS
66 extern int tlb_flush_count; /* XXX */
72 __asm __volatile("int $3");
78 __asm __volatile("pause");
82 * Find the first 1 in mask, starting with bit 0 and return the
83 * bit number. If mask is 0 the result is undefined.
90 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
95 * Find the last 1 in mask, starting with bit 31 and return the
96 * bit number. If mask is 0 the result is undefined.
103 __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
108 * Test and set the specified bit (1 << bit) in the integer. The
109 * previous value of the bit is returned (0 or 1).
112 btsl(u_int *mask, int bit)
116 __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
117 "=r"(result), "=m"(*mask) : "r" (bit));
122 * Test and clear the specified bit (1 << bit) in the integer. The
123 * previous value of the bit is returned (0 or 1).
126 btrl(u_int *mask, int bit)
130 __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
131 "=r"(result), "=m"(*mask) : "r" (bit));
136 do_cpuid(u_int ax, u_int *p)
138 __asm __volatile("cpuid"
139 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
144 cpuid_count(u_int ax, u_int cx, u_int *p)
146 __asm __volatile("cpuid"
147 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
148 : "0" (ax), "c" (cx));
151 #ifndef _CPU_DISABLE_INTR_DEFINED
154 cpu_disable_intr(void)
156 __asm __volatile("cli" : : : "memory");
161 #ifndef _CPU_ENABLE_INTR_DEFINED
164 cpu_enable_intr(void)
166 __asm __volatile("sti");
172 * Cpu and compiler memory ordering fence. mfence ensures strong read and
175 * A serializing or fence instruction is required here. A locked bus
176 * cycle on data for which we already own cache mastership is the most
184 __asm __volatile("mfence" : : : "memory");
186 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
189 __asm __volatile("" : : : "memory");
194 * cpu_lfence() ensures strong read ordering for reads issued prior
195 * to the instruction verses reads issued afterwords.
197 * A serializing or fence instruction is required here. A locked bus
198 * cycle on data for which we already own cache mastership is the most
206 __asm __volatile("lfence" : : : "memory");
208 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
211 __asm __volatile("" : : : "memory");
216 * cpu_sfence() ensures strong write ordering for writes issued prior
217 * to the instruction verses writes issued afterwords. Writes are
218 * ordered on intel cpus so we do not actually have to do anything.
225 * Don't use 'sfence' here, as it will create a lot of
226 * unnecessary stalls.
228 __asm __volatile("" : : : "memory");
232 * cpu_ccfence() prevents the compiler from reordering instructions, in
233 * particular stores, relative to the current cpu. Use cpu_sfence() if
234 * you need to guarentee ordering by both the compiler and by the cpu.
236 * This also prevents the compiler from caching memory loads into local
237 * variables across the routine.
242 __asm __volatile("" : : : "memory");
247 #define HAVE_INLINE_FFS
253 * Note that gcc-2's builtin ffs would be used if we didn't declare
254 * this inline or turn off the builtin. The builtin is faster but
255 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
258 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
261 #define HAVE_INLINE_FLS
266 return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
272 * The following complications are to get around gcc not having a
273 * constraint letter for the range 0..255. We still put "d" in the
274 * constraint because "i" isn't a valid constraint when the port
275 * isn't constant. This only matters for -O0 because otherwise
276 * the non-working version gets optimized away.
278 * Use an expression-statement instead of a conditional expression
279 * because gcc-2.6.0 would promote the operands of the conditional
280 * and produce poor code for "if ((inb(var) & const1) == const2)".
282 * The unnecessary test `(port) < 0x10000' is to generate a warning if
283 * the `port' has type u_short or smaller. Such types are pessimal.
284 * This actually only works for signed types. The range check is
285 * careful to avoid generating warnings.
287 #define inb(port) __extension__ ({ \
289 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
290 && (port) < 0x10000) \
291 _data = inbc(port); \
293 _data = inbv(port); \
296 #define outb(port, data) ( \
297 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
298 && (port) < 0x10000 \
299 ? outbc(port, data) : outbv(port, data))
301 static __inline u_char
306 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
311 outbc(u_int port, u_char data)
313 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
316 static __inline u_char
321 * We use %%dx and not %1 here because i/o is done at %dx and not at
322 * %edx, while gcc generates inferior code (movw instead of movl)
323 * if we tell it to load (u_short) port.
325 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
329 static __inline u_int
334 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
339 insb(u_int port, void *addr, size_t cnt)
341 __asm __volatile("cld; rep; insb"
342 : "=D" (addr), "=c" (cnt)
343 : "0" (addr), "1" (cnt), "d" (port)
348 insw(u_int port, void *addr, size_t cnt)
350 __asm __volatile("cld; rep; insw"
351 : "=D" (addr), "=c" (cnt)
352 : "0" (addr), "1" (cnt), "d" (port)
357 insl(u_int port, void *addr, size_t cnt)
359 __asm __volatile("cld; rep; insl"
360 : "=D" (addr), "=c" (cnt)
361 : "0" (addr), "1" (cnt), "d" (port)
368 __asm __volatile("invd");
374 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
375 * will cause the invl*() functions to be equivalent to the cpu_invl*()
379 void smp_invltlb(void);
380 void smp_invltlb_intr(void);
382 #define smp_invltlb()
385 #ifndef _CPU_INVLPG_DEFINED
388 * Invalidate a patricular VA on this cpu only
391 cpu_invlpg(void *addr)
393 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
398 #ifndef _CPU_INVLTLB_DEFINED
401 * Invalidate the TLB on this cpu only
408 * This should be implemented as load_cr3(rcr3()) when load_cr3()
411 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
413 #if defined(SWTCH_OPTIM_STATS)
423 __asm __volatile("rep; nop");
428 static __inline u_short
433 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
437 static __inline u_int
438 loadandclear(volatile u_int *addr)
442 __asm __volatile("xorl %0,%0; xchgl %1,%0"
443 : "=&r" (result) : "m" (*addr));
448 outbv(u_int port, u_char data)
452 * Use an unnecessary assignment to help gcc's register allocator.
453 * This make a large difference for gcc-1.40 and a tiny difference
454 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
455 * best results. gcc-2.6.0 can't handle this.
458 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
462 outl(u_int port, u_int data)
465 * outl() and outw() aren't used much so we haven't looked at
466 * possible micro-optimizations such as the unnecessary
467 * assignment for them.
469 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
473 outsb(u_int port, const void *addr, size_t cnt)
475 __asm __volatile("cld; rep; outsb"
476 : "=S" (addr), "=c" (cnt)
477 : "0" (addr), "1" (cnt), "d" (port));
481 outsw(u_int port, const void *addr, size_t cnt)
483 __asm __volatile("cld; rep; outsw"
484 : "=S" (addr), "=c" (cnt)
485 : "0" (addr), "1" (cnt), "d" (port));
489 outsl(u_int port, const void *addr, size_t cnt)
491 __asm __volatile("cld; rep; outsl"
492 : "=S" (addr), "=c" (cnt)
493 : "0" (addr), "1" (cnt), "d" (port));
497 outw(u_int port, u_short data)
499 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
502 static __inline u_int
507 __asm __volatile("movl %%cr2,%0" : "=r" (data));
511 static __inline u_int
516 __asm __volatile("pushfl; popl %0" : "=r" (ef));
520 static __inline u_int64_t
525 __asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
529 static __inline u_int64_t
534 __asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
538 #define _RDTSC_SUPPORTED_
540 static __inline u_int64_t
545 __asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
552 __asm __volatile("wbinvd");
556 write_eflags(u_int ef)
558 __asm __volatile("pushl %0; popfl" : : "r" (ef));
562 wrmsr(u_int msr, u_int64_t newval)
564 __asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
567 static __inline u_short
571 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
575 static __inline u_short
579 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
586 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
592 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
595 static __inline u_int
599 __asm __volatile("movl %%dr0,%0" : "=r" (data));
606 __asm __volatile("movl %0,%%dr0" : : "r" (sel));
609 static __inline u_int
613 __asm __volatile("movl %%dr1,%0" : "=r" (data));
620 __asm __volatile("movl %0,%%dr1" : : "r" (sel));
623 static __inline u_int
627 __asm __volatile("movl %%dr2,%0" : "=r" (data));
634 __asm __volatile("movl %0,%%dr2" : : "r" (sel));
637 static __inline u_int
641 __asm __volatile("movl %%dr3,%0" : "=r" (data));
648 __asm __volatile("movl %0,%%dr3" : : "r" (sel));
651 static __inline u_int
655 __asm __volatile("movl %%dr4,%0" : "=r" (data));
662 __asm __volatile("movl %0,%%dr4" : : "r" (sel));
665 static __inline u_int
669 __asm __volatile("movl %%dr5,%0" : "=r" (data));
676 __asm __volatile("movl %0,%%dr5" : : "r" (sel));
679 static __inline u_int
683 __asm __volatile("movl %%dr6,%0" : "=r" (data));
690 __asm __volatile("movl %0,%%dr6" : : "r" (sel));
693 static __inline u_int
697 __asm __volatile("movl %%dr7,%0" : "=r" (data));
704 __asm __volatile("movl %0,%%dr7" : : "r" (sel));
707 #else /* !__GNUC__ */
709 int breakpoint (void);
710 void cpu_pause (void);
711 u_int bsfl (u_int mask);
712 u_int bsrl (u_int mask);
713 void cpu_disable_intr (void);
714 void do_cpuid (u_int ax, u_int *p);
715 void cpu_enable_intr (void);
716 u_char inb (u_int port);
717 u_int inl (u_int port);
718 void insb (u_int port, void *addr, size_t cnt);
719 void insl (u_int port, void *addr, size_t cnt);
720 void insw (u_int port, void *addr, size_t cnt);
722 u_short inw (u_int port);
723 u_int loadandclear (u_int *addr);
724 void outb (u_int port, u_char data);
725 void outl (u_int port, u_int data);
726 void outsb (u_int port, void *addr, size_t cnt);
727 void outsl (u_int port, void *addr, size_t cnt);
728 void outsw (u_int port, void *addr, size_t cnt);
729 void outw (u_int port, u_short data);
731 u_int64_t rdmsr (u_int msr);
732 u_int64_t rdpmc (u_int pmc);
733 u_int64_t rdtsc (void);
734 u_int read_eflags (void);
736 void write_eflags (u_int ef);
737 void wrmsr (u_int msr, u_int64_t newval);
740 void load_fs (u_short sel);
741 void load_gs (u_short sel);
743 #endif /* __GNUC__ */
745 void load_cr0 (u_int cr0);
746 void load_cr3 (u_int cr3);
747 void load_cr4 (u_int cr4);
748 void ltr (u_short sel);
752 int rdmsr_safe (u_int msr, uint64_t *val);
753 void reset_dbregs (void);
756 #endif /* !_CPU_CPUFUNC_H_ */