2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
167 typedef int (*mptable_iter_func)(void *, const void *, int);
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int need_hyperthreading_fixup;
222 static u_int logical_cpus;
223 u_int logical_cpus_mask;
225 static int madt_probe_test;
226 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
228 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
229 int current_postcode;
231 /** XXX FIXME: what system files declare these??? */
232 extern struct region_descriptor r_gdt, r_idt;
234 int mp_naps; /* # of Applications processors */
236 static int mp_nbusses; /* # of busses */
237 int mp_napics; /* # of IO APICs */
239 static vm_offset_t cpu_apic_address;
241 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
242 u_int32_t *io_apic_versions;
246 u_int32_t cpu_apic_versions[MAXCPU];
248 extern int64_t tsc_offsets[];
250 extern u_long ebda_addr;
253 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
257 * APIC ID logical/physical mapping structures.
258 * We oversize these to simplify boot-time config.
260 int cpu_num_to_apic_id[NAPICID];
262 int io_num_to_apic_id[NAPICID];
264 int apic_id_to_logical[NAPICID];
266 /* AP uses this during bootstrap. Do not staticize. */
270 /* Hotwire a 0->4MB V==P mapping */
271 extern pt_entry_t *KPTphys;
274 * SMP page table page. Setup by locore to point to a page table
275 * page from which we allocate per-cpu privatespace areas io_apics,
279 #define IO_MAPPING_START_INDEX \
280 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
282 extern pt_entry_t *SMPpt;
283 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
285 struct pcb stoppcbs[MAXCPU];
287 static basetable_entry basetable_entry_types[] =
289 {0, 20, "Processor"},
297 * Local data and functions.
300 static u_int boot_address;
301 static u_int base_memory;
302 static int mp_finish;
304 static void mp_enable(u_int boot_addr);
306 static int mptable_iterate_entries(const mpcth_t,
307 mptable_iter_func, void *);
308 static int mptable_probe(void);
309 static int mptable_check(vm_paddr_t);
310 static int mptable_search_sig(u_int32_t target, int count);
311 static void mptable_hyperthread_fixup(u_int id_mask);
312 static void mptable_pass1(struct mptable_pos *);
313 static int mptable_pass2(struct mptable_pos *);
314 static void mptable_default(int type);
315 static void mptable_fix(void);
316 static int mptable_map(struct mptable_pos *, vm_paddr_t);
317 static void mptable_unmap(struct mptable_pos *);
318 static void mptable_lapic_enumerate(struct mptable_pos *);
321 static void setup_apic_irq_mapping(void);
322 static int apic_int_is_bus_type(int intr, int bus_type);
324 static int start_all_aps(u_int boot_addr);
325 static void install_ap_tramp(u_int boot_addr);
326 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
327 static void lapic_init(vm_offset_t);
329 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
330 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
331 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
334 * Calculate usable address in base memory for AP trampoline code.
337 mp_bootaddress(u_int basemem)
339 POSTCODE(MP_BOOTADDRESS_POST);
341 base_memory = basemem;
343 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
344 if ((base_memory - boot_address) < bootMP_size)
345 boot_address -= 4096; /* not enough, lower by 4k */
352 * Look for an Intel MP spec table (ie, SMP capable hardware).
361 * Make sure our SMPpt[] page table is big enough to hold all the
364 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
366 POSTCODE(MP_PROBE_POST);
368 /* see if EBDA exists */
369 if (ebda_addr != 0) {
370 /* search first 1K of EBDA */
371 target = (u_int32_t)ebda_addr;
372 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
375 /* last 1K of base memory, effective 'top of base' passed in */
376 target = (u_int32_t)(base_memory - 0x400);
377 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
381 /* search the BIOS */
382 target = (u_int32_t)BIOS_BASE;
383 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
390 struct mptable_check_cbarg {
396 mptable_check_callback(void *xarg, const void *pos, int type)
398 const struct PROCENTRY *ent;
399 struct mptable_check_cbarg *arg = xarg;
405 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
409 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
410 if (arg->found_bsp) {
411 kprintf("more than one BSP in base MP table\n");
420 mptable_check(vm_paddr_t mpfps_paddr)
422 struct mptable_pos mpt;
423 struct mptable_check_cbarg arg;
427 if (mpfps_paddr == 0)
430 error = mptable_map(&mpt, mpfps_paddr);
434 if (mpt.mp_fps->mpfb1 != 0)
442 if (cth->apic_address == 0)
445 bzero(&arg, sizeof(arg));
446 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
448 if (arg.cpu_count == 0) {
449 kprintf("MP table contains no processor entries\n");
451 } else if (!arg.found_bsp) {
452 kprintf("MP table does not contains BSP entry\n");
462 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
464 int count, total_size;
465 const void *position;
467 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
468 total_size = cth->base_table_length - sizeof(struct MPCTH);
469 position = (const uint8_t *)cth + sizeof(struct MPCTH);
470 count = cth->entry_count;
475 KKASSERT(total_size >= 0);
476 if (total_size == 0) {
477 kprintf("invalid base MP table, "
478 "entry count and length mismatch\n");
482 type = *(const uint8_t *)position;
484 case 0: /* processor_entry */
485 case 1: /* bus_entry */
486 case 2: /* io_apic_entry */
487 case 3: /* int_entry */
488 case 4: /* int_entry */
491 kprintf("unknown base MP table entry type %d\n", type);
495 if (total_size < basetable_entry_types[type].length) {
496 kprintf("invalid base MP table length, "
497 "does not contain all entries\n");
500 total_size -= basetable_entry_types[type].length;
502 error = func(arg, position, type);
506 position = (const uint8_t *)position +
507 basetable_entry_types[type].length;
514 * Startup the SMP processors.
519 POSTCODE(MP_START_POST);
520 mp_enable(boot_address);
525 * Print various information about the SMP system hardware and setup.
532 POSTCODE(MP_ANNOUNCE_POST);
534 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
535 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
536 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
537 kprintf(", at 0x%08x\n", cpu_apic_address);
538 for (x = 1; x <= mp_naps; ++x) {
539 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
540 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
541 kprintf(", at 0x%08x\n", cpu_apic_address);
545 for (x = 0; x < mp_napics; ++x) {
546 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
547 kprintf(", version: 0x%08x", io_apic_versions[x]);
548 kprintf(", at 0x%08x\n", io_apic_address[x]);
551 kprintf(" Warning: APIC I/O disabled\n");
556 * AP cpu's call this to sync up protected mode.
558 * WARNING! We must ensure that the cpu is sufficiently initialized to
559 * be able to use to the FP for our optimized bzero/bcopy code before
560 * we enter more mainstream C code.
562 * WARNING! %fs is not set up on entry. This routine sets up %fs.
568 int x, myid = bootAP;
570 struct mdglobaldata *md;
571 struct privatespace *ps;
573 ps = &CPU_prvspace[myid];
575 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
576 gdt_segs[GPROC0_SEL].ssd_base =
577 (int) &ps->mdglobaldata.gd_common_tss;
578 ps->mdglobaldata.mi.gd_prvspace = ps;
580 for (x = 0; x < NGDT; x++) {
581 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
584 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
585 r_gdt.rd_base = (int) &gdt[myid * NGDT];
586 lgdt(&r_gdt); /* does magic intra-segment return */
591 mdcpu->gd_currentldt = _default_ldt;
593 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
594 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
596 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
598 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
599 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
600 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
601 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
602 md->gd_common_tssd = *md->gd_tss_gdt;
606 * Set to a known state:
607 * Set by mpboot.s: CR0_PG, CR0_PE
608 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
611 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
613 pmap_set_opt(); /* PSE/4MB pages, etc */
615 /* set up CPU registers and state */
618 /* set up FPU state on the AP */
619 npxinit(__INITIAL_NPXCW__);
621 /* set up SSE registers */
625 /*******************************************************************
626 * local functions and data
630 * start the SMP system
633 mp_enable(u_int boot_addr)
640 vm_paddr_t mpfps_paddr;
642 POSTCODE(MP_ENABLE_POST);
644 if (madt_probe_test) {
647 mpfps_paddr = mptable_probe();
648 if (mptable_check(mpfps_paddr))
653 struct mptable_pos mpt;
655 mptable_map(&mpt, mpfps_paddr);
657 mptable_lapic_enumerate(&mpt);
660 * We can safely map physical memory into SMPpt after
661 * mptable_pass1() completes.
666 * Examine the MP table for needed info
668 x = mptable_pass2(&mpt);
673 * Can't process default configs till the
674 * CPU APIC is pmapped
679 /* Post scan cleanup */
682 vm_paddr_t madt_paddr;
683 vm_offset_t lapic_addr;
686 madt_paddr = madt_probe();
688 panic("mp_enable: madt_probe failed\n");
690 lapic_addr = madt_pass1(madt_paddr);
692 panic("mp_enable: no local apic (madt)!\n");
694 lapic_init(lapic_addr);
696 bsp_apic_id = (lapic.id & 0xff000000) >> 24;
697 if (madt_pass2(madt_paddr, bsp_apic_id))
698 panic("mp_enable: madt_pass2 failed\n");
703 setup_apic_irq_mapping();
705 /* fill the LOGICAL io_apic_versions table */
706 for (apic = 0; apic < mp_napics; ++apic) {
707 ux = io_apic_read(apic, IOAPIC_VER);
708 io_apic_versions[apic] = ux;
709 io_apic_set_id(apic, IO_TO_ID(apic));
712 /* program each IO APIC in the system */
713 for (apic = 0; apic < mp_napics; ++apic)
714 if (io_apic_setup(apic) < 0)
715 panic("IO APIC setup failure");
720 * These are required for SMP operation
723 /* install a 'Spurious INTerrupt' vector */
724 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
725 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
727 /* install an inter-CPU IPI for TLB invalidation */
728 setidt(XINVLTLB_OFFSET, Xinvltlb,
729 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
731 /* install an inter-CPU IPI for IPIQ messaging */
732 setidt(XIPIQ_OFFSET, Xipiq,
733 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
735 /* install a timer vector */
736 setidt(XTIMER_OFFSET, Xtimer,
737 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
739 /* install an inter-CPU IPI for CPU stop/restart */
740 setidt(XCPUSTOP_OFFSET, Xcpustop,
741 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
743 /* start each Application Processor */
744 start_all_aps(boot_addr);
749 * look for the MP spec signature
752 /* string defined by the Intel MP Spec as identifying the MP table */
753 #define MP_SIG 0x5f504d5f /* _MP_ */
754 #define NEXT(X) ((X) += 4)
756 mptable_search_sig(u_int32_t target, int count)
762 KKASSERT(target != 0);
764 map_size = count * sizeof(u_int32_t);
765 addr = pmap_mapdev((vm_paddr_t)target, map_size);
768 for (x = 0; x < count; NEXT(x)) {
769 if (addr[x] == MP_SIG) {
770 /* make array index a byte index */
771 ret = target + (x * sizeof(u_int32_t));
776 pmap_unmapdev((vm_offset_t)addr, map_size);
781 typedef struct BUSDATA {
783 enum busTypes bus_type;
786 typedef struct INTDATA {
796 typedef struct BUSTYPENAME {
801 static bus_type_name bus_type_table[] =
807 {UNKNOWN_BUSTYPE, "---"},
810 {UNKNOWN_BUSTYPE, "---"},
811 {UNKNOWN_BUSTYPE, "---"},
812 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
817 {UNKNOWN_BUSTYPE, "---"},
818 {UNKNOWN_BUSTYPE, "---"},
819 {UNKNOWN_BUSTYPE, "---"},
821 {UNKNOWN_BUSTYPE, "---"}
823 /* from MP spec v1.4, table 5-1 */
824 static int default_data[7][5] =
826 /* nbus, id0, type0, id1, type1 */
827 {1, 0, ISA, 255, 255},
828 {1, 0, EISA, 255, 255},
829 {1, 0, EISA, 255, 255},
830 {1, 0, MCA, 255, 255},
832 {2, 0, EISA, 1, PCI},
840 static bus_datum *bus_data;
842 /* the IO INT data, one entry per possible APIC INTerrupt */
843 static io_int *io_apic_ints;
848 static int processor_entry (const struct PROCENTRY *entry, int cpu);
850 static int bus_entry (bus_entry_ptr entry, int bus);
851 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
852 static int int_entry (int_entry_ptr entry, int intr);
854 static int lookup_bus_type (char *name);
858 * 1st pass on motherboard's Intel MP specification table.
867 mptable_pass1(struct mptable_pos *mpt)
879 POSTCODE(MPTABLE_PASS1_POST);
882 KKASSERT(fps != NULL);
885 /* clear various tables */
886 for (x = 0; x < NAPICID; ++x) {
887 io_apic_address[x] = ~0; /* IO APIC address table */
897 /* check for use of 'default' configuration */
898 if (fps->mpfb1 != 0) {
900 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
901 mp_nbusses = default_data[fps->mpfb1 - 1][0];
908 KKASSERT(cth != NULL);
910 /* walk the table, recording info of interest */
911 totalSize = cth->base_table_length - sizeof(struct MPCTH);
912 position = (u_char *) cth + sizeof(struct MPCTH);
913 count = cth->entry_count;
916 switch (type = *(u_char *) position) {
917 case 0: /* processor_entry */
919 case 1: /* bus_entry */
924 case 2: /* io_apic_entry */
926 if (((io_apic_entry_ptr)position)->apic_flags
927 & IOAPICENTRY_FLAG_EN)
928 io_apic_address[mp_napics++] =
929 (vm_offset_t)((io_apic_entry_ptr)
930 position)->apic_address;
933 case 3: /* int_entry */
938 case 4: /* int_entry */
941 panic("mpfps Base Table HOSED!");
945 totalSize -= basetable_entry_types[type].length;
946 position = (uint8_t *)position +
947 basetable_entry_types[type].length;
954 * 2nd pass on motherboard's Intel MP specification table.
957 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
958 * IO_TO_ID(N), logical IO to APIC ID table
963 mptable_pass2(struct mptable_pos *mpt)
975 POSTCODE(MPTABLE_PASS2_POST);
978 KKASSERT(fps != NULL);
981 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
983 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
984 M_DEVBUF, M_WAITOK | M_ZERO);
985 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
987 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
992 for (i = 0; i < mp_napics; i++) {
993 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
997 /* clear various tables */
998 for (x = 0; x < NAPICID; ++x) {
1000 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1001 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1006 /* clear bus data table */
1007 for (x = 0; x < mp_nbusses; ++x)
1008 bus_data[x].bus_id = 0xff;
1010 /* clear IO APIC INT table */
1011 for (x = 0; x < (nintrs + 1); ++x) {
1012 io_apic_ints[x].int_type = 0xff;
1013 io_apic_ints[x].int_vector = 0xff;
1017 /* record whether PIC or virtual-wire mode */
1018 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
1020 /* check for use of 'default' configuration */
1021 if (fps->mpfb1 != 0)
1022 return fps->mpfb1; /* return default configuration type */
1025 KKASSERT(cth != NULL);
1027 /* walk the table, recording info of interest */
1028 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1029 position = (u_char *) cth + sizeof(struct MPCTH);
1030 count = cth->entry_count;
1031 apic = bus = intr = 0;
1034 switch (type = *(u_char *) position) {
1039 if (bus_entry(position, bus))
1045 if (io_apic_entry(position, apic))
1051 if (int_entry(position, intr))
1056 /* int_entry(position); */
1059 panic("mpfps Base Table HOSED!");
1063 totalSize -= basetable_entry_types[type].length;
1064 position = (uint8_t *)position + basetable_entry_types[type].length;
1067 /* report fact that its NOT a default configuration */
1072 * Check if we should perform a hyperthreading "fix-up" to
1073 * enumerate any logical CPU's that aren't already listed
1076 * XXX: We assume that all of the physical CPUs in the
1077 * system have the same number of logical CPUs.
1079 * XXX: We assume that APIC ID's are allocated such that
1080 * the APIC ID's for a physical processor are aligned
1081 * with the number of logical CPU's in the processor.
1084 mptable_hyperthread_fixup(u_int id_mask)
1086 int i, id, lcpus_max;
1088 if ((cpu_feature & CPUID_HTT) == 0)
1091 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1095 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1097 * INSTRUCTION SET REFERENCE, A-M (#253666)
1098 * Page 3-181, Table 3-20
1099 * "The nearest power-of-2 integer that is not smaller
1100 * than EBX[23:16] is the number of unique initial APIC
1101 * IDs reserved for addressing different logical
1102 * processors in a physical package."
1104 for (i = 0; ; ++i) {
1105 if ((1 << i) >= lcpus_max) {
1112 if (mp_naps == lcpus_max) {
1113 /* We have nothing to fix */
1115 } else if (mp_naps == 1) {
1116 /* XXX this may be incorrect */
1117 logical_cpus = lcpus_max;
1119 int cur, prev, dist;
1122 * Calculate the distances between two nearest
1123 * APIC IDs. If all such distances are same,
1124 * then it is the number of missing cpus that
1125 * we are going to fill later.
1127 dist = cur = prev = -1;
1128 for (id = 0; id < MAXCPU; ++id) {
1129 if ((id_mask & 1 << id) == 0)
1134 int new_dist = cur - prev;
1140 * Make sure that all distances
1141 * between two nearest APIC IDs
1144 if (dist != new_dist)
1152 /* Must be power of 2 */
1153 if (dist & (dist - 1))
1156 /* Can't exceed CPU package capacity */
1157 if (dist > lcpus_max)
1158 logical_cpus = lcpus_max;
1160 logical_cpus = dist;
1164 * For each APIC ID of a CPU that is set in the mask,
1165 * scan the other candidate APIC ID's for this
1166 * physical processor. If any of those ID's are
1167 * already in the table, then kill the fixup.
1169 for (id = 0; id < MAXCPU; id++) {
1170 if ((id_mask & 1 << id) == 0)
1172 /* First, make sure we are on a logical_cpus boundary. */
1173 if (id % logical_cpus != 0)
1175 for (i = id + 1; i < id + logical_cpus; i++)
1176 if ((id_mask & 1 << i) != 0)
1181 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1182 * mp_naps right now.
1184 need_hyperthreading_fixup = 1;
1185 mp_naps *= logical_cpus;
1189 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1193 vm_size_t cth_mapsz = 0;
1195 bzero(mpt, sizeof(*mpt));
1197 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1198 if (fps->pap != 0) {
1200 * Map configuration table header to get
1201 * the base table size
1203 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1204 cth_mapsz = cth->base_table_length;
1205 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1207 if (cth_mapsz < sizeof(*cth)) {
1208 kprintf("invalid base MP table length %d\n",
1210 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1215 * Map the base table
1217 cth = pmap_mapdev(fps->pap, cth_mapsz);
1222 mpt->mp_cth_mapsz = cth_mapsz;
1228 mptable_unmap(struct mptable_pos *mpt)
1230 if (mpt->mp_cth != NULL) {
1231 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1233 mpt->mp_cth_mapsz = 0;
1235 if (mpt->mp_fps != NULL) {
1236 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1244 assign_apic_irq(int apic, int intpin, int irq)
1248 if (int_to_apicintpin[irq].ioapic != -1)
1249 panic("assign_apic_irq: inconsistent table");
1251 int_to_apicintpin[irq].ioapic = apic;
1252 int_to_apicintpin[irq].int_pin = intpin;
1253 int_to_apicintpin[irq].apic_address = ioapic[apic];
1254 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1256 for (x = 0; x < nintrs; x++) {
1257 if ((io_apic_ints[x].int_type == 0 ||
1258 io_apic_ints[x].int_type == 3) &&
1259 io_apic_ints[x].int_vector == 0xff &&
1260 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1261 io_apic_ints[x].dst_apic_int == intpin)
1262 io_apic_ints[x].int_vector = irq;
1267 revoke_apic_irq(int irq)
1273 if (int_to_apicintpin[irq].ioapic == -1)
1274 panic("revoke_apic_irq: inconsistent table");
1276 oldapic = int_to_apicintpin[irq].ioapic;
1277 oldintpin = int_to_apicintpin[irq].int_pin;
1279 int_to_apicintpin[irq].ioapic = -1;
1280 int_to_apicintpin[irq].int_pin = 0;
1281 int_to_apicintpin[irq].apic_address = NULL;
1282 int_to_apicintpin[irq].redirindex = 0;
1284 for (x = 0; x < nintrs; x++) {
1285 if ((io_apic_ints[x].int_type == 0 ||
1286 io_apic_ints[x].int_type == 3) &&
1287 io_apic_ints[x].int_vector != 0xff &&
1288 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1289 io_apic_ints[x].dst_apic_int == oldintpin)
1290 io_apic_ints[x].int_vector = 0xff;
1298 allocate_apic_irq(int intr)
1304 if (io_apic_ints[intr].int_vector != 0xff)
1305 return; /* Interrupt handler already assigned */
1307 if (io_apic_ints[intr].int_type != 0 &&
1308 (io_apic_ints[intr].int_type != 3 ||
1309 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1310 io_apic_ints[intr].dst_apic_int == 0)))
1311 return; /* Not INT or ExtInt on != (0, 0) */
1314 while (irq < APIC_INTMAPSIZE &&
1315 int_to_apicintpin[irq].ioapic != -1)
1318 if (irq >= APIC_INTMAPSIZE)
1319 return; /* No free interrupt handlers */
1321 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1322 intpin = io_apic_ints[intr].dst_apic_int;
1324 assign_apic_irq(apic, intpin, irq);
1325 io_apic_setup_intpin(apic, intpin);
1330 swap_apic_id(int apic, int oldid, int newid)
1337 return; /* Nothing to do */
1339 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1340 apic, oldid, newid);
1342 /* Swap physical APIC IDs in interrupt entries */
1343 for (x = 0; x < nintrs; x++) {
1344 if (io_apic_ints[x].dst_apic_id == oldid)
1345 io_apic_ints[x].dst_apic_id = newid;
1346 else if (io_apic_ints[x].dst_apic_id == newid)
1347 io_apic_ints[x].dst_apic_id = oldid;
1350 /* Swap physical APIC IDs in IO_TO_ID mappings */
1351 for (oapic = 0; oapic < mp_napics; oapic++)
1352 if (IO_TO_ID(oapic) == newid)
1355 if (oapic < mp_napics) {
1356 kprintf("Changing APIC ID for IO APIC #%d from "
1357 "%d to %d in MP table\n",
1358 oapic, newid, oldid);
1359 IO_TO_ID(oapic) = oldid;
1361 IO_TO_ID(apic) = newid;
1366 fix_id_to_io_mapping(void)
1370 for (x = 0; x < NAPICID; x++)
1373 for (x = 0; x <= mp_naps; x++)
1374 if (CPU_TO_ID(x) < NAPICID)
1375 ID_TO_IO(CPU_TO_ID(x)) = x;
1377 for (x = 0; x < mp_napics; x++)
1378 if (IO_TO_ID(x) < NAPICID)
1379 ID_TO_IO(IO_TO_ID(x)) = x;
1384 first_free_apic_id(void)
1388 for (freeid = 0; freeid < NAPICID; freeid++) {
1389 for (x = 0; x <= mp_naps; x++)
1390 if (CPU_TO_ID(x) == freeid)
1394 for (x = 0; x < mp_napics; x++)
1395 if (IO_TO_ID(x) == freeid)
1406 io_apic_id_acceptable(int apic, int id)
1408 int cpu; /* Logical CPU number */
1409 int oapic; /* Logical IO APIC number for other IO APIC */
1412 return 0; /* Out of range */
1414 for (cpu = 0; cpu <= mp_naps; cpu++)
1415 if (CPU_TO_ID(cpu) == id)
1416 return 0; /* Conflict with CPU */
1418 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1419 if (IO_TO_ID(oapic) == id)
1420 return 0; /* Conflict with other APIC */
1422 return 1; /* ID is acceptable for IO APIC */
1427 io_apic_find_int_entry(int apic, int pin)
1431 /* search each of the possible INTerrupt sources */
1432 for (x = 0; x < nintrs; ++x) {
1433 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1434 (pin == io_apic_ints[x].dst_apic_int))
1435 return (&io_apic_ints[x]);
1443 * parse an Intel MP specification table
1451 int apic; /* IO APIC unit number */
1452 int freeid; /* Free physical APIC ID */
1453 int physid; /* Current physical IO APIC ID */
1455 int bus_0 = 0; /* Stop GCC warning */
1456 int bus_pci = 0; /* Stop GCC warning */
1460 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1461 * did it wrong. The MP spec says that when more than 1 PCI bus
1462 * exists the BIOS must begin with bus entries for the PCI bus and use
1463 * actual PCI bus numbering. This implies that when only 1 PCI bus
1464 * exists the BIOS can choose to ignore this ordering, and indeed many
1465 * MP motherboards do ignore it. This causes a problem when the PCI
1466 * sub-system makes requests of the MP sub-system based on PCI bus
1467 * numbers. So here we look for the situation and renumber the
1468 * busses and associated INTs in an effort to "make it right".
1471 /* find bus 0, PCI bus, count the number of PCI busses */
1472 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1473 if (bus_data[x].bus_id == 0) {
1476 if (bus_data[x].bus_type == PCI) {
1482 * bus_0 == slot of bus with ID of 0
1483 * bus_pci == slot of last PCI bus encountered
1486 /* check the 1 PCI bus case for sanity */
1487 /* if it is number 0 all is well */
1488 if (num_pci_bus == 1 &&
1489 bus_data[bus_pci].bus_id != 0) {
1491 /* mis-numbered, swap with whichever bus uses slot 0 */
1493 /* swap the bus entry types */
1494 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1495 bus_data[bus_0].bus_type = PCI;
1497 /* swap each relavant INTerrupt entry */
1498 id = bus_data[bus_pci].bus_id;
1499 for (x = 0; x < nintrs; ++x) {
1500 if (io_apic_ints[x].src_bus_id == id) {
1501 io_apic_ints[x].src_bus_id = 0;
1503 else if (io_apic_ints[x].src_bus_id == 0) {
1504 io_apic_ints[x].src_bus_id = id;
1509 /* Assign IO APIC IDs.
1511 * First try the existing ID. If a conflict is detected, try
1512 * the ID in the MP table. If a conflict is still detected, find
1515 * We cannot use the ID_TO_IO table before all conflicts has been
1516 * resolved and the table has been corrected.
1518 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1520 /* First try to use the value set by the BIOS */
1521 physid = io_apic_get_id(apic);
1522 if (io_apic_id_acceptable(apic, physid)) {
1523 if (IO_TO_ID(apic) != physid)
1524 swap_apic_id(apic, IO_TO_ID(apic), physid);
1528 /* Then check if the value in the MP table is acceptable */
1529 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1532 /* Last resort, find a free APIC ID and use it */
1533 freeid = first_free_apic_id();
1534 if (freeid >= NAPICID)
1535 panic("No free physical APIC IDs found");
1537 if (io_apic_id_acceptable(apic, freeid)) {
1538 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1541 panic("Free physical APIC ID not usable");
1543 fix_id_to_io_mapping();
1545 /* detect and fix broken Compaq MP table */
1546 if (apic_int_type(0, 0) == -1) {
1547 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1548 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1549 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1550 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1551 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1552 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1554 } else if (apic_int_type(0, 0) == 0) {
1555 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1556 for (x = 0; x < nintrs; ++x)
1557 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1558 (0 == io_apic_ints[x].dst_apic_int)) {
1559 io_apic_ints[x].int_type = 3;
1560 io_apic_ints[x].int_vector = 0xff;
1566 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1567 * controllers universally come in pairs. If IRQ 14 is specified
1568 * as an ISA interrupt, then IRQ 15 had better be too.
1570 * [ Shuttle XPC / AMD Athlon X2 ]
1571 * The MPTable is missing an entry for IRQ 15. Note that the
1572 * ACPI table has an entry for both 14 and 15.
1574 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1575 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1576 io14 = io_apic_find_int_entry(0, 14);
1577 io_apic_ints[nintrs] = *io14;
1578 io_apic_ints[nintrs].src_bus_irq = 15;
1579 io_apic_ints[nintrs].dst_apic_int = 15;
1587 /* Assign low level interrupt handlers */
1589 setup_apic_irq_mapping(void)
1595 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1596 int_to_apicintpin[x].ioapic = -1;
1597 int_to_apicintpin[x].int_pin = 0;
1598 int_to_apicintpin[x].apic_address = NULL;
1599 int_to_apicintpin[x].redirindex = 0;
1602 /* First assign ISA/EISA interrupts */
1603 for (x = 0; x < nintrs; x++) {
1604 int_vector = io_apic_ints[x].src_bus_irq;
1605 if (int_vector < APIC_INTMAPSIZE &&
1606 io_apic_ints[x].int_vector == 0xff &&
1607 int_to_apicintpin[int_vector].ioapic == -1 &&
1608 (apic_int_is_bus_type(x, ISA) ||
1609 apic_int_is_bus_type(x, EISA)) &&
1610 io_apic_ints[x].int_type == 0) {
1611 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1612 io_apic_ints[x].dst_apic_int,
1617 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1618 for (x = 0; x < nintrs; x++) {
1619 if (io_apic_ints[x].dst_apic_int == 0 &&
1620 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1621 io_apic_ints[x].int_vector == 0xff &&
1622 int_to_apicintpin[0].ioapic == -1 &&
1623 io_apic_ints[x].int_type == 3) {
1624 assign_apic_irq(0, 0, 0);
1628 /* PCI interrupt assignment is deferred */
1634 mp_set_cpuids(int cpu_id, int apic_id)
1636 CPU_TO_ID(cpu_id) = apic_id;
1637 ID_TO_CPU(apic_id) = cpu_id;
1641 processor_entry(const struct PROCENTRY *entry, int cpu)
1645 /* check for usability */
1646 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1649 if(entry->apic_id >= NAPICID)
1650 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1651 /* check for BSP flag */
1652 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1653 mp_set_cpuids(0, entry->apic_id);
1654 return 0; /* its already been counted */
1657 /* add another AP to list, if less than max number of CPUs */
1658 else if (cpu < MAXCPU) {
1659 mp_set_cpuids(cpu, entry->apic_id);
1669 bus_entry(bus_entry_ptr entry, int bus)
1674 /* encode the name into an index */
1675 for (x = 0; x < 6; ++x) {
1676 if ((c = entry->bus_type[x]) == ' ')
1682 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1683 panic("unknown bus type: '%s'", name);
1685 bus_data[bus].bus_id = entry->bus_id;
1686 bus_data[bus].bus_type = x;
1692 io_apic_entry(io_apic_entry_ptr entry, int apic)
1694 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1697 IO_TO_ID(apic) = entry->apic_id;
1698 if (entry->apic_id < NAPICID)
1699 ID_TO_IO(entry->apic_id) = apic;
1707 lookup_bus_type(char *name)
1711 for (x = 0; x < MAX_BUSTYPE; ++x)
1712 if (strcmp(bus_type_table[x].name, name) == 0)
1713 return bus_type_table[x].type;
1715 return UNKNOWN_BUSTYPE;
1721 int_entry(int_entry_ptr entry, int intr)
1725 io_apic_ints[intr].int_type = entry->int_type;
1726 io_apic_ints[intr].int_flags = entry->int_flags;
1727 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1728 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1729 if (entry->dst_apic_id == 255) {
1730 /* This signal goes to all IO APICS. Select an IO APIC
1731 with sufficient number of interrupt pins */
1732 for (apic = 0; apic < mp_napics; apic++)
1733 if (((io_apic_read(apic, IOAPIC_VER) &
1734 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1735 entry->dst_apic_int)
1737 if (apic < mp_napics)
1738 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1740 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1742 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1743 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1749 apic_int_is_bus_type(int intr, int bus_type)
1753 for (bus = 0; bus < mp_nbusses; ++bus)
1754 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1755 && ((int) bus_data[bus].bus_type == bus_type))
1762 * Given a traditional ISA INT mask, return an APIC mask.
1765 isa_apic_mask(u_int isa_mask)
1770 #if defined(SKIP_IRQ15_REDIRECT)
1771 if (isa_mask == (1 << 15)) {
1772 kprintf("skipping ISA IRQ15 redirect\n");
1775 #endif /* SKIP_IRQ15_REDIRECT */
1777 isa_irq = ffs(isa_mask); /* find its bit position */
1778 if (isa_irq == 0) /* doesn't exist */
1780 --isa_irq; /* make it zero based */
1782 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1786 return (1 << apic_pin); /* convert pin# to a mask */
1790 * Determine which APIC pin an ISA/EISA INT is attached to.
1792 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1793 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1794 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1795 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1797 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1799 isa_apic_irq(int isa_irq)
1803 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1804 if (INTTYPE(intr) == 0) { /* standard INT */
1805 if (SRCBUSIRQ(intr) == isa_irq) {
1806 if (apic_int_is_bus_type(intr, ISA) ||
1807 apic_int_is_bus_type(intr, EISA)) {
1808 if (INTIRQ(intr) == 0xff)
1809 return -1; /* unassigned */
1810 return INTIRQ(intr); /* found */
1815 return -1; /* NOT found */
1820 * Determine which APIC pin a PCI INT is attached to.
1822 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1823 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1824 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1826 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1830 --pciInt; /* zero based */
1832 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1833 if ((INTTYPE(intr) == 0) /* standard INT */
1834 && (SRCBUSID(intr) == pciBus)
1835 && (SRCBUSDEVICE(intr) == pciDevice)
1836 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1837 if (apic_int_is_bus_type(intr, PCI)) {
1838 if (INTIRQ(intr) == 0xff)
1839 allocate_apic_irq(intr);
1840 if (INTIRQ(intr) == 0xff)
1841 return -1; /* unassigned */
1842 return INTIRQ(intr); /* exact match */
1847 return -1; /* NOT found */
1851 next_apic_irq(int irq)
1858 for (intr = 0; intr < nintrs; intr++) {
1859 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1861 bus = SRCBUSID(intr);
1862 bustype = apic_bus_type(bus);
1863 if (bustype != ISA &&
1869 if (intr >= nintrs) {
1872 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1873 if (INTTYPE(ointr) != 0)
1875 if (bus != SRCBUSID(ointr))
1877 if (bustype == PCI) {
1878 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1880 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1883 if (bustype == ISA || bustype == EISA) {
1884 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1887 if (INTPIN(intr) == INTPIN(ointr))
1891 if (ointr >= nintrs) {
1894 return INTIRQ(ointr);
1909 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1912 * Exactly what this means is unclear at this point. It is a solution
1913 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1914 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1915 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1919 undirect_isa_irq(int rirq)
1923 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1924 /** FIXME: tickle the MB redirector chip */
1928 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1935 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1938 undirect_pci_irq(int rirq)
1942 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1944 /** FIXME: tickle the MB redirector chip */
1948 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1958 * given a bus ID, return:
1959 * the bus type if found
1963 apic_bus_type(int id)
1967 for (x = 0; x < mp_nbusses; ++x)
1968 if (bus_data[x].bus_id == id)
1969 return bus_data[x].bus_type;
1975 * given a LOGICAL APIC# and pin#, return:
1976 * the associated src bus ID if found
1980 apic_src_bus_id(int apic, int pin)
1984 /* search each of the possible INTerrupt sources */
1985 for (x = 0; x < nintrs; ++x)
1986 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1987 (pin == io_apic_ints[x].dst_apic_int))
1988 return (io_apic_ints[x].src_bus_id);
1990 return -1; /* NOT found */
1994 * given a LOGICAL APIC# and pin#, return:
1995 * the associated src bus IRQ if found
1999 apic_src_bus_irq(int apic, int pin)
2003 for (x = 0; x < nintrs; x++)
2004 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2005 (pin == io_apic_ints[x].dst_apic_int))
2006 return (io_apic_ints[x].src_bus_irq);
2008 return -1; /* NOT found */
2013 * given a LOGICAL APIC# and pin#, return:
2014 * the associated INTerrupt type if found
2018 apic_int_type(int apic, int pin)
2022 /* search each of the possible INTerrupt sources */
2023 for (x = 0; x < nintrs; ++x) {
2024 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2025 (pin == io_apic_ints[x].dst_apic_int))
2026 return (io_apic_ints[x].int_type);
2028 return -1; /* NOT found */
2032 * Return the IRQ associated with an APIC pin
2035 apic_irq(int apic, int pin)
2040 for (x = 0; x < nintrs; ++x) {
2041 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2042 (pin == io_apic_ints[x].dst_apic_int)) {
2043 res = io_apic_ints[x].int_vector;
2046 if (apic != int_to_apicintpin[res].ioapic)
2047 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2048 if (pin != int_to_apicintpin[res].int_pin)
2049 panic("apic_irq inconsistent table (2)");
2058 * given a LOGICAL APIC# and pin#, return:
2059 * the associated trigger mode if found
2063 apic_trigger(int apic, int pin)
2067 /* search each of the possible INTerrupt sources */
2068 for (x = 0; x < nintrs; ++x)
2069 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2070 (pin == io_apic_ints[x].dst_apic_int))
2071 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2073 return -1; /* NOT found */
2078 * given a LOGICAL APIC# and pin#, return:
2079 * the associated 'active' level if found
2083 apic_polarity(int apic, int pin)
2087 /* search each of the possible INTerrupt sources */
2088 for (x = 0; x < nintrs; ++x)
2089 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2090 (pin == io_apic_ints[x].dst_apic_int))
2091 return (io_apic_ints[x].int_flags & 0x03);
2093 return -1; /* NOT found */
2099 * set data according to MP defaults
2100 * FIXME: probably not complete yet...
2103 mptable_default(int type)
2105 #if defined(APIC_IO)
2108 #endif /* APIC_IO */
2111 kprintf(" MP default config type: %d\n", type);
2114 kprintf(" bus: ISA, APIC: 82489DX\n");
2117 kprintf(" bus: EISA, APIC: 82489DX\n");
2120 kprintf(" bus: EISA, APIC: 82489DX\n");
2123 kprintf(" bus: MCA, APIC: 82489DX\n");
2126 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2129 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2132 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2135 kprintf(" future type\n");
2141 #if defined(APIC_IO)
2142 /* one and only IO APIC */
2143 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2146 * sanity check, refer to MP spec section 3.6.6, last paragraph
2147 * necessary as some hardware isn't properly setting up the IO APIC
2149 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2150 if (io_apic_id != 2) {
2152 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2153 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2154 io_apic_set_id(0, 2);
2157 IO_TO_ID(0) = io_apic_id;
2158 ID_TO_IO(io_apic_id) = 0;
2159 #endif /* APIC_IO */
2161 /* fill out bus entries */
2171 bus_data[0].bus_id = default_data[type - 1][1];
2172 bus_data[0].bus_type = default_data[type - 1][2];
2173 bus_data[1].bus_id = default_data[type - 1][3];
2174 bus_data[1].bus_type = default_data[type - 1][4];
2178 /* case 4: case 7: MCA NOT supported */
2179 default: /* illegal/reserved */
2180 panic("BAD default MP config: %d", type);
2184 #if defined(APIC_IO)
2185 /* general cases from MP v1.4, table 5-2 */
2186 for (pin = 0; pin < 16; ++pin) {
2187 io_apic_ints[pin].int_type = 0;
2188 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2189 io_apic_ints[pin].src_bus_id = 0;
2190 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2191 io_apic_ints[pin].dst_apic_id = io_apic_id;
2192 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2195 /* special cases from MP v1.4, table 5-2 */
2197 io_apic_ints[2].int_type = 0xff; /* N/C */
2198 io_apic_ints[13].int_type = 0xff; /* N/C */
2199 #if !defined(APIC_MIXED_MODE)
2201 panic("sorry, can't support type 2 default yet");
2202 #endif /* APIC_MIXED_MODE */
2205 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2208 io_apic_ints[0].int_type = 0xff; /* N/C */
2210 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2211 #endif /* APIC_IO */
2215 * Map a physical memory address representing I/O into KVA. The I/O
2216 * block is assumed not to cross a page boundary.
2219 permanent_io_mapping(vm_paddr_t pa)
2225 KKASSERT(pa < 0x100000000LL);
2227 pgeflag = 0; /* not used for SMP yet */
2230 * If the requested physical address has already been incidently
2231 * mapped, just use the existing mapping. Otherwise create a new
2234 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2235 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2236 ((vm_offset_t)pa & PG_FRAME)) {
2240 if (i == SMPpt_alloc_index) {
2241 if (i == NPTEPG - 2) {
2242 panic("permanent_io_mapping: We ran out of space"
2245 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2246 ((vm_offset_t)pa & PG_FRAME));
2247 ++SMPpt_alloc_index;
2249 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2250 ((vm_offset_t)pa & PAGE_MASK);
2251 return ((void *)vaddr);
2255 * start each AP in our list
2258 start_all_aps(u_int boot_addr)
2262 u_char mpbiosreason;
2263 u_long mpbioswarmvec;
2264 struct mdglobaldata *gd;
2265 struct privatespace *ps;
2269 POSTCODE(START_ALL_APS_POST);
2271 /* Initialize BSP's local APIC */
2272 apic_initialize(TRUE);
2274 /* install the AP 1st level boot code */
2275 install_ap_tramp(boot_addr);
2278 /* save the current value of the warm-start vector */
2279 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2280 outb(CMOS_REG, BIOS_RESET);
2281 mpbiosreason = inb(CMOS_DATA);
2283 /* set up temporary P==V mapping for AP boot */
2284 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2285 kptbase = (uintptr_t)(void *)KPTphys;
2286 for (x = 0; x < NKPT; x++) {
2287 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2288 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2293 for (x = 1; x <= mp_naps; ++x) {
2295 /* This is a bit verbose, it will go away soon. */
2297 /* first page of AP's private space */
2298 pg = x * i386_btop(sizeof(struct privatespace));
2300 /* allocate new private data page(s) */
2301 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2302 MDGLOBALDATA_BASEALLOC_SIZE);
2303 /* wire it into the private page table page */
2304 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2305 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2306 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2308 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2310 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2311 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2312 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2313 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2315 /* allocate and set up an idle stack data page */
2316 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2317 for (i = 0; i < UPAGES; i++) {
2318 SMPpt[pg + 4 + i] = (pt_entry_t)
2319 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2322 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2323 bzero(gd, sizeof(*gd));
2324 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2326 /* prime data page for it to use */
2327 mi_gdinit(&gd->mi, x);
2329 gd->gd_CMAP1 = &SMPpt[pg + 0];
2330 gd->gd_CMAP2 = &SMPpt[pg + 1];
2331 gd->gd_CMAP3 = &SMPpt[pg + 2];
2332 gd->gd_PMAP1 = &SMPpt[pg + 3];
2333 gd->gd_CADDR1 = ps->CPAGE1;
2334 gd->gd_CADDR2 = ps->CPAGE2;
2335 gd->gd_CADDR3 = ps->CPAGE3;
2336 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2337 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2338 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2340 /* setup a vector to our boot code */
2341 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2342 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2343 outb(CMOS_REG, BIOS_RESET);
2344 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2347 * Setup the AP boot stack
2349 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2352 /* attempt to start the Application Processor */
2353 CHECK_INIT(99); /* setup checkpoints */
2354 if (!start_ap(gd, boot_addr)) {
2355 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2356 CHECK_PRINT("trace"); /* show checkpoints */
2357 /* better panic as the AP may be running loose */
2358 kprintf("panic y/n? [y] ");
2359 if (cngetc() != 'n')
2362 CHECK_PRINT("trace"); /* show checkpoints */
2364 /* record its version info */
2365 cpu_apic_versions[x] = cpu_apic_versions[0];
2368 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2371 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2372 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2375 ncpus2_shift = shift;
2376 ncpus2 = 1 << shift;
2377 ncpus2_mask = ncpus2 - 1;
2379 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2380 if ((1 << shift) < ncpus)
2382 ncpus_fit = 1 << shift;
2383 ncpus_fit_mask = ncpus_fit - 1;
2385 /* build our map of 'other' CPUs */
2386 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2387 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2388 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2390 /* fill in our (BSP) APIC version */
2391 cpu_apic_versions[0] = lapic.version;
2393 /* restore the warmstart vector */
2394 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2395 outb(CMOS_REG, BIOS_RESET);
2396 outb(CMOS_DATA, mpbiosreason);
2399 * NOTE! The idlestack for the BSP was setup by locore. Finish
2400 * up, clean out the P==V mapping we did earlier.
2402 for (x = 0; x < NKPT; x++)
2406 /* number of APs actually started */
2412 * load the 1st level AP boot code into base memory.
2415 /* targets for relocation */
2416 extern void bigJump(void);
2417 extern void bootCodeSeg(void);
2418 extern void bootDataSeg(void);
2419 extern void MPentry(void);
2420 extern u_int MP_GDT;
2421 extern u_int mp_gdtbase;
2424 install_ap_tramp(u_int boot_addr)
2427 int size = *(int *) ((u_long) & bootMP_size);
2428 u_char *src = (u_char *) ((u_long) bootMP);
2429 u_char *dst = (u_char *) boot_addr + KERNBASE;
2430 u_int boot_base = (u_int) bootMP;
2435 POSTCODE(INSTALL_AP_TRAMP_POST);
2437 for (x = 0; x < size; ++x)
2441 * modify addresses in code we just moved to basemem. unfortunately we
2442 * need fairly detailed info about mpboot.s for this to work. changes
2443 * to mpboot.s might require changes here.
2446 /* boot code is located in KERNEL space */
2447 dst = (u_char *) boot_addr + KERNBASE;
2449 /* modify the lgdt arg */
2450 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2451 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2453 /* modify the ljmp target for MPentry() */
2454 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2455 *dst32 = ((u_int) MPentry - KERNBASE);
2457 /* modify the target for boot code segment */
2458 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2459 dst8 = (u_int8_t *) (dst16 + 1);
2460 *dst16 = (u_int) boot_addr & 0xffff;
2461 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2463 /* modify the target for boot data segment */
2464 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2465 dst8 = (u_int8_t *) (dst16 + 1);
2466 *dst16 = (u_int) boot_addr & 0xffff;
2467 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2472 * this function starts the AP (application processor) identified
2473 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2474 * to accomplish this. This is necessary because of the nuances
2475 * of the different hardware we might encounter. It ain't pretty,
2476 * but it seems to work.
2478 * NOTE: eventually an AP gets to ap_init(), which is called just
2479 * before the AP goes into the LWKT scheduler's idle loop.
2482 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2486 u_long icr_lo, icr_hi;
2488 POSTCODE(START_AP_POST);
2490 /* get the PHYSICAL APIC ID# */
2491 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2493 /* calculate the vector */
2494 vector = (boot_addr >> 12) & 0xff;
2496 /* Make sure the target cpu sees everything */
2500 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2501 * and running the target CPU. OR this INIT IPI might be latched (P5
2502 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2506 /* setup the address for the target AP */
2507 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2508 icr_hi |= (physical_cpu << 24);
2509 lapic.icr_hi = icr_hi;
2511 /* do an INIT IPI: assert RESET */
2512 icr_lo = lapic.icr_lo & 0xfff00000;
2513 lapic.icr_lo = icr_lo | 0x0000c500;
2515 /* wait for pending status end */
2516 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2519 /* do an INIT IPI: deassert RESET */
2520 lapic.icr_lo = icr_lo | 0x00008500;
2522 /* wait for pending status end */
2523 u_sleep(10000); /* wait ~10mS */
2524 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2528 * next we do a STARTUP IPI: the previous INIT IPI might still be
2529 * latched, (P5 bug) this 1st STARTUP would then terminate
2530 * immediately, and the previously started INIT IPI would continue. OR
2531 * the previous INIT IPI has already run. and this STARTUP IPI will
2532 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2536 /* do a STARTUP IPI */
2537 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2538 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2540 u_sleep(200); /* wait ~200uS */
2543 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2544 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2545 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2546 * recognized after hardware RESET or INIT IPI.
2549 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2550 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2552 u_sleep(200); /* wait ~200uS */
2554 /* wait for it to start, see ap_init() */
2555 set_apic_timer(5000000);/* == 5 seconds */
2556 while (read_apic_timer()) {
2557 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2558 return 1; /* return SUCCESS */
2560 return 0; /* return FAILURE */
2565 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2567 * If for some reason we were unable to start all cpus we cannot safely
2568 * use broadcast IPIs.
2574 if (smp_startup_mask == smp_active_mask) {
2575 all_but_self_ipi(XINVLTLB_OFFSET);
2577 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2578 APIC_DELMODE_FIXED);
2584 * When called the executing CPU will send an IPI to all other CPUs
2585 * requesting that they halt execution.
2587 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2589 * - Signals all CPUs in map to stop.
2590 * - Waits for each to stop.
2597 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2598 * from executing at same time.
2601 stop_cpus(u_int map)
2603 map &= smp_active_mask;
2605 /* send the Xcpustop IPI to all CPUs in map */
2606 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2608 while ((stopped_cpus & map) != map)
2616 * Called by a CPU to restart stopped CPUs.
2618 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2620 * - Signals all CPUs in map to restart.
2621 * - Waits for each to restart.
2629 restart_cpus(u_int map)
2631 /* signal other cpus to restart */
2632 started_cpus = map & smp_active_mask;
2634 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2641 * This is called once the mpboot code has gotten us properly relocated
2642 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2643 * and when it returns the scheduler will call the real cpu_idle() main
2644 * loop for the idlethread. Interrupts are disabled on entry and should
2645 * remain disabled at return.
2653 * Adjust smp_startup_mask to signal the BSP that we have started
2654 * up successfully. Note that we do not yet hold the BGL. The BSP
2655 * is waiting for our signal.
2657 * We can't set our bit in smp_active_mask yet because we are holding
2658 * interrupts physically disabled and remote cpus could deadlock
2659 * trying to send us an IPI.
2661 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2665 * Interlock for finalization. Wait until mp_finish is non-zero,
2666 * then get the MP lock.
2668 * Note: We are in a critical section.
2670 * Note: We have to synchronize td_mpcount to our desired MP state
2671 * before calling cpu_try_mplock().
2673 * Note: we are the idle thread, we can only spin.
2675 * Note: The load fence is memory volatile and prevents the compiler
2676 * from improperly caching mp_finish, and the cpu from improperly
2679 while (mp_finish == 0)
2681 ++curthread->td_mpcount;
2682 while (cpu_try_mplock() == 0)
2685 if (cpu_feature & CPUID_TSC) {
2687 * The BSP is constantly updating tsc0_offset, figure out the
2688 * relative difference to synchronize ktrdump.
2690 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2693 /* BSP may have changed PTD while we're waiting for the lock */
2696 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2700 /* Build our map of 'other' CPUs. */
2701 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2703 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2705 /* A quick check from sanity claus */
2706 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2707 if (mycpu->gd_cpuid != apic_id) {
2708 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2709 kprintf("SMP: apic_id = %d\n", apic_id);
2710 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2711 panic("cpuid mismatch! boom!!");
2714 /* Initialize AP's local APIC for irq's */
2715 apic_initialize(FALSE);
2717 /* Set memory range attributes for this CPU to match the BSP */
2718 mem_range_AP_init();
2721 * Once we go active we must process any IPIQ messages that may
2722 * have been queued, because no actual IPI will occur until we
2723 * set our bit in the smp_active_mask. If we don't the IPI
2724 * message interlock could be left set which would also prevent
2727 * The idle loop doesn't expect the BGL to be held and while
2728 * lwkt_switch() normally cleans things up this is a special case
2729 * because we returning almost directly into the idle loop.
2731 * The idle thread is never placed on the runq, make sure
2732 * nothing we've done put it there.
2734 KKASSERT(curthread->td_mpcount == 1);
2735 smp_active_mask |= 1 << mycpu->gd_cpuid;
2738 * Enable interrupts here. idle_restore will also do it, but
2739 * doing it here lets us clean up any strays that got posted to
2740 * the CPU during the AP boot while we are still in a critical
2743 __asm __volatile("sti; pause; pause"::);
2744 mdcpu->gd_fpending = 0;
2745 mdcpu->gd_ipending = 0;
2747 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2748 lwkt_process_ipiq();
2751 * Releasing the mp lock lets the BSP finish up the SMP init
2754 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2758 * Get SMP fully working before we start initializing devices.
2766 kprintf("Finish MP startup\n");
2767 if (cpu_feature & CPUID_TSC)
2768 tsc0_offset = rdtsc();
2771 while (smp_active_mask != smp_startup_mask) {
2773 if (cpu_feature & CPUID_TSC)
2774 tsc0_offset = rdtsc();
2776 while (try_mplock() == 0)
2779 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2782 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2785 cpu_send_ipiq(int dcpu)
2787 if ((1 << dcpu) & smp_active_mask)
2788 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2791 #if 0 /* single_apic_ipi_passive() not working yet */
2793 * Returns 0 on failure, 1 on success
2796 cpu_send_ipiq_passive(int dcpu)
2799 if ((1 << dcpu) & smp_active_mask) {
2800 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2801 APIC_DELMODE_FIXED);
2807 struct mptable_lapic_cbarg1 {
2813 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2815 const struct PROCENTRY *ent;
2816 struct mptable_lapic_cbarg1 *arg = xarg;
2822 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2826 arg->id_mask |= 1 << ent->apic_id;
2830 struct mptable_lapic_cbarg2 {
2836 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2838 const struct PROCENTRY *ent;
2839 struct mptable_lapic_cbarg2 *arg = xarg;
2845 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2846 KKASSERT(!arg->found_bsp);
2850 if (processor_entry(ent, arg->cpu))
2853 if (need_hyperthreading_fixup) {
2854 struct PROCENTRY proc;
2858 * Create fake mptable processor entries
2859 * and feed them to processor_entry() to
2860 * enumerate the logical CPUs.
2862 bzero(&proc, sizeof(proc));
2864 proc.cpu_flags = PROCENTRY_FLAG_EN;
2865 proc.apic_id = ent->apic_id;
2867 for (i = 1; i < logical_cpus; i++) {
2869 processor_entry(&proc, arg->cpu);
2870 logical_cpus_mask |= (1 << arg->cpu);
2879 * cpu_apic_address (common to all CPUs)
2881 * need_hyperthreading_fixup
2884 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
2885 * CPU_TO_ID(N), logical CPU to APIC ID table
2888 mptable_lapic_enumerate(struct mptable_pos *mpt)
2892 vm_offset_t lapic_addr;
2895 KKASSERT(fps != NULL);
2897 /* init everything to empty */
2900 /* check for use of 'default' configuration */
2901 if (fps->mpfb1 != 0) {
2902 /* use default addresses */
2903 lapic_addr = DEFAULT_APIC_BASE;
2905 /* fill in with defaults */
2906 mp_naps = 1; /* exclude BSP */
2908 struct mptable_lapic_cbarg1 arg;
2912 KKASSERT(cth != NULL);
2914 lapic_addr = (vm_offset_t)cth->apic_address;
2915 KKASSERT(lapic_addr != 0);
2917 bzero(&arg, sizeof(arg));
2918 error = mptable_iterate_entries(cth,
2919 mptable_lapic_pass1_callback, &arg);
2921 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2923 KKASSERT(arg.cpu_count != 0);
2924 mp_naps = arg.cpu_count;
2926 /* Qualify the numbers */
2927 if (mp_naps > MAXCPU) {
2928 kprintf("Warning: only using %d of %d available CPUs!\n",
2933 /* See if we need to fixup HT logical CPUs. */
2934 mptable_hyperthread_fixup(arg.id_mask);
2936 /* Qualify the numbers again, after hyperthreading fixup */
2937 if (mp_naps > MAXCPU) {
2938 kprintf("Warning: only using %d of %d available CPUs!\n",
2943 --mp_naps; /* subtract the BSP */
2946 lapic_init(lapic_addr);
2948 if (fps->mpfb1 != 0) {
2949 int ap_cpu_id, boot_cpu_id;
2951 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
2952 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2955 CPU_TO_ID(0) = boot_cpu_id;
2956 ID_TO_CPU(boot_cpu_id) = 0;
2958 /* one and only AP */
2959 CPU_TO_ID(1) = ap_cpu_id;
2960 ID_TO_CPU(ap_cpu_id) = 1;
2962 struct mptable_lapic_cbarg2 arg;
2964 bzero(&arg, sizeof(arg));
2967 error = mptable_iterate_entries(mpt->mp_cth,
2968 mptable_lapic_pass2_callback, &arg);
2970 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2971 KKASSERT(arg.found_bsp);
2976 lapic_init(vm_offset_t lapic_addr)
2978 /* Local apic is mapped on last page */
2979 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
2980 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
2982 /* Just for printing */
2983 cpu_apic_address = lapic_addr;