2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 #include "opt_polling.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/socket.h>
44 #include <sys/sysctl.h>
45 #include <sys/thread2.h>
48 #include <net/ifq_var.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
53 #include <sys/sockio.h>
57 #include <net/ethernet.h>
58 #include <net/if_arp.h>
60 #include <vm/vm.h> /* for vtophys */
61 #include <vm/pmap.h> /* for vtophys */
63 #include <net/if_types.h>
64 #include <net/vlan/if_vlan_var.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
69 #include "../mii_layer/mii.h"
70 #include "../mii_layer/miivar.h"
72 #include "if_fxpreg.h"
73 #include "if_fxpvar.h"
76 #include "miibus_if.h"
79 * NOTE! On the Alpha, we have an alignment constraint. The
80 * card DMAs the packet immediately following the RFA. However,
81 * the first thing in the packet is a 14-byte Ethernet header.
82 * This means that the packet is misaligned. To compensate,
83 * we actually offset the RFA 2 bytes into the cluster. This
84 * alignes the packet after the Ethernet header at a 32-bit
85 * boundary. HOWEVER! This means that the RFA is misaligned!
87 #define RFA_ALIGNMENT_FUDGE 2
90 * Set initial transmit threshold at 64 (512 bytes). This is
91 * increased by 64 (512 bytes) at a time, to maximum of 192
92 * (1536 bytes), if an underrun occurs.
94 static int tx_threshold = 64;
97 * The configuration byte map has several undefined fields which
98 * must be one or must be zero. Set up a template for these bits
99 * only, (assuming a 82557 chip) leaving the actual configuration
102 * See struct fxp_cb_config for the bit definitions.
104 static u_char fxp_cb_config_template[] = {
105 0x0, 0x0, /* cb_status */
106 0x0, 0x0, /* cb_command */
107 0x0, 0x0, 0x0, 0x0, /* link_addr */
134 int16_t revid; /* -1 matches anything */
139 * Claim various Intel PCI device identifiers for this driver. The
140 * sub-vendor and sub-device field are extensively used to identify
141 * particular variants, but we don't currently differentiate between
144 static struct fxp_ident fxp_ident_table[] = {
145 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
146 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
147 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
148 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
149 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
150 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
151 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
152 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
153 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
154 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
156 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
157 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
158 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
159 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
160 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
161 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
162 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
163 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
164 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" },
165 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
166 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
167 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
168 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" },
169 { 0x1092, -1, "Intel Pro/100 VE Network Connection" },
170 { 0x1093, -1, "Intel Pro/100 VM Network Connection" },
171 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" },
172 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
173 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
174 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
175 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
176 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
177 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
178 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
179 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
180 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
181 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
182 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
183 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
184 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
185 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
186 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
187 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
188 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
189 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" },
193 static int fxp_probe(device_t dev);
194 static int fxp_attach(device_t dev);
195 static int fxp_detach(device_t dev);
196 static int fxp_shutdown(device_t dev);
197 static int fxp_suspend(device_t dev);
198 static int fxp_resume(device_t dev);
200 static void fxp_intr(void *xsc);
201 static void fxp_intr_body(struct fxp_softc *sc,
202 u_int8_t statack, int count);
204 static void fxp_init(void *xsc);
205 static void fxp_tick(void *xsc);
206 static void fxp_powerstate_d0(device_t dev);
207 static void fxp_start(struct ifnet *ifp);
208 static void fxp_stop(struct fxp_softc *sc);
209 static void fxp_release(device_t dev);
210 static int fxp_ioctl(struct ifnet *ifp, u_long command,
211 caddr_t data, struct ucred *);
212 static void fxp_watchdog(struct ifnet *ifp);
213 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
214 static int fxp_mc_addrs(struct fxp_softc *sc);
215 static void fxp_mc_setup(struct fxp_softc *sc);
216 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
218 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
220 static void fxp_autosize_eeprom(struct fxp_softc *sc);
221 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
222 int offset, int words);
223 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
224 int offset, int words);
225 static int fxp_ifmedia_upd(struct ifnet *ifp);
226 static void fxp_ifmedia_sts(struct ifnet *ifp,
227 struct ifmediareq *ifmr);
228 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
229 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
230 struct ifmediareq *ifmr);
231 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
232 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
234 static void fxp_load_ucode(struct fxp_softc *sc);
235 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
236 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
237 #ifdef DEVICE_POLLING
238 static poll_handler_t fxp_poll;
241 static void fxp_lwcopy(volatile u_int32_t *src,
242 volatile u_int32_t *dst);
243 static void fxp_scb_wait(struct fxp_softc *sc);
244 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
245 static void fxp_dma_wait(volatile u_int16_t *status,
246 struct fxp_softc *sc);
248 static device_method_t fxp_methods[] = {
249 /* Device interface */
250 DEVMETHOD(device_probe, fxp_probe),
251 DEVMETHOD(device_attach, fxp_attach),
252 DEVMETHOD(device_detach, fxp_detach),
253 DEVMETHOD(device_shutdown, fxp_shutdown),
254 DEVMETHOD(device_suspend, fxp_suspend),
255 DEVMETHOD(device_resume, fxp_resume),
258 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
259 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
264 static driver_t fxp_driver = {
267 sizeof(struct fxp_softc),
270 static devclass_t fxp_devclass;
272 DECLARE_DUMMY_MODULE(if_fxp);
273 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
274 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, NULL, NULL);
275 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, NULL, NULL);
276 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
279 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
282 * Copy a 16-bit aligned 32-bit quantity.
285 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
290 volatile u_int16_t *a = (volatile u_int16_t *)src;
291 volatile u_int16_t *b = (volatile u_int16_t *)dst;
299 * Wait for the previous command to be accepted (but not necessarily
303 fxp_scb_wait(struct fxp_softc *sc)
307 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
310 if_printf(&sc->arpcom.ac_if,
311 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
312 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
313 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
314 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
315 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
320 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
323 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
324 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
327 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
331 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
335 while (!(*status & FXP_CB_STATUS_C) && --i)
338 if_printf(&sc->arpcom.ac_if, "DMA timeout\n");
342 * Return identification string if this is device is ours.
345 fxp_probe(device_t dev)
349 struct fxp_ident *ident;
351 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
352 devid = pci_get_device(dev);
353 revid = pci_get_revid(dev);
354 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
355 if (ident->devid == devid &&
356 (ident->revid == revid || ident->revid == -1)) {
357 device_set_desc(dev, ident->name);
366 fxp_powerstate_d0(device_t dev)
368 u_int32_t iobase, membase, irq;
370 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
371 /* Save important PCI config data. */
372 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
373 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
374 irq = pci_read_config(dev, PCIR_INTLINE, 4);
376 /* Reset the power state. */
377 device_printf(dev, "chip is in D%d power mode "
378 "-- setting to D0\n", pci_get_powerstate(dev));
380 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
382 /* Restore PCI config data. */
383 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
384 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
385 pci_write_config(dev, PCIR_INTLINE, irq, 4);
390 fxp_attach(device_t dev)
393 struct fxp_softc *sc = device_get_softc(dev);
397 int i, rid, m1, m2, prefer_iomap;
399 callout_init(&sc->fxp_stat_timer);
400 sysctl_ctx_init(&sc->sysctl_ctx);
403 * Enable bus mastering. Enable memory space too, in case
404 * BIOS/Prom forgot about it.
406 pci_enable_busmaster(dev);
407 pci_enable_io(dev, SYS_RES_MEMORY);
408 val = pci_read_config(dev, PCIR_COMMAND, 2);
410 fxp_powerstate_d0(dev);
413 * Figure out which we should try first - memory mapping or i/o mapping?
414 * We default to memory mapping. Then we accept an override from the
415 * command line. Then we check to see which one is enabled.
418 m2 = PCIM_CMD_PORTEN;
420 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
421 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
422 m1 = PCIM_CMD_PORTEN;
428 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
429 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
430 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
433 if (sc->mem == NULL && (val & m2)) {
435 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
436 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
437 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
442 device_printf(dev, "could not map device registers\n");
447 device_printf(dev, "using %s space register mapping\n",
448 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
451 sc->sc_st = rman_get_bustag(sc->mem);
452 sc->sc_sh = rman_get_bushandle(sc->mem);
455 * Allocate our interrupt.
458 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
459 RF_SHAREABLE | RF_ACTIVE);
460 if (sc->irq == NULL) {
461 device_printf(dev, "could not map interrupt\n");
467 * Reset to a stable state.
469 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
472 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
473 M_DEVBUF, M_WAITOK | M_ZERO);
475 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF,
478 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
481 * Pre-allocate our receive buffers.
483 for (i = 0; i < FXP_NRFABUFS; i++) {
484 if (fxp_add_rfabuf(sc, NULL) != 0) {
490 * Find out how large of an SEEPROM we have.
492 fxp_autosize_eeprom(sc);
495 * Determine whether we must use the 503 serial interface.
497 fxp_read_eeprom(sc, &data, 6, 1);
498 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
499 (data & FXP_PHY_SERIAL_ONLY))
500 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
503 * Create the sysctl tree
505 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
506 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
507 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
508 if (sc->sysctl_tree == NULL)
510 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
511 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
512 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
513 "FXP driver receive interrupt microcode bundling delay");
514 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
515 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
516 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
517 "FXP driver receive interrupt microcode bundle size limit");
520 * Pull in device tunables.
522 sc->tunable_int_delay = TUNABLE_INT_DELAY;
523 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
524 resource_int_value(device_get_name(dev), device_get_unit(dev),
525 "int_delay", &sc->tunable_int_delay);
526 resource_int_value(device_get_name(dev), device_get_unit(dev),
527 "bundle_max", &sc->tunable_bundle_max);
530 * Find out the chip revision; lump all 82557 revs together.
532 fxp_read_eeprom(sc, &data, 5, 1);
533 if ((data >> 8) == 1)
534 sc->revision = FXP_REV_82557;
536 sc->revision = pci_get_revid(dev);
539 * Enable workarounds for certain chip revision deficiencies.
541 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
542 * some systems based a normal 82559 design, have a defect where
543 * the chip can cause a PCI protocol violation if it receives
544 * a CU_RESUME command when it is entering the IDLE state. The
545 * workaround is to disable Dynamic Standby Mode, so the chip never
546 * deasserts CLKRUN#, and always remains in an active state.
548 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
550 i = pci_get_device(dev);
551 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
552 sc->revision >= FXP_REV_82559_A0) {
553 fxp_read_eeprom(sc, &data, 10, 1);
554 if (data & 0x02) { /* STB enable */
559 "Disabling dynamic standby mode in EEPROM\n");
561 fxp_write_eeprom(sc, &data, 10, 1);
562 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
564 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
565 fxp_read_eeprom(sc, &data, i, 1);
568 i = (1 << sc->eeprom_size) - 1;
569 cksum = 0xBABA - cksum;
570 fxp_read_eeprom(sc, &data, i, 1);
571 fxp_write_eeprom(sc, &cksum, i, 1);
573 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
577 * If the user elects to continue, try the software
578 * workaround, as it is better than nothing.
580 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
586 * If we are not a 82557 chip, we can enable extended features.
588 if (sc->revision != FXP_REV_82557) {
590 * If MWI is enabled in the PCI configuration, and there
591 * is a valid cacheline size (8 or 16 dwords), then tell
592 * the board to turn on MWI.
594 if (val & PCIM_CMD_MWRICEN &&
595 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
596 sc->flags |= FXP_FLAG_MWI_ENABLE;
598 /* turn on the extended TxCB feature */
599 sc->flags |= FXP_FLAG_EXT_TXCB;
601 /* enable reception of long frames for VLAN */
602 sc->flags |= FXP_FLAG_LONG_PKT_EN;
608 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
609 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
610 device_printf(dev, "10Mbps\n");
612 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
613 pci_get_vendor(dev), pci_get_device(dev),
614 pci_get_subvendor(dev), pci_get_subdevice(dev),
616 fxp_read_eeprom(sc, &data, 10, 1);
617 device_printf(dev, "Dynamic Standby mode is %s\n",
618 data & 0x02 ? "enabled" : "disabled");
622 * If this is only a 10Mbps device, then there is no MII, and
623 * the PHY will use a serial interface instead.
625 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
626 * doesn't have a programming interface of any sort. The
627 * media is sensed automatically based on how the link partner
628 * is configured. This is, in essence, manual configuration.
630 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
631 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
632 fxp_serial_ifmedia_sts);
633 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
634 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
636 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
638 device_printf(dev, "MII without any PHY!\n");
644 ifp = &sc->arpcom.ac_if;
645 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
646 ifp->if_baudrate = 100000000;
647 ifp->if_init = fxp_init;
649 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
650 ifp->if_ioctl = fxp_ioctl;
651 ifp->if_start = fxp_start;
652 #ifdef DEVICE_POLLING
653 ifp->if_poll = fxp_poll;
655 ifp->if_watchdog = fxp_watchdog;
658 * Attach the interface.
660 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
663 * Tell the upper layer(s) we support long frames.
665 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
668 * Let the system queue as many packets as we have available
671 ifq_set_maxlen(&ifp->if_snd, FXP_USABLE_TXCB);
672 ifq_set_ready(&ifp->if_snd);
674 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
675 fxp_intr, sc, &sc->ih,
679 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
680 ifmedia_removeall(&sc->sc_media);
681 device_printf(dev, "could not setup irq\n");
685 ifp->if_cpuid = rman_get_cpuid(sc->irq);
686 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
691 device_printf(dev, "Failed to malloc memory\n");
699 * release all resources
702 fxp_release(device_t dev)
704 struct fxp_softc *sc = device_get_softc(dev);
707 device_delete_child(dev, sc->miibus);
708 bus_generic_detach(dev);
711 kfree(sc->cbl_base, M_DEVBUF);
713 kfree(sc->fxp_stats, M_DEVBUF);
715 kfree(sc->mcsp, M_DEVBUF);
717 m_freem(sc->rfa_headm);
720 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
722 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
724 sysctl_ctx_free(&sc->sysctl_ctx);
731 fxp_detach(device_t dev)
733 struct fxp_softc *sc = device_get_softc(dev);
735 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
738 * Stop DMA and drop transmit queue.
743 * Disable interrupts.
745 * NOTE: This should be done after fxp_stop(), because software
746 * resetting in fxp_stop() may leave interrupts turned on.
748 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
751 * Free all media structures.
753 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
754 ifmedia_removeall(&sc->sc_media);
757 bus_teardown_intr(dev, sc->irq, sc->ih);
759 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
762 * Close down routes etc.
764 ether_ifdetach(&sc->arpcom.ac_if);
766 /* Release our allocated resources. */
773 * Device shutdown routine. Called at system shutdown after sync. The
774 * main purpose of this routine is to shut off receiver DMA so that
775 * kernel memory doesn't get clobbered during warmboot.
778 fxp_shutdown(device_t dev)
780 struct fxp_softc *sc = device_get_softc(dev);
781 struct ifnet *ifp = &sc->arpcom.ac_if;
783 lwkt_serialize_enter(ifp->if_serializer);
785 * Make sure that DMA is disabled prior to reboot. Not doing
786 * do could allow DMA to corrupt kernel memory during the
787 * reboot before the driver initializes.
790 lwkt_serialize_exit(ifp->if_serializer);
795 * Device suspend routine. Stop the interface and save some PCI
796 * settings in case the BIOS doesn't restore them properly on
800 fxp_suspend(device_t dev)
802 struct fxp_softc *sc = device_get_softc(dev);
805 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
809 for (i = 0; i < 5; i++)
810 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
811 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
812 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
813 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
814 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
818 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
823 * Device resume routine. Restore some PCI settings in case the BIOS
824 * doesn't, re-enable busmastering, and restart the interface if
828 fxp_resume(device_t dev)
830 struct fxp_softc *sc = device_get_softc(dev);
831 struct ifnet *ifp = &sc->arpcom.ac_if;
834 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
836 fxp_powerstate_d0(dev);
838 /* better way to do this? */
839 for (i = 0; i < 5; i++)
840 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
841 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
842 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
843 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
844 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
846 /* reenable busmastering and memory space */
847 pci_enable_busmaster(dev);
848 pci_enable_io(dev, SYS_RES_MEMORY);
850 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
853 /* reinitialize interface if necessary */
854 if (ifp->if_flags & IFF_UP)
859 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
864 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
872 for (x = 1 << (length - 1); x; x >>= 1) {
874 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
876 reg = FXP_EEPROM_EECS;
877 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
879 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
881 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
887 * Read from the serial EEPROM. Basically, you manually shift in
888 * the read opcode (one bit at a time) and then shift in the address,
889 * and then you shift out the data (all of this one bit at a time).
890 * The word size is 16 bits, so you have to provide the address for
891 * every 16 bits of data.
894 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
899 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
901 * Shift in read opcode.
903 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
908 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
910 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
912 reg = FXP_EEPROM_EECS;
913 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
915 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
917 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
919 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
921 if (autosize && reg == 0) {
922 sc->eeprom_size = data;
930 reg = FXP_EEPROM_EECS;
931 for (x = 1 << 15; x; x >>= 1) {
932 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
934 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
936 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
946 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
951 * Erase/write enable.
953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
954 fxp_eeprom_shiftin(sc, 0x4, 3);
955 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
956 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
959 * Shift in write opcode, address, data.
961 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
962 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
963 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
964 fxp_eeprom_shiftin(sc, data, 16);
965 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
968 * Wait for EEPROM to finish up.
970 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
972 for (i = 0; i < 1000; i++) {
973 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
977 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
980 * Erase/write disable.
982 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
983 fxp_eeprom_shiftin(sc, 0x4, 3);
984 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
985 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
992 * Figure out EEPROM size.
994 * 559's can have either 64-word or 256-word EEPROMs, the 558
995 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
996 * talks about the existance of 16 to 256 word EEPROMs.
998 * The only known sizes are 64 and 256, where the 256 version is used
999 * by CardBus cards to store CIS information.
1001 * The address is shifted in msb-to-lsb, and after the last
1002 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1003 * after which follows the actual data. We try to detect this zero, by
1004 * probing the data-out bit in the EEPROM control register just after
1005 * having shifted in a bit. If the bit is zero, we assume we've
1006 * shifted enough address bits. The data-out should be tri-state,
1007 * before this, which should translate to a logical one.
1010 fxp_autosize_eeprom(struct fxp_softc *sc)
1013 /* guess maximum size of 256 words */
1014 sc->eeprom_size = 8;
1017 fxp_eeprom_getword(sc, 0, 1);
1021 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1025 for (i = 0; i < words; i++)
1026 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1030 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1034 for (i = 0; i < words; i++)
1035 fxp_eeprom_putword(sc, offset + i, data[i]);
1039 * Start packet transmission on the interface.
1042 fxp_start(struct ifnet *ifp)
1044 struct fxp_softc *sc = ifp->if_softc;
1045 struct fxp_cb_tx *txp;
1047 ASSERT_SERIALIZED(ifp->if_serializer);
1050 * See if we need to suspend xmit until the multicast filter
1051 * has been reprogrammed (which can only be done at the head
1052 * of the command chain).
1054 if (sc->need_mcsetup) {
1055 ifq_purge(&ifp->if_snd);
1059 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1065 * We're finished if there is nothing more to add to the list or if
1066 * we're all filled up with buffers to transmit.
1067 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1068 * a NOP command when needed.
1070 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_USABLE_TXCB) {
1071 struct mbuf *m, *mb_head;
1072 int segment, ntries = 0;
1075 * Grab a packet to transmit.
1077 mb_head = ifq_dequeue(&ifp->if_snd, NULL);
1078 if (mb_head == NULL)
1082 * Make sure that the packet fits into one TX desc
1085 for (m = mb_head; m != NULL; m = m->m_next) {
1086 if (m->m_len != 0) {
1088 if (segment >= FXP_NTXSEG)
1092 if (segment >= FXP_NTXSEG) {
1097 * Packet is excessively fragmented,
1098 * and will never fit into one TX
1106 mn = m_dup(mb_head, MB_DONTWAIT);
1120 * Get pointer to next available tx desc.
1122 txp = sc->cbl_last->next;
1125 * Go through each of the mbufs in the chain and initialize
1126 * the transmit buffer descriptors with the physical address
1127 * and size of the mbuf.
1129 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1130 if (m->m_len != 0) {
1131 KKASSERT(segment < FXP_NTXSEG);
1133 txp->tbd[segment].tb_addr =
1134 vtophys(mtod(m, vm_offset_t));
1135 txp->tbd[segment].tb_size = m->m_len;
1139 KKASSERT(m == NULL);
1141 txp->tbd_number = segment;
1142 txp->mb_head = mb_head;
1144 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1146 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1150 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1151 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1153 txp->tx_threshold = tx_threshold;
1156 * Advance the end of list forward.
1158 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1162 * Advance the beginning of the list forward if there are
1163 * no other packets queued (when nothing is queued, cbl_first
1164 * sits on the last TxCB that was sent out).
1166 if (sc->tx_queued == 0)
1167 sc->cbl_first = txp;
1171 * Set a 5 second timer just in case we don't hear
1172 * from the card again.
1176 BPF_MTAP(ifp, mb_head);
1179 if (sc->tx_queued >= FXP_USABLE_TXCB)
1180 ifp->if_flags |= IFF_OACTIVE;
1183 * We're finished. If we added to the list, issue a RESUME to get DMA
1184 * going again if suspended.
1188 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1192 #ifdef DEVICE_POLLING
1195 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1197 struct fxp_softc *sc = ifp->if_softc;
1200 ASSERT_SERIALIZED(ifp->if_serializer);
1204 /* disable interrupts */
1205 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1207 case POLL_DEREGISTER:
1208 /* enable interrupts */
1209 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1212 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1214 if (cmd == POLL_AND_CHECK_STATUS) {
1217 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1218 if (tmp == 0xff || tmp == 0)
1219 return; /* nothing to do */
1221 /* ack what we can */
1223 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1226 fxp_intr_body(sc, statack, count);
1231 #endif /* DEVICE_POLLING */
1234 * Process interface interrupts.
1239 struct fxp_softc *sc = xsc;
1242 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
1244 if (sc->suspended) {
1248 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1250 * It should not be possible to have all bits set; the
1251 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1252 * all bits are set, this may indicate that the card has
1253 * been physically ejected, so ignore it.
1255 if (statack == 0xff)
1259 * First ACK all the interrupts in this pass.
1261 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1262 fxp_intr_body(sc, statack, -1);
1267 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1269 struct ifnet *ifp = &sc->arpcom.ac_if;
1271 struct fxp_rfa *rfa;
1272 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1273 struct mbuf_chain chain[MAXCPU];
1277 #ifdef DEVICE_POLLING
1278 /* Pick up a deferred RNR condition if `count' ran out last time. */
1279 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1280 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1286 * Free any finished transmit mbuf chains.
1288 * Handle the CNA event likt a CXTNO event. It used to
1289 * be that this event (control unit not ready) was not
1290 * encountered, but it is now with the SMPng modifications.
1291 * The exact sequence of events that occur when the interface
1292 * is brought up are different now, and if this event
1293 * goes unhandled, the configuration/rxfilter setup sequence
1294 * can stall for several seconds. The result is that no
1295 * packets go out onto the wire for about 5 to 10 seconds
1296 * after the interface is ifconfig'ed for the first time.
1298 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1299 struct fxp_cb_tx *txp;
1301 for (txp = sc->cbl_first; sc->tx_queued &&
1302 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1304 if ((m = txp->mb_head) != NULL) {
1305 txp->mb_head = NULL;
1312 sc->cbl_first = txp;
1314 if (sc->tx_queued < FXP_USABLE_TXCB)
1315 ifp->if_flags &= ~IFF_OACTIVE;
1317 if (sc->tx_queued == 0) {
1319 if (sc->need_mcsetup)
1324 * Try to start more packets transmitting.
1326 if (!ifq_is_empty(&ifp->if_snd))
1331 * Just return if nothing happened on the receive side.
1333 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1336 ether_input_chain_init(chain);
1339 * Process receiver interrupts. If a no-resource (RNR)
1340 * condition exists, get whatever packets we can and
1341 * re-start the receiver.
1343 * When using polling, we do not process the list to completion,
1344 * so when we get an RNR interrupt we must defer the restart
1345 * until we hit the last buffer with the C bit set.
1346 * If we run out of cycles and rfa_headm has the C bit set,
1347 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1348 * that the info will be used in the subsequent polling cycle.
1352 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1353 RFA_ALIGNMENT_FUDGE);
1355 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1356 if (count >= 0 && count-- == 0) {
1358 /* Defer RNR processing until the next time. */
1359 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1364 #endif /* DEVICE_POLLING */
1366 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1370 * Remove first packet from the chain.
1372 sc->rfa_headm = m->m_next;
1373 if (sc->rfa_headm == NULL)
1374 sc->rfa_tailm = NULL;
1378 * Add a new buffer to the receive chain.
1379 * If this fails, the old buffer is recycled
1382 if (fxp_add_rfabuf(sc, m) == 0) {
1386 * Fetch packet length (the top 2 bits of
1387 * actual_size are flags set by the controller
1388 * upon completion), and drop the packet in case
1389 * of bogus length or CRC errors.
1391 total_len = rfa->actual_size & 0x3fff;
1392 if (total_len < sizeof(struct ether_header) ||
1393 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1394 sizeof(struct fxp_rfa) ||
1395 (rfa->rfa_status & FXP_RFA_STATUS_CRC)) {
1399 m->m_pkthdr.len = m->m_len = total_len;
1400 ether_input_chain(ifp, m, NULL, chain);
1404 ether_input_dispatch(chain);
1408 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1409 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1410 RFA_ALIGNMENT_FUDGE);
1411 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1416 * Update packet in/out/collision statistics. The i82557 doesn't
1417 * allow you to access these counters without doing a fairly
1418 * expensive DMA to get _all_ of the statistics it maintains, so
1419 * we do this operation here only once per second. The statistics
1420 * counters in the kernel are updated from the previous dump-stats
1421 * DMA and then a new dump-stats DMA is started. The on-chip
1422 * counters are zeroed when the DMA completes. If we can't start
1423 * the DMA immediately, we don't wait - we just prepare to read
1424 * them again next time.
1429 struct fxp_softc *sc = xsc;
1430 struct ifnet *ifp = &sc->arpcom.ac_if;
1431 struct fxp_stats *sp = sc->fxp_stats;
1432 struct fxp_cb_tx *txp;
1435 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1437 ifp->if_opackets += sp->tx_good;
1438 ifp->if_collisions += sp->tx_total_collisions;
1440 ifp->if_ipackets += sp->rx_good;
1441 sc->rx_idle_secs = 0;
1444 * Receiver's been idle for another second.
1450 sp->rx_alignment_errors +
1452 sp->rx_overrun_errors;
1454 * If any transmit underruns occured, bump up the transmit
1455 * threshold by another 512 bytes (64 * 8).
1457 if (sp->tx_underruns) {
1458 ifp->if_oerrors += sp->tx_underruns;
1459 if (tx_threshold < 192)
1464 * Release any xmit buffers that have completed DMA. This isn't
1465 * strictly necessary to do here, but it's advantagous for mbufs
1466 * with external storage to be released in a timely manner rather
1467 * than being defered for a potentially long time. This limits
1468 * the delay to a maximum of one second.
1470 for (txp = sc->cbl_first; sc->tx_queued &&
1471 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1473 if ((m = txp->mb_head) != NULL) {
1474 txp->mb_head = NULL;
1481 sc->cbl_first = txp;
1483 if (sc->tx_queued < FXP_USABLE_TXCB)
1484 ifp->if_flags &= ~IFF_OACTIVE;
1485 if (sc->tx_queued == 0)
1489 * Try to start more packets transmitting.
1491 if (!ifq_is_empty(&ifp->if_snd))
1495 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1496 * then assume the receiver has locked up and attempt to clear
1497 * the condition by reprogramming the multicast filter. This is
1498 * a work-around for a bug in the 82557 where the receiver locks
1499 * up if it gets certain types of garbage in the syncronization
1500 * bits prior to the packet header. This bug is supposed to only
1501 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1502 * mode as well (perhaps due to a 10/100 speed transition).
1504 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1505 sc->rx_idle_secs = 0;
1509 * If there is no pending command, start another stats
1510 * dump. Otherwise punt for now.
1512 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1514 * Start another stats dump.
1516 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1519 * A previous command is still waiting to be accepted.
1520 * Just zero our copy of the stats and wait for the
1521 * next timer event to update them.
1524 sp->tx_underruns = 0;
1525 sp->tx_total_collisions = 0;
1528 sp->rx_crc_errors = 0;
1529 sp->rx_alignment_errors = 0;
1530 sp->rx_rnr_errors = 0;
1531 sp->rx_overrun_errors = 0;
1533 if (sc->miibus != NULL)
1534 mii_tick(device_get_softc(sc->miibus));
1536 * Schedule another timeout one second from now.
1538 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1540 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1544 * Stop the interface. Cancels the statistics updater and resets
1548 fxp_stop(struct fxp_softc *sc)
1550 struct ifnet *ifp = &sc->arpcom.ac_if;
1551 struct fxp_cb_tx *txp;
1554 ASSERT_SERIALIZED(ifp->if_serializer);
1556 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1560 * Cancel stats updater.
1562 callout_stop(&sc->fxp_stat_timer);
1565 * Issue software reset, which also unloads the microcode.
1567 sc->flags &= ~FXP_FLAG_UCODE;
1568 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1572 * Release any xmit buffers.
1576 for (i = 0; i < FXP_NTXCB; i++) {
1577 if (txp[i].mb_head != NULL) {
1578 m_freem(txp[i].mb_head);
1579 txp[i].mb_head = NULL;
1586 * Free all the receive buffers then reallocate/reinitialize
1588 if (sc->rfa_headm != NULL)
1589 m_freem(sc->rfa_headm);
1590 sc->rfa_headm = NULL;
1591 sc->rfa_tailm = NULL;
1592 for (i = 0; i < FXP_NRFABUFS; i++) {
1593 if (fxp_add_rfabuf(sc, NULL) != 0) {
1595 * This "can't happen" - we're at splimp()
1596 * and we just freed all the buffers we need
1599 panic("fxp_stop: no buffers!");
1605 * Watchdog/transmission transmit timeout handler. Called when a
1606 * transmission is started on the interface, but no interrupt is
1607 * received before the timeout. This usually indicates that the
1608 * card has wedged for some reason.
1611 fxp_watchdog(struct ifnet *ifp)
1613 ASSERT_SERIALIZED(ifp->if_serializer);
1615 if_printf(ifp, "device timeout\n");
1617 fxp_init(ifp->if_softc);
1623 struct fxp_softc *sc = xsc;
1624 struct ifnet *ifp = &sc->arpcom.ac_if;
1625 struct fxp_cb_config *cbp;
1626 struct fxp_cb_ias *cb_ias;
1627 struct fxp_cb_tx *txp;
1628 struct fxp_cb_mcs *mcsp;
1631 ASSERT_SERIALIZED(ifp->if_serializer);
1634 * Cancel any pending I/O
1638 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1641 * Initialize base of CBL and RFA memory. Loading with zero
1642 * sets it up for regular linear addressing.
1644 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1645 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1648 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1651 * Initialize base of dump-stats buffer.
1654 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1655 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1658 * Attempt to load microcode if requested.
1660 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1664 * Initialize the multicast address list.
1666 if (fxp_mc_addrs(sc)) {
1668 mcsp->cb_status = 0;
1669 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1670 mcsp->link_addr = -1;
1672 * Start the multicast setup command.
1675 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1676 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1677 /* ...and wait for it to complete. */
1678 fxp_dma_wait(&mcsp->cb_status, sc);
1682 * We temporarily use memory that contains the TxCB list to
1683 * construct the config CB. The TxCB list memory is rebuilt
1686 cbp = (struct fxp_cb_config *) sc->cbl_base;
1689 * This bcopy is kind of disgusting, but there are a bunch of must be
1690 * zero and must be one bits in this structure and this is the easiest
1691 * way to initialize them all to proper values.
1693 bcopy(fxp_cb_config_template,
1694 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1695 sizeof(fxp_cb_config_template));
1698 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1699 cbp->link_addr = -1; /* (no) next command */
1700 cbp->byte_count = 22; /* (22) bytes to config */
1701 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1702 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1703 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1704 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1705 cbp->type_enable = 0; /* actually reserved */
1706 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1707 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1708 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1709 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1710 cbp->dma_mbce = 0; /* (disable) dma max counters */
1711 cbp->late_scb = 0; /* (don't) defer SCB update */
1712 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1713 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1714 cbp->ci_int = 1; /* interrupt on CU idle */
1715 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1716 cbp->ext_stats_dis = 1; /* disable extended counters */
1717 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1718 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1719 cbp->disc_short_rx = !prm; /* discard short packets */
1720 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1721 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1722 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1723 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1724 cbp->csma_dis = 0; /* (don't) disable link */
1725 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1726 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1727 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1728 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1729 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1730 cbp->nsai = 1; /* (don't) disable source addr insert */
1731 cbp->preamble_length = 2; /* (7 byte) preamble */
1732 cbp->loopback = 0; /* (don't) loopback */
1733 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1734 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1735 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1736 cbp->promiscuous = prm; /* promiscuous mode */
1737 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1738 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1739 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1740 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1741 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1743 cbp->stripping = !prm; /* truncate rx packet to byte count */
1744 cbp->padding = 1; /* (do) pad short tx packets */
1745 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1746 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1747 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1748 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1749 /* must set wake_en in PMCSR also */
1750 cbp->force_fdx = 0; /* (don't) force full duplex */
1751 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1752 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1753 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1755 if (sc->revision == FXP_REV_82557) {
1757 * The 82557 has no hardware flow control, the values
1758 * below are the defaults for the chip.
1760 cbp->fc_delay_lsb = 0;
1761 cbp->fc_delay_msb = 0x40;
1762 cbp->pri_fc_thresh = 3;
1764 cbp->rx_fc_restop = 0;
1765 cbp->rx_fc_restart = 0;
1767 cbp->pri_fc_loc = 1;
1769 cbp->fc_delay_lsb = 0x1f;
1770 cbp->fc_delay_msb = 0x01;
1771 cbp->pri_fc_thresh = 3;
1772 cbp->tx_fc_dis = 0; /* enable transmit FC */
1773 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1774 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1775 cbp->fc_filter = !prm; /* drop FC frames to host */
1776 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1780 * Start the config command/DMA.
1783 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1784 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1785 /* ...and wait for it to complete. */
1786 fxp_dma_wait(&cbp->cb_status, sc);
1789 * Now initialize the station address. Temporarily use the TxCB
1790 * memory area like we did above for the config CB.
1792 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1793 cb_ias->cb_status = 0;
1794 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1795 cb_ias->link_addr = -1;
1796 bcopy(sc->arpcom.ac_enaddr,
1797 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1798 sizeof(sc->arpcom.ac_enaddr));
1801 * Start the IAS (Individual Address Setup) command/DMA.
1804 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1805 /* ...and wait for it to complete. */
1806 fxp_dma_wait(&cb_ias->cb_status, sc);
1809 * Initialize transmit control block (TxCB) list.
1813 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1814 for (i = 0; i < FXP_NTXCB; i++) {
1815 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1816 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1818 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1819 if (sc->flags & FXP_FLAG_EXT_TXCB)
1820 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1822 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1823 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1826 * Set the suspend flag on the first TxCB and start the control
1827 * unit. It will execute the NOP and then suspend.
1829 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1830 sc->cbl_first = sc->cbl_last = txp;
1834 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1837 * Initialize receiver buffer area - RFA.
1840 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1841 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1842 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1845 * Set current media.
1847 if (sc->miibus != NULL)
1848 mii_mediachg(device_get_softc(sc->miibus));
1850 ifp->if_flags |= IFF_RUNNING;
1851 ifp->if_flags &= ~IFF_OACTIVE;
1854 * Enable interrupts.
1856 #ifdef DEVICE_POLLING
1858 * ... but only do that if we are not polling. And because (presumably)
1859 * the default is interrupts on, we need to disable them explicitly!
1861 if ( ifp->if_flags & IFF_POLLING )
1862 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1864 #endif /* DEVICE_POLLING */
1865 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1868 * Start stats updater.
1870 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1874 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1876 ASSERT_SERIALIZED(ifp->if_serializer);
1881 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1883 ASSERT_SERIALIZED(ifp->if_serializer);
1884 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1888 * Change media according to request.
1891 fxp_ifmedia_upd(struct ifnet *ifp)
1893 struct fxp_softc *sc = ifp->if_softc;
1894 struct mii_data *mii;
1896 ASSERT_SERIALIZED(ifp->if_serializer);
1898 mii = device_get_softc(sc->miibus);
1904 * Notify the world which media we're using.
1907 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1909 struct fxp_softc *sc = ifp->if_softc;
1910 struct mii_data *mii;
1912 ASSERT_SERIALIZED(ifp->if_serializer);
1914 mii = device_get_softc(sc->miibus);
1916 ifmr->ifm_active = mii->mii_media_active;
1917 ifmr->ifm_status = mii->mii_media_status;
1919 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1920 sc->cu_resume_bug = 1;
1922 sc->cu_resume_bug = 0;
1926 * Add a buffer to the end of the RFA buffer list.
1927 * Return 0 if successful, 1 for failure. A failure results in
1928 * adding the 'oldm' (if non-NULL) on to the end of the list -
1929 * tossing out its old contents and recycling it.
1930 * The RFA struct is stuck at the beginning of mbuf cluster and the
1931 * data pointer is fixed up to point just past it.
1934 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1938 struct fxp_rfa *rfa, *p_rfa;
1940 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1941 if (m == NULL) { /* try to recycle the old mbuf instead */
1945 m->m_data = m->m_ext.ext_buf;
1949 * Move the data pointer up so that the incoming data packet
1950 * will be 32-bit aligned.
1952 m->m_data += RFA_ALIGNMENT_FUDGE;
1955 * Get a pointer to the base of the mbuf cluster and move
1956 * data start past it.
1958 rfa = mtod(m, struct fxp_rfa *);
1959 m->m_data += sizeof(struct fxp_rfa);
1960 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) -
1961 RFA_ALIGNMENT_FUDGE);
1964 * Initialize the rest of the RFA. Note that since the RFA
1965 * is misaligned, we cannot store values directly. Instead,
1966 * we use an optimized, inline copy.
1969 rfa->rfa_status = 0;
1970 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1971 rfa->actual_size = 0;
1974 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1975 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1978 * If there are other buffers already on the list, attach this
1979 * one to the end by fixing up the tail to point to this one.
1981 if (sc->rfa_headm != NULL) {
1982 p_rfa = (struct fxp_rfa *)(sc->rfa_tailm->m_ext.ext_buf +
1983 RFA_ALIGNMENT_FUDGE);
1984 sc->rfa_tailm->m_next = m;
1986 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1987 p_rfa->rfa_control = 0;
1997 fxp_miibus_readreg(device_t dev, int phy, int reg)
1999 struct fxp_softc *sc = device_get_softc(dev);
2003 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2004 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2006 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2011 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2013 return (value & 0xffff);
2017 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2019 struct fxp_softc *sc = device_get_softc(dev);
2022 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2023 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2026 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2031 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2035 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2037 struct fxp_softc *sc = ifp->if_softc;
2038 struct ifreq *ifr = (struct ifreq *)data;
2039 struct mii_data *mii;
2042 ASSERT_SERIALIZED(ifp->if_serializer);
2047 if (ifp->if_flags & IFF_ALLMULTI)
2048 sc->flags |= FXP_FLAG_ALL_MCAST;
2050 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2053 * If interface is marked up and not running, then start it.
2054 * If it is marked down and running, stop it.
2055 * XXX If it's up then re-initialize it. This is so flags
2056 * such as IFF_PROMISC are handled.
2058 if (ifp->if_flags & IFF_UP) {
2061 if (ifp->if_flags & IFF_RUNNING)
2068 if (ifp->if_flags & IFF_ALLMULTI)
2069 sc->flags |= FXP_FLAG_ALL_MCAST;
2071 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2073 * Multicast list has changed; set the hardware filter
2076 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2079 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2080 * again rather than else {}.
2082 if (sc->flags & FXP_FLAG_ALL_MCAST)
2089 if (sc->miibus != NULL) {
2090 mii = device_get_softc(sc->miibus);
2091 error = ifmedia_ioctl(ifp, ifr,
2092 &mii->mii_media, command);
2094 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2099 error = ether_ioctl(ifp, command, data);
2106 * Fill in the multicast address list and return number of entries.
2109 fxp_mc_addrs(struct fxp_softc *sc)
2111 struct fxp_cb_mcs *mcsp = sc->mcsp;
2112 struct ifnet *ifp = &sc->arpcom.ac_if;
2113 struct ifmultiaddr *ifma;
2117 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2118 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2119 if (ifma->ifma_addr->sa_family != AF_LINK)
2121 if (nmcasts >= MAXMCADDR) {
2122 sc->flags |= FXP_FLAG_ALL_MCAST;
2126 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2127 (void *)(uintptr_t)(volatile void *)
2128 &sc->mcsp->mc_addr[nmcasts][0], 6);
2132 mcsp->mc_cnt = nmcasts * 6;
2137 * Program the multicast filter.
2139 * We have an artificial restriction that the multicast setup command
2140 * must be the first command in the chain, so we take steps to ensure
2141 * this. By requiring this, it allows us to keep up the performance of
2142 * the pre-initialized command ring (esp. link pointers) by not actually
2143 * inserting the mcsetup command in the ring - i.e. its link pointer
2144 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2145 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2146 * lead into the regular TxCB ring when it completes.
2148 * This function must be called at splimp.
2151 fxp_mc_setup(struct fxp_softc *sc)
2153 struct fxp_cb_mcs *mcsp = sc->mcsp;
2154 struct ifnet *ifp = &sc->arpcom.ac_if;
2158 * If there are queued commands, we must wait until they are all
2159 * completed. If we are already waiting, then add a NOP command
2160 * with interrupt option so that we're notified when all commands
2161 * have been completed - fxp_start() ensures that no additional
2162 * TX commands will be added when need_mcsetup is true.
2164 if (sc->tx_queued) {
2165 struct fxp_cb_tx *txp;
2168 * need_mcsetup will be true if we are already waiting for the
2169 * NOP command to be completed (see below). In this case, bail.
2171 if (sc->need_mcsetup)
2173 sc->need_mcsetup = 1;
2176 * Add a NOP command with interrupt so that we are notified
2177 * when all TX commands have been processed.
2179 txp = sc->cbl_last->next;
2180 txp->mb_head = NULL;
2182 txp->cb_command = FXP_CB_COMMAND_NOP |
2183 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2185 * Advance the end of list forward.
2187 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2191 * Issue a resume in case the CU has just suspended.
2194 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2196 * Set a 5 second timer just in case we don't hear from the
2203 sc->need_mcsetup = 0;
2206 * Initialize multicast setup descriptor.
2208 mcsp->next = sc->cbl_base;
2209 mcsp->mb_head = NULL;
2210 mcsp->cb_status = 0;
2211 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2212 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2213 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2215 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2219 * Wait until command unit is not active. This should never
2220 * be the case when nothing is queued, but make sure anyway.
2223 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2224 FXP_SCB_CUS_ACTIVE && --count)
2227 if_printf(&sc->arpcom.ac_if, "command queue timeout\n");
2232 * Start the multicast setup command.
2235 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2236 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2242 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2243 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2244 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2245 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2246 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2247 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2249 #define UCODE(x) x, sizeof(x)
2255 u_short int_delay_offset;
2256 u_short bundle_max_offset;
2258 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2259 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2260 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2261 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2262 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2263 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2264 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2265 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2266 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2267 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2268 { 0, NULL, 0, 0, 0 }
2272 fxp_load_ucode(struct fxp_softc *sc)
2275 struct fxp_cb_ucode *cbp;
2277 for (uc = ucode_table; uc->ucode != NULL; uc++)
2278 if (sc->revision == uc->revision)
2280 if (uc->ucode == NULL)
2282 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2284 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2285 cbp->link_addr = -1; /* (no) next command */
2286 memcpy(cbp->ucode, uc->ucode, uc->length);
2287 if (uc->int_delay_offset)
2288 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2289 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2290 if (uc->bundle_max_offset)
2291 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2292 sc->tunable_bundle_max;
2294 * Download the ucode to the chip.
2297 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2298 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2299 /* ...and wait for it to complete. */
2300 fxp_dma_wait(&cbp->cb_status, sc);
2301 if_printf(&sc->arpcom.ac_if,
2302 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2303 sc->tunable_int_delay,
2304 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2305 sc->flags |= FXP_FLAG_UCODE;
2309 * Interrupt delay is expressed in microseconds, a multiplier is used
2310 * to convert this to the appropriate clock ticks before using.
2313 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2315 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2319 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2321 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));