sys/platform/pc32/apic/ioapic_abi.c

   1 /*
   2  * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
   3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
   4  * Copyright (c) 1991 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The DragonFly Project
   8  * by Matthew Dillon <dillon@backplane.com>
   9  *
  10  * This code is derived from software contributed to Berkeley by
  11  * William Jolitz.
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  * 3. Neither the name of The DragonFly Project nor the names of its
  24  *    contributors may be used to endorse or promote products derived
  25  *    from this software without specific, prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  */
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/kernel.h>
  44 #include <sys/machintr.h>
  45 #include <sys/interrupt.h>
  46 #include <sys/bus.h>
  47 #include <sys/rman.h>
  48 #include <sys/thread2.h>
  49
  50 #include <machine/smp.h>
  51 #include <machine/segments.h>
  52 #include <machine/md_var.h>
  53 #include <machine/intr_machdep.h>
  54 #include <machine/globaldata.h>
  55 #include <machine/msi_var.h>
  56
  57 #include <machine_base/isa/isa_intr.h>
  58 #include <machine_base/icu/icu.h>
  59 #include <machine_base/icu/icu_var.h>
  60 #include <machine_base/apic/ioapic.h>
  61 #include <machine_base/apic/ioapic_abi.h>
  62 #include <machine_base/apic/ioapic_ipl.h>
  63 #include <machine_base/apic/apicreg.h>
  64
  65 #include <dev/acpica/acpi_sci_var.h>
  66
  67 #define IOAPIC_HWI_VECTORS      IDT_HWI_VECTORS
  68
  69 extern inthand_t
  70         IDTVEC(ioapic_intr0),
  71         IDTVEC(ioapic_intr1),
  72         IDTVEC(ioapic_intr2),
  73         IDTVEC(ioapic_intr3),
  74         IDTVEC(ioapic_intr4),
  75         IDTVEC(ioapic_intr5),
  76         IDTVEC(ioapic_intr6),
  77         IDTVEC(ioapic_intr7),
  78         IDTVEC(ioapic_intr8),
  79         IDTVEC(ioapic_intr9),
  80         IDTVEC(ioapic_intr10),
  81         IDTVEC(ioapic_intr11),
  82         IDTVEC(ioapic_intr12),
  83         IDTVEC(ioapic_intr13),
  84         IDTVEC(ioapic_intr14),
  85         IDTVEC(ioapic_intr15),
  86         IDTVEC(ioapic_intr16),
  87         IDTVEC(ioapic_intr17),
  88         IDTVEC(ioapic_intr18),
  89         IDTVEC(ioapic_intr19),
  90         IDTVEC(ioapic_intr20),
  91         IDTVEC(ioapic_intr21),
  92         IDTVEC(ioapic_intr22),
  93         IDTVEC(ioapic_intr23),
  94         IDTVEC(ioapic_intr24),
  95         IDTVEC(ioapic_intr25),
  96         IDTVEC(ioapic_intr26),
  97         IDTVEC(ioapic_intr27),
  98         IDTVEC(ioapic_intr28),
  99         IDTVEC(ioapic_intr29),
 100         IDTVEC(ioapic_intr30),
 101         IDTVEC(ioapic_intr31),
 102         IDTVEC(ioapic_intr32),
 103         IDTVEC(ioapic_intr33),
 104         IDTVEC(ioapic_intr34),
 105         IDTVEC(ioapic_intr35),
 106         IDTVEC(ioapic_intr36),
 107         IDTVEC(ioapic_intr37),
 108         IDTVEC(ioapic_intr38),
 109         IDTVEC(ioapic_intr39),
 110         IDTVEC(ioapic_intr40),
 111         IDTVEC(ioapic_intr41),
 112         IDTVEC(ioapic_intr42),
 113         IDTVEC(ioapic_intr43),
 114         IDTVEC(ioapic_intr44),
 115         IDTVEC(ioapic_intr45),
 116         IDTVEC(ioapic_intr46),
 117         IDTVEC(ioapic_intr47),
 118         IDTVEC(ioapic_intr48),
 119         IDTVEC(ioapic_intr49),
 120         IDTVEC(ioapic_intr50),
 121         IDTVEC(ioapic_intr51),
 122         IDTVEC(ioapic_intr52),
 123         IDTVEC(ioapic_intr53),
 124         IDTVEC(ioapic_intr54),
 125         IDTVEC(ioapic_intr55),
 126         IDTVEC(ioapic_intr56),
 127         IDTVEC(ioapic_intr57),
 128         IDTVEC(ioapic_intr58),
 129         IDTVEC(ioapic_intr59),
 130         IDTVEC(ioapic_intr60),
 131         IDTVEC(ioapic_intr61),
 132         IDTVEC(ioapic_intr62),
 133         IDTVEC(ioapic_intr63),
 134         IDTVEC(ioapic_intr64),
 135         IDTVEC(ioapic_intr65),
 136         IDTVEC(ioapic_intr66),
 137         IDTVEC(ioapic_intr67),
 138         IDTVEC(ioapic_intr68),
 139         IDTVEC(ioapic_intr69),
 140         IDTVEC(ioapic_intr70),
 141         IDTVEC(ioapic_intr71),
 142         IDTVEC(ioapic_intr72),
 143         IDTVEC(ioapic_intr73),
 144         IDTVEC(ioapic_intr74),
 145         IDTVEC(ioapic_intr75),
 146         IDTVEC(ioapic_intr76),
 147         IDTVEC(ioapic_intr77),
 148         IDTVEC(ioapic_intr78),
 149         IDTVEC(ioapic_intr79),
 150         IDTVEC(ioapic_intr80),
 151         IDTVEC(ioapic_intr81),
 152         IDTVEC(ioapic_intr82),
 153         IDTVEC(ioapic_intr83),
 154         IDTVEC(ioapic_intr84),
 155         IDTVEC(ioapic_intr85),
 156         IDTVEC(ioapic_intr86),
 157         IDTVEC(ioapic_intr87),
 158         IDTVEC(ioapic_intr88),
 159         IDTVEC(ioapic_intr89),
 160         IDTVEC(ioapic_intr90),
 161         IDTVEC(ioapic_intr91),
 162         IDTVEC(ioapic_intr92),
 163         IDTVEC(ioapic_intr93),
 164         IDTVEC(ioapic_intr94),
 165         IDTVEC(ioapic_intr95),
 166         IDTVEC(ioapic_intr96),
 167         IDTVEC(ioapic_intr97),
 168         IDTVEC(ioapic_intr98),
 169         IDTVEC(ioapic_intr99),
 170         IDTVEC(ioapic_intr100),
 171         IDTVEC(ioapic_intr101),
 172         IDTVEC(ioapic_intr102),
 173         IDTVEC(ioapic_intr103),
 174         IDTVEC(ioapic_intr104),
 175         IDTVEC(ioapic_intr105),
 176         IDTVEC(ioapic_intr106),
 177         IDTVEC(ioapic_intr107),
 178         IDTVEC(ioapic_intr108),
 179         IDTVEC(ioapic_intr109),
 180         IDTVEC(ioapic_intr110),
 181         IDTVEC(ioapic_intr111),
 182         IDTVEC(ioapic_intr112),
 183         IDTVEC(ioapic_intr113),
 184         IDTVEC(ioapic_intr114),
 185         IDTVEC(ioapic_intr115),
 186         IDTVEC(ioapic_intr116),
 187         IDTVEC(ioapic_intr117),
 188         IDTVEC(ioapic_intr118),
 189         IDTVEC(ioapic_intr119),
 190         IDTVEC(ioapic_intr120),
 191         IDTVEC(ioapic_intr121),
 192         IDTVEC(ioapic_intr122),
 193         IDTVEC(ioapic_intr123),
 194         IDTVEC(ioapic_intr124),
 195         IDTVEC(ioapic_intr125),
 196         IDTVEC(ioapic_intr126),
 197         IDTVEC(ioapic_intr127),
 198         IDTVEC(ioapic_intr128),
 199         IDTVEC(ioapic_intr129),
 200         IDTVEC(ioapic_intr130),
 201         IDTVEC(ioapic_intr131),
 202         IDTVEC(ioapic_intr132),
 203         IDTVEC(ioapic_intr133),
 204         IDTVEC(ioapic_intr134),
 205         IDTVEC(ioapic_intr135),
 206         IDTVEC(ioapic_intr136),
 207         IDTVEC(ioapic_intr137),
 208         IDTVEC(ioapic_intr138),
 209         IDTVEC(ioapic_intr139),
 210         IDTVEC(ioapic_intr140),
 211         IDTVEC(ioapic_intr141),
 212         IDTVEC(ioapic_intr142),
 213         IDTVEC(ioapic_intr143),
 214         IDTVEC(ioapic_intr144),
 215         IDTVEC(ioapic_intr145),
 216         IDTVEC(ioapic_intr146),
 217         IDTVEC(ioapic_intr147),
 218         IDTVEC(ioapic_intr148),
 219         IDTVEC(ioapic_intr149),
 220         IDTVEC(ioapic_intr150),
 221         IDTVEC(ioapic_intr151),
 222         IDTVEC(ioapic_intr152),
 223         IDTVEC(ioapic_intr153),
 224         IDTVEC(ioapic_intr154),
 225         IDTVEC(ioapic_intr155),
 226         IDTVEC(ioapic_intr156),
 227         IDTVEC(ioapic_intr157),
 228         IDTVEC(ioapic_intr158),
 229         IDTVEC(ioapic_intr159),
 230         IDTVEC(ioapic_intr160),
 231         IDTVEC(ioapic_intr161),
 232         IDTVEC(ioapic_intr162),
 233         IDTVEC(ioapic_intr163),
 234         IDTVEC(ioapic_intr164),
 235         IDTVEC(ioapic_intr165),
 236         IDTVEC(ioapic_intr166),
 237         IDTVEC(ioapic_intr167),
 238         IDTVEC(ioapic_intr168),
 239         IDTVEC(ioapic_intr169),
 240         IDTVEC(ioapic_intr170),
 241         IDTVEC(ioapic_intr171),
 242         IDTVEC(ioapic_intr172),
 243         IDTVEC(ioapic_intr173),
 244         IDTVEC(ioapic_intr174),
 245         IDTVEC(ioapic_intr175),
 246         IDTVEC(ioapic_intr176),
 247         IDTVEC(ioapic_intr177),
 248         IDTVEC(ioapic_intr178),
 249         IDTVEC(ioapic_intr179),
 250         IDTVEC(ioapic_intr180),
 251         IDTVEC(ioapic_intr181),
 252         IDTVEC(ioapic_intr182),
 253         IDTVEC(ioapic_intr183),
 254         IDTVEC(ioapic_intr184),
 255         IDTVEC(ioapic_intr185),
 256         IDTVEC(ioapic_intr186),
 257         IDTVEC(ioapic_intr187),
 258         IDTVEC(ioapic_intr188),
 259         IDTVEC(ioapic_intr189),
 260         IDTVEC(ioapic_intr190),
 261         IDTVEC(ioapic_intr191);
 262
 263 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
 264         &IDTVEC(ioapic_intr0),
 265         &IDTVEC(ioapic_intr1),
 266         &IDTVEC(ioapic_intr2),
 267         &IDTVEC(ioapic_intr3),
 268         &IDTVEC(ioapic_intr4),
 269         &IDTVEC(ioapic_intr5),
 270         &IDTVEC(ioapic_intr6),
 271         &IDTVEC(ioapic_intr7),
 272         &IDTVEC(ioapic_intr8),
 273         &IDTVEC(ioapic_intr9),
 274         &IDTVEC(ioapic_intr10),
 275         &IDTVEC(ioapic_intr11),
 276         &IDTVEC(ioapic_intr12),
 277         &IDTVEC(ioapic_intr13),
 278         &IDTVEC(ioapic_intr14),
 279         &IDTVEC(ioapic_intr15),
 280         &IDTVEC(ioapic_intr16),
 281         &IDTVEC(ioapic_intr17),
 282         &IDTVEC(ioapic_intr18),
 283         &IDTVEC(ioapic_intr19),
 284         &IDTVEC(ioapic_intr20),
 285         &IDTVEC(ioapic_intr21),
 286         &IDTVEC(ioapic_intr22),
 287         &IDTVEC(ioapic_intr23),
 288         &IDTVEC(ioapic_intr24),
 289         &IDTVEC(ioapic_intr25),
 290         &IDTVEC(ioapic_intr26),
 291         &IDTVEC(ioapic_intr27),
 292         &IDTVEC(ioapic_intr28),
 293         &IDTVEC(ioapic_intr29),
 294         &IDTVEC(ioapic_intr30),
 295         &IDTVEC(ioapic_intr31),
 296         &IDTVEC(ioapic_intr32),
 297         &IDTVEC(ioapic_intr33),
 298         &IDTVEC(ioapic_intr34),
 299         &IDTVEC(ioapic_intr35),
 300         &IDTVEC(ioapic_intr36),
 301         &IDTVEC(ioapic_intr37),
 302         &IDTVEC(ioapic_intr38),
 303         &IDTVEC(ioapic_intr39),
 304         &IDTVEC(ioapic_intr40),
 305         &IDTVEC(ioapic_intr41),
 306         &IDTVEC(ioapic_intr42),
 307         &IDTVEC(ioapic_intr43),
 308         &IDTVEC(ioapic_intr44),
 309         &IDTVEC(ioapic_intr45),
 310         &IDTVEC(ioapic_intr46),
 311         &IDTVEC(ioapic_intr47),
 312         &IDTVEC(ioapic_intr48),
 313         &IDTVEC(ioapic_intr49),
 314         &IDTVEC(ioapic_intr50),
 315         &IDTVEC(ioapic_intr51),
 316         &IDTVEC(ioapic_intr52),
 317         &IDTVEC(ioapic_intr53),
 318         &IDTVEC(ioapic_intr54),
 319         &IDTVEC(ioapic_intr55),
 320         &IDTVEC(ioapic_intr56),
 321         &IDTVEC(ioapic_intr57),
 322         &IDTVEC(ioapic_intr58),
 323         &IDTVEC(ioapic_intr59),
 324         &IDTVEC(ioapic_intr60),
 325         &IDTVEC(ioapic_intr61),
 326         &IDTVEC(ioapic_intr62),
 327         &IDTVEC(ioapic_intr63),
 328         &IDTVEC(ioapic_intr64),
 329         &IDTVEC(ioapic_intr65),
 330         &IDTVEC(ioapic_intr66),
 331         &IDTVEC(ioapic_intr67),
 332         &IDTVEC(ioapic_intr68),
 333         &IDTVEC(ioapic_intr69),
 334         &IDTVEC(ioapic_intr70),
 335         &IDTVEC(ioapic_intr71),
 336         &IDTVEC(ioapic_intr72),
 337         &IDTVEC(ioapic_intr73),
 338         &IDTVEC(ioapic_intr74),
 339         &IDTVEC(ioapic_intr75),
 340         &IDTVEC(ioapic_intr76),
 341         &IDTVEC(ioapic_intr77),
 342         &IDTVEC(ioapic_intr78),
 343         &IDTVEC(ioapic_intr79),
 344         &IDTVEC(ioapic_intr80),
 345         &IDTVEC(ioapic_intr81),
 346         &IDTVEC(ioapic_intr82),
 347         &IDTVEC(ioapic_intr83),
 348         &IDTVEC(ioapic_intr84),
 349         &IDTVEC(ioapic_intr85),
 350         &IDTVEC(ioapic_intr86),
 351         &IDTVEC(ioapic_intr87),
 352         &IDTVEC(ioapic_intr88),
 353         &IDTVEC(ioapic_intr89),
 354         &IDTVEC(ioapic_intr90),
 355         &IDTVEC(ioapic_intr91),
 356         &IDTVEC(ioapic_intr92),
 357         &IDTVEC(ioapic_intr93),
 358         &IDTVEC(ioapic_intr94),
 359         &IDTVEC(ioapic_intr95),
 360         &IDTVEC(ioapic_intr96),
 361         &IDTVEC(ioapic_intr97),
 362         &IDTVEC(ioapic_intr98),
 363         &IDTVEC(ioapic_intr99),
 364         &IDTVEC(ioapic_intr100),
 365         &IDTVEC(ioapic_intr101),
 366         &IDTVEC(ioapic_intr102),
 367         &IDTVEC(ioapic_intr103),
 368         &IDTVEC(ioapic_intr104),
 369         &IDTVEC(ioapic_intr105),
 370         &IDTVEC(ioapic_intr106),
 371         &IDTVEC(ioapic_intr107),
 372         &IDTVEC(ioapic_intr108),
 373         &IDTVEC(ioapic_intr109),
 374         &IDTVEC(ioapic_intr110),
 375         &IDTVEC(ioapic_intr111),
 376         &IDTVEC(ioapic_intr112),
 377         &IDTVEC(ioapic_intr113),
 378         &IDTVEC(ioapic_intr114),
 379         &IDTVEC(ioapic_intr115),
 380         &IDTVEC(ioapic_intr116),
 381         &IDTVEC(ioapic_intr117),
 382         &IDTVEC(ioapic_intr118),
 383         &IDTVEC(ioapic_intr119),
 384         &IDTVEC(ioapic_intr120),
 385         &IDTVEC(ioapic_intr121),
 386         &IDTVEC(ioapic_intr122),
 387         &IDTVEC(ioapic_intr123),
 388         &IDTVEC(ioapic_intr124),
 389         &IDTVEC(ioapic_intr125),
 390         &IDTVEC(ioapic_intr126),
 391         &IDTVEC(ioapic_intr127),
 392         &IDTVEC(ioapic_intr128),
 393         &IDTVEC(ioapic_intr129),
 394         &IDTVEC(ioapic_intr130),
 395         &IDTVEC(ioapic_intr131),
 396         &IDTVEC(ioapic_intr132),
 397         &IDTVEC(ioapic_intr133),
 398         &IDTVEC(ioapic_intr134),
 399         &IDTVEC(ioapic_intr135),
 400         &IDTVEC(ioapic_intr136),
 401         &IDTVEC(ioapic_intr137),
 402         &IDTVEC(ioapic_intr138),
 403         &IDTVEC(ioapic_intr139),
 404         &IDTVEC(ioapic_intr140),
 405         &IDTVEC(ioapic_intr141),
 406         &IDTVEC(ioapic_intr142),
 407         &IDTVEC(ioapic_intr143),
 408         &IDTVEC(ioapic_intr144),
 409         &IDTVEC(ioapic_intr145),
 410         &IDTVEC(ioapic_intr146),
 411         &IDTVEC(ioapic_intr147),
 412         &IDTVEC(ioapic_intr148),
 413         &IDTVEC(ioapic_intr149),
 414         &IDTVEC(ioapic_intr150),
 415         &IDTVEC(ioapic_intr151),
 416         &IDTVEC(ioapic_intr152),
 417         &IDTVEC(ioapic_intr153),
 418         &IDTVEC(ioapic_intr154),
 419         &IDTVEC(ioapic_intr155),
 420         &IDTVEC(ioapic_intr156),
 421         &IDTVEC(ioapic_intr157),
 422         &IDTVEC(ioapic_intr158),
 423         &IDTVEC(ioapic_intr159),
 424         &IDTVEC(ioapic_intr160),
 425         &IDTVEC(ioapic_intr161),
 426         &IDTVEC(ioapic_intr162),
 427         &IDTVEC(ioapic_intr163),
 428         &IDTVEC(ioapic_intr164),
 429         &IDTVEC(ioapic_intr165),
 430         &IDTVEC(ioapic_intr166),
 431         &IDTVEC(ioapic_intr167),
 432         &IDTVEC(ioapic_intr168),
 433         &IDTVEC(ioapic_intr169),
 434         &IDTVEC(ioapic_intr170),
 435         &IDTVEC(ioapic_intr171),
 436         &IDTVEC(ioapic_intr172),
 437         &IDTVEC(ioapic_intr173),
 438         &IDTVEC(ioapic_intr174),
 439         &IDTVEC(ioapic_intr175),
 440         &IDTVEC(ioapic_intr176),
 441         &IDTVEC(ioapic_intr177),
 442         &IDTVEC(ioapic_intr178),
 443         &IDTVEC(ioapic_intr179),
 444         &IDTVEC(ioapic_intr180),
 445         &IDTVEC(ioapic_intr181),
 446         &IDTVEC(ioapic_intr182),
 447         &IDTVEC(ioapic_intr183),
 448         &IDTVEC(ioapic_intr184),
 449         &IDTVEC(ioapic_intr185),
 450         &IDTVEC(ioapic_intr186),
 451         &IDTVEC(ioapic_intr187),
 452         &IDTVEC(ioapic_intr188),
 453         &IDTVEC(ioapic_intr189),
 454         &IDTVEC(ioapic_intr190),
 455         &IDTVEC(ioapic_intr191)
 456 };
 457
 458 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
 459
 460 static struct ioapic_irqmap {
 461         int                     im_type;        /* IOAPIC_IMT_ */
 462         enum intr_trigger       im_trig;
 463         enum intr_polarity      im_pola;
 464         int                     im_gsi;
 465         int                     im_msi_base;
 466         uint32_t                im_flags;       /* IOAPIC_IMF_ */
 467 } ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
 468
 469 static struct lwkt_token ioapic_irqmap_tok =
 470         LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token);
 471
 472 #define IOAPIC_IMT_UNUSED       0
 473 #define IOAPIC_IMT_RESERVED     1
 474 #define IOAPIC_IMT_LEGACY       2
 475 #define IOAPIC_IMT_SYSCALL      3
 476 #define IOAPIC_IMT_SHADOW       4
 477 #define IOAPIC_IMT_MSI          5
 478 #define IOAPIC_IMT_MSIX         6
 479
 480 #define IOAPIC_IMT_ISHWI(map)   ((map)->im_type != IOAPIC_IMT_RESERVED && \
 481                                  (map)->im_type != IOAPIC_IMT_SYSCALL && \
 482                                  (map)->im_type != IOAPIC_IMT_SHADOW)
 483
 484 #define IOAPIC_IMF_CONF         0x1
 485
 486 extern void     IOAPIC_INTREN(int);
 487 extern void     IOAPIC_INTRDIS(int);
 488
 489 extern int      imcr_present;
 490
 491 static void     ioapic_abi_intr_enable(int);
 492 static void     ioapic_abi_intr_disable(int);
 493 static void     ioapic_abi_intr_setup(int, int);
 494 static void     ioapic_abi_intr_teardown(int);
 495
 496 static void     ioapic_abi_legacy_intr_config(int,
 497                     enum intr_trigger, enum intr_polarity);
 498 static int      ioapic_abi_legacy_intr_cpuid(int);
 499 static int      ioapic_abi_legacy_intr_find(int,
 500                     enum intr_trigger, enum intr_polarity);
 501 static int      ioapic_abi_legacy_intr_find_bygsi(int,
 502                     enum intr_trigger, enum intr_polarity);
 503
 504 static int      ioapic_abi_msi_alloc(int [], int, int);
 505 static void     ioapic_abi_msi_release(const int [], int, int);
 506 static void     ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int);
 507 static int      ioapic_abi_msix_alloc(int *, int);
 508 static void     ioapic_abi_msix_release(int, int);
 509
 510 static int      ioapic_abi_msi_alloc_intern(int, const char *,
 511                     int [], int, int);
 512 static void     ioapic_abi_msi_release_intern(int, const char *,
 513                     const int [], int, int);
 514
 515 static void     ioapic_abi_finalize(void);
 516 static void     ioapic_abi_cleanup(void);
 517 static void     ioapic_abi_setdefault(void);
 518 static void     ioapic_abi_stabilize(void);
 519 static void     ioapic_abi_initmap(void);
 520 static void     ioapic_abi_rman_setup(struct rman *);
 521
 522 static int      ioapic_abi_gsi_cpuid(int, int);
 523 static int      ioapic_find_unused_irqmap(int);
 524
 525 struct machintr_abi MachIntrABI_IOAPIC = {
 526         MACHINTR_IOAPIC,
 527
 528         .intr_disable   = ioapic_abi_intr_disable,
 529         .intr_enable    = ioapic_abi_intr_enable,
 530         .intr_setup     = ioapic_abi_intr_setup,
 531         .intr_teardown  = ioapic_abi_intr_teardown,
 532
 533         .legacy_intr_config = ioapic_abi_legacy_intr_config,
 534         .legacy_intr_cpuid = ioapic_abi_legacy_intr_cpuid,
 535         .legacy_intr_find = ioapic_abi_legacy_intr_find,
 536         .legacy_intr_find_bygsi = ioapic_abi_legacy_intr_find_bygsi,
 537
 538         .msi_alloc      = ioapic_abi_msi_alloc,
 539         .msi_release    = ioapic_abi_msi_release,
 540         .msi_map        = ioapic_abi_msi_map,
 541         .msix_alloc     = ioapic_abi_msix_alloc,
 542         .msix_release   = ioapic_abi_msix_release,
 543
 544         .finalize       = ioapic_abi_finalize,
 545         .cleanup        = ioapic_abi_cleanup,
 546         .setdefault     = ioapic_abi_setdefault,
 547         .stabilize      = ioapic_abi_stabilize,
 548         .initmap        = ioapic_abi_initmap,
 549         .rman_setup     = ioapic_abi_rman_setup
 550 };
 551
 552 static int      ioapic_abi_extint_irq = -1;
 553 static int      ioapic_abi_legacy_irq_max;
 554 static int      ioapic_abi_gsi_balance;
 555 static int      ioapic_abi_msi_start;   /* NOTE: for testing only */
 556
 557 struct ioapic_irqinfo   ioapic_irqs[IOAPIC_HWI_VECTORS];
 558
 559 static void
 560 ioapic_abi_intr_enable(int irq)
 561 {
 562         const struct ioapic_irqmap *map;
 563
 564         KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
 565             ("ioapic enable, invalid irq %d", irq));
 566
 567         map = &ioapic_irqmaps[mycpuid][irq];
 568         KASSERT(IOAPIC_IMT_ISHWI(map),
 569             ("ioapic enable, not hwi irq %d, type %d, cpu%d",
 570              irq, map->im_type, mycpuid));
 571         if (map->im_type != IOAPIC_IMT_LEGACY)
 572                 return;
 573
 574         IOAPIC_INTREN(irq);
 575 }
 576
 577 static void
 578 ioapic_abi_intr_disable(int irq)
 579 {
 580         const struct ioapic_irqmap *map;
 581
 582         KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
 583             ("ioapic disable, invalid irq %d", irq));
 584
 585         map = &ioapic_irqmaps[mycpuid][irq];
 586         KASSERT(IOAPIC_IMT_ISHWI(map),
 587             ("ioapic disable, not hwi irq %d, type %d, cpu%d",
 588              irq, map->im_type, mycpuid));
 589         if (map->im_type != IOAPIC_IMT_LEGACY)
 590                 return;
 591
 592         IOAPIC_INTRDIS(irq);
 593 }
 594
 595 static void
 596 ioapic_abi_finalize(void)
 597 {
 598         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
 599         KKASSERT(ioapic_enable);
 600
 601         /*
 602          * If an IMCR is present, program bit 0 to disconnect the 8259
 603          * from the BSP.
 604          */
 605         if (imcr_present) {
 606                 outb(0x22, 0x70);       /* select IMCR */
 607                 outb(0x23, 0x01);       /* disconnect 8259 */
 608         }
 609 }
 610
 611 /*
 612  * This routine is called after physical interrupts are enabled but before
 613  * the critical section is released.  We need to clean out any interrupts
 614  * that had already been posted to the cpu.
 615  */
 616 static void
 617 ioapic_abi_cleanup(void)
 618 {
 619         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
 620 }
 621
 622 /* Must never be called */
 623 static void
 624 ioapic_abi_stabilize(void)
 625 {
 626         panic("ioapic_stabilize() is called");
 627 }
 628
 629 static void
 630 ioapic_abi_intr_setup(int intr, int flags)
 631 {
 632         const struct ioapic_irqmap *map;
 633         int vector, select;
 634         uint32_t value;
 635         u_long ef;
 636
 637         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
 638             ("ioapic setup, invalid irq %d", intr));
 639
 640         map = &ioapic_irqmaps[mycpuid][intr];
 641         KASSERT(IOAPIC_IMT_ISHWI(map),
 642             ("ioapic setup, not hwi irq %d, type %d, cpu%d",
 643              intr, map->im_type, mycpuid));
 644         if (map->im_type != IOAPIC_IMT_LEGACY)
 645                 return;
 646
 647         KASSERT(ioapic_irqs[intr].io_addr != NULL,
 648             ("ioapic setup, no GSI information, irq %d", intr));
 649
 650         ef = read_eflags();
 651         cpu_disable_intr();
 652
 653         vector = IDT_OFFSET + intr;
 654
 655         /*
 656          * Now reprogram the vector in the IO APIC.  In order to avoid
 657          * losing an EOI for a level interrupt, which is vector based,
 658          * make sure that the IO APIC is programmed for edge-triggering
 659          * first, then reprogrammed with the new vector.  This should
 660          * clear the IRR bit.
 661          */
 662         imen_lock();
 663
 664         select = ioapic_irqs[intr].io_idx;
 665         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 666         value |= IOART_INTMSET;
 667
 668         ioapic_write(ioapic_irqs[intr].io_addr, select,
 669             (value & ~APIC_TRIGMOD_MASK));
 670         ioapic_write(ioapic_irqs[intr].io_addr, select,
 671             (value & ~IOART_INTVEC) | vector);
 672
 673         imen_unlock();
 674
 675         IOAPIC_INTREN(intr);
 676
 677         write_eflags(ef);
 678 }
 679
 680 static void
 681 ioapic_abi_intr_teardown(int intr)
 682 {
 683         const struct ioapic_irqmap *map;
 684         int vector, select;
 685         uint32_t value;
 686         u_long ef;
 687
 688         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
 689             ("ioapic teardown, invalid irq %d", intr));
 690
 691         map = &ioapic_irqmaps[mycpuid][intr];
 692         KASSERT(IOAPIC_IMT_ISHWI(map),
 693             ("ioapic teardown, not hwi irq %d, type %d, cpu%d",
 694              intr, map->im_type, mycpuid));
 695         if (map->im_type != IOAPIC_IMT_LEGACY)
 696                 return;
 697
 698         KASSERT(ioapic_irqs[intr].io_addr != NULL,
 699             ("ioapic teardown, no GSI information, irq %d", intr));
 700
 701         ef = read_eflags();
 702         cpu_disable_intr();
 703
 704         /*
 705          * Teardown an interrupt vector.  The vector should already be
 706          * installed in the cpu's IDT, but make sure.
 707          */
 708         IOAPIC_INTRDIS(intr);
 709
 710         vector = IDT_OFFSET + intr;
 711
 712         /*
 713          * In order to avoid losing an EOI for a level interrupt, which
 714          * is vector based, make sure that the IO APIC is programmed for
 715          * edge-triggering first, then reprogrammed with the new vector.
 716          * This should clear the IRR bit.
 717          */
 718         imen_lock();
 719
 720         select = ioapic_irqs[intr].io_idx;
 721         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 722
 723         ioapic_write(ioapic_irqs[intr].io_addr, select,
 724             (value & ~APIC_TRIGMOD_MASK));
 725         ioapic_write(ioapic_irqs[intr].io_addr, select,
 726             (value & ~IOART_INTVEC) | vector);
 727
 728         imen_unlock();
 729
 730         write_eflags(ef);
 731 }
 732
 733 static void
 734 ioapic_abi_setdefault(void)
 735 {
 736         int intr;
 737
 738         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
 739                 if (intr == IOAPIC_HWI_SYSCALL)
 740                         continue;
 741                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
 742                        SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 743         }
 744 }
 745
 746 static void
 747 ioapic_abi_initmap(void)
 748 {
 749         int cpu;
 750
 751         kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
 752
 753         kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start);
 754         ioapic_abi_msi_start &= ~0x1f;  /* MUST be 32 aligned */
 755
 756         /*
 757          * NOTE: ncpus is not ready yet
 758          */
 759         for (cpu = 0; cpu < MAXCPU; ++cpu) {
 760                 int i;
 761
 762                 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
 763                         ioapic_irqmaps[cpu][i].im_gsi = -1;
 764                         ioapic_irqmaps[cpu][i].im_msi_base = -1;
 765                 }
 766                 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
 767                     IOAPIC_IMT_SYSCALL;
 768         }
 769 }
 770
 771 static int
 772 ioapic_find_unused_irqmap(int gsi)
 773 {
 774         int cpuid, i;
 775
 776         cpuid = ioapic_abi_gsi_cpuid(-1, gsi);
 777
 778         for (i = ISA_IRQ_CNT; i < IOAPIC_HWI_VECTORS; ++i) {
 779                 if (i == acpi_sci_irqno())
 780                         continue;
 781                 if (ioapic_irqmaps[cpuid][i].im_type == IOAPIC_IMT_UNUSED)
 782                         return i;
 783         }
 784         return -1;
 785 }
 786
 787 void
 788 ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig,
 789     enum intr_polarity pola)
 790 {
 791         struct ioapic_irqinfo *info;
 792         struct ioapic_irqmap *map;
 793         void *ioaddr;
 794         int pin, cpuid;
 795
 796         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 797         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 798
 799         KKASSERT(irq >= 0);
 800         if (irq >= IOAPIC_HWI_VECTORS) {
 801                 /*
 802                  * Some BIOSes seem to assume that all 256 IDT vectors
 803                  * could be used, while we limit the available IDT
 804                  * vectors to 192; find an unused IRQ for this GSI.
 805                  */
 806                 irq = ioapic_find_unused_irqmap(gsi);
 807                 if (irq < 0) {
 808                         kprintf("failed to find unused irq for gsi %d\n", gsi);
 809                         return;
 810                 }
 811         }
 812         KKASSERT(irq < IOAPIC_HWI_VECTORS);
 813
 814         if (irq > ioapic_abi_legacy_irq_max)
 815                 ioapic_abi_legacy_irq_max = irq;
 816
 817         cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
 818
 819         map = &ioapic_irqmaps[cpuid][irq];
 820
 821         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
 822         map->im_type = IOAPIC_IMT_LEGACY;
 823
 824         map->im_gsi = gsi;
 825         map->im_trig = trig;
 826         map->im_pola = pola;
 827
 828         if (bootverbose) {
 829                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
 830                         irq, map->im_gsi,
 831                         intr_str_trigger(map->im_trig),
 832                         intr_str_polarity(map->im_pola));
 833         }
 834
 835         pin = ioapic_gsi_pin(map->im_gsi);
 836         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 837
 838         info = &ioapic_irqs[irq];
 839
 840         imen_lock();
 841
 842         info->io_addr = ioaddr;
 843         info->io_idx = IOAPIC_REDTBL + (2 * pin);
 844         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
 845         if (map->im_trig == INTR_TRIGGER_LEVEL)
 846                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 847
 848         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 849             map->im_trig, map->im_pola, cpuid);
 850
 851         imen_unlock();
 852 }
 853
 854 void
 855 ioapic_fixup_legacy_irqmaps(void)
 856 {
 857         int cpu;
 858
 859         ioapic_abi_legacy_irq_max += 1;
 860         if (bootverbose) {
 861                 kprintf("IOAPIC: legacy irq max %d\n",
 862                     ioapic_abi_legacy_irq_max);
 863         }
 864
 865         for (cpu = 0; cpu < ncpus; ++cpu) {
 866                 int i;
 867
 868                 for (i = 0; i < ioapic_abi_legacy_irq_max; ++i) {
 869                         struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
 870
 871                         if (map->im_type == IOAPIC_IMT_UNUSED) {
 872                                 map->im_type = IOAPIC_IMT_RESERVED;
 873                                 if (bootverbose) {
 874                                         kprintf("IOAPIC: "
 875                                             "cpu%d irq %d reserved\n", cpu, i);
 876                                 }
 877                         }
 878                 }
 879         }
 880 }
 881
 882 static int
 883 ioapic_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig,
 884     enum intr_polarity pola)
 885 {
 886         int cpu;
 887
 888 #ifdef INVARIANTS
 889         if (trig == INTR_TRIGGER_CONFORM) {
 890                 KKASSERT(pola == INTR_POLARITY_CONFORM);
 891         } else {
 892                 KKASSERT(trig == INTR_TRIGGER_EDGE ||
 893                     trig == INTR_TRIGGER_LEVEL);
 894                 KKASSERT(pola == INTR_POLARITY_HIGH ||
 895                     pola == INTR_POLARITY_LOW);
 896         }
 897 #endif
 898
 899         for (cpu = 0; cpu < ncpus; ++cpu) {
 900                 int irq;
 901
 902                 for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) {
 903                         const struct ioapic_irqmap *map =
 904                             &ioapic_irqmaps[cpu][irq];
 905
 906                         if (map->im_gsi == gsi) {
 907                                 KKASSERT(map->im_type == IOAPIC_IMT_LEGACY);
 908
 909                                 if ((map->im_flags & IOAPIC_IMF_CONF) &&
 910                                     trig != INTR_TRIGGER_CONFORM &&
 911                                     pola != INTR_POLARITY_CONFORM) {
 912                                         if (map->im_trig != trig ||
 913                                             map->im_pola != pola)
 914                                                 return -1;
 915                                 }
 916                                 return irq;
 917                         }
 918                 }
 919         }
 920         return -1;
 921 }
 922
 923 static int
 924 ioapic_abi_legacy_intr_find(int irq, enum intr_trigger trig,
 925     enum intr_polarity pola)
 926 {
 927         int cpu;
 928
 929 #ifdef INVARIANTS
 930         if (trig == INTR_TRIGGER_CONFORM) {
 931                 KKASSERT(pola == INTR_POLARITY_CONFORM);
 932         } else {
 933                 KKASSERT(trig == INTR_TRIGGER_EDGE ||
 934                     trig == INTR_TRIGGER_LEVEL);
 935                 KKASSERT(pola == INTR_POLARITY_HIGH ||
 936                     pola == INTR_POLARITY_LOW);
 937         }
 938 #endif
 939
 940         if (irq < 0 || irq >= ioapic_abi_legacy_irq_max)
 941                 return -1;
 942
 943         for (cpu = 0; cpu < ncpus; ++cpu) {
 944                 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
 945
 946                 if (map->im_type == IOAPIC_IMT_LEGACY) {
 947                         if ((map->im_flags & IOAPIC_IMF_CONF) &&
 948                             trig != INTR_TRIGGER_CONFORM &&
 949                             pola != INTR_POLARITY_CONFORM) {
 950                                 if (map->im_trig != trig ||
 951                                     map->im_pola != pola)
 952                                         return -1;
 953                         }
 954                         return irq;
 955                 }
 956         }
 957         return -1;
 958 }
 959
 960 static void
 961 ioapic_abi_legacy_intr_config(int irq, enum intr_trigger trig,
 962     enum intr_polarity pola)
 963 {
 964         struct ioapic_irqinfo *info;
 965         struct ioapic_irqmap *map = NULL;
 966         void *ioaddr;
 967         int pin, cpuid;
 968
 969         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 970         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 971
 972         KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
 973         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
 974                 map = &ioapic_irqmaps[cpuid][irq];
 975                 if (map->im_type == IOAPIC_IMT_LEGACY)
 976                         break;
 977         }
 978         KKASSERT(cpuid < ncpus);
 979
 980 #ifdef notyet
 981         if (map->im_flags & IOAPIC_IMF_CONF) {
 982                 if (trig != map->im_trig) {
 983                         panic("ioapic_intr_config: trig %s -> %s",
 984                               intr_str_trigger(map->im_trig),
 985                               intr_str_trigger(trig));
 986                 }
 987                 if (pola != map->im_pola) {
 988                         panic("ioapic_intr_config: pola %s -> %s",
 989                               intr_str_polarity(map->im_pola),
 990                               intr_str_polarity(pola));
 991                 }
 992                 return;
 993         }
 994 #endif
 995         map->im_flags |= IOAPIC_IMF_CONF;
 996
 997         if (trig == map->im_trig && pola == map->im_pola)
 998                 return;
 999
1000         if (bootverbose) {
1001                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
1002                         irq, map->im_gsi,
1003                         intr_str_trigger(map->im_trig),
1004                         intr_str_polarity(map->im_pola),
1005                         intr_str_trigger(trig),
1006                         intr_str_polarity(pola));
1007         }
1008         map->im_trig = trig;
1009         map->im_pola = pola;
1010
1011         pin = ioapic_gsi_pin(map->im_gsi);
1012         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
1013
1014         info = &ioapic_irqs[irq];
1015
1016         imen_lock();
1017
1018         info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
1019         if (map->im_trig == INTR_TRIGGER_LEVEL)
1020                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
1021
1022         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
1023             map->im_trig, map->im_pola, cpuid);
1024
1025         imen_unlock();
1026 }
1027
1028 int
1029 ioapic_conf_legacy_extint(int irq)
1030 {
1031         struct ioapic_irqinfo *info;
1032         struct ioapic_irqmap *map;
1033         void *ioaddr;
1034         int pin, error, vec;
1035
1036         /* XXX only irq0 is allowed */
1037         KKASSERT(irq == 0);
1038
1039         vec = IDT_OFFSET + irq;
1040
1041         if (ioapic_abi_extint_irq == irq)
1042                 return 0;
1043         else if (ioapic_abi_extint_irq >= 0)
1044                 return EEXIST;
1045
1046         error = icu_ioapic_extint(irq, vec);
1047         if (error)
1048                 return error;
1049
1050         /* ExtINT is always targeted to cpu0 */
1051         map = &ioapic_irqmaps[0][irq];
1052
1053         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
1054                  map->im_type == IOAPIC_IMT_LEGACY);
1055         if (map->im_type == IOAPIC_IMT_LEGACY) {
1056                 if (map->im_flags & IOAPIC_IMF_CONF)
1057                         return EEXIST;
1058         }
1059         ioapic_abi_extint_irq = irq;
1060
1061         map->im_type = IOAPIC_IMT_LEGACY;
1062         map->im_trig = INTR_TRIGGER_EDGE;
1063         map->im_pola = INTR_POLARITY_HIGH;
1064         map->im_flags = IOAPIC_IMF_CONF;
1065
1066         map->im_gsi = ioapic_extpin_gsi();
1067         KKASSERT(map->im_gsi >= 0);
1068
1069         if (bootverbose) {
1070                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
1071                         irq, map->im_gsi,
1072                         intr_str_trigger(map->im_trig),
1073                         intr_str_polarity(map->im_pola));
1074         }
1075
1076         pin = ioapic_gsi_pin(map->im_gsi);
1077         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
1078
1079         info = &ioapic_irqs[irq];
1080
1081         imen_lock();
1082
1083         info->io_addr = ioaddr;
1084         info->io_idx = IOAPIC_REDTBL + (2 * pin);
1085         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
1086
1087         ioapic_extpin_setup(ioaddr, pin, vec);
1088
1089         imen_unlock();
1090
1091         return 0;
1092 }
1093
1094 static int
1095 ioapic_abi_legacy_intr_cpuid(int irq)
1096 {
1097         const struct ioapic_irqmap *map = NULL;
1098         int cpuid;
1099
1100         KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
1101
1102         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1103                 map = &ioapic_irqmaps[cpuid][irq];
1104                 if (map->im_type == IOAPIC_IMT_LEGACY)
1105                         return cpuid;
1106         }
1107
1108         /* XXX some drivers tries to peek at reserved IRQs */
1109         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1110                 map = &ioapic_irqmaps[cpuid][irq];
1111                 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
1112         }
1113         return 0;
1114 }
1115
1116 static int
1117 ioapic_abi_gsi_cpuid(int irq, int gsi)
1118 {
1119         char envpath[32];
1120         int cpuid = -1;
1121
1122         KKASSERT(gsi >= 0);
1123
1124         if (irq == 0 || gsi == 0) {
1125                 KKASSERT(irq >= 0);
1126                 if (bootverbose) {
1127                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1128                             irq, gsi);
1129                 }
1130                 return 0;
1131         }
1132
1133         if (irq >= 0 && irq == acpi_sci_irqno()) {
1134                 if (bootverbose) {
1135                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1136                             irq, gsi);
1137                 }
1138                 return 0;
1139         }
1140
1141         ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1142         kgetenv_int(envpath, &cpuid);
1143
1144         if (cpuid < 0) {
1145                 if (!ioapic_abi_gsi_balance) {
1146                         if (irq >= 0 && bootverbose) {
1147                                 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 "
1148                                     "(fixed)\n", irq, gsi);
1149                         }
1150                         return 0;
1151                 }
1152
1153                 cpuid = gsi % ncpus;
1154                 if (irq >= 0 && bootverbose) {
1155                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1156                             irq, gsi, cpuid);
1157                 }
1158         } else if (cpuid >= ncpus) {
1159                 cpuid = ncpus - 1;
1160                 if (irq >= 0 && bootverbose) {
1161                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1162                             irq, gsi, cpuid);
1163                 }
1164         } else {
1165                 if (irq >= 0 && bootverbose) {
1166                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1167                             irq, gsi, cpuid);
1168                 }
1169         }
1170         return cpuid;
1171 }
1172
1173 static void
1174 ioapic_abi_rman_setup(struct rman *rm)
1175 {
1176         int start, end, i;
1177
1178         KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1179             ("invalid rman cpuid %d", rm->rm_cpuid));
1180
1181         start = end = -1;
1182         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1183                 const struct ioapic_irqmap *map =
1184                     &ioapic_irqmaps[rm->rm_cpuid][i];
1185
1186                 if (start < 0) {
1187                         if (IOAPIC_IMT_ISHWI(map))
1188                                 start = end = i;
1189                 } else {
1190                         if (IOAPIC_IMT_ISHWI(map)) {
1191                                 end = i;
1192                         } else {
1193                                 KKASSERT(end >= 0);
1194                                 if (bootverbose) {
1195                                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1196                                             rm->rm_cpuid, start, end);
1197                                 }
1198                                 if (rman_manage_region(rm, start, end)) {
1199                                         panic("rman_manage_region"
1200                                             "(cpu%d %d - %d)", rm->rm_cpuid,
1201                                             start, end);
1202                                 }
1203                                 start = end = -1;
1204                         }
1205                 }
1206         }
1207         if (start >= 0) {
1208                 KKASSERT(end >= 0);
1209                 if (bootverbose) {
1210                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1211                             rm->rm_cpuid, start, end);
1212                 }
1213                 if (rman_manage_region(rm, start, end)) {
1214                         panic("rman_manage_region(cpu%d %d - %d)",
1215                             rm->rm_cpuid, start, end);
1216                 }
1217         }
1218 }
1219
1220 static int
1221 ioapic_abi_msi_alloc_intern(int type, const char *desc,
1222     int intrs[], int count, int cpuid)
1223 {
1224         int i, error;
1225
1226         KASSERT(cpuid >= 0 && cpuid < ncpus,
1227             ("invalid cpuid %d", cpuid));
1228
1229         KASSERT(count > 0 && count <= 32, ("invalid count %d", count));
1230         KASSERT((count & (count - 1)) == 0,
1231             ("count %d is not power of 2", count));
1232
1233         lwkt_gettoken(&ioapic_irqmap_tok);
1234
1235         /*
1236          * NOTE:
1237          * Since IDT_OFFSET is 32, which is the maximum valid 'count',
1238          * we do not need to find out the first properly aligned
1239          * interrupt vector.
1240          */
1241
1242         error = EMSGSIZE;
1243         for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) {
1244                 int j;
1245
1246                 if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED)
1247                         continue;
1248
1249                 for (j = 1; j < count; ++j) {
1250                         if (ioapic_irqmaps[cpuid][i + j].im_type !=
1251                             IOAPIC_IMT_UNUSED)
1252                                 break;
1253                 }
1254                 if (j != count)
1255                         continue;
1256
1257                 for (j = 0; j < count; ++j) {
1258                         int intr = i + j, cpu;
1259
1260                         for (cpu = 0; cpu < ncpus; ++cpu) {
1261                                 struct ioapic_irqmap *map;
1262
1263                                 map = &ioapic_irqmaps[cpu][intr];
1264                                 KASSERT(map->im_msi_base < 0,
1265                                     ("intr %d cpu%d, stale %s-base %d",
1266                                      intr, cpu, desc, map->im_msi_base));
1267                                 KASSERT(map->im_type == IOAPIC_IMT_UNUSED,
1268                                     ("intr %d cpu%d, already allocated",
1269                                      intr, cpu));
1270
1271                                 if (cpu == cpuid) {
1272                                         map->im_type = type;
1273                                         map->im_msi_base = i;
1274                                 } else {
1275                                         map->im_type = IOAPIC_IMT_SHADOW;
1276                                 }
1277                         }
1278
1279                         intrs[j] = intr;
1280                         msi_setup(intr);
1281
1282                         if (bootverbose) {
1283                                 kprintf("alloc %s intr %d on cpu%d\n",
1284                                     desc, intr, cpuid);
1285                         }
1286                 }
1287                 error = 0;
1288                 break;
1289         }
1290
1291         lwkt_reltoken(&ioapic_irqmap_tok);
1292
1293         return error;
1294 }
1295
1296 static void
1297 ioapic_abi_msi_release_intern(int type, const char *desc,
1298     const int intrs[], int count, int cpuid)
1299 {
1300         int i, msi_base = -1, intr_next = -1, mask;
1301
1302         KASSERT(cpuid >= 0 && cpuid < ncpus,
1303             ("invalid cpuid %d", cpuid));
1304
1305         KASSERT(count > 0 && count <= 32, ("invalid count %d", count));
1306
1307         mask = count - 1;
1308         KASSERT((count & mask) == 0, ("count %d is not power of 2", count));
1309
1310         lwkt_gettoken(&ioapic_irqmap_tok);
1311
1312         for (i = 0; i < count; ++i) {
1313                 int intr = intrs[i], cpu;
1314
1315                 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
1316                     ("invalid intr %d", intr));
1317
1318                 for (cpu = 0; cpu < ncpus; ++cpu) {
1319                         struct ioapic_irqmap *map;
1320
1321                         map = &ioapic_irqmaps[cpu][intr];
1322
1323                         if (cpu == cpuid) {
1324                                 KASSERT(map->im_type == type,
1325                                     ("trying to release non-%s intr %d cpu%d, "
1326                                      "type %d", desc, intr, cpu,
1327                                      map->im_type));
1328                                 KASSERT(map->im_msi_base >= 0 &&
1329                                     map->im_msi_base <= intr,
1330                                     ("intr %d cpu%d, invalid %s-base %d",
1331                                      intr, cpu, desc, map->im_msi_base));
1332                                 KASSERT((map->im_msi_base & mask) == 0,
1333                                     ("intr %d cpu%d, %s-base %d is "
1334                                      "not properly aligned %d",
1335                                      intr, cpu, desc, map->im_msi_base, count));
1336
1337                                 if (msi_base < 0) {
1338                                         msi_base = map->im_msi_base;
1339                                 } else {
1340                                         KASSERT(map->im_msi_base == msi_base,
1341                                             ("intr %d cpu%d, "
1342                                              "inconsistent %s-base, "
1343                                              "was %d, now %d",
1344                                              intr, cpu, desc,
1345                                              msi_base, map->im_msi_base));
1346                                 }
1347                                 map->im_msi_base = -1;
1348                         } else {
1349                                 KASSERT(map->im_type == IOAPIC_IMT_SHADOW,
1350                                     ("trying to release non-%ssh intr %d cpu%d, "
1351                                      "type %d", desc, intr, cpu,
1352                                      map->im_type));
1353                                 KASSERT(map->im_msi_base < 0,
1354                                     ("intr %d cpu%d, invalid %ssh-base %d",
1355                                      intr, cpu, desc, map->im_msi_base));
1356                         }
1357                         map->im_type = IOAPIC_IMT_UNUSED;
1358                 }
1359
1360                 if (intr_next < intr)
1361                         intr_next = intr;
1362
1363                 if (bootverbose) {
1364                         kprintf("release %s intr %d on cpu%d\n",
1365                             desc, intr, cpuid);
1366                 }
1367         }
1368
1369         KKASSERT(intr_next > 0);
1370         KKASSERT(msi_base >= 0);
1371
1372         ++intr_next;
1373         if (intr_next < IOAPIC_HWI_VECTORS) {
1374                 int cpu;
1375
1376                 for (cpu = 0; cpu < ncpus; ++cpu) {
1377                         const struct ioapic_irqmap *map =
1378                             &ioapic_irqmaps[cpu][intr_next];
1379
1380                         if (map->im_type == type) {
1381                                 KASSERT(map->im_msi_base != msi_base,
1382                                     ("more than %d %s was allocated",
1383                                      count, desc));
1384                         }
1385                 }
1386         }
1387
1388         lwkt_reltoken(&ioapic_irqmap_tok);
1389 }
1390
1391 static int
1392 ioapic_abi_msi_alloc(int intrs[], int count, int cpuid)
1393 {
1394         return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSI, "MSI",
1395             intrs, count, cpuid);
1396 }
1397
1398 static void
1399 ioapic_abi_msi_release(const int intrs[], int count, int cpuid)
1400 {
1401         ioapic_abi_msi_release_intern(IOAPIC_IMT_MSI, "MSI",
1402             intrs, count, cpuid);
1403 }
1404
1405 static int
1406 ioapic_abi_msix_alloc(int *intr, int cpuid)
1407 {
1408         return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSIX, "MSI-X",
1409             intr, 1, cpuid);
1410 }
1411
1412 static void
1413 ioapic_abi_msix_release(int intr, int cpuid)
1414 {
1415         ioapic_abi_msi_release_intern(IOAPIC_IMT_MSIX, "MSI-X",
1416             &intr, 1, cpuid);
1417 }
1418
1419 static void
1420 ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
1421 {
1422         const struct ioapic_irqmap *map;
1423
1424         KASSERT(cpuid >= 0 && cpuid < ncpus,
1425             ("invalid cpuid %d", cpuid));
1426
1427         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
1428             ("invalid intr %d", intr));
1429
1430         lwkt_gettoken(&ioapic_irqmap_tok);
1431
1432         map = &ioapic_irqmaps[cpuid][intr];
1433         KASSERT(map->im_type == IOAPIC_IMT_MSI ||
1434             map->im_type == IOAPIC_IMT_MSIX,
1435             ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type));
1436         KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
1437             ("intr %d, invalid %s-base %d", intr,
1438              map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X",
1439              map->im_msi_base));
1440
1441         msi_map(map->im_msi_base, addr, data, cpuid);
1442
1443         if (bootverbose) {
1444                 kprintf("map %s intr %d on cpu%d\n",
1445                     map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X",
1446                     intr, cpuid);
1447         }
1448
1449         lwkt_reltoken(&ioapic_irqmap_tok);
1450 }