2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 #define MPTABLE_POS_USE_DEFAULT(mpt) \
172 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
176 int mb_type; /* MPTABLE_BUS_ */
177 TAILQ_ENTRY(mptable_bus) mb_link;
180 #define MPTABLE_BUS_ISA 0
181 #define MPTABLE_BUS_PCI 1
183 struct mptable_bus_info {
184 TAILQ_HEAD(, mptable_bus) mbi_list;
187 struct mptable_pci_int {
194 TAILQ_ENTRY(mptable_pci_int) mpci_link;
197 struct mptable_ioapic {
203 TAILQ_ENTRY(mptable_ioapic) mio_link;
206 typedef int (*mptable_iter_func)(void *, const void *, int);
209 * this code MUST be enabled here and in mpboot.s.
210 * it follows the very early stages of AP boot by placing values in CMOS ram.
211 * it NORMALLY will never be needed and thus the primitive method for enabling.
214 #if defined(CHECK_POINTS)
215 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
216 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
218 #define CHECK_INIT(D); \
219 CHECK_WRITE(0x34, (D)); \
220 CHECK_WRITE(0x35, (D)); \
221 CHECK_WRITE(0x36, (D)); \
222 CHECK_WRITE(0x37, (D)); \
223 CHECK_WRITE(0x38, (D)); \
224 CHECK_WRITE(0x39, (D));
226 #define CHECK_PRINT(S); \
227 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
236 #else /* CHECK_POINTS */
238 #define CHECK_INIT(D)
239 #define CHECK_PRINT(S)
241 #endif /* CHECK_POINTS */
244 * Values to send to the POST hardware.
246 #define MP_BOOTADDRESS_POST 0x10
247 #define MP_PROBE_POST 0x11
248 #define MPTABLE_PASS1_POST 0x12
250 #define MP_START_POST 0x13
251 #define MP_ENABLE_POST 0x14
252 #define MPTABLE_PASS2_POST 0x15
254 #define START_ALL_APS_POST 0x16
255 #define INSTALL_AP_TRAMP_POST 0x17
256 #define START_AP_POST 0x18
258 #define MP_ANNOUNCE_POST 0x19
260 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
261 int current_postcode;
263 /** XXX FIXME: what system files declare these??? */
264 extern struct region_descriptor r_gdt, r_idt;
266 int mp_naps; /* # of Applications processors */
267 #ifdef SMP /* APIC-IO */
268 static int mp_nbusses; /* # of busses */
269 int mp_napics; /* # of IO APICs */
270 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
271 u_int32_t *io_apic_versions;
275 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
277 extern int64_t tsc_offsets[];
279 extern u_long ebda_addr;
281 #ifdef SMP /* APIC-IO */
282 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
286 * APIC ID logical/physical mapping structures.
287 * We oversize these to simplify boot-time config.
289 int cpu_num_to_apic_id[NAPICID];
290 #ifdef SMP /* APIC-IO */
291 int io_num_to_apic_id[NAPICID];
293 int apic_id_to_logical[NAPICID];
295 /* AP uses this during bootstrap. Do not staticize. */
299 struct pcb stoppcbs[MAXCPU];
301 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
303 static basetable_entry basetable_entry_types[] =
305 {0, 20, "Processor"},
313 * Local data and functions.
316 static u_int boot_address;
317 static u_int base_memory;
318 static int mp_finish;
320 static void mp_enable(u_int boot_addr);
322 static int mptable_iterate_entries(const mpcth_t,
323 mptable_iter_func, void *);
324 static int mptable_search(void);
325 static long mptable_search_sig(u_int32_t target, int count);
326 static int mptable_hyperthread_fixup(cpumask_t, int);
327 #ifdef SMP /* APIC-IO */
328 static void mptable_pass1(struct mptable_pos *);
329 static void mptable_pass2(struct mptable_pos *);
330 static void mptable_default(int type);
331 static void mptable_fix(void);
333 static int mptable_map(struct mptable_pos *);
334 static void mptable_unmap(struct mptable_pos *);
335 static void mptable_bus_info_alloc(const mpcth_t,
336 struct mptable_bus_info *);
337 static void mptable_bus_info_free(struct mptable_bus_info *);
339 static int mptable_lapic_probe(struct lapic_enumerator *);
340 static void mptable_lapic_enumerate(struct lapic_enumerator *);
341 static void mptable_lapic_default(void);
343 static int mptable_ioapic_probe(struct ioapic_enumerator *);
344 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
346 #ifdef SMP /* APIC-IO */
347 static void setup_apic_irq_mapping(void);
348 static int apic_int_is_bus_type(int intr, int bus_type);
350 static int start_all_aps(u_int boot_addr);
352 static void install_ap_tramp(u_int boot_addr);
354 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
355 static int smitest(void);
357 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
358 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
359 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
360 static u_int bootMP_size;
364 static vm_paddr_t mptable_fps_phyaddr;
365 static int mptable_use_default;
366 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
367 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
368 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
369 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
372 * Calculate usable address in base memory for AP trampoline code.
375 mp_bootaddress(u_int basemem)
377 POSTCODE(MP_BOOTADDRESS_POST);
379 base_memory = basemem;
381 bootMP_size = mptramp_end - mptramp_start;
382 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
383 if (((basemem * 1024) - boot_address) < bootMP_size)
384 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
385 /* 3 levels of page table pages */
386 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
388 return mptramp_pagetables;
395 struct mptable_pos mpt;
398 KKASSERT(mptable_fps_phyaddr == 0);
400 mptable_fps_phyaddr = mptable_search();
401 if (mptable_fps_phyaddr == 0)
404 error = mptable_map(&mpt);
406 mptable_fps_phyaddr = 0;
410 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
411 kprintf("MPTABLE: use default configuration\n");
412 mptable_use_default = 1;
414 if (mpt.mp_fps->mpfb2 & 0x80)
419 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
422 * Look for an Intel MP spec table (ie, SMP capable hardware).
430 POSTCODE(MP_PROBE_POST);
432 /* see if EBDA exists */
433 if (ebda_addr != 0) {
434 /* search first 1K of EBDA */
435 target = (u_int32_t)ebda_addr;
436 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
439 /* last 1K of base memory, effective 'top of base' passed in */
440 target = (u_int32_t)(base_memory - 0x400);
441 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
445 /* search the BIOS */
446 target = (u_int32_t)BIOS_BASE;
447 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
450 /* search the extended BIOS */
451 target = (u_int32_t)BIOS_BASE2;
452 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
460 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
462 int count, total_size;
463 const void *position;
465 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
466 total_size = cth->base_table_length - sizeof(struct MPCTH);
467 position = (const uint8_t *)cth + sizeof(struct MPCTH);
468 count = cth->entry_count;
473 KKASSERT(total_size >= 0);
474 if (total_size == 0) {
475 kprintf("invalid base MP table, "
476 "entry count and length mismatch\n");
480 type = *(const uint8_t *)position;
482 case 0: /* processor_entry */
483 case 1: /* bus_entry */
484 case 2: /* io_apic_entry */
485 case 3: /* int_entry */
486 case 4: /* int_entry */
489 kprintf("unknown base MP table entry type %d\n", type);
493 if (total_size < basetable_entry_types[type].length) {
494 kprintf("invalid base MP table length, "
495 "does not contain all entries\n");
498 total_size -= basetable_entry_types[type].length;
500 error = func(arg, position, type);
504 position = (const uint8_t *)position +
505 basetable_entry_types[type].length;
512 * Startup the SMP processors.
517 POSTCODE(MP_START_POST);
518 mp_enable(boot_address);
523 * Print various information about the SMP system hardware and setup.
530 POSTCODE(MP_ANNOUNCE_POST);
532 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
533 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
534 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
535 for (x = 1; x <= mp_naps; ++x) {
536 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
537 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
540 if (apic_io_enable) {
541 if (ioapic_use_old) {
542 for (x = 0; x < mp_napics; ++x) {
543 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
544 kprintf(", version: 0x%08x", io_apic_versions[x]);
545 kprintf(", at 0x%08lx\n", io_apic_address[x]);
549 kprintf(" Warning: APIC I/O disabled\n");
554 * AP cpu's call this to sync up protected mode.
556 * WARNING! %gs is not set up on entry. This routine sets up %gs.
562 int x, myid = bootAP;
564 struct mdglobaldata *md;
565 struct privatespace *ps;
567 ps = &CPU_prvspace[myid];
569 gdt_segs[GPROC0_SEL].ssd_base =
570 (long) &ps->mdglobaldata.gd_common_tss;
571 ps->mdglobaldata.mi.gd_prvspace = ps;
573 /* We fill the 32-bit segment descriptors */
574 for (x = 0; x < NGDT; x++) {
575 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
576 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
578 /* And now a 64-bit one */
579 ssdtosyssd(&gdt_segs[GPROC0_SEL],
580 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
582 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
583 r_gdt.rd_base = (long) &gdt[myid * NGDT];
584 lgdt(&r_gdt); /* does magic intra-segment return */
586 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
587 wrmsr(MSR_FSBASE, 0); /* User value */
588 wrmsr(MSR_GSBASE, (u_int64_t)ps);
589 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
595 mdcpu->gd_currentldt = _default_ldt;
598 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
599 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
601 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
603 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
605 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
607 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
608 md->gd_common_tssd = *md->gd_tss_gdt;
610 /* double fault stack */
611 md->gd_common_tss.tss_ist1 =
612 (long)&md->mi.gd_prvspace->idlestack[
613 sizeof(md->mi.gd_prvspace->idlestack)];
618 * Set to a known state:
619 * Set by mpboot.s: CR0_PG, CR0_PE
620 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
623 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
626 /* Set up the fast syscall stuff */
627 msr = rdmsr(MSR_EFER) | EFER_SCE;
628 wrmsr(MSR_EFER, msr);
629 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
630 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
631 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
632 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
633 wrmsr(MSR_STAR, msr);
634 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
636 pmap_set_opt(); /* PSE/4MB pages, etc */
638 /* Initialize the PAT MSR. */
642 /* set up CPU registers and state */
645 /* set up SSE/NX registers */
648 /* set up FPU state on the AP */
649 npxinit(__INITIAL_NPXCW__);
651 /* disable the APIC, just to be SURE */
652 lapic->svr &= ~APIC_SVR_ENABLE;
654 /* data returned to BSP */
655 cpu_apic_versions[0] = lapic->version;
658 /*******************************************************************
659 * local functions and data
663 * start the SMP system
666 mp_enable(u_int boot_addr)
670 struct mptable_pos mpt;
672 POSTCODE(MP_ENABLE_POST);
679 if (apic_io_enable && ioapic_use_old) {
681 if (!mptable_fps_phyaddr)
682 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
687 * Examine the MP table for needed info
694 /* Post scan cleanup */
697 setup_apic_irq_mapping();
699 /* fill the LOGICAL io_apic_versions table */
700 for (apic = 0; apic < mp_napics; ++apic) {
701 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
702 io_apic_versions[apic] = ux;
703 io_apic_set_id(apic, IO_TO_ID(apic));
706 /* program each IO APIC in the system */
707 for (apic = 0; apic < mp_napics; ++apic)
708 if (io_apic_setup(apic) < 0)
709 panic("IO APIC setup failure");
714 * These are required for SMP operation
717 /* install a 'Spurious INTerrupt' vector */
718 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
719 SDT_SYSIGT, SEL_KPL, 0);
721 /* install an inter-CPU IPI for TLB invalidation */
722 setidt(XINVLTLB_OFFSET, Xinvltlb,
723 SDT_SYSIGT, SEL_KPL, 0);
725 /* install an inter-CPU IPI for IPIQ messaging */
726 setidt(XIPIQ_OFFSET, Xipiq,
727 SDT_SYSIGT, SEL_KPL, 0);
729 /* install a timer vector */
730 setidt(XTIMER_OFFSET, Xtimer,
731 SDT_SYSIGT, SEL_KPL, 0);
733 /* install an inter-CPU IPI for CPU stop/restart */
734 setidt(XCPUSTOP_OFFSET, Xcpustop,
735 SDT_SYSIGT, SEL_KPL, 0);
737 /* start each Application Processor */
738 start_all_aps(boot_addr);
743 * look for the MP spec signature
746 /* string defined by the Intel MP Spec as identifying the MP table */
747 #define MP_SIG 0x5f504d5f /* _MP_ */
748 #define NEXT(X) ((X) += 4)
750 mptable_search_sig(u_int32_t target, int count)
756 KKASSERT(target != 0);
758 map_size = count * sizeof(u_int32_t);
759 addr = pmap_mapdev((vm_paddr_t)target, map_size);
762 for (x = 0; x < count; NEXT(x)) {
763 if (addr[x] == MP_SIG) {
764 /* make array index a byte index */
765 ret = target + (x * sizeof(u_int32_t));
770 pmap_unmapdev((vm_offset_t)addr, map_size);
775 typedef struct BUSDATA {
777 enum busTypes bus_type;
780 typedef struct INTDATA {
790 typedef struct BUSTYPENAME {
795 static bus_type_name bus_type_table[] =
801 {UNKNOWN_BUSTYPE, "---"},
804 {UNKNOWN_BUSTYPE, "---"},
805 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
807 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"},
810 {UNKNOWN_BUSTYPE, "---"},
811 {UNKNOWN_BUSTYPE, "---"},
812 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"}
818 /* from MP spec v1.4, table 5-1 */
819 static int default_data[7][5] =
821 /* nbus, id0, type0, id1, type1 */
822 {1, 0, ISA, 255, 255},
823 {1, 0, EISA, 255, 255},
824 {1, 0, EISA, 255, 255},
825 {1, 0, MCA, 255, 255},
827 {2, 0, EISA, 1, PCI},
832 static bus_datum *bus_data;
834 /* the IO INT data, one entry per possible APIC INTerrupt */
835 static io_int *io_apic_ints;
838 static int processor_entry (const struct PROCENTRY *entry, int cpu);
839 static int bus_entry (const struct BUSENTRY *entry, int bus);
840 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
841 static int int_entry (const struct INTENTRY *entry, int intr);
842 static int lookup_bus_type (char *name);
845 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
847 const struct IOAPICENTRY *ioapic_ent;
850 case 1: /* bus_entry */
854 case 2: /* io_apic_entry */
856 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
857 io_apic_address[mp_napics++] =
858 (vm_offset_t)ioapic_ent->apic_address;
862 case 3: /* int_entry */
870 * 1st pass on motherboard's Intel MP specification table.
879 mptable_pass1(struct mptable_pos *mpt)
884 POSTCODE(MPTABLE_PASS1_POST);
887 KKASSERT(fps != NULL);
889 /* clear various tables */
890 for (x = 0; x < NAPICID; ++x)
891 io_apic_address[x] = ~0; /* IO APIC address table */
897 /* check for use of 'default' configuration */
898 if (fps->mpfb1 != 0) {
899 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
900 mp_nbusses = default_data[fps->mpfb1 - 1][0];
906 error = mptable_iterate_entries(mpt->mp_cth,
907 mptable_ioapic_pass1_callback, NULL);
909 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
913 struct mptable_ioapic2_cbarg {
920 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
922 struct mptable_ioapic2_cbarg *arg = xarg;
926 if (bus_entry(pos, arg->bus))
931 if (io_apic_entry(pos, arg->apic))
936 if (int_entry(pos, arg->intr))
944 * 2nd pass on motherboard's Intel MP specification table.
947 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
948 * IO_TO_ID(N), logical IO to APIC ID table
953 mptable_pass2(struct mptable_pos *mpt)
955 struct mptable_ioapic2_cbarg arg;
959 POSTCODE(MPTABLE_PASS2_POST);
962 KKASSERT(fps != NULL);
964 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
966 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
967 M_DEVBUF, M_WAITOK | M_ZERO);
968 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
970 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
973 for (x = 0; x < mp_napics; x++)
974 ioapic[x] = ioapic_map(io_apic_address[x]);
976 /* clear various tables */
977 for (x = 0; x < NAPICID; ++x) {
978 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
979 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
982 /* clear bus data table */
983 for (x = 0; x < mp_nbusses; ++x)
984 bus_data[x].bus_id = 0xff;
986 /* clear IO APIC INT table */
987 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
988 io_apic_ints[x].int_type = 0xff;
989 io_apic_ints[x].int_vector = 0xff;
992 /* check for use of 'default' configuration */
993 if (fps->mpfb1 != 0) {
994 mptable_default(fps->mpfb1);
998 bzero(&arg, sizeof(arg));
999 error = mptable_iterate_entries(mpt->mp_cth,
1000 mptable_ioapic_pass2_callback, &arg);
1002 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1006 * Check if we should perform a hyperthreading "fix-up" to
1007 * enumerate any logical CPU's that aren't already listed
1010 * XXX: We assume that all of the physical CPUs in the
1011 * system have the same number of logical CPUs.
1013 * XXX: We assume that APIC ID's are allocated such that
1014 * the APIC ID's for a physical processor are aligned
1015 * with the number of logical CPU's in the processor.
1018 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
1020 int i, id, lcpus_max, logical_cpus;
1022 if ((cpu_feature & CPUID_HTT) == 0)
1025 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1029 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1031 * INSTRUCTION SET REFERENCE, A-M (#253666)
1032 * Page 3-181, Table 3-20
1033 * "The nearest power-of-2 integer that is not smaller
1034 * than EBX[23:16] is the number of unique initial APIC
1035 * IDs reserved for addressing different logical
1036 * processors in a physical package."
1038 for (i = 0; ; ++i) {
1039 if ((1 << i) >= lcpus_max) {
1046 KKASSERT(cpu_count != 0);
1047 if (cpu_count == lcpus_max) {
1048 /* We have nothing to fix */
1050 } else if (cpu_count == 1) {
1051 /* XXX this may be incorrect */
1052 logical_cpus = lcpus_max;
1054 int cur, prev, dist;
1057 * Calculate the distances between two nearest
1058 * APIC IDs. If all such distances are same,
1059 * then it is the number of missing cpus that
1060 * we are going to fill later.
1062 dist = cur = prev = -1;
1063 for (id = 0; id < MAXCPU; ++id) {
1064 if ((id_mask & CPUMASK(id)) == 0)
1069 int new_dist = cur - prev;
1075 * Make sure that all distances
1076 * between two nearest APIC IDs
1079 if (dist != new_dist)
1087 /* Must be power of 2 */
1088 if (dist & (dist - 1))
1091 /* Can't exceed CPU package capacity */
1092 if (dist > lcpus_max)
1093 logical_cpus = lcpus_max;
1095 logical_cpus = dist;
1099 * For each APIC ID of a CPU that is set in the mask,
1100 * scan the other candidate APIC ID's for this
1101 * physical processor. If any of those ID's are
1102 * already in the table, then kill the fixup.
1104 for (id = 0; id < MAXCPU; id++) {
1105 if ((id_mask & CPUMASK(id)) == 0)
1107 /* First, make sure we are on a logical_cpus boundary. */
1108 if (id % logical_cpus != 0)
1110 for (i = id + 1; i < id + logical_cpus; i++)
1111 if ((id_mask & CPUMASK(i)) != 0)
1114 return logical_cpus;
1118 mptable_map(struct mptable_pos *mpt)
1122 vm_size_t cth_mapsz = 0;
1124 KKASSERT(mptable_fps_phyaddr != 0);
1126 bzero(mpt, sizeof(*mpt));
1128 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1129 if (fps->pap != 0) {
1131 * Map configuration table header to get
1132 * the base table size
1134 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1135 cth_mapsz = cth->base_table_length;
1136 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1138 if (cth_mapsz < sizeof(*cth)) {
1139 kprintf("invalid base MP table length %d\n",
1141 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1146 * Map the base table
1148 cth = pmap_mapdev(fps->pap, cth_mapsz);
1153 mpt->mp_cth_mapsz = cth_mapsz;
1159 mptable_unmap(struct mptable_pos *mpt)
1161 if (mpt->mp_cth != NULL) {
1162 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1164 mpt->mp_cth_mapsz = 0;
1166 if (mpt->mp_fps != NULL) {
1167 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1173 assign_apic_irq(int apic, int intpin, int irq)
1177 if (int_to_apicintpin[irq].ioapic != -1)
1178 panic("assign_apic_irq: inconsistent table");
1180 int_to_apicintpin[irq].ioapic = apic;
1181 int_to_apicintpin[irq].int_pin = intpin;
1182 int_to_apicintpin[irq].apic_address = ioapic[apic];
1183 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1185 for (x = 0; x < nintrs; x++) {
1186 if ((io_apic_ints[x].int_type == 0 ||
1187 io_apic_ints[x].int_type == 3) &&
1188 io_apic_ints[x].int_vector == 0xff &&
1189 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1190 io_apic_ints[x].dst_apic_int == intpin)
1191 io_apic_ints[x].int_vector = irq;
1196 revoke_apic_irq(int irq)
1202 if (int_to_apicintpin[irq].ioapic == -1)
1203 panic("revoke_apic_irq: inconsistent table");
1205 oldapic = int_to_apicintpin[irq].ioapic;
1206 oldintpin = int_to_apicintpin[irq].int_pin;
1208 int_to_apicintpin[irq].ioapic = -1;
1209 int_to_apicintpin[irq].int_pin = 0;
1210 int_to_apicintpin[irq].apic_address = NULL;
1211 int_to_apicintpin[irq].redirindex = 0;
1213 for (x = 0; x < nintrs; x++) {
1214 if ((io_apic_ints[x].int_type == 0 ||
1215 io_apic_ints[x].int_type == 3) &&
1216 io_apic_ints[x].int_vector != 0xff &&
1217 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1218 io_apic_ints[x].dst_apic_int == oldintpin)
1219 io_apic_ints[x].int_vector = 0xff;
1227 allocate_apic_irq(int intr)
1233 if (io_apic_ints[intr].int_vector != 0xff)
1234 return; /* Interrupt handler already assigned */
1236 if (io_apic_ints[intr].int_type != 0 &&
1237 (io_apic_ints[intr].int_type != 3 ||
1238 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1239 io_apic_ints[intr].dst_apic_int == 0)))
1240 return; /* Not INT or ExtInt on != (0, 0) */
1243 while (irq < APIC_INTMAPSIZE &&
1244 int_to_apicintpin[irq].ioapic != -1)
1247 if (irq >= APIC_INTMAPSIZE)
1248 return; /* No free interrupt handlers */
1250 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1251 intpin = io_apic_ints[intr].dst_apic_int;
1253 assign_apic_irq(apic, intpin, irq);
1258 swap_apic_id(int apic, int oldid, int newid)
1265 return; /* Nothing to do */
1267 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1268 apic, oldid, newid);
1270 /* Swap physical APIC IDs in interrupt entries */
1271 for (x = 0; x < nintrs; x++) {
1272 if (io_apic_ints[x].dst_apic_id == oldid)
1273 io_apic_ints[x].dst_apic_id = newid;
1274 else if (io_apic_ints[x].dst_apic_id == newid)
1275 io_apic_ints[x].dst_apic_id = oldid;
1278 /* Swap physical APIC IDs in IO_TO_ID mappings */
1279 for (oapic = 0; oapic < mp_napics; oapic++)
1280 if (IO_TO_ID(oapic) == newid)
1283 if (oapic < mp_napics) {
1284 kprintf("Changing APIC ID for IO APIC #%d from "
1285 "%d to %d in MP table\n",
1286 oapic, newid, oldid);
1287 IO_TO_ID(oapic) = oldid;
1289 IO_TO_ID(apic) = newid;
1294 fix_id_to_io_mapping(void)
1298 for (x = 0; x < NAPICID; x++)
1301 for (x = 0; x <= mp_naps; x++) {
1302 if ((u_int)CPU_TO_ID(x) < NAPICID)
1303 ID_TO_IO(CPU_TO_ID(x)) = x;
1306 for (x = 0; x < mp_napics; x++) {
1307 if ((u_int)IO_TO_ID(x) < NAPICID)
1308 ID_TO_IO(IO_TO_ID(x)) = x;
1314 first_free_apic_id(void)
1318 for (freeid = 0; freeid < NAPICID; freeid++) {
1319 for (x = 0; x <= mp_naps; x++)
1320 if (CPU_TO_ID(x) == freeid)
1324 for (x = 0; x < mp_napics; x++)
1325 if (IO_TO_ID(x) == freeid)
1336 io_apic_id_acceptable(int apic, int id)
1338 int cpu; /* Logical CPU number */
1339 int oapic; /* Logical IO APIC number for other IO APIC */
1341 if ((u_int)id >= NAPICID)
1342 return 0; /* Out of range */
1344 for (cpu = 0; cpu <= mp_naps; cpu++) {
1345 if (CPU_TO_ID(cpu) == id)
1346 return 0; /* Conflict with CPU */
1349 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) {
1350 if (IO_TO_ID(oapic) == id)
1351 return 0; /* Conflict with other APIC */
1354 return 1; /* ID is acceptable for IO APIC */
1359 io_apic_find_int_entry(int apic, int pin)
1363 /* search each of the possible INTerrupt sources */
1364 for (x = 0; x < nintrs; ++x) {
1365 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1366 (pin == io_apic_ints[x].dst_apic_int))
1367 return (&io_apic_ints[x]);
1373 * parse an Intel MP specification table
1380 int apic; /* IO APIC unit number */
1381 int freeid; /* Free physical APIC ID */
1382 int physid; /* Current physical IO APIC ID */
1384 int bus_0 = 0; /* Stop GCC warning */
1385 int bus_pci = 0; /* Stop GCC warning */
1389 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1390 * did it wrong. The MP spec says that when more than 1 PCI bus
1391 * exists the BIOS must begin with bus entries for the PCI bus and use
1392 * actual PCI bus numbering. This implies that when only 1 PCI bus
1393 * exists the BIOS can choose to ignore this ordering, and indeed many
1394 * MP motherboards do ignore it. This causes a problem when the PCI
1395 * sub-system makes requests of the MP sub-system based on PCI bus
1396 * numbers. So here we look for the situation and renumber the
1397 * busses and associated INTs in an effort to "make it right".
1400 /* find bus 0, PCI bus, count the number of PCI busses */
1401 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1402 if (bus_data[x].bus_id == 0) {
1405 if (bus_data[x].bus_type == PCI) {
1411 * bus_0 == slot of bus with ID of 0
1412 * bus_pci == slot of last PCI bus encountered
1415 /* check the 1 PCI bus case for sanity */
1416 /* if it is number 0 all is well */
1417 if (num_pci_bus == 1 &&
1418 bus_data[bus_pci].bus_id != 0) {
1420 /* mis-numbered, swap with whichever bus uses slot 0 */
1422 /* swap the bus entry types */
1423 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1424 bus_data[bus_0].bus_type = PCI;
1426 /* swap each relevant INTerrupt entry */
1427 id = bus_data[bus_pci].bus_id;
1428 for (x = 0; x < nintrs; ++x) {
1429 if (io_apic_ints[x].src_bus_id == id) {
1430 io_apic_ints[x].src_bus_id = 0;
1432 else if (io_apic_ints[x].src_bus_id == 0) {
1433 io_apic_ints[x].src_bus_id = id;
1438 /* Assign IO APIC IDs.
1440 * First try the existing ID. If a conflict is detected, try
1441 * the ID in the MP table. If a conflict is still detected, find
1444 * We cannot use the ID_TO_IO table before all conflicts has been
1445 * resolved and the table has been corrected.
1447 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1449 /* First try to use the value set by the BIOS */
1450 physid = io_apic_get_id(apic);
1451 if (io_apic_id_acceptable(apic, physid)) {
1452 if (IO_TO_ID(apic) != physid)
1453 swap_apic_id(apic, IO_TO_ID(apic), physid);
1457 /* Then check if the value in the MP table is acceptable */
1458 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1461 /* Last resort, find a free APIC ID and use it */
1462 freeid = first_free_apic_id();
1463 if (freeid >= NAPICID)
1464 panic("No free physical APIC IDs found");
1466 if (io_apic_id_acceptable(apic, freeid)) {
1467 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1470 panic("Free physical APIC ID not usable");
1472 fix_id_to_io_mapping();
1474 /* detect and fix broken Compaq MP table */
1475 if (apic_int_type(0, 0) == -1) {
1476 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1477 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1478 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1479 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1480 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1481 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1483 } else if (apic_int_type(0, 0) == 0) {
1484 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1485 for (x = 0; x < nintrs; ++x)
1486 if ((ID_TO_IO(io_apic_ints[x].dst_apic_id) == 0) &&
1487 (io_apic_ints[x].dst_apic_int) == 0) {
1488 io_apic_ints[x].int_type = 3;
1489 io_apic_ints[x].int_vector = 0xff;
1495 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1496 * controllers universally come in pairs. If IRQ 14 is specified
1497 * as an ISA interrupt, then IRQ 15 had better be too.
1499 * [ Shuttle XPC / AMD Athlon X2 ]
1500 * The MPTable is missing an entry for IRQ 15. Note that the
1501 * ACPI table has an entry for both 14 and 15.
1503 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1504 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1505 io14 = io_apic_find_int_entry(0, 14);
1506 io_apic_ints[nintrs] = *io14;
1507 io_apic_ints[nintrs].src_bus_irq = 15;
1508 io_apic_ints[nintrs].dst_apic_int = 15;
1513 /* Assign low level interrupt handlers */
1515 setup_apic_irq_mapping(void)
1521 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1522 int_to_apicintpin[x].ioapic = -1;
1523 int_to_apicintpin[x].int_pin = 0;
1524 int_to_apicintpin[x].apic_address = NULL;
1525 int_to_apicintpin[x].redirindex = 0;
1527 /* Default to masked */
1528 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1531 /* First assign ISA/EISA interrupts */
1532 for (x = 0; x < nintrs; x++) {
1533 int_vector = io_apic_ints[x].src_bus_irq;
1534 if (int_vector < APIC_INTMAPSIZE &&
1535 io_apic_ints[x].int_vector == 0xff &&
1536 int_to_apicintpin[int_vector].ioapic == -1 &&
1537 (apic_int_is_bus_type(x, ISA) ||
1538 apic_int_is_bus_type(x, EISA)) &&
1539 io_apic_ints[x].int_type == 0) {
1540 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1541 io_apic_ints[x].dst_apic_int,
1546 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1547 for (x = 0; x < nintrs; x++) {
1548 if (io_apic_ints[x].dst_apic_int == 0 &&
1549 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1550 io_apic_ints[x].int_vector == 0xff &&
1551 int_to_apicintpin[0].ioapic == -1 &&
1552 io_apic_ints[x].int_type == 3) {
1553 assign_apic_irq(0, 0, 0);
1558 /* Assign PCI interrupts */
1559 for (x = 0; x < nintrs; ++x) {
1560 if (io_apic_ints[x].int_type == 0 &&
1561 io_apic_ints[x].int_vector == 0xff &&
1562 apic_int_is_bus_type(x, PCI))
1563 allocate_apic_irq(x);
1568 mp_set_cpuids(int cpu_id, int apic_id)
1570 CPU_TO_ID(cpu_id) = apic_id;
1571 ID_TO_CPU(apic_id) = cpu_id;
1573 if (apic_id > lapic_id_max)
1574 lapic_id_max = apic_id;
1578 processor_entry(const struct PROCENTRY *entry, int cpu)
1582 /* check for usability */
1583 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1586 /* check for BSP flag */
1587 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1588 mp_set_cpuids(0, entry->apic_id);
1589 return 0; /* its already been counted */
1592 /* add another AP to list, if less than max number of CPUs */
1593 else if (cpu < MAXCPU) {
1594 mp_set_cpuids(cpu, entry->apic_id);
1602 bus_entry(const struct BUSENTRY *entry, int bus)
1607 /* encode the name into an index */
1608 for (x = 0; x < 6; ++x) {
1609 if ((c = entry->bus_type[x]) == ' ')
1615 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1616 panic("unknown bus type: '%s'", name);
1618 bus_data[bus].bus_id = entry->bus_id;
1619 bus_data[bus].bus_type = x;
1625 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1627 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1630 IO_TO_ID(apic) = entry->apic_id;
1631 ID_TO_IO(entry->apic_id) = apic;
1637 lookup_bus_type(char *name)
1641 for (x = 0; x < MAX_BUSTYPE; ++x)
1642 if (strcmp(bus_type_table[x].name, name) == 0)
1643 return bus_type_table[x].type;
1645 return UNKNOWN_BUSTYPE;
1649 int_entry(const struct INTENTRY *entry, int intr)
1653 io_apic_ints[intr].int_type = entry->int_type;
1654 io_apic_ints[intr].int_flags = entry->int_flags;
1655 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1656 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1657 if (entry->dst_apic_id == 255) {
1658 /* This signal goes to all IO APICS. Select an IO APIC
1659 with sufficient number of interrupt pins */
1660 for (apic = 0; apic < mp_napics; apic++)
1661 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1662 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1663 entry->dst_apic_int)
1665 if (apic < mp_napics)
1666 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1668 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1670 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1671 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1677 apic_int_is_bus_type(int intr, int bus_type)
1681 for (bus = 0; bus < mp_nbusses; ++bus)
1682 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1683 && ((int) bus_data[bus].bus_type == bus_type))
1690 * Given a traditional ISA INT mask, return an APIC mask.
1693 isa_apic_mask(u_int isa_mask)
1698 #if defined(SKIP_IRQ15_REDIRECT)
1699 if (isa_mask == (1 << 15)) {
1700 kprintf("skipping ISA IRQ15 redirect\n");
1703 #endif /* SKIP_IRQ15_REDIRECT */
1705 isa_irq = ffs(isa_mask); /* find its bit position */
1706 if (isa_irq == 0) /* doesn't exist */
1708 --isa_irq; /* make it zero based */
1710 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1714 return (1 << apic_pin); /* convert pin# to a mask */
1718 * Determine which APIC pin an ISA/EISA INT is attached to.
1720 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1721 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1722 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1723 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1725 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1727 isa_apic_irq(int isa_irq)
1731 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1732 if (INTTYPE(intr) == 0) { /* standard INT */
1733 if (SRCBUSIRQ(intr) == isa_irq) {
1734 if (apic_int_is_bus_type(intr, ISA) ||
1735 apic_int_is_bus_type(intr, EISA)) {
1736 if (INTIRQ(intr) == 0xff)
1737 return -1; /* unassigned */
1738 return INTIRQ(intr); /* found */
1743 return -1; /* NOT found */
1748 * Determine which APIC pin a PCI INT is attached to.
1750 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1751 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1752 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1754 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1758 --pciInt; /* zero based */
1760 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1761 if ((INTTYPE(intr) == 0) /* standard INT */
1762 && (SRCBUSID(intr) == pciBus)
1763 && (SRCBUSDEVICE(intr) == pciDevice)
1764 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1765 if (apic_int_is_bus_type(intr, PCI)) {
1766 if (INTIRQ(intr) == 0xff) {
1767 kprintf("IOAPIC: pci_apic_irq() "
1769 return -1; /* unassigned */
1771 return INTIRQ(intr); /* exact match */
1776 return -1; /* NOT found */
1780 next_apic_irq(int irq)
1787 for (intr = 0; intr < nintrs; intr++) {
1788 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1790 bus = SRCBUSID(intr);
1791 bustype = apic_bus_type(bus);
1792 if (bustype != ISA &&
1798 if (intr >= nintrs) {
1801 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1802 if (INTTYPE(ointr) != 0)
1804 if (bus != SRCBUSID(ointr))
1806 if (bustype == PCI) {
1807 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1809 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1812 if (bustype == ISA || bustype == EISA) {
1813 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1816 if (INTPIN(intr) == INTPIN(ointr))
1820 if (ointr >= nintrs) {
1823 return INTIRQ(ointr);
1836 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1839 * Exactly what this means is unclear at this point. It is a solution
1840 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1841 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1842 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1846 undirect_isa_irq(int rirq)
1850 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1851 /** FIXME: tickle the MB redirector chip */
1855 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1862 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1865 undirect_pci_irq(int rirq)
1869 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1871 /** FIXME: tickle the MB redirector chip */
1875 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1883 * given a bus ID, return:
1884 * the bus type if found
1888 apic_bus_type(int id)
1892 for (x = 0; x < mp_nbusses; ++x)
1893 if (bus_data[x].bus_id == id)
1894 return bus_data[x].bus_type;
1900 * given a LOGICAL APIC# and pin#, return:
1901 * the associated src bus ID if found
1905 apic_src_bus_id(int apic, int pin)
1909 /* search each of the possible INTerrupt sources */
1910 for (x = 0; x < nintrs; ++x)
1911 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1912 (pin == io_apic_ints[x].dst_apic_int))
1913 return (io_apic_ints[x].src_bus_id);
1915 return -1; /* NOT found */
1919 * given a LOGICAL APIC# and pin#, return:
1920 * the associated src bus IRQ if found
1924 apic_src_bus_irq(int apic, int pin)
1928 for (x = 0; x < nintrs; x++)
1929 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1930 (pin == io_apic_ints[x].dst_apic_int))
1931 return (io_apic_ints[x].src_bus_irq);
1933 return -1; /* NOT found */
1938 * given a LOGICAL APIC# and pin#, return:
1939 * the associated INTerrupt type if found
1943 apic_int_type(int apic, int pin)
1947 /* search each of the possible INTerrupt sources */
1948 for (x = 0; x < nintrs; ++x) {
1949 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1950 (pin == io_apic_ints[x].dst_apic_int))
1951 return (io_apic_ints[x].int_type);
1953 return -1; /* NOT found */
1957 * Return the IRQ associated with an APIC pin
1960 apic_irq(int apic, int pin)
1965 for (x = 0; x < nintrs; ++x) {
1966 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1967 (pin == io_apic_ints[x].dst_apic_int)) {
1968 res = io_apic_ints[x].int_vector;
1971 if (apic != int_to_apicintpin[res].ioapic)
1972 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1973 if (pin != int_to_apicintpin[res].int_pin)
1974 panic("apic_irq inconsistent table (2)");
1983 * given a LOGICAL APIC# and pin#, return:
1984 * the associated trigger mode if found
1988 apic_trigger(int apic, int pin)
1992 /* search each of the possible INTerrupt sources */
1993 for (x = 0; x < nintrs; ++x)
1994 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1995 (pin == io_apic_ints[x].dst_apic_int))
1996 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1998 return -1; /* NOT found */
2003 * given a LOGICAL APIC# and pin#, return:
2004 * the associated 'active' level if found
2008 apic_polarity(int apic, int pin)
2012 /* search each of the possible INTerrupt sources */
2013 for (x = 0; x < nintrs; ++x)
2014 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2015 (pin == io_apic_ints[x].dst_apic_int))
2016 return (io_apic_ints[x].int_flags & 0x03);
2018 return -1; /* NOT found */
2022 * set data according to MP defaults
2023 * FIXME: probably not complete yet...
2026 mptable_default(int type)
2032 kprintf(" MP default config type: %d\n", type);
2035 kprintf(" bus: ISA, APIC: 82489DX\n");
2038 kprintf(" bus: EISA, APIC: 82489DX\n");
2041 kprintf(" bus: EISA, APIC: 82489DX\n");
2044 kprintf(" bus: MCA, APIC: 82489DX\n");
2047 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2050 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2053 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2056 kprintf(" future type\n");
2062 /* one and only IO APIC */
2063 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2066 * sanity check, refer to MP spec section 3.6.6, last paragraph
2067 * necessary as some hardware isn't properly setting up the IO APIC
2069 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2070 if (io_apic_id != 2) {
2072 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2073 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2074 io_apic_set_id(0, 2);
2077 IO_TO_ID(0) = io_apic_id;
2078 ID_TO_IO(io_apic_id) = 0;
2080 /* fill out bus entries */
2089 bus_data[0].bus_id = default_data[type - 1][1];
2090 bus_data[0].bus_type = default_data[type - 1][2];
2091 bus_data[1].bus_id = default_data[type - 1][3];
2092 bus_data[1].bus_type = default_data[type - 1][4];
2095 /* case 4: case 7: MCA NOT supported */
2096 default: /* illegal/reserved */
2097 panic("BAD default MP config: %d", type);
2101 /* general cases from MP v1.4, table 5-2 */
2102 for (pin = 0; pin < 16; ++pin) {
2103 io_apic_ints[pin].int_type = 0;
2104 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2105 io_apic_ints[pin].src_bus_id = 0;
2106 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2107 io_apic_ints[pin].dst_apic_id = io_apic_id;
2108 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2111 /* special cases from MP v1.4, table 5-2 */
2113 io_apic_ints[2].int_type = 0xff; /* N/C */
2114 io_apic_ints[13].int_type = 0xff; /* N/C */
2115 #if !defined(APIC_MIXED_MODE)
2117 panic("sorry, can't support type 2 default yet");
2118 #endif /* APIC_MIXED_MODE */
2121 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2124 io_apic_ints[0].int_type = 0xff; /* N/C */
2126 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2130 * Map a physical memory address representing I/O into KVA. The I/O
2131 * block is assumed not to cross a page boundary.
2134 ioapic_map(vm_paddr_t pa)
2136 KKASSERT(pa < 0x100000000LL);
2138 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2142 * start each AP in our list
2145 start_all_aps(u_int boot_addr)
2147 vm_offset_t va = boot_address + KERNBASE;
2148 u_int64_t *pt4, *pt3, *pt2;
2154 u_char mpbiosreason;
2155 u_long mpbioswarmvec;
2156 struct mdglobaldata *gd;
2157 struct privatespace *ps;
2159 POSTCODE(START_ALL_APS_POST);
2161 /* Initialize BSP's local APIC */
2165 MachIntrABI.finalize();
2167 /* install the AP 1st level boot code */
2168 pmap_kenter(va, boot_address);
2169 cpu_invlpg((void *)va); /* JG XXX */
2170 bcopy(mptramp_start, (void *)va, bootMP_size);
2172 /* Locate the page tables, they'll be below the trampoline */
2173 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2174 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2175 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2177 /* Create the initial 1GB replicated page tables */
2178 for (i = 0; i < 512; i++) {
2179 /* Each slot of the level 4 pages points to the same level 3 page */
2180 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2181 pt4[i] |= PG_V | PG_RW | PG_U;
2183 /* Each slot of the level 3 pages points to the same level 2 page */
2184 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2185 pt3[i] |= PG_V | PG_RW | PG_U;
2187 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2188 pt2[i] = i * (2 * 1024 * 1024);
2189 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2192 /* save the current value of the warm-start vector */
2193 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2194 outb(CMOS_REG, BIOS_RESET);
2195 mpbiosreason = inb(CMOS_DATA);
2197 /* setup a vector to our boot code */
2198 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2199 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2200 outb(CMOS_REG, BIOS_RESET);
2201 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2204 * If we have a TSC we can figure out the SMI interrupt rate.
2205 * The SMI does not necessarily use a constant rate. Spend
2206 * up to 250ms trying to figure it out.
2209 if (cpu_feature & CPUID_TSC) {
2210 set_apic_timer(275000);
2211 smilast = read_apic_timer();
2212 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2213 smicount = smitest();
2214 if (smibest == 0 || smilast - smicount < smibest)
2215 smibest = smilast - smicount;
2218 if (smibest > 250000)
2221 smibest = smibest * (int64_t)1000000 /
2222 get_apic_timer_frequency();
2226 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2227 1000000 / smibest, smibest);
2229 kprintf("SMP: Starting %d APs: ", mp_naps);
2231 for (x = 1; x <= mp_naps; ++x) {
2233 /* This is a bit verbose, it will go away soon. */
2235 /* first page of AP's private space */
2236 pg = x * x86_64_btop(sizeof(struct privatespace));
2238 /* allocate new private data page(s) */
2239 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2240 MDGLOBALDATA_BASEALLOC_SIZE);
2242 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2243 bzero(gd, sizeof(*gd));
2244 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2246 /* prime data page for it to use */
2247 mi_gdinit(&gd->mi, x);
2249 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2250 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2252 /* setup a vector to our boot code */
2253 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2254 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2255 outb(CMOS_REG, BIOS_RESET);
2256 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2259 * Setup the AP boot stack
2261 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2264 /* attempt to start the Application Processor */
2265 CHECK_INIT(99); /* setup checkpoints */
2266 if (!start_ap(gd, boot_addr, smibest)) {
2267 kprintf("\nAP #%d (PHY# %d) failed!\n",
2269 CHECK_PRINT("trace"); /* show checkpoints */
2270 /* better panic as the AP may be running loose */
2271 kprintf("panic y/n? [y] ");
2272 if (cngetc() != 'n')
2275 CHECK_PRINT("trace"); /* show checkpoints */
2277 /* record its version info */
2278 cpu_apic_versions[x] = cpu_apic_versions[0];
2281 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2284 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2285 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2288 ncpus2_shift = shift;
2289 ncpus2 = 1 << shift;
2290 ncpus2_mask = ncpus2 - 1;
2292 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2293 if ((1 << shift) < ncpus)
2295 ncpus_fit = 1 << shift;
2296 ncpus_fit_mask = ncpus_fit - 1;
2298 /* build our map of 'other' CPUs */
2299 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2300 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2301 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2303 /* fill in our (BSP) APIC version */
2304 cpu_apic_versions[0] = lapic->version;
2306 /* restore the warmstart vector */
2307 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2308 outb(CMOS_REG, BIOS_RESET);
2309 outb(CMOS_DATA, mpbiosreason);
2312 * NOTE! The idlestack for the BSP was setup by locore. Finish
2313 * up, clean out the P==V mapping we did earlier.
2317 /* number of APs actually started */
2323 * load the 1st level AP boot code into base memory.
2326 /* targets for relocation */
2327 extern void bigJump(void);
2328 extern void bootCodeSeg(void);
2329 extern void bootDataSeg(void);
2330 extern void MPentry(void);
2331 extern u_int MP_GDT;
2332 extern u_int mp_gdtbase;
2337 install_ap_tramp(u_int boot_addr)
2340 int size = *(int *) ((u_long) & bootMP_size);
2341 u_char *src = (u_char *) ((u_long) bootMP);
2342 u_char *dst = (u_char *) boot_addr + KERNBASE;
2343 u_int boot_base = (u_int) bootMP;
2348 POSTCODE(INSTALL_AP_TRAMP_POST);
2350 for (x = 0; x < size; ++x)
2354 * modify addresses in code we just moved to basemem. unfortunately we
2355 * need fairly detailed info about mpboot.s for this to work. changes
2356 * to mpboot.s might require changes here.
2359 /* boot code is located in KERNEL space */
2360 dst = (u_char *) boot_addr + KERNBASE;
2362 /* modify the lgdt arg */
2363 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2364 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2366 /* modify the ljmp target for MPentry() */
2367 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2368 *dst32 = ((u_int) MPentry - KERNBASE);
2370 /* modify the target for boot code segment */
2371 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2372 dst8 = (u_int8_t *) (dst16 + 1);
2373 *dst16 = (u_int) boot_addr & 0xffff;
2374 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2376 /* modify the target for boot data segment */
2377 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2378 dst8 = (u_int8_t *) (dst16 + 1);
2379 *dst16 = (u_int) boot_addr & 0xffff;
2380 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2386 * This function starts the AP (application processor) identified
2387 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2388 * to accomplish this. This is necessary because of the nuances
2389 * of the different hardware we might encounter. It ain't pretty,
2390 * but it seems to work.
2392 * NOTE: eventually an AP gets to ap_init(), which is called just
2393 * before the AP goes into the LWKT scheduler's idle loop.
2396 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2400 u_long icr_lo, icr_hi;
2402 POSTCODE(START_AP_POST);
2404 /* get the PHYSICAL APIC ID# */
2405 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2407 /* calculate the vector */
2408 vector = (boot_addr >> 12) & 0xff;
2410 /* We don't want anything interfering */
2413 /* Make sure the target cpu sees everything */
2417 * Try to detect when a SMI has occurred, wait up to 200ms.
2419 * If a SMI occurs during an AP reset but before we issue
2420 * the STARTUP command, the AP may brick. To work around
2421 * this problem we hold off doing the AP startup until
2422 * after we have detected the SMI. Hopefully another SMI
2423 * will not occur before we finish the AP startup.
2425 * Retries don't seem to help. SMIs have a window of opportunity
2426 * and if USB->legacy keyboard emulation is enabled in the BIOS
2427 * the interrupt rate can be quite high.
2429 * NOTE: Don't worry about the L1 cache load, it might bloat
2430 * ldelta a little but ndelta will be so huge when the SMI
2431 * occurs the detection logic will still work fine.
2434 set_apic_timer(200000);
2439 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2440 * and running the target CPU. OR this INIT IPI might be latched (P5
2441 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2444 * see apic/apicreg.h for icr bit definitions.
2446 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2450 * Setup the address for the target AP. We can setup
2451 * icr_hi once and then just trigger operations with
2454 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2455 icr_hi |= (physical_cpu << 24);
2456 icr_lo = lapic->icr_lo & 0xfff00000;
2457 lapic->icr_hi = icr_hi;
2460 * Do an INIT IPI: assert RESET
2462 * Use edge triggered mode to assert INIT
2464 lapic->icr_lo = icr_lo | 0x00004500;
2465 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2469 * The spec calls for a 10ms delay but we may have to use a
2470 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2471 * interrupt. We have other loops here too and dividing by 2
2472 * doesn't seem to be enough even after subtracting 350us,
2473 * so we divide by 4.
2475 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2476 * interrupt was detected we use the full 10ms.
2480 else if (smibest < 150 * 4 + 350)
2482 else if ((smibest - 350) / 4 < 10000)
2483 u_sleep((smibest - 350) / 4);
2488 * Do an INIT IPI: deassert RESET
2490 * Use level triggered mode to deassert. It is unclear
2491 * why we need to do this.
2493 lapic->icr_lo = icr_lo | 0x00008500;
2494 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2496 u_sleep(150); /* wait 150us */
2499 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2500 * latched, (P5 bug) this 1st STARTUP would then terminate
2501 * immediately, and the previously started INIT IPI would continue. OR
2502 * the previous INIT IPI has already run. and this STARTUP IPI will
2503 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2506 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2507 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2509 u_sleep(200); /* wait ~200uS */
2512 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2513 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2514 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2515 * recognized after hardware RESET or INIT IPI.
2517 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2518 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2521 /* Resume normal operation */
2524 /* wait for it to start, see ap_init() */
2525 set_apic_timer(5000000);/* == 5 seconds */
2526 while (read_apic_timer()) {
2527 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2528 return 1; /* return SUCCESS */
2531 return 0; /* return FAILURE */
2546 while (read_apic_timer()) {
2548 for (count = 0; count < 100; ++count)
2549 ntsc = rdtsc(); /* force loop to occur */
2551 ndelta = ntsc - ltsc;
2552 if (ldelta > ndelta)
2554 if (ndelta > ldelta * 2)
2557 ldelta = ntsc - ltsc;
2560 return(read_apic_timer());
2564 * Synchronously flush the TLB on all other CPU's. The current cpu's
2565 * TLB is not flushed. If the caller wishes to flush the current cpu's
2566 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2568 * NOTE: If for some reason we were unable to start all cpus we cannot
2569 * safely use broadcast IPIs.
2572 static cpumask_t smp_invltlb_req;
2574 #define SMP_INVLTLB_DEBUG
2580 struct mdglobaldata *md = mdcpu;
2581 #ifdef SMP_INVLTLB_DEBUG
2586 crit_enter_gd(&md->mi);
2587 md->gd_invltlb_ret = 0;
2588 ++md->mi.gd_cnt.v_smpinvltlb;
2589 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2590 #ifdef SMP_INVLTLB_DEBUG
2593 if (smp_startup_mask == smp_active_mask) {
2594 all_but_self_ipi(XINVLTLB_OFFSET);
2596 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2597 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2600 #ifdef SMP_INVLTLB_DEBUG
2602 kprintf("smp_invltlb: ipi sent\n");
2604 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2605 (smp_active_mask & ~md->mi.gd_cpumask)) {
2608 #ifdef SMP_INVLTLB_DEBUG
2610 if (++count == 400000000) {
2611 print_backtrace(-1);
2612 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2613 "rflags %016jx retry",
2614 (long)md->gd_invltlb_ret,
2615 (long)smp_invltlb_req,
2616 (intmax_t)read_rflags());
2617 __asm __volatile ("sti");
2620 lwkt_process_ipiq();
2622 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2623 ~md->mi.gd_cpumask &
2627 kprintf("bcpu %d\n", bcpu);
2628 xgd = globaldata_find(bcpu);
2629 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2632 Debugger("giving up");
2638 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2639 crit_exit_gd(&md->mi);
2646 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2647 * bother to bump the critical section count or nested interrupt count
2648 * so only do very low level operations here.
2651 smp_invltlb_intr(void)
2653 struct mdglobaldata *md = mdcpu;
2654 struct mdglobaldata *omd;
2659 mask = smp_invltlb_req;
2662 cpu = BSFCPUMASK(mask);
2663 mask &= ~CPUMASK(cpu);
2664 omd = (struct mdglobaldata *)globaldata_find(cpu);
2665 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2672 * When called the executing CPU will send an IPI to all other CPUs
2673 * requesting that they halt execution.
2675 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2677 * - Signals all CPUs in map to stop.
2678 * - Waits for each to stop.
2685 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2686 * from executing at same time.
2689 stop_cpus(cpumask_t map)
2691 map &= smp_active_mask;
2693 /* send the Xcpustop IPI to all CPUs in map */
2694 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2696 while ((stopped_cpus & map) != map)
2704 * Called by a CPU to restart stopped CPUs.
2706 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2708 * - Signals all CPUs in map to restart.
2709 * - Waits for each to restart.
2717 restart_cpus(cpumask_t map)
2719 /* signal other cpus to restart */
2720 started_cpus = map & smp_active_mask;
2722 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2729 * This is called once the mpboot code has gotten us properly relocated
2730 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2731 * and when it returns the scheduler will call the real cpu_idle() main
2732 * loop for the idlethread. Interrupts are disabled on entry and should
2733 * remain disabled at return.
2741 * Adjust smp_startup_mask to signal the BSP that we have started
2742 * up successfully. Note that we do not yet hold the BGL. The BSP
2743 * is waiting for our signal.
2745 * We can't set our bit in smp_active_mask yet because we are holding
2746 * interrupts physically disabled and remote cpus could deadlock
2747 * trying to send us an IPI.
2749 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2753 * Interlock for finalization. Wait until mp_finish is non-zero,
2754 * then get the MP lock.
2756 * Note: We are in a critical section.
2758 * Note: we are the idle thread, we can only spin.
2760 * Note: The load fence is memory volatile and prevents the compiler
2761 * from improperly caching mp_finish, and the cpu from improperly
2764 while (mp_finish == 0)
2766 while (try_mplock() == 0)
2769 if (cpu_feature & CPUID_TSC) {
2771 * The BSP is constantly updating tsc0_offset, figure out
2772 * the relative difference to synchronize ktrdump.
2774 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2777 /* BSP may have changed PTD while we're waiting for the lock */
2780 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2784 /* Build our map of 'other' CPUs. */
2785 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2787 kprintf(" %d", mycpu->gd_cpuid);
2789 /* A quick check from sanity claus */
2790 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
2791 if (mycpu->gd_cpuid != apic_id) {
2792 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2793 kprintf("SMP: apic_id = %d lapicid %d\n",
2794 apic_id, (lapic->id & 0xff000000) >> 24);
2796 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2798 panic("cpuid mismatch! boom!!");
2801 /* Initialize AP's local APIC for irq's */
2804 /* Set memory range attributes for this CPU to match the BSP */
2805 mem_range_AP_init();
2808 * Once we go active we must process any IPIQ messages that may
2809 * have been queued, because no actual IPI will occur until we
2810 * set our bit in the smp_active_mask. If we don't the IPI
2811 * message interlock could be left set which would also prevent
2814 * The idle loop doesn't expect the BGL to be held and while
2815 * lwkt_switch() normally cleans things up this is a special case
2816 * because we returning almost directly into the idle loop.
2818 * The idle thread is never placed on the runq, make sure
2819 * nothing we've done put it there.
2821 KKASSERT(get_mplock_count(curthread) == 1);
2822 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2825 * Enable interrupts here. idle_restore will also do it, but
2826 * doing it here lets us clean up any strays that got posted to
2827 * the CPU during the AP boot while we are still in a critical
2830 __asm __volatile("sti; pause; pause"::);
2831 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2833 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2834 lwkt_process_ipiq();
2837 * Releasing the mp lock lets the BSP finish up the SMP init
2840 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2844 * Get SMP fully working before we start initializing devices.
2852 kprintf("Finish MP startup\n");
2853 if (cpu_feature & CPUID_TSC)
2854 tsc0_offset = rdtsc();
2857 while (smp_active_mask != smp_startup_mask) {
2859 if (cpu_feature & CPUID_TSC)
2860 tsc0_offset = rdtsc();
2862 while (try_mplock() == 0)
2866 kprintf("Active CPU Mask: %016jx\n",
2867 (uintmax_t)smp_active_mask);
2871 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2874 cpu_send_ipiq(int dcpu)
2876 if (CPUMASK(dcpu) & smp_active_mask)
2877 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2880 #if 0 /* single_apic_ipi_passive() not working yet */
2882 * Returns 0 on failure, 1 on success
2885 cpu_send_ipiq_passive(int dcpu)
2888 if (CPUMASK(dcpu) & smp_active_mask) {
2889 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2890 APIC_DELMODE_FIXED);
2897 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2899 struct mptable_bus_info *bus_info = xarg;
2900 const struct BUSENTRY *ent;
2901 struct mptable_bus *bus;
2907 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2908 if (bus->mb_id == ent->bus_id) {
2909 kprintf("mptable_bus_info_alloc: duplicated bus id "
2910 "(%d)\n", bus->mb_id);
2916 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2917 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2918 bus->mb_type = MPTABLE_BUS_PCI;
2919 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2920 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2921 bus->mb_type = MPTABLE_BUS_ISA;
2925 bus->mb_id = ent->bus_id;
2926 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2932 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2936 bzero(bus_info, sizeof(*bus_info));
2937 TAILQ_INIT(&bus_info->mbi_list);
2939 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2941 mptable_bus_info_free(bus_info);
2945 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2947 struct mptable_bus *bus;
2949 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2950 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2955 struct mptable_lapic_cbarg1 {
2958 u_int ht_apicid_mask;
2962 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2964 const struct PROCENTRY *ent;
2965 struct mptable_lapic_cbarg1 *arg = xarg;
2971 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2975 if (ent->apic_id < 32) {
2976 arg->ht_apicid_mask |= 1 << ent->apic_id;
2977 } else if (arg->ht_fixup) {
2978 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2984 struct mptable_lapic_cbarg2 {
2991 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2993 const struct PROCENTRY *ent;
2994 struct mptable_lapic_cbarg2 *arg = xarg;
3000 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3001 KKASSERT(!arg->found_bsp);
3005 if (processor_entry(ent, arg->cpu))
3008 if (arg->logical_cpus) {
3009 struct PROCENTRY proc;
3013 * Create fake mptable processor entries
3014 * and feed them to processor_entry() to
3015 * enumerate the logical CPUs.
3017 bzero(&proc, sizeof(proc));
3019 proc.cpu_flags = PROCENTRY_FLAG_EN;
3020 proc.apic_id = ent->apic_id;
3022 for (i = 1; i < arg->logical_cpus; i++) {
3024 processor_entry(&proc, arg->cpu);
3032 mptable_lapic_default(void)
3034 int ap_apicid, bsp_apicid;
3036 mp_naps = 1; /* exclude BSP */
3038 /* Map local apic before the id field is accessed */
3039 lapic_map(DEFAULT_APIC_BASE);
3041 bsp_apicid = APIC_ID(lapic->id);
3042 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3045 mp_set_cpuids(0, bsp_apicid);
3046 /* one and only AP */
3047 mp_set_cpuids(1, ap_apicid);
3053 * ID_TO_CPU(N), APIC ID to logical CPU table
3054 * CPU_TO_ID(N), logical CPU to APIC ID table
3057 mptable_lapic_enumerate(struct lapic_enumerator *e)
3059 struct mptable_pos mpt;
3060 struct mptable_lapic_cbarg1 arg1;
3061 struct mptable_lapic_cbarg2 arg2;
3063 int error, logical_cpus = 0;
3064 vm_offset_t lapic_addr;
3066 if (mptable_use_default) {
3067 mptable_lapic_default();
3071 error = mptable_map(&mpt);
3073 panic("mptable_lapic_enumerate mptable_map failed\n");
3074 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3078 /* Save local apic address */
3079 lapic_addr = (vm_offset_t)cth->apic_address;
3080 KKASSERT(lapic_addr != 0);
3083 * Find out how many CPUs do we have
3085 bzero(&arg1, sizeof(arg1));
3086 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3088 error = mptable_iterate_entries(cth,
3089 mptable_lapic_pass1_callback, &arg1);
3091 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3092 KKASSERT(arg1.cpu_count != 0);
3094 /* See if we need to fixup HT logical CPUs. */
3095 if (arg1.ht_fixup) {
3096 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3098 if (logical_cpus != 0)
3099 arg1.cpu_count *= logical_cpus;
3101 mp_naps = arg1.cpu_count;
3103 /* Qualify the numbers again, after possible HT fixup */
3104 if (mp_naps > MAXCPU) {
3105 kprintf("Warning: only using %d of %d available CPUs!\n",
3111 --mp_naps; /* subtract the BSP */
3114 * Link logical CPU id to local apic id
3116 bzero(&arg2, sizeof(arg2));
3118 arg2.logical_cpus = logical_cpus;
3120 error = mptable_iterate_entries(cth,
3121 mptable_lapic_pass2_callback, &arg2);
3123 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3124 KKASSERT(arg2.found_bsp);
3126 /* Map local apic */
3127 lapic_map(lapic_addr);
3129 mptable_unmap(&mpt);
3132 struct mptable_lapic_probe_cbarg {
3138 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3140 const struct PROCENTRY *ent;
3141 struct mptable_lapic_probe_cbarg *arg = xarg;
3147 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3151 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3152 if (arg->found_bsp) {
3153 kprintf("more than one BSP in base MP table\n");
3162 mptable_lapic_probe(struct lapic_enumerator *e)
3164 struct mptable_pos mpt;
3165 struct mptable_lapic_probe_cbarg arg;
3169 if (mptable_fps_phyaddr == 0)
3172 if (mptable_use_default)
3175 error = mptable_map(&mpt);
3178 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3183 if (cth->apic_address == 0)
3186 bzero(&arg, sizeof(arg));
3187 error = mptable_iterate_entries(cth,
3188 mptable_lapic_probe_callback, &arg);
3190 if (arg.cpu_count == 0) {
3191 kprintf("MP table contains no processor entries\n");
3193 } else if (!arg.found_bsp) {
3194 kprintf("MP table does not contains BSP entry\n");
3199 mptable_unmap(&mpt);
3203 static struct lapic_enumerator mptable_lapic_enumerator = {
3204 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3205 .lapic_probe = mptable_lapic_probe,
3206 .lapic_enumerate = mptable_lapic_enumerate
3210 mptable_lapic_enum_register(void)
3212 lapic_enumerator_register(&mptable_lapic_enumerator);
3214 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3215 mptable_lapic_enum_register, 0);
3218 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
3220 const struct IOAPICENTRY *ent;
3221 struct mptable_ioapic *nioapic, *ioapic;
3227 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3230 if (ent->apic_address == 0) {
3231 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
3235 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3236 if (ioapic->mio_apic_id == ent->apic_id) {
3237 kprintf("mptable_ioapic_create_list: duplicated "
3238 "apic id %d\n", ioapic->mio_apic_id);
3241 if (ioapic->mio_addr == ent->apic_address) {
3242 kprintf("mptable_ioapic_create_list: overlapped "
3243 "IOAPIC addr 0x%08x", ioapic->mio_addr);
3248 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3249 nioapic->mio_apic_id = ent->apic_id;
3250 nioapic->mio_addr = ent->apic_address;
3253 * Create IOAPIC list in ascending order of APIC ID
3255 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
3256 mptable_ioapic_list, mio_link) {
3257 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
3258 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
3259 ioapic, nioapic, mio_link);
3264 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
3270 mptable_ioapic_create_list(void)
3272 struct mptable_ioapic *ioapic;
3273 struct mptable_pos mpt;
3276 if (mptable_fps_phyaddr == 0)
3279 if (mptable_use_default) {
3280 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3281 ioapic->mio_idx = 0;
3282 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
3283 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
3285 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
3289 error = mptable_map(&mpt);
3291 panic("mptable_ioapic_create_list: mptable_map failed\n");
3292 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3294 error = mptable_iterate_entries(mpt.mp_cth,
3295 mptable_ioapic_list_callback, NULL);
3297 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
3298 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
3299 kfree(ioapic, M_DEVBUF);
3305 * Assign index number for each IOAPIC
3308 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3309 ioapic->mio_idx = idx;
3313 mptable_unmap(&mpt);
3315 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
3316 mptable_ioapic_create_list, 0);
3319 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3321 const struct mptable_bus_info *bus_info = xarg;
3322 const struct mptable_ioapic *ioapic;
3323 const struct mptable_bus *bus;
3324 struct mptable_pci_int *pci_int;
3325 const struct INTENTRY *ent;
3326 int pci_pin, pci_dev;
3332 if (ent->int_type != 0)
3335 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3336 if (bus->mb_type == MPTABLE_BUS_PCI &&
3337 bus->mb_id == ent->src_bus_id)
3343 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3344 if (ioapic->mio_apic_id == ent->dst_apic_id)
3347 if (ioapic == NULL) {
3348 kprintf("MPTABLE: warning PCI int dst apic id %d "
3349 "does not exist\n", ent->dst_apic_id);
3353 pci_pin = ent->src_bus_irq & 0x3;
3354 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3356 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3357 if (pci_int->mpci_bus == ent->src_bus_id &&
3358 pci_int->mpci_dev == pci_dev &&
3359 pci_int->mpci_pin == pci_pin) {
3360 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
3361 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3362 kprintf("MPTABLE: warning duplicated "
3363 "PCI int entry for "
3364 "bus %d, dev %d, pin %d\n",
3370 kprintf("mptable_pci_int_register: "
3371 "conflict PCI int entry for "
3372 "bus %d, dev %d, pin %d, "
3373 "IOAPIC %d.%d -> %d.%d\n",
3377 pci_int->mpci_ioapic_idx,
3378 pci_int->mpci_ioapic_pin,
3386 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3388 pci_int->mpci_bus = ent->src_bus_id;
3389 pci_int->mpci_dev = pci_dev;
3390 pci_int->mpci_pin = pci_pin;
3391 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
3392 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3394 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3400 mptable_pci_int_register(void)
3402 struct mptable_bus_info bus_info;
3403 const struct mptable_bus *bus;
3404 struct mptable_pci_int *pci_int;
3405 struct mptable_pos mpt;
3406 int error, force_pci0, npcibus;
3409 if (mptable_fps_phyaddr == 0)
3412 if (mptable_use_default)
3415 if (TAILQ_EMPTY(&mptable_ioapic_list))
3418 error = mptable_map(&mpt);
3420 panic("mptable_pci_int_register: mptable_map failed\n");
3421 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3425 mptable_bus_info_alloc(cth, &bus_info);
3426 if (TAILQ_EMPTY(&bus_info.mbi_list))
3430 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3431 if (bus->mb_type == MPTABLE_BUS_PCI)
3435 mptable_bus_info_free(&bus_info);
3437 } else if (npcibus == 1) {
3441 error = mptable_iterate_entries(cth,
3442 mptable_pci_int_callback, &bus_info);
3444 mptable_bus_info_free(&bus_info);
3447 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3448 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3449 kfree(pci_int, M_DEVBUF);
3455 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3456 pci_int->mpci_bus = 0;
3459 mptable_unmap(&mpt);
3461 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3462 mptable_pci_int_register, 0);
3464 struct mptable_ioapic_probe_cbarg {
3465 const struct mptable_bus_info *bus_info;
3469 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3471 struct mptable_ioapic_probe_cbarg *arg = xarg;
3472 const struct mptable_ioapic *ioapic;
3473 const struct mptable_bus *bus;
3474 const struct INTENTRY *ent;
3480 if (ent->int_type != 0)
3483 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3484 if (bus->mb_type == MPTABLE_BUS_ISA &&
3485 bus->mb_id == ent->src_bus_id)
3491 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3492 if (ioapic->mio_apic_id == ent->dst_apic_id)
3495 if (ioapic == NULL) {
3496 kprintf("MPTABLE: warning ISA int dst apic id %d "
3497 "does not exist\n", ent->dst_apic_id);
3501 /* XXX magic number */
3502 if (ent->src_bus_irq >= 16) {
3503 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
3511 mptable_ioapic_probe(struct ioapic_enumerator *e)
3513 struct mptable_ioapic_probe_cbarg arg;
3514 struct mptable_bus_info bus_info;
3515 struct mptable_pos mpt;
3519 if (mptable_fps_phyaddr == 0)
3522 if (mptable_use_default)
3525 if (TAILQ_EMPTY(&mptable_ioapic_list))
3528 error = mptable_map(&mpt);
3530 panic("mptable_ioapic_probe: mptable_map failed\n");
3531 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3535 mptable_bus_info_alloc(cth, &bus_info);
3537 bzero(&arg, sizeof(arg));
3538 arg.bus_info = &bus_info;
3540 error = mptable_iterate_entries(cth,
3541 mptable_ioapic_probe_callback, &arg);
3543 mptable_bus_info_free(&bus_info);
3544 mptable_unmap(&mpt);
3549 struct mptable_ioapic_int_cbarg {
3550 const struct mptable_bus_info *bus_info;
3555 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3557 struct mptable_ioapic_int_cbarg *arg = xarg;
3558 const struct mptable_ioapic *ioapic;
3559 const struct mptable_bus *bus;
3560 const struct INTENTRY *ent;
3568 if (ent->int_type != 0)
3571 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3572 if (bus->mb_type == MPTABLE_BUS_ISA &&
3573 bus->mb_id == ent->src_bus_id)
3579 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3580 if (ioapic->mio_apic_id == ent->dst_apic_id)
3583 if (ioapic == NULL) {
3584 kprintf("MPTABLE: warning ISA int dst apic id %d "
3585 "does not exist\n", ent->dst_apic_id);
3589 if (!ioapic_use_old) {
3592 if (ent->dst_apic_int >= ioapic->mio_npin) {
3593 panic("mptable_ioapic_enumerate: invalid I/O APIC "
3594 "pin %d, should be < %d",
3595 ent->dst_apic_int, ioapic->mio_npin);
3597 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
3599 if (ent->src_bus_irq != gsi) {
3601 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3602 ent->src_bus_irq, gsi);
3604 ioapic_intsrc(ent->src_bus_irq, gsi);
3607 /* XXX rough estimation */
3608 if (ent->src_bus_irq != ent->dst_apic_int) {
3610 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3611 ent->src_bus_irq, ent->dst_apic_int);
3619 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3621 struct mptable_bus_info bus_info;
3622 struct mptable_ioapic *ioapic;
3623 struct mptable_pos mpt;
3627 KKASSERT(mptable_fps_phyaddr != 0);
3628 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
3630 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3631 if (!ioapic_use_old) {
3632 const struct mptable_ioapic *prev_ioapic;
3636 addr = ioapic_map(ioapic->mio_addr);
3638 ver = ioapic_read(addr, IOAPIC_VER);
3639 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
3640 >> MAXREDIRSHIFT) + 1;
3642 prev_ioapic = TAILQ_PREV(ioapic,
3643 mptable_ioapic_list, mio_link);
3644 if (prev_ioapic == NULL) {
3645 ioapic->mio_gsi_base = 0;
3647 ioapic->mio_gsi_base =
3648 prev_ioapic->mio_gsi_base +
3649 prev_ioapic->mio_npin;
3651 ioapic_add(addr, ioapic->mio_gsi_base,
3655 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
3656 "apic id %d, idx %d, gsi base %d, npin %d\n",
3658 ioapic->mio_apic_id,
3660 ioapic->mio_gsi_base,
3665 if (mptable_use_default) {
3667 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3668 ioapic_intsrc(0, 2);
3672 error = mptable_map(&mpt);
3674 panic("mptable_ioapic_probe: mptable_map failed\n");
3675 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3679 mptable_bus_info_alloc(cth, &bus_info);
3681 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3683 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3684 ioapic_intsrc(0, 2);
3686 struct mptable_ioapic_int_cbarg arg;
3688 bzero(&arg, sizeof(arg));
3689 arg.bus_info = &bus_info;
3691 error = mptable_iterate_entries(cth,
3692 mptable_ioapic_int_callback, &arg);
3694 panic("mptable_ioapic_int failed\n");
3696 if (arg.ioapic_nint == 0) {
3698 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3701 ioapic_intsrc(0, 2);
3705 mptable_bus_info_free(&bus_info);
3707 mptable_unmap(&mpt);
3710 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3711 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3712 .ioapic_probe = mptable_ioapic_probe,
3713 .ioapic_enumerate = mptable_ioapic_enumerate
3717 mptable_ioapic_enum_register(void)
3719 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3721 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3722 mptable_ioapic_enum_register, 0);