2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2008 The DragonFly Project.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
27 * $DragonFly: src/sys/platform/pc64/apic/mpapic.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine_base/apic/mpapic.h>
35 #include <machine/segments.h>
36 #include <sys/thread2.h>
38 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
40 /* EISA Edge/Level trigger control registers */
41 #define ELCR0 0x4d0 /* eisa irq 0-7 */
42 #define ELCR1 0x4d1 /* eisa irq 8-15 */
45 * pointers to pmapped apic hardware.
48 volatile ioapic_t **ioapic;
50 void lapic_timer_fixup(void);
53 * Enable APIC, configure interrupts.
61 * setup LVT1 as ExtINT on the BSP. This is theoretically an
62 * aggregate interrupt input from the 8259. The INTA cycle
63 * will be routed to the external controller (the 8259) which
64 * is expected to supply the vector.
66 * Must be setup edge triggered, active high.
68 * Disable LVT1 on the APs. It doesn't matter what delivery
69 * mode we use because we leave it masked.
71 temp = lapic.lvt_lint0;
72 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
73 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
74 if (mycpu->gd_cpuid == 0)
75 temp |= APIC_LVT_DM_EXTINT;
77 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
78 lapic.lvt_lint0 = temp;
81 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
83 temp = lapic.lvt_lint1;
84 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
85 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
86 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
87 lapic.lvt_lint1 = temp;
90 * Mask the apic error interrupt, apic performance counter
91 * interrupt, and the apic timer interrupt.
93 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
94 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
95 lapic.lvt_timer = lapic.lvt_timer | APIC_LVT_MASKED;
98 * Set the Task Priority Register as needed. At the moment allow
99 * interrupts on all cpus (the APs will remain CLId until they are
100 * ready to deal). We could disable all but IPIs by setting
101 * temp |= TPR_IPI_ONLY for cpu != 0.
104 temp &= ~APIC_TPR_PRIO; /* clear priority field */
107 * If we are NOT running the IO APICs, the LAPIC will only be used
108 * for IPIs. Set the TPR to prevent any unintentional interrupts.
110 temp |= TPR_IPI_ONLY;
116 * enable the local APIC
119 temp |= APIC_SVR_ENABLE; /* enable the APIC */
120 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
123 * Set the spurious interrupt vector. The low 4 bits of the vector
126 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
127 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
128 temp &= ~APIC_SVR_VECTOR;
129 temp |= XSPURIOUSINT_OFFSET;
134 * Pump out a few EOIs to clean out interrupts that got through
135 * before we were able to set the TPR.
142 apic_dump("apic_initialize()");
146 lapic_timer_fixup(void)
152 * dump contents of local APIC registers
157 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
158 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
159 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
169 #define IOAPIC_ISA_INTS 16
170 #define REDIRCNT_IOAPIC(A) \
171 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
173 static int trigger (int apic, int pin, u_int32_t * flags);
174 static void polarity (int apic, int pin, u_int32_t * flags, int level);
176 #define DEFAULT_FLAGS \
182 #define DEFAULT_ISA_FLAGS \
191 io_apic_set_id(int apic, int id)
195 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
196 if (((ux & APIC_ID_MASK) >> 24) != id) {
197 kprintf("Changing APIC ID for IO APIC #%d"
198 " from %d to %d on chip\n",
199 apic, ((ux & APIC_ID_MASK) >> 24), id);
200 ux &= ~APIC_ID_MASK; /* clear the ID field */
202 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
203 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
204 if (((ux & APIC_ID_MASK) >> 24) != id)
205 panic("can't control IO APIC #%d ID, reg: 0x%08x",
212 io_apic_get_id(int apic)
214 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
223 extern int apic_pin_trigger; /* 'opaque' */
226 io_apic_setup_intpin(int apic, int pin)
228 int bus, bustype, irq;
229 u_char select; /* the select register is 8 bits */
230 u_int32_t flags; /* the window register is 32 bits */
231 u_int32_t target; /* the window register is 32 bits */
232 u_int32_t vector; /* the window register is 32 bits */
235 select = pin * 2 + IOAPIC_REDTBL0; /* register */
238 * Always clear an IO APIC pin before [re]programming it. This is
239 * particularly important if the pin is set up for a level interrupt
240 * as the IOART_REM_IRR bit might be set. When we reprogram the
241 * vector any EOI from pending ints on this pin could be lost and
242 * IRR might never get reset.
244 * To fix this problem, clear the vector and make sure it is
245 * programmed as an edge interrupt. This should theoretically
246 * clear IRR so we can later, safely program it as a level
251 flags = io_apic_read(apic, select) & IOART_RESV;
252 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
253 flags |= IOART_DESTPHY | IOART_DELFIXED;
255 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
256 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
260 io_apic_write(apic, select, flags | vector);
261 io_apic_write(apic, select + 1, target);
266 * We only deal with vectored interrupts here. ? documentation is
267 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
270 * This test also catches unconfigured pins.
272 if (apic_int_type(apic, pin) != 0)
276 * Leave the pin unprogrammed if it does not correspond to
279 irq = apic_irq(apic, pin);
283 /* determine the bus type for this pin */
284 bus = apic_src_bus_id(apic, pin);
287 bustype = apic_bus_type(bus);
289 if ((bustype == ISA) &&
290 (pin < IOAPIC_ISA_INTS) &&
292 (apic_polarity(apic, pin) == 0x1) &&
293 (apic_trigger(apic, pin) == 0x3)) {
295 * A broken BIOS might describe some ISA
296 * interrupts as active-high level-triggered.
297 * Use default ISA flags for those interrupts.
299 flags = DEFAULT_ISA_FLAGS;
302 * Program polarity and trigger mode according to
305 flags = DEFAULT_FLAGS;
306 level = trigger(apic, pin, &flags);
308 apic_pin_trigger |= (1 << irq);
309 polarity(apic, pin, &flags, level);
313 kprintf("IOAPIC #%d intpin %d -> irq %d\n",
318 * Program the appropriate registers. This routing may be
319 * overridden when an interrupt handler for a device is
320 * actually added (see register_int(), which calls through
321 * the MACHINTR ABI to set up an interrupt handler/vector).
323 * The order in which we must program the two registers for
324 * safety is unclear! XXX
328 vector = IDT_OFFSET + irq; /* IDT vec */
329 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
330 target |= IOART_HI_DEST_BROADCAST;
331 flags |= io_apic_read(apic, select) & IOART_RESV;
332 io_apic_write(apic, select, flags | vector);
333 io_apic_write(apic, select + 1, target);
339 io_apic_setup(int apic)
345 apic_pin_trigger = 0; /* default to edge-triggered */
347 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
348 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
350 for (pin = 0; pin < maxpin; ++pin) {
351 io_apic_setup_intpin(apic, pin);
354 if (apic_int_type(apic, pin) >= 0) {
355 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
356 " cannot program!\n", apic, pin);
361 /* return GOOD status */
364 #undef DEFAULT_ISA_FLAGS
368 #define DEFAULT_EXTINT_FLAGS \
377 * Setup the source of External INTerrupts.
380 ext_int_setup(int apic, int intr)
382 u_char select; /* the select register is 8 bits */
383 u_int32_t flags; /* the window register is 32 bits */
384 u_int32_t target; /* the window register is 32 bits */
385 u_int32_t vector; /* the window register is 32 bits */
387 if (apic_int_type(apic, intr) != 3)
390 target = IOART_HI_DEST_BROADCAST;
391 select = IOAPIC_REDTBL0 + (2 * intr);
392 vector = IDT_OFFSET + intr;
393 flags = DEFAULT_EXTINT_FLAGS;
395 io_apic_write(apic, select, flags | vector);
396 io_apic_write(apic, select + 1, target);
400 #undef DEFAULT_EXTINT_FLAGS
404 * Set the trigger level for an IO APIC pin.
407 trigger(int apic, int pin, u_int32_t * flags)
412 static int intcontrol = -1;
414 switch (apic_trigger(apic, pin)) {
420 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
424 *flags |= IOART_TRGRLVL;
432 if ((id = apic_src_bus_id(apic, pin)) == -1)
435 switch (apic_bus_type(id)) {
437 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
441 eirq = apic_src_bus_irq(apic, pin);
443 if (eirq < 0 || eirq > 15) {
444 kprintf("EISA IRQ %d?!?!\n", eirq);
448 if (intcontrol == -1) {
449 intcontrol = inb(ELCR1) << 8;
450 intcontrol |= inb(ELCR0);
451 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
454 /* Use ELCR settings to determine level or edge mode */
455 level = (intcontrol >> eirq) & 1;
458 * Note that on older Neptune chipset based systems, any
459 * pci interrupts often show up here and in the ELCR as well
460 * as level sensitive interrupts attributed to the EISA bus.
464 *flags |= IOART_TRGRLVL;
466 *flags &= ~IOART_TRGRLVL;
471 *flags |= IOART_TRGRLVL;
480 panic("bad APIC IO INT flags");
485 * Set the polarity value for an IO APIC pin.
488 polarity(int apic, int pin, u_int32_t * flags, int level)
492 switch (apic_polarity(apic, pin)) {
498 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
502 *flags |= IOART_INTALO;
510 if ((id = apic_src_bus_id(apic, pin)) == -1)
513 switch (apic_bus_type(id)) {
515 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
519 /* polarity converter always gives active high */
520 *flags &= ~IOART_INTALO;
524 *flags |= IOART_INTALO;
533 panic("bad APIC IO INT flags");
538 * Print contents of apic_imen.
540 extern u_int apic_imen; /* keep apic_imen 'opaque' */
546 kprintf("SMP: enabled INTs: ");
547 for (x = 0; x < 24; ++x)
548 if ((apic_imen & (1 << x)) == 0)
550 kprintf("apic_imen: 0x%08x\n", apic_imen);
555 * Inter Processor Interrupt functions.
561 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
563 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
564 * vector is any valid SYSTEM INT vector
565 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
567 * A backlog of requests can create a deadlock between cpus. To avoid this
568 * we have to be able to accept IPIs at the same time we are trying to send
569 * them. The critical section prevents us from attempting to send additional
570 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
571 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
572 * to occur but fortunately it does not happen too often.
575 apic_ipi(int dest_type, int vector, int delivery_mode)
580 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
581 unsigned int eflags = read_eflags();
583 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
586 write_eflags(eflags);
589 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
590 delivery_mode | vector;
591 lapic.icr_lo = icr_lo;
597 single_apic_ipi(int cpu, int vector, int delivery_mode)
603 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
604 unsigned int eflags = read_eflags();
606 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
609 write_eflags(eflags);
611 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
612 icr_hi |= (CPU_TO_ID(cpu) << 24);
613 lapic.icr_hi = icr_hi;
616 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
617 | APIC_DEST_DESTFLD | delivery_mode | vector;
620 lapic.icr_lo = icr_lo;
627 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
629 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
630 * to the target, and the scheduler does not 'poll' for IPI messages.
633 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
639 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
643 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
644 icr_hi |= (CPU_TO_ID(cpu) << 24);
645 lapic.icr_hi = icr_hi;
648 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
649 | APIC_DEST_DESTFLD | delivery_mode | vector;
652 lapic.icr_lo = icr_lo;
660 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
662 * target is a bitmask of destination cpus. Vector is any
663 * valid system INT vector. Delivery mode may be either
664 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
667 selected_apic_ipi(u_int target, int vector, int delivery_mode)
671 int n = bsfl(target);
673 single_apic_ipi(n, vector, delivery_mode);
679 * Timer code, in development...
680 * - suggested by rgrimes@gndrsh.aac.dev.com
683 /** XXX FIXME: temp hack till we can determin bus clock */
685 #define BUS_CLOCK 66000000
686 #define bus_clock() 66000000
690 int acquire_apic_timer (void);
691 int release_apic_timer (void);
694 * Acquire the APIC timer for exclusive use.
697 acquire_apic_timer(void)
702 /** XXX FIXME: make this really do something */
703 panic("APIC timer in use when attempting to acquire");
709 * Return the APIC timer.
712 release_apic_timer(void)
717 /** XXX FIXME: make this really do something */
718 panic("APIC timer was already released");
725 * Load a 'downcount time' in uSeconds.
728 set_apic_timer(int value)
731 long ticks_per_microsec;
734 * Calculate divisor and count from value:
736 * timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128]
737 * value == time in uS
739 lapic.dcr_timer = APIC_TDCR_1;
740 ticks_per_microsec = bus_clock() / 1000000;
742 /* configure timer as one-shot */
743 lvtt = lapic.lvt_timer;
744 lvtt &= ~(APIC_LVTT_VECTOR | APIC_LVTT_DS);
745 lvtt &= ~(APIC_LVTT_PERIODIC);
746 lvtt |= APIC_LVTT_MASKED; /* no INT, one-shot */
747 lapic.lvt_timer = lvtt;
750 lapic.icr_timer = value * ticks_per_microsec;
755 * Read remaining time in timer.
758 read_apic_timer(void)
761 /** XXX FIXME: we need to return the actual remaining time,
762 * for now we just return the remaining count.
765 return lapic.ccr_timer;
771 * Spin-style delay, set delay time in uS, spin till it drains.
776 set_apic_timer(count);
777 while (read_apic_timer())