2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.4 2003/07/06 21:23:48 dillon Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <machine/smptests.h> /** TEST_TEST1, GRAB_LOPRIO */
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/mpapic.h>
35 #include <machine/segments.h>
37 #include <i386/isa/intr_machdep.h> /* Xspuriousint() */
39 /* EISA Edge/Level trigger control registers */
40 #define ELCR0 0x4d0 /* eisa irq 0-7 */
41 #define ELCR1 0x4d1 /* eisa irq 8-15 */
44 * pointers to pmapped apic hardware.
48 volatile ioapic_t **ioapic;
52 * Enable APIC, configure interrupts.
59 /* setup LVT1 as ExtINT */
60 temp = lapic.lvt_lint0;
61 temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM);
62 if (mycpu->gd_cpuid == 0)
63 temp |= 0x00000700; /* process ExtInts */
65 temp |= 0x00010700; /* mask ExtInts */
66 lapic.lvt_lint0 = temp;
68 /* setup LVT2 as NMI, masked till later... */
69 temp = lapic.lvt_lint1;
70 temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM);
71 temp |= 0x00010400; /* masked, edge trigger, active hi */
72 lapic.lvt_lint1 = temp;
74 /* set the Task Priority Register as needed */
76 temp &= ~APIC_TPR_PRIO; /* clear priority field */
79 * Leave the BSP and TPR 0 during boot so it gets all the interrupts,
80 * set APs at TPR 0xF0 at boot so they get no ints.
82 if (mycpu->gd_cpuid != 0)
83 temp |= TPR_IPI_ONLY; /* disable INTs on this cpu */
86 /* enable the local APIC */
88 temp |= APIC_SVR_SWEN; /* software enable APIC */
89 temp &= ~APIC_SVR_FOCUS; /* enable 'focus processor' */
91 /* set the 'spurious INT' vector */
92 if ((XSPURIOUSINT_OFFSET & APIC_SVR_VEC_FIX) != APIC_SVR_VEC_FIX)
93 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
94 temp &= ~APIC_SVR_VEC_PROG; /* clear (programmable) vector field */
95 temp |= (XSPURIOUSINT_OFFSET & APIC_SVR_VEC_PROG);
97 #if defined(TEST_TEST1)
98 if (cpuid == GUARD_CPU) {
99 temp &= ~APIC_SVR_SWEN; /* software DISABLE APIC */
101 #endif /** TEST_TEST1 */
106 apic_dump("apic_initialize()");
111 * dump contents of local APIC registers
116 printf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
117 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
118 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
128 #define IOAPIC_ISA_INTS 16
129 #define REDIRCNT_IOAPIC(A) \
130 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
132 static int trigger __P((int apic, int pin, u_int32_t * flags));
133 static void polarity __P((int apic, int pin, u_int32_t * flags, int level));
135 #define DEFAULT_FLAGS \
141 #define DEFAULT_ISA_FLAGS \
150 io_apic_set_id(int apic, int id)
154 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
155 if (((ux & APIC_ID_MASK) >> 24) != id) {
156 printf("Changing APIC ID for IO APIC #%d"
157 " from %d to %d on chip\n",
158 apic, ((ux & APIC_ID_MASK) >> 24), id);
159 ux &= ~APIC_ID_MASK; /* clear the ID field */
161 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
162 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
163 if (((ux & APIC_ID_MASK) >> 24) != id)
164 panic("can't control IO APIC #%d ID, reg: 0x%08x",
171 io_apic_get_id(int apic)
173 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
182 extern int apic_pin_trigger; /* 'opaque' */
185 io_apic_setup_intpin(int apic, int pin)
187 int bus, bustype, irq;
188 u_char select; /* the select register is 8 bits */
189 u_int32_t flags; /* the window register is 32 bits */
190 u_int32_t target; /* the window register is 32 bits */
191 u_int32_t vector; /* the window register is 32 bits */
196 select = pin * 2 + IOAPIC_REDTBL0; /* register */
198 * Always disable interrupts, and by default map
199 * pin X to IRQX because the disable doesn't stick
200 * and the uninitialize vector will get translated
203 * This is correct for IRQs 1 and 3-15. In the other cases,
204 * any robust driver will handle the spurious interrupt, and
205 * the effective NOP beats a panic.
207 * A dedicated "bogus interrupt" entry in the IDT would
208 * be a nicer hack, although some one should find out
209 * why some systems are generating interrupts when they
210 * shouldn't and stop the carnage.
212 vector = NRSVIDT + pin; /* IDT vec */
214 io_apic_write(apic, select,
215 (io_apic_read(apic, select) & ~IOART_INTMASK
216 & ~0xff)|IOART_INTMSET|vector);
219 /* we only deal with vectored INTs here */
220 if (apic_int_type(apic, pin) != 0)
223 irq = apic_irq(apic, pin);
227 /* determine the bus type for this pin */
228 bus = apic_src_bus_id(apic, pin);
231 bustype = apic_bus_type(bus);
233 if ((bustype == ISA) &&
234 (pin < IOAPIC_ISA_INTS) &&
236 (apic_polarity(apic, pin) == 0x1) &&
237 (apic_trigger(apic, pin) == 0x3)) {
239 * A broken BIOS might describe some ISA
240 * interrupts as active-high level-triggered.
241 * Use default ISA flags for those interrupts.
243 flags = DEFAULT_ISA_FLAGS;
246 * Program polarity and trigger mode according to
249 flags = DEFAULT_FLAGS;
250 level = trigger(apic, pin, &flags);
252 apic_pin_trigger |= (1 << irq);
253 polarity(apic, pin, &flags, level);
256 /* program the appropriate registers */
257 if (apic != 0 || pin != irq)
258 printf("IOAPIC #%d intpin %d -> irq %d\n",
260 vector = NRSVIDT + irq; /* IDT vec */
262 io_apic_write(apic, select, flags | vector);
263 io_apic_write(apic, select + 1, target);
268 io_apic_setup(int apic)
274 apic_pin_trigger = 0; /* default to edge-triggered */
276 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
277 printf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
279 for (pin = 0; pin < maxpin; ++pin) {
280 io_apic_setup_intpin(apic, pin);
283 /* return GOOD status */
286 #undef DEFAULT_ISA_FLAGS
290 #define DEFAULT_EXTINT_FLAGS \
299 * Setup the source of External INTerrupts.
302 ext_int_setup(int apic, int intr)
304 u_char select; /* the select register is 8 bits */
305 u_int32_t flags; /* the window register is 32 bits */
306 u_int32_t target; /* the window register is 32 bits */
307 u_int32_t vector; /* the window register is 32 bits */
309 if (apic_int_type(apic, intr) != 3)
313 select = IOAPIC_REDTBL0 + (2 * intr);
314 vector = NRSVIDT + intr;
315 flags = DEFAULT_EXTINT_FLAGS;
317 io_apic_write(apic, select, flags | vector);
318 io_apic_write(apic, select + 1, target);
322 #undef DEFAULT_EXTINT_FLAGS
326 * Set the trigger level for an IO APIC pin.
329 trigger(int apic, int pin, u_int32_t * flags)
334 static int intcontrol = -1;
336 switch (apic_trigger(apic, pin)) {
342 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
346 *flags |= IOART_TRGRLVL;
354 if ((id = apic_src_bus_id(apic, pin)) == -1)
357 switch (apic_bus_type(id)) {
359 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
363 eirq = apic_src_bus_irq(apic, pin);
365 if (eirq < 0 || eirq > 15) {
366 printf("EISA IRQ %d?!?!\n", eirq);
370 if (intcontrol == -1) {
371 intcontrol = inb(ELCR1) << 8;
372 intcontrol |= inb(ELCR0);
373 printf("EISA INTCONTROL = %08x\n", intcontrol);
376 /* Use ELCR settings to determine level or edge mode */
377 level = (intcontrol >> eirq) & 1;
380 * Note that on older Neptune chipset based systems, any
381 * pci interrupts often show up here and in the ELCR as well
382 * as level sensitive interrupts attributed to the EISA bus.
386 *flags |= IOART_TRGRLVL;
388 *flags &= ~IOART_TRGRLVL;
393 *flags |= IOART_TRGRLVL;
402 panic("bad APIC IO INT flags");
407 * Set the polarity value for an IO APIC pin.
410 polarity(int apic, int pin, u_int32_t * flags, int level)
414 switch (apic_polarity(apic, pin)) {
420 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
424 *flags |= IOART_INTALO;
432 if ((id = apic_src_bus_id(apic, pin)) == -1)
435 switch (apic_bus_type(id)) {
437 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
441 /* polarity converter always gives active high */
442 *flags &= ~IOART_INTALO;
446 *flags |= IOART_INTALO;
455 panic("bad APIC IO INT flags");
460 * Print contents of apic_imen.
462 extern u_int apic_imen; /* keep apic_imen 'opaque' */
468 printf("SMP: enabled INTs: ");
469 for (x = 0; x < 24; ++x)
470 if ((apic_imen & (1 << x)) == 0)
472 printf("apic_imen: 0x%08x\n", apic_imen);
477 * Inter Processor Interrupt functions.
482 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
484 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
485 * vector is any valid SYSTEM INT vector
486 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
488 #define DETECT_DEADLOCK
490 apic_ipi(int dest_type, int vector, int delivery_mode)
494 #if defined(DETECT_DEADLOCK)
495 #define MAX_SPIN1 10000000
496 #define MAX_SPIN2 1000
499 /* "lazy delivery", ie we only barf if they stack up on us... */
500 for (x = MAX_SPIN1; x; --x) {
501 if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
505 panic("apic_ipi was stuck");
506 #endif /* DETECT_DEADLOCK */
509 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
510 | dest_type | delivery_mode | vector;
513 lapic.icr_lo = icr_lo;
515 /* wait for pending status end */
516 #if defined(DETECT_DEADLOCK)
517 for (x = MAX_SPIN2; x; --x) {
518 if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
521 #ifdef needsattention
524 * The above loop waits for the message to actually be delivered.
525 * It breaks out after an arbitrary timout on the theory that it eventually
526 * will be delivered and we will catch a real failure on the next entry to
527 * this function, which would panic().
528 * We could skip this wait entirely, EXCEPT it probably protects us from
529 * other "less robust" routines that assume the message was delivered and
530 * acted upon when this function returns. TLB shootdowns are one such
531 * "less robust" function.
534 printf("apic_ipi might be stuck\n");
539 while (lapic.icr_lo & APIC_DELSTAT_MASK)
541 #endif /* DETECT_DEADLOCK */
543 /** XXX FIXME: return result */
548 apic_ipi_singledest(int cpu, int vector, int delivery_mode)
554 #if defined(DETECT_DEADLOCK)
555 #define MAX_SPIN1 10000000
556 #define MAX_SPIN2 1000
559 /* "lazy delivery", ie we only barf if they stack up on us... */
560 for (x = MAX_SPIN1; x; --x) {
561 if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
565 panic("apic_ipi was stuck");
566 #endif /* DETECT_DEADLOCK */
568 eflags = read_eflags();
569 __asm __volatile("cli" : : : "memory");
570 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
571 icr_hi |= (CPU_TO_ID(cpu) << 24);
572 lapic.icr_hi = icr_hi;
575 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
576 | APIC_DEST_DESTFLD | delivery_mode | vector;
579 lapic.icr_lo = icr_lo;
580 write_eflags(eflags);
582 /* wait for pending status end */
583 #if defined(DETECT_DEADLOCK)
584 for (x = MAX_SPIN2; x; --x) {
585 if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
588 #ifdef needsattention
591 * The above loop waits for the message to actually be delivered.
592 * It breaks out after an arbitrary timout on the theory that it eventually
593 * will be delivered and we will catch a real failure on the next entry to
594 * this function, which would panic().
595 * We could skip this wait entirely, EXCEPT it probably protects us from
596 * other "less robust" routines that assume the message was delivered and
597 * acted upon when this function returns. TLB shootdowns are one such
598 * "less robust" function.
601 printf("apic_ipi might be stuck\n");
606 while (lapic.icr_lo & APIC_DELSTAT_MASK)
608 #endif /* DETECT_DEADLOCK */
610 /** XXX FIXME: return result */
616 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
618 * target contains a bitfield with a bit set for selected APICs.
619 * vector is any valid SYSTEM INT vector
620 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
623 selected_apic_ipi(u_int target, int vector, int delivery_mode)
628 if (target & ~0x7fff)
629 return -1; /* only 15 targets allowed */
631 for (status = 0, x = 0; x <= 14; ++x)
632 if (target & (1 << x)) {
635 if (apic_ipi_singledest(x, vector,
636 delivery_mode) == -1)
645 * Send an IPI INTerrupt containing 'vector' to CPU 'target'
646 * NOTE: target is a LOGICAL APIC ID
649 selected_proc_ipi(int target, int vector)
654 /* write the destination field for the target AP */
655 icr_hi = (lapic.icr_hi & ~APIC_ID_MASK) |
656 (cpu_num_to_apic_id[target] << 24);
657 lapic.icr_hi = icr_hi;
660 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) |
661 APIC_DEST_DESTFLD | APIC_DELMODE_FIXED | vector;
662 lapic.icr_lo = icr_lo;
664 /* wait for pending status end */
665 while (lapic.icr_lo & APIC_DELSTAT_MASK)
668 return 0; /** XXX FIXME: return result */
676 * Timer code, in development...
677 * - suggested by rgrimes@gndrsh.aac.dev.com
680 /** XXX FIXME: temp hack till we can determin bus clock */
682 #define BUS_CLOCK 66000000
683 #define bus_clock() 66000000
687 int acquire_apic_timer __P((void));
688 int release_apic_timer __P((void));
691 * Acquire the APIC timer for exclusive use.
694 acquire_apic_timer(void)
699 /** XXX FIXME: make this really do something */
700 panic("APIC timer in use when attempting to aquire");
706 * Return the APIC timer.
709 release_apic_timer(void)
714 /** XXX FIXME: make this really do something */
715 panic("APIC timer was already released");
722 * Load a 'downcount time' in uSeconds.
725 set_apic_timer(int value)
728 long ticks_per_microsec;
731 * Calculate divisor and count from value:
733 * timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128]
734 * value == time in uS
736 lapic.dcr_timer = APIC_TDCR_1;
737 ticks_per_microsec = bus_clock() / 1000000;
739 /* configure timer as one-shot */
740 lvtt = lapic.lvt_timer;
741 lvtt &= ~(APIC_LVTT_VECTOR | APIC_LVTT_DS | APIC_LVTT_M | APIC_LVTT_TM);
742 lvtt |= APIC_LVTT_M; /* no INT, one-shot */
743 lapic.lvt_timer = lvtt;
746 lapic.icr_timer = value * ticks_per_microsec;
751 * Read remaining time in timer.
754 read_apic_timer(void)
757 /** XXX FIXME: we need to return the actual remaining time,
758 * for now we just return the remaining count.
761 return lapic.ccr_timer;
767 * Spin-style delay, set delay time in uS, spin till it drains.
772 set_apic_timer(count);
773 while (read_apic_timer())