1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const insn_template *start;
101 const insn_template *end;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c);
147 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
149 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS *);
154 static int i386_intel_parse_name (const char *, expressionS *);
155 static const reg_entry *parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const insn_template *match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry *build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS *, offsetT);
174 static void output_disp (fragS *, offsetT);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED);
182 static const char *default_arch = DEFAULT_ARCH;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry *regs;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types[MAX_OPERANDS];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op[MAX_OPERANDS];
229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry *seg[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
262 typedef struct _i386_insn i386_insn;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_DragonFly) \
282 && !defined (TE_NetBSD)))
283 /* This array holds the chars that always start a comment. If the
284 pre-processor is disabled, these aren't very useful. The option
285 --divide will remove '/' from this list. */
286 const char *i386_comment_chars = "#/";
287 #define SVR4_COMMENT_CHARS 1
288 #define PREFIX_SEPARATOR '\\'
291 const char *i386_comment_chars = "#";
292 #define PREFIX_SEPARATOR '/'
295 /* This array holds the chars that only start a comment at the beginning of
296 a line. If the line seems to have the form '# 123 filename'
297 .line and .file directives will appear in the pre-processed output.
298 Note that input_file.c hand checks for '#' at the beginning of the
299 first line of the input file. This is because the compiler outputs
300 #NO_APP at the beginning of its output.
301 Also note that comments started like this one will always work if
302 '/' isn't otherwise defined. */
303 const char line_comment_chars[] = "#/";
305 const char line_separator_chars[] = ";";
307 /* Chars that can be used to separate mant from exp in floating point
309 const char EXP_CHARS[] = "eE";
311 /* Chars that mean this number is a floating point constant
314 const char FLT_CHARS[] = "fFdDxX";
316 /* Tables for lexical analysis. */
317 static char mnemonic_chars[256];
318 static char register_chars[256];
319 static char operand_chars[256];
320 static char identifier_chars[256];
321 static char digit_chars[256];
323 /* Lexical macros. */
324 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
325 #define is_operand_char(x) (operand_chars[(unsigned char) x])
326 #define is_register_char(x) (register_chars[(unsigned char) x])
327 #define is_space_char(x) ((x) == ' ')
328 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
329 #define is_digit_char(x) (digit_chars[(unsigned char) x])
331 /* All non-digit non-letter characters that may occur in an operand. */
332 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
334 /* md_assemble() always leaves the strings it's passed unaltered. To
335 effect this we maintain a stack of saved characters that we've smashed
336 with '\0's (indicating end of strings for various sub-fields of the
337 assembler instruction). */
338 static char save_stack[32];
339 static char *save_stack_p;
340 #define END_STRING_AND_SAVE(s) \
341 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
342 #define RESTORE_END_STRING(s) \
343 do { *(s) = *--save_stack_p; } while (0)
345 /* The instruction we're assembling. */
348 /* Possible templates for current insn. */
349 static const templates *current_templates;
351 /* Per instruction expressionS buffers: max displacements & immediates. */
352 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
353 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
355 /* Current operand we are working on. */
356 static int this_operand = -1;
358 /* We support four different modes. FLAG_CODE variable is used to distinguish
366 static enum flag_code flag_code;
367 static unsigned int object_64bit;
368 static int use_rela_relocations = 0;
370 /* The names used to print error messages. */
371 static const char *flag_code_names[] =
378 /* 1 for intel syntax,
380 static int intel_syntax = 0;
382 /* 1 for intel mnemonic,
383 0 if att mnemonic. */
384 static int intel_mnemonic = !SYSV386_COMPAT;
386 /* 1 if support old (<= 2.8.1) versions of gcc. */
387 static int old_gcc = OLDGCC_COMPAT;
389 /* 1 if pseudo registers are permitted. */
390 static int allow_pseudo_reg = 0;
392 /* 1 if register prefix % not required. */
393 static int allow_naked_reg = 0;
395 /* 1 if pseudo index register, eiz/riz, is allowed . */
396 static int allow_index_reg = 0;
406 /* Register prefix used for error message. */
407 static const char *register_prefix = "%";
409 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
410 leave, push, and pop instructions so that gcc has the same stack
411 frame as in 32 bit mode. */
412 static char stackop_size = '\0';
414 /* Non-zero to optimize code alignment. */
415 int optimize_align_code = 1;
417 /* Non-zero to quieten some warnings. */
418 static int quiet_warnings = 0;
421 static const char *cpu_arch_name = NULL;
422 static char *cpu_sub_arch_name = NULL;
424 /* CPU feature flags. */
425 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
427 /* If we have selected a cpu we are generating instructions for. */
428 static int cpu_arch_tune_set = 0;
430 /* Cpu we are generating instructions for. */
431 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
433 /* CPU feature flags of cpu we are generating instructions for. */
434 static i386_cpu_flags cpu_arch_tune_flags;
436 /* CPU instruction set architecture used. */
437 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
439 /* CPU feature flags of instruction set architecture used. */
440 i386_cpu_flags cpu_arch_isa_flags;
442 /* If set, conditional jumps are not automatically promoted to handle
443 larger than a byte offset. */
444 static unsigned int no_cond_jump_promotion = 0;
446 /* Encode SSE instructions with VEX prefix. */
447 static unsigned int sse2avx;
449 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
450 static symbolS *GOT_symbol;
452 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
453 unsigned int x86_dwarf2_return_column;
455 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
456 int x86_cie_data_alignment;
458 /* Interface to relax_segment.
459 There are 3 major relax states for 386 jump insns because the
460 different types of jumps add different sizes to frags when we're
461 figuring out what sort of jump to choose to reach a given label. */
464 #define UNCOND_JUMP 0
466 #define COND_JUMP86 2
471 #define SMALL16 (SMALL | CODE16)
473 #define BIG16 (BIG | CODE16)
477 #define INLINE __inline__
483 #define ENCODE_RELAX_STATE(type, size) \
484 ((relax_substateT) (((type) << 2) | (size)))
485 #define TYPE_FROM_RELAX_STATE(s) \
487 #define DISP_SIZE_FROM_RELAX_STATE(s) \
488 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
490 /* This table is used by relax_frag to promote short jumps to long
491 ones where necessary. SMALL (short) jumps may be promoted to BIG
492 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
493 don't allow a short jump in a 32 bit code segment to be promoted to
494 a 16 bit offset jump because it's slower (requires data size
495 prefix), and doesn't work, unless the destination is in the bottom
496 64k of the code segment (The top 16 bits of eip are zeroed). */
498 const relax_typeS md_relax_table[] =
501 1) most positive reach of this state,
502 2) most negative reach of this state,
503 3) how many bytes this mode will have in the variable part of the frag
504 4) which index into the table to try if we can't fit into this one. */
506 /* UNCOND_JUMP states. */
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
508 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
509 /* dword jmp adds 4 bytes to frag:
510 0 extra opcode bytes, 4 displacement bytes. */
512 /* word jmp adds 2 byte2 to frag:
513 0 extra opcode bytes, 2 displacement bytes. */
516 /* COND_JUMP states. */
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
518 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
519 /* dword conditionals adds 5 bytes to frag:
520 1 extra opcode byte, 4 displacement bytes. */
522 /* word conditionals add 3 bytes to frag:
523 1 extra opcode byte, 2 displacement bytes. */
526 /* COND_JUMP86 states. */
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
528 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
529 /* dword conditionals adds 5 bytes to frag:
530 1 extra opcode byte, 4 displacement bytes. */
532 /* word conditionals add 4 bytes to frag:
533 1 displacement byte and a 3 byte long branch insn. */
537 static const arch_entry cpu_arch[] =
539 { "generic32", PROCESSOR_GENERIC32,
540 CPU_GENERIC32_FLAGS },
541 { "generic64", PROCESSOR_GENERIC64,
542 CPU_GENERIC64_FLAGS },
543 { "i8086", PROCESSOR_UNKNOWN,
545 { "i186", PROCESSOR_UNKNOWN,
547 { "i286", PROCESSOR_UNKNOWN,
549 { "i386", PROCESSOR_I386,
551 { "i486", PROCESSOR_I486,
553 { "i586", PROCESSOR_PENTIUM,
555 { "i686", PROCESSOR_PENTIUMPRO,
557 { "pentium", PROCESSOR_PENTIUM,
559 { "pentiumpro", PROCESSOR_PENTIUMPRO,
561 { "pentiumii", PROCESSOR_PENTIUMPRO,
563 { "pentiumiii",PROCESSOR_PENTIUMPRO,
565 { "pentium4", PROCESSOR_PENTIUM4,
567 { "prescott", PROCESSOR_NOCONA,
569 { "nocona", PROCESSOR_NOCONA,
571 { "yonah", PROCESSOR_CORE,
573 { "core", PROCESSOR_CORE,
575 { "merom", PROCESSOR_CORE2,
577 { "core2", PROCESSOR_CORE2,
579 { "corei7", PROCESSOR_COREI7,
581 { "l1om", PROCESSOR_L1OM,
583 { "k6", PROCESSOR_K6,
585 { "k6_2", PROCESSOR_K6,
587 { "athlon", PROCESSOR_ATHLON,
589 { "sledgehammer", PROCESSOR_K8,
591 { "opteron", PROCESSOR_K8,
593 { "k8", PROCESSOR_K8,
595 { "amdfam10", PROCESSOR_AMDFAM10,
596 CPU_AMDFAM10_FLAGS },
597 { ".8087", PROCESSOR_UNKNOWN,
599 { ".287", PROCESSOR_UNKNOWN,
601 { ".387", PROCESSOR_UNKNOWN,
603 { ".no87", PROCESSOR_UNKNOWN,
605 { ".mmx", PROCESSOR_UNKNOWN,
607 { ".nommx", PROCESSOR_UNKNOWN,
609 { ".sse", PROCESSOR_UNKNOWN,
611 { ".sse2", PROCESSOR_UNKNOWN,
613 { ".sse3", PROCESSOR_UNKNOWN,
615 { ".ssse3", PROCESSOR_UNKNOWN,
617 { ".sse4.1", PROCESSOR_UNKNOWN,
619 { ".sse4.2", PROCESSOR_UNKNOWN,
621 { ".sse4", PROCESSOR_UNKNOWN,
623 { ".nosse", PROCESSOR_UNKNOWN,
625 { ".avx", PROCESSOR_UNKNOWN,
627 { ".noavx", PROCESSOR_UNKNOWN,
629 { ".vmx", PROCESSOR_UNKNOWN,
631 { ".smx", PROCESSOR_UNKNOWN,
633 { ".xsave", PROCESSOR_UNKNOWN,
635 { ".aes", PROCESSOR_UNKNOWN,
637 { ".pclmul", PROCESSOR_UNKNOWN,
639 { ".clmul", PROCESSOR_UNKNOWN,
641 { ".fma", PROCESSOR_UNKNOWN,
643 { ".fma4", PROCESSOR_UNKNOWN,
645 { ".movbe", PROCESSOR_UNKNOWN,
647 { ".ept", PROCESSOR_UNKNOWN,
649 { ".clflush", PROCESSOR_UNKNOWN,
651 { ".syscall", PROCESSOR_UNKNOWN,
653 { ".rdtscp", PROCESSOR_UNKNOWN,
655 { ".3dnow", PROCESSOR_UNKNOWN,
657 { ".3dnowa", PROCESSOR_UNKNOWN,
659 { ".padlock", PROCESSOR_UNKNOWN,
661 { ".pacifica", PROCESSOR_UNKNOWN,
663 { ".svme", PROCESSOR_UNKNOWN,
665 { ".sse4a", PROCESSOR_UNKNOWN,
667 { ".abm", PROCESSOR_UNKNOWN,
672 /* Like s_lcomm_internal in gas/read.c but the alignment string
673 is allowed to be optional. */
676 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
683 && *input_line_pointer == ',')
685 align = parse_align (needs_align - 1);
687 if (align == (addressT) -1)
702 bss_alloc (symbolP, size, align);
707 pe_lcomm (int needs_align)
709 s_comm_internal (needs_align * 2, pe_lcomm_internal);
713 const pseudo_typeS md_pseudo_table[] =
715 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
716 {"align", s_align_bytes, 0},
718 {"align", s_align_ptwo, 0},
720 {"arch", set_cpu_arch, 0},
724 {"lcomm", pe_lcomm, 1},
726 {"ffloat", float_cons, 'f'},
727 {"dfloat", float_cons, 'd'},
728 {"tfloat", float_cons, 'x'},
730 {"slong", signed_cons, 4},
731 {"noopt", s_ignore, 0},
732 {"optim", s_ignore, 0},
733 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
734 {"code16", set_code_flag, CODE_16BIT},
735 {"code32", set_code_flag, CODE_32BIT},
736 {"code64", set_code_flag, CODE_64BIT},
737 {"intel_syntax", set_intel_syntax, 1},
738 {"att_syntax", set_intel_syntax, 0},
739 {"intel_mnemonic", set_intel_mnemonic, 1},
740 {"att_mnemonic", set_intel_mnemonic, 0},
741 {"allow_index_reg", set_allow_index_reg, 1},
742 {"disallow_index_reg", set_allow_index_reg, 0},
743 {"sse_check", set_sse_check, 0},
744 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
745 {"largecomm", handle_large_common, 0},
747 {"file", (void (*) (int)) dwarf2_directive_file, 0},
748 {"loc", dwarf2_directive_loc, 0},
749 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
752 {"secrel32", pe_directive_secrel, 0},
757 /* For interface with expression (). */
758 extern char *input_line_pointer;
760 /* Hash table for instruction mnemonic lookup. */
761 static struct hash_control *op_hash;
763 /* Hash table for register lookup. */
764 static struct hash_control *reg_hash;
767 i386_align_code (fragS *fragP, int count)
769 /* Various efficient no-op patterns for aligning code labels.
770 Note: Don't try to assemble the instructions in the comments.
771 0L and 0w are not legal. */
772 static const char f32_1[] =
774 static const char f32_2[] =
775 {0x66,0x90}; /* xchg %ax,%ax */
776 static const char f32_3[] =
777 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
778 static const char f32_4[] =
779 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
780 static const char f32_5[] =
782 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
783 static const char f32_6[] =
784 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
785 static const char f32_7[] =
786 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
787 static const char f32_8[] =
789 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
790 static const char f32_9[] =
791 {0x89,0xf6, /* movl %esi,%esi */
792 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
793 static const char f32_10[] =
794 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
795 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
796 static const char f32_11[] =
797 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_12[] =
800 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
801 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
802 static const char f32_13[] =
803 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_14[] =
806 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
807 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
808 static const char f16_3[] =
809 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
810 static const char f16_4[] =
811 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
812 static const char f16_5[] =
814 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
815 static const char f16_6[] =
816 {0x89,0xf6, /* mov %si,%si */
817 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
818 static const char f16_7[] =
819 {0x8d,0x74,0x00, /* lea 0(%si),%si */
820 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
821 static const char f16_8[] =
822 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char jump_31[] =
825 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
828 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
829 static const char *const f32_patt[] = {
830 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
831 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
833 static const char *const f16_patt[] = {
834 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
837 static const char alt_3[] =
839 /* nopl 0(%[re]ax) */
840 static const char alt_4[] =
841 {0x0f,0x1f,0x40,0x00};
842 /* nopl 0(%[re]ax,%[re]ax,1) */
843 static const char alt_5[] =
844 {0x0f,0x1f,0x44,0x00,0x00};
845 /* nopw 0(%[re]ax,%[re]ax,1) */
846 static const char alt_6[] =
847 {0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopl 0L(%[re]ax) */
849 static const char alt_7[] =
850 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
851 /* nopl 0L(%[re]ax,%[re]ax,1) */
852 static const char alt_8[] =
853 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
854 /* nopw 0L(%[re]ax,%[re]ax,1) */
855 static const char alt_9[] =
856 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_10[] =
859 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
861 nopw %cs:0L(%[re]ax,%[re]ax,1) */
862 static const char alt_long_11[] =
864 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_12[] =
871 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_13[] =
880 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
885 nopw %cs:0L(%[re]ax,%[re]ax,1) */
886 static const char alt_long_14[] =
891 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
897 nopw %cs:0L(%[re]ax,%[re]ax,1) */
898 static const char alt_long_15[] =
904 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 /* nopl 0(%[re]ax,%[re]ax,1)
906 nopw 0(%[re]ax,%[re]ax,1) */
907 static const char alt_short_11[] =
908 {0x0f,0x1f,0x44,0x00,0x00,
909 0x66,0x0f,0x1f,0x44,0x00,0x00};
910 /* nopw 0(%[re]ax,%[re]ax,1)
911 nopw 0(%[re]ax,%[re]ax,1) */
912 static const char alt_short_12[] =
913 {0x66,0x0f,0x1f,0x44,0x00,0x00,
914 0x66,0x0f,0x1f,0x44,0x00,0x00};
915 /* nopw 0(%[re]ax,%[re]ax,1)
917 static const char alt_short_13[] =
918 {0x66,0x0f,0x1f,0x44,0x00,0x00,
919 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
922 static const char alt_short_14[] =
923 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
924 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
926 nopl 0L(%[re]ax,%[re]ax,1) */
927 static const char alt_short_15[] =
928 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
929 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
930 static const char *const alt_short_patt[] = {
931 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
932 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
933 alt_short_14, alt_short_15
935 static const char *const alt_long_patt[] = {
936 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
937 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
938 alt_long_14, alt_long_15
941 /* Only align for at least a positive non-zero boundary. */
942 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
945 /* We need to decide which NOP sequence to use for 32bit and
946 64bit. When -mtune= is used:
948 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
949 PROCESSOR_GENERIC32, f32_patt will be used.
950 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
951 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
952 PROCESSOR_GENERIC64, alt_long_patt will be used.
953 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
954 PROCESSOR_AMDFAM10, alt_short_patt will be used.
956 When -mtune= isn't used, alt_long_patt will be used if
957 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
960 When -march= or .arch is used, we can't use anything beyond
961 cpu_arch_isa_flags. */
963 if (flag_code == CODE_16BIT)
967 memcpy (fragP->fr_literal + fragP->fr_fix,
969 /* Adjust jump offset. */
970 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
973 memcpy (fragP->fr_literal + fragP->fr_fix,
974 f16_patt[count - 1], count);
978 const char *const *patt = NULL;
980 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
982 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
983 switch (cpu_arch_tune)
985 case PROCESSOR_UNKNOWN:
986 /* We use cpu_arch_isa_flags to check if we SHOULD
987 optimize for Cpu686. */
988 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
989 patt = alt_long_patt;
993 case PROCESSOR_PENTIUMPRO:
994 case PROCESSOR_PENTIUM4:
995 case PROCESSOR_NOCONA:
997 case PROCESSOR_CORE2:
998 case PROCESSOR_COREI7:
1000 case PROCESSOR_GENERIC64:
1001 patt = alt_long_patt;
1004 case PROCESSOR_ATHLON:
1006 case PROCESSOR_AMDFAM10:
1007 patt = alt_short_patt;
1009 case PROCESSOR_I386:
1010 case PROCESSOR_I486:
1011 case PROCESSOR_PENTIUM:
1012 case PROCESSOR_GENERIC32:
1019 switch (fragP->tc_frag_data.tune)
1021 case PROCESSOR_UNKNOWN:
1022 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1023 PROCESSOR_UNKNOWN. */
1027 case PROCESSOR_I386:
1028 case PROCESSOR_I486:
1029 case PROCESSOR_PENTIUM:
1031 case PROCESSOR_ATHLON:
1033 case PROCESSOR_AMDFAM10:
1034 case PROCESSOR_GENERIC32:
1035 /* We use cpu_arch_isa_flags to check if we CAN optimize
1037 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
1038 patt = alt_short_patt;
1042 case PROCESSOR_PENTIUMPRO:
1043 case PROCESSOR_PENTIUM4:
1044 case PROCESSOR_NOCONA:
1045 case PROCESSOR_CORE:
1046 case PROCESSOR_CORE2:
1047 case PROCESSOR_COREI7:
1048 case PROCESSOR_L1OM:
1049 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
1050 patt = alt_long_patt;
1054 case PROCESSOR_GENERIC64:
1055 patt = alt_long_patt;
1060 if (patt == f32_patt)
1062 /* If the padding is less than 15 bytes, we use the normal
1063 ones. Otherwise, we use a jump instruction and adjust
1067 /* For 64bit, the limit is 3 bytes. */
1068 if (flag_code == CODE_64BIT
1069 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1074 memcpy (fragP->fr_literal + fragP->fr_fix,
1075 patt[count - 1], count);
1078 memcpy (fragP->fr_literal + fragP->fr_fix,
1080 /* Adjust jump offset. */
1081 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1086 /* Maximum length of an instruction is 15 byte. If the
1087 padding is greater than 15 bytes and we don't use jump,
1088 we have to break it into smaller pieces. */
1089 int padding = count;
1090 while (padding > 15)
1093 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1098 memcpy (fragP->fr_literal + fragP->fr_fix,
1099 patt [padding - 1], padding);
1102 fragP->fr_var = count;
1106 operand_type_all_zero (const union i386_operand_type *x)
1108 switch (ARRAY_SIZE(x->array))
1117 return !x->array[0];
1124 operand_type_set (union i386_operand_type *x, unsigned int v)
1126 switch (ARRAY_SIZE(x->array))
1141 operand_type_equal (const union i386_operand_type *x,
1142 const union i386_operand_type *y)
1144 switch (ARRAY_SIZE(x->array))
1147 if (x->array[2] != y->array[2])
1150 if (x->array[1] != y->array[1])
1153 return x->array[0] == y->array[0];
1161 cpu_flags_all_zero (const union i386_cpu_flags *x)
1163 switch (ARRAY_SIZE(x->array))
1172 return !x->array[0];
1179 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1181 switch (ARRAY_SIZE(x->array))
1196 cpu_flags_equal (const union i386_cpu_flags *x,
1197 const union i386_cpu_flags *y)
1199 switch (ARRAY_SIZE(x->array))
1202 if (x->array[2] != y->array[2])
1205 if (x->array[1] != y->array[1])
1208 return x->array[0] == y->array[0];
1216 cpu_flags_check_cpu64 (i386_cpu_flags f)
1218 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1219 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1222 static INLINE i386_cpu_flags
1223 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1225 switch (ARRAY_SIZE (x.array))
1228 x.array [2] &= y.array [2];
1230 x.array [1] &= y.array [1];
1232 x.array [0] &= y.array [0];
1240 static INLINE i386_cpu_flags
1241 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1243 switch (ARRAY_SIZE (x.array))
1246 x.array [2] |= y.array [2];
1248 x.array [1] |= y.array [1];
1250 x.array [0] |= y.array [0];
1258 static INLINE i386_cpu_flags
1259 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1261 switch (ARRAY_SIZE (x.array))
1264 x.array [2] &= ~y.array [2];
1266 x.array [1] &= ~y.array [1];
1268 x.array [0] &= ~y.array [0];
1276 #define CPU_FLAGS_ARCH_MATCH 0x1
1277 #define CPU_FLAGS_64BIT_MATCH 0x2
1278 #define CPU_FLAGS_AES_MATCH 0x4
1279 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1280 #define CPU_FLAGS_AVX_MATCH 0x10
1282 #define CPU_FLAGS_32BIT_MATCH \
1283 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1284 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1285 #define CPU_FLAGS_PERFECT_MATCH \
1286 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1288 /* Return CPU flags match bits. */
1291 cpu_flags_match (const insn_template *t)
1293 i386_cpu_flags x = t->cpu_flags;
1294 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1296 x.bitfield.cpu64 = 0;
1297 x.bitfield.cpuno64 = 0;
1299 if (cpu_flags_all_zero (&x))
1301 /* This instruction is available on all archs. */
1302 match |= CPU_FLAGS_32BIT_MATCH;
1306 /* This instruction is available only on some archs. */
1307 i386_cpu_flags cpu = cpu_arch_flags;
1309 cpu.bitfield.cpu64 = 0;
1310 cpu.bitfield.cpuno64 = 0;
1311 cpu = cpu_flags_and (x, cpu);
1312 if (!cpu_flags_all_zero (&cpu))
1314 if (x.bitfield.cpuavx)
1316 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1317 if (cpu.bitfield.cpuavx)
1319 /* Check SSE2AVX. */
1320 if (!t->opcode_modifier.sse2avx|| sse2avx)
1322 match |= (CPU_FLAGS_ARCH_MATCH
1323 | CPU_FLAGS_AVX_MATCH);
1325 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1326 match |= CPU_FLAGS_AES_MATCH;
1328 if (!x.bitfield.cpupclmul
1329 || cpu.bitfield.cpupclmul)
1330 match |= CPU_FLAGS_PCLMUL_MATCH;
1334 match |= CPU_FLAGS_ARCH_MATCH;
1337 match |= CPU_FLAGS_32BIT_MATCH;
1343 static INLINE i386_operand_type
1344 operand_type_and (i386_operand_type x, i386_operand_type y)
1346 switch (ARRAY_SIZE (x.array))
1349 x.array [2] &= y.array [2];
1351 x.array [1] &= y.array [1];
1353 x.array [0] &= y.array [0];
1361 static INLINE i386_operand_type
1362 operand_type_or (i386_operand_type x, i386_operand_type y)
1364 switch (ARRAY_SIZE (x.array))
1367 x.array [2] |= y.array [2];
1369 x.array [1] |= y.array [1];
1371 x.array [0] |= y.array [0];
1379 static INLINE i386_operand_type
1380 operand_type_xor (i386_operand_type x, i386_operand_type y)
1382 switch (ARRAY_SIZE (x.array))
1385 x.array [2] ^= y.array [2];
1387 x.array [1] ^= y.array [1];
1389 x.array [0] ^= y.array [0];
1397 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1398 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1399 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1400 static const i386_operand_type inoutportreg
1401 = OPERAND_TYPE_INOUTPORTREG;
1402 static const i386_operand_type reg16_inoutportreg
1403 = OPERAND_TYPE_REG16_INOUTPORTREG;
1404 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1405 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1406 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1407 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1408 static const i386_operand_type anydisp
1409 = OPERAND_TYPE_ANYDISP;
1410 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1411 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1412 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1413 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1414 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1415 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1416 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1417 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1418 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1419 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1420 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1431 operand_type_check (i386_operand_type t, enum operand_type c)
1436 return (t.bitfield.reg8
1439 || t.bitfield.reg64);
1442 return (t.bitfield.imm8
1446 || t.bitfield.imm32s
1447 || t.bitfield.imm64);
1450 return (t.bitfield.disp8
1451 || t.bitfield.disp16
1452 || t.bitfield.disp32
1453 || t.bitfield.disp32s
1454 || t.bitfield.disp64);
1457 return (t.bitfield.disp8
1458 || t.bitfield.disp16
1459 || t.bitfield.disp32
1460 || t.bitfield.disp32s
1461 || t.bitfield.disp64
1462 || t.bitfield.baseindex);
1471 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1472 operand J for instruction template T. */
1475 match_reg_size (const insn_template *t, unsigned int j)
1477 return !((i.types[j].bitfield.byte
1478 && !t->operand_types[j].bitfield.byte)
1479 || (i.types[j].bitfield.word
1480 && !t->operand_types[j].bitfield.word)
1481 || (i.types[j].bitfield.dword
1482 && !t->operand_types[j].bitfield.dword)
1483 || (i.types[j].bitfield.qword
1484 && !t->operand_types[j].bitfield.qword));
1487 /* Return 1 if there is no conflict in any size on operand J for
1488 instruction template T. */
1491 match_mem_size (const insn_template *t, unsigned int j)
1493 return (match_reg_size (t, j)
1494 && !((i.types[j].bitfield.unspecified
1495 && !t->operand_types[j].bitfield.unspecified)
1496 || (i.types[j].bitfield.fword
1497 && !t->operand_types[j].bitfield.fword)
1498 || (i.types[j].bitfield.tbyte
1499 && !t->operand_types[j].bitfield.tbyte)
1500 || (i.types[j].bitfield.xmmword
1501 && !t->operand_types[j].bitfield.xmmword)
1502 || (i.types[j].bitfield.ymmword
1503 && !t->operand_types[j].bitfield.ymmword)));
1506 /* Return 1 if there is no size conflict on any operands for
1507 instruction template T. */
1510 operand_size_match (const insn_template *t)
1515 /* Don't check jump instructions. */
1516 if (t->opcode_modifier.jump
1517 || t->opcode_modifier.jumpbyte
1518 || t->opcode_modifier.jumpdword
1519 || t->opcode_modifier.jumpintersegment)
1522 /* Check memory and accumulator operand size. */
1523 for (j = 0; j < i.operands; j++)
1525 if (t->operand_types[j].bitfield.anysize)
1528 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1534 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1542 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1545 /* Check reverse. */
1546 gas_assert (i.operands == 2);
1549 for (j = 0; j < 2; j++)
1551 if (t->operand_types[j].bitfield.acc
1552 && !match_reg_size (t, j ? 0 : 1))
1558 if (i.types[j].bitfield.mem
1559 && !match_mem_size (t, j ? 0 : 1))
1570 operand_type_match (i386_operand_type overlap,
1571 i386_operand_type given)
1573 i386_operand_type temp = overlap;
1575 temp.bitfield.jumpabsolute = 0;
1576 temp.bitfield.unspecified = 0;
1577 temp.bitfield.byte = 0;
1578 temp.bitfield.word = 0;
1579 temp.bitfield.dword = 0;
1580 temp.bitfield.fword = 0;
1581 temp.bitfield.qword = 0;
1582 temp.bitfield.tbyte = 0;
1583 temp.bitfield.xmmword = 0;
1584 temp.bitfield.ymmword = 0;
1585 if (operand_type_all_zero (&temp))
1588 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1589 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1592 /* If given types g0 and g1 are registers they must be of the same type
1593 unless the expected operand type register overlap is null.
1594 Note that Acc in a template matches every size of reg. */
1597 operand_type_register_match (i386_operand_type m0,
1598 i386_operand_type g0,
1599 i386_operand_type t0,
1600 i386_operand_type m1,
1601 i386_operand_type g1,
1602 i386_operand_type t1)
1604 if (!operand_type_check (g0, reg))
1607 if (!operand_type_check (g1, reg))
1610 if (g0.bitfield.reg8 == g1.bitfield.reg8
1611 && g0.bitfield.reg16 == g1.bitfield.reg16
1612 && g0.bitfield.reg32 == g1.bitfield.reg32
1613 && g0.bitfield.reg64 == g1.bitfield.reg64)
1616 if (m0.bitfield.acc)
1618 t0.bitfield.reg8 = 1;
1619 t0.bitfield.reg16 = 1;
1620 t0.bitfield.reg32 = 1;
1621 t0.bitfield.reg64 = 1;
1624 if (m1.bitfield.acc)
1626 t1.bitfield.reg8 = 1;
1627 t1.bitfield.reg16 = 1;
1628 t1.bitfield.reg32 = 1;
1629 t1.bitfield.reg64 = 1;
1632 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1633 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1634 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1635 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1638 static INLINE unsigned int
1639 mode_from_disp_size (i386_operand_type t)
1641 if (t.bitfield.disp8)
1643 else if (t.bitfield.disp16
1644 || t.bitfield.disp32
1645 || t.bitfield.disp32s)
1652 fits_in_signed_byte (offsetT num)
1654 return (num >= -128) && (num <= 127);
1658 fits_in_unsigned_byte (offsetT num)
1660 return (num & 0xff) == num;
1664 fits_in_unsigned_word (offsetT num)
1666 return (num & 0xffff) == num;
1670 fits_in_signed_word (offsetT num)
1672 return (-32768 <= num) && (num <= 32767);
1676 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1681 return (!(((offsetT) -1 << 31) & num)
1682 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1684 } /* fits_in_signed_long() */
1687 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1692 return (num & (((offsetT) 2 << 31) - 1)) == num;
1694 } /* fits_in_unsigned_long() */
1696 static i386_operand_type
1697 smallest_imm_type (offsetT num)
1699 i386_operand_type t;
1701 operand_type_set (&t, 0);
1702 t.bitfield.imm64 = 1;
1704 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1706 /* This code is disabled on the 486 because all the Imm1 forms
1707 in the opcode table are slower on the i486. They're the
1708 versions with the implicitly specified single-position
1709 displacement, which has another syntax if you really want to
1711 t.bitfield.imm1 = 1;
1712 t.bitfield.imm8 = 1;
1713 t.bitfield.imm8s = 1;
1714 t.bitfield.imm16 = 1;
1715 t.bitfield.imm32 = 1;
1716 t.bitfield.imm32s = 1;
1718 else if (fits_in_signed_byte (num))
1720 t.bitfield.imm8 = 1;
1721 t.bitfield.imm8s = 1;
1722 t.bitfield.imm16 = 1;
1723 t.bitfield.imm32 = 1;
1724 t.bitfield.imm32s = 1;
1726 else if (fits_in_unsigned_byte (num))
1728 t.bitfield.imm8 = 1;
1729 t.bitfield.imm16 = 1;
1730 t.bitfield.imm32 = 1;
1731 t.bitfield.imm32s = 1;
1733 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1735 t.bitfield.imm16 = 1;
1736 t.bitfield.imm32 = 1;
1737 t.bitfield.imm32s = 1;
1739 else if (fits_in_signed_long (num))
1741 t.bitfield.imm32 = 1;
1742 t.bitfield.imm32s = 1;
1744 else if (fits_in_unsigned_long (num))
1745 t.bitfield.imm32 = 1;
1751 offset_in_range (offsetT val, int size)
1757 case 1: mask = ((addressT) 1 << 8) - 1; break;
1758 case 2: mask = ((addressT) 1 << 16) - 1; break;
1759 case 4: mask = ((addressT) 2 << 31) - 1; break;
1761 case 8: mask = ((addressT) 2 << 63) - 1; break;
1766 /* If BFD64, sign extend val. */
1767 if (!use_rela_relocations)
1768 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1769 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1771 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1773 char buf1[40], buf2[40];
1775 sprint_value (buf1, val);
1776 sprint_value (buf2, val & mask);
1777 as_warn (_("%s shortened to %s"), buf1, buf2);
1782 /* Returns 0 if attempting to add a prefix where one from the same
1783 class already exists, 1 if non rep/repne added, 2 if rep/repne
1786 add_prefix (unsigned int prefix)
1791 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1792 && flag_code == CODE_64BIT)
1794 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1795 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1796 && (prefix & (REX_R | REX_X | REX_B))))
1807 case CS_PREFIX_OPCODE:
1808 case DS_PREFIX_OPCODE:
1809 case ES_PREFIX_OPCODE:
1810 case FS_PREFIX_OPCODE:
1811 case GS_PREFIX_OPCODE:
1812 case SS_PREFIX_OPCODE:
1816 case REPNE_PREFIX_OPCODE:
1817 case REPE_PREFIX_OPCODE:
1820 case LOCK_PREFIX_OPCODE:
1828 case ADDR_PREFIX_OPCODE:
1832 case DATA_PREFIX_OPCODE:
1836 if (i.prefix[q] != 0)
1844 i.prefix[q] |= prefix;
1847 as_bad (_("same type of prefix used twice"));
1853 set_code_flag (int value)
1855 flag_code = (enum flag_code) value;
1856 if (flag_code == CODE_64BIT)
1858 cpu_arch_flags.bitfield.cpu64 = 1;
1859 cpu_arch_flags.bitfield.cpuno64 = 0;
1863 cpu_arch_flags.bitfield.cpu64 = 0;
1864 cpu_arch_flags.bitfield.cpuno64 = 1;
1866 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1868 as_bad (_("64bit mode not supported on this CPU."));
1870 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1872 as_bad (_("32bit mode not supported on this CPU."));
1874 stackop_size = '\0';
1878 set_16bit_gcc_code_flag (int new_code_flag)
1880 flag_code = (enum flag_code) new_code_flag;
1881 if (flag_code != CODE_16BIT)
1883 cpu_arch_flags.bitfield.cpu64 = 0;
1884 cpu_arch_flags.bitfield.cpuno64 = 1;
1885 stackop_size = LONG_MNEM_SUFFIX;
1889 set_intel_syntax (int syntax_flag)
1891 /* Find out if register prefixing is specified. */
1892 int ask_naked_reg = 0;
1895 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1897 char *string = input_line_pointer;
1898 int e = get_symbol_end ();
1900 if (strcmp (string, "prefix") == 0)
1902 else if (strcmp (string, "noprefix") == 0)
1905 as_bad (_("bad argument to syntax directive."));
1906 *input_line_pointer = e;
1908 demand_empty_rest_of_line ();
1910 intel_syntax = syntax_flag;
1912 if (ask_naked_reg == 0)
1913 allow_naked_reg = (intel_syntax
1914 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1916 allow_naked_reg = (ask_naked_reg < 0);
1918 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
1920 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1921 identifier_chars['$'] = intel_syntax ? '$' : 0;
1922 register_prefix = allow_naked_reg ? "" : "%";
1926 set_intel_mnemonic (int mnemonic_flag)
1928 intel_mnemonic = mnemonic_flag;
1932 set_allow_index_reg (int flag)
1934 allow_index_reg = flag;
1938 set_sse_check (int dummy ATTRIBUTE_UNUSED)
1942 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1944 char *string = input_line_pointer;
1945 int e = get_symbol_end ();
1947 if (strcmp (string, "none") == 0)
1948 sse_check = sse_check_none;
1949 else if (strcmp (string, "warning") == 0)
1950 sse_check = sse_check_warning;
1951 else if (strcmp (string, "error") == 0)
1952 sse_check = sse_check_error;
1954 as_bad (_("bad argument to sse_check directive."));
1955 *input_line_pointer = e;
1958 as_bad (_("missing argument for sse_check directive"));
1960 demand_empty_rest_of_line ();
1964 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1965 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
1967 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1968 static const char *arch;
1970 /* Intel LIOM is only supported on ELF. */
1976 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1977 use default_arch. */
1978 arch = cpu_arch_name;
1980 arch = default_arch;
1983 /* If we are targeting Intel L1OM, we must enable it. */
1984 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1985 || new_flag.bitfield.cpul1om)
1988 as_bad (_("`%s' is not supported on `%s'"), name, arch);
1993 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1997 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1999 char *string = input_line_pointer;
2000 int e = get_symbol_end ();
2002 i386_cpu_flags flags;
2004 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
2006 if (strcmp (string, cpu_arch[i].name) == 0)
2008 check_cpu_arch_compatible (string, cpu_arch[i].flags);
2012 cpu_arch_name = cpu_arch[i].name;
2013 cpu_sub_arch_name = NULL;
2014 cpu_arch_flags = cpu_arch[i].flags;
2015 if (flag_code == CODE_64BIT)
2017 cpu_arch_flags.bitfield.cpu64 = 1;
2018 cpu_arch_flags.bitfield.cpuno64 = 0;
2022 cpu_arch_flags.bitfield.cpu64 = 0;
2023 cpu_arch_flags.bitfield.cpuno64 = 1;
2025 cpu_arch_isa = cpu_arch[i].type;
2026 cpu_arch_isa_flags = cpu_arch[i].flags;
2027 if (!cpu_arch_tune_set)
2029 cpu_arch_tune = cpu_arch_isa;
2030 cpu_arch_tune_flags = cpu_arch_isa_flags;
2035 if (strncmp (string + 1, "no", 2))
2036 flags = cpu_flags_or (cpu_arch_flags,
2039 flags = cpu_flags_and_not (cpu_arch_flags,
2041 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2043 if (cpu_sub_arch_name)
2045 char *name = cpu_sub_arch_name;
2046 cpu_sub_arch_name = concat (name,
2048 (const char *) NULL);
2052 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
2053 cpu_arch_flags = flags;
2055 *input_line_pointer = e;
2056 demand_empty_rest_of_line ();
2060 if (i >= ARRAY_SIZE (cpu_arch))
2061 as_bad (_("no such architecture: `%s'"), string);
2063 *input_line_pointer = e;
2066 as_bad (_("missing cpu architecture"));
2068 no_cond_jump_promotion = 0;
2069 if (*input_line_pointer == ','
2070 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2072 char *string = ++input_line_pointer;
2073 int e = get_symbol_end ();
2075 if (strcmp (string, "nojumps") == 0)
2076 no_cond_jump_promotion = 1;
2077 else if (strcmp (string, "jumps") == 0)
2080 as_bad (_("no such architecture modifier: `%s'"), string);
2082 *input_line_pointer = e;
2085 demand_empty_rest_of_line ();
2088 enum bfd_architecture
2091 if (cpu_arch_isa == PROCESSOR_L1OM)
2093 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2094 || flag_code != CODE_64BIT)
2095 as_fatal (_("Intel L1OM is 64bit ELF only"));
2096 return bfd_arch_l1om;
2099 return bfd_arch_i386;
2105 if (!strcmp (default_arch, "x86_64"))
2107 if (cpu_arch_isa == PROCESSOR_L1OM)
2109 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2110 as_fatal (_("Intel L1OM is 64bit ELF only"));
2111 return bfd_mach_l1om;
2114 return bfd_mach_x86_64;
2116 else if (!strcmp (default_arch, "i386"))
2117 return bfd_mach_i386_i386;
2119 as_fatal (_("Unknown architecture"));
2125 const char *hash_err;
2127 /* Initialize op_hash hash table. */
2128 op_hash = hash_new ();
2131 const insn_template *optab;
2132 templates *core_optab;
2134 /* Setup for loop. */
2136 core_optab = (templates *) xmalloc (sizeof (templates));
2137 core_optab->start = optab;
2142 if (optab->name == NULL
2143 || strcmp (optab->name, (optab - 1)->name) != 0)
2145 /* different name --> ship out current template list;
2146 add to hash table; & begin anew. */
2147 core_optab->end = optab;
2148 hash_err = hash_insert (op_hash,
2150 (void *) core_optab);
2153 as_fatal (_("Internal Error: Can't hash %s: %s"),
2157 if (optab->name == NULL)
2159 core_optab = (templates *) xmalloc (sizeof (templates));
2160 core_optab->start = optab;
2165 /* Initialize reg_hash hash table. */
2166 reg_hash = hash_new ();
2168 const reg_entry *regtab;
2169 unsigned int regtab_size = i386_regtab_size;
2171 for (regtab = i386_regtab; regtab_size--; regtab++)
2173 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2175 as_fatal (_("Internal Error: Can't hash %s: %s"),
2181 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2186 for (c = 0; c < 256; c++)
2191 mnemonic_chars[c] = c;
2192 register_chars[c] = c;
2193 operand_chars[c] = c;
2195 else if (ISLOWER (c))
2197 mnemonic_chars[c] = c;
2198 register_chars[c] = c;
2199 operand_chars[c] = c;
2201 else if (ISUPPER (c))
2203 mnemonic_chars[c] = TOLOWER (c);
2204 register_chars[c] = mnemonic_chars[c];
2205 operand_chars[c] = c;
2208 if (ISALPHA (c) || ISDIGIT (c))
2209 identifier_chars[c] = c;
2212 identifier_chars[c] = c;
2213 operand_chars[c] = c;
2218 identifier_chars['@'] = '@';
2221 identifier_chars['?'] = '?';
2222 operand_chars['?'] = '?';
2224 digit_chars['-'] = '-';
2225 mnemonic_chars['_'] = '_';
2226 mnemonic_chars['-'] = '-';
2227 mnemonic_chars['.'] = '.';
2228 identifier_chars['_'] = '_';
2229 identifier_chars['.'] = '.';
2231 for (p = operand_special_chars; *p != '\0'; p++)
2232 operand_chars[(unsigned char) *p] = *p;
2235 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2238 record_alignment (text_section, 2);
2239 record_alignment (data_section, 2);
2240 record_alignment (bss_section, 2);
2244 if (flag_code == CODE_64BIT)
2246 x86_dwarf2_return_column = 16;
2247 x86_cie_data_alignment = -8;
2251 x86_dwarf2_return_column = 8;
2252 x86_cie_data_alignment = -4;
2257 i386_print_statistics (FILE *file)
2259 hash_print_statistics (file, "i386 opcode", op_hash);
2260 hash_print_statistics (file, "i386 register", reg_hash);
2265 /* Debugging routines for md_assemble. */
2266 static void pte (insn_template *);
2267 static void pt (i386_operand_type);
2268 static void pe (expressionS *);
2269 static void ps (symbolS *);
2272 pi (char *line, i386_insn *x)
2276 fprintf (stdout, "%s: template ", line);
2278 fprintf (stdout, " address: base %s index %s scale %x\n",
2279 x->base_reg ? x->base_reg->reg_name : "none",
2280 x->index_reg ? x->index_reg->reg_name : "none",
2281 x->log2_scale_factor);
2282 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2283 x->rm.mode, x->rm.reg, x->rm.regmem);
2284 fprintf (stdout, " sib: base %x index %x scale %x\n",
2285 x->sib.base, x->sib.index, x->sib.scale);
2286 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2287 (x->rex & REX_W) != 0,
2288 (x->rex & REX_R) != 0,
2289 (x->rex & REX_X) != 0,
2290 (x->rex & REX_B) != 0);
2291 for (i = 0; i < x->operands; i++)
2293 fprintf (stdout, " #%d: ", i + 1);
2295 fprintf (stdout, "\n");
2296 if (x->types[i].bitfield.reg8
2297 || x->types[i].bitfield.reg16
2298 || x->types[i].bitfield.reg32
2299 || x->types[i].bitfield.reg64
2300 || x->types[i].bitfield.regmmx
2301 || x->types[i].bitfield.regxmm
2302 || x->types[i].bitfield.regymm
2303 || x->types[i].bitfield.sreg2
2304 || x->types[i].bitfield.sreg3
2305 || x->types[i].bitfield.control
2306 || x->types[i].bitfield.debug
2307 || x->types[i].bitfield.test)
2308 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2309 if (operand_type_check (x->types[i], imm))
2311 if (operand_type_check (x->types[i], disp))
2312 pe (x->op[i].disps);
2317 pte (insn_template *t)
2320 fprintf (stdout, " %d operands ", t->operands);
2321 fprintf (stdout, "opcode %x ", t->base_opcode);
2322 if (t->extension_opcode != None)
2323 fprintf (stdout, "ext %x ", t->extension_opcode);
2324 if (t->opcode_modifier.d)
2325 fprintf (stdout, "D");
2326 if (t->opcode_modifier.w)
2327 fprintf (stdout, "W");
2328 fprintf (stdout, "\n");
2329 for (i = 0; i < t->operands; i++)
2331 fprintf (stdout, " #%d type ", i + 1);
2332 pt (t->operand_types[i]);
2333 fprintf (stdout, "\n");
2340 fprintf (stdout, " operation %d\n", e->X_op);
2341 fprintf (stdout, " add_number %ld (%lx)\n",
2342 (long) e->X_add_number, (long) e->X_add_number);
2343 if (e->X_add_symbol)
2345 fprintf (stdout, " add_symbol ");
2346 ps (e->X_add_symbol);
2347 fprintf (stdout, "\n");
2351 fprintf (stdout, " op_symbol ");
2352 ps (e->X_op_symbol);
2353 fprintf (stdout, "\n");
2360 fprintf (stdout, "%s type %s%s",
2362 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2363 segment_name (S_GET_SEGMENT (s)));
2366 static struct type_name
2368 i386_operand_type mask;
2371 const type_names[] =
2373 { OPERAND_TYPE_REG8, "r8" },
2374 { OPERAND_TYPE_REG16, "r16" },
2375 { OPERAND_TYPE_REG32, "r32" },
2376 { OPERAND_TYPE_REG64, "r64" },
2377 { OPERAND_TYPE_IMM8, "i8" },
2378 { OPERAND_TYPE_IMM8, "i8s" },
2379 { OPERAND_TYPE_IMM16, "i16" },
2380 { OPERAND_TYPE_IMM32, "i32" },
2381 { OPERAND_TYPE_IMM32S, "i32s" },
2382 { OPERAND_TYPE_IMM64, "i64" },
2383 { OPERAND_TYPE_IMM1, "i1" },
2384 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2385 { OPERAND_TYPE_DISP8, "d8" },
2386 { OPERAND_TYPE_DISP16, "d16" },
2387 { OPERAND_TYPE_DISP32, "d32" },
2388 { OPERAND_TYPE_DISP32S, "d32s" },
2389 { OPERAND_TYPE_DISP64, "d64" },
2390 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2391 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2392 { OPERAND_TYPE_CONTROL, "control reg" },
2393 { OPERAND_TYPE_TEST, "test reg" },
2394 { OPERAND_TYPE_DEBUG, "debug reg" },
2395 { OPERAND_TYPE_FLOATREG, "FReg" },
2396 { OPERAND_TYPE_FLOATACC, "FAcc" },
2397 { OPERAND_TYPE_SREG2, "SReg2" },
2398 { OPERAND_TYPE_SREG3, "SReg3" },
2399 { OPERAND_TYPE_ACC, "Acc" },
2400 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2401 { OPERAND_TYPE_REGMMX, "rMMX" },
2402 { OPERAND_TYPE_REGXMM, "rXMM" },
2403 { OPERAND_TYPE_REGYMM, "rYMM" },
2404 { OPERAND_TYPE_ESSEG, "es" },
2408 pt (i386_operand_type t)
2411 i386_operand_type a;
2413 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2415 a = operand_type_and (t, type_names[j].mask);
2416 if (!operand_type_all_zero (&a))
2417 fprintf (stdout, "%s, ", type_names[j].name);
2422 #endif /* DEBUG386 */
2424 static bfd_reloc_code_real_type
2425 reloc (unsigned int size,
2428 bfd_reloc_code_real_type other)
2430 if (other != NO_RELOC)
2432 reloc_howto_type *reloc;
2437 case BFD_RELOC_X86_64_GOT32:
2438 return BFD_RELOC_X86_64_GOT64;
2440 case BFD_RELOC_X86_64_PLTOFF64:
2441 return BFD_RELOC_X86_64_PLTOFF64;
2443 case BFD_RELOC_X86_64_GOTPC32:
2444 other = BFD_RELOC_X86_64_GOTPC64;
2446 case BFD_RELOC_X86_64_GOTPCREL:
2447 other = BFD_RELOC_X86_64_GOTPCREL64;
2449 case BFD_RELOC_X86_64_TPOFF32:
2450 other = BFD_RELOC_X86_64_TPOFF64;
2452 case BFD_RELOC_X86_64_DTPOFF32:
2453 other = BFD_RELOC_X86_64_DTPOFF64;
2459 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2460 if (size == 4 && flag_code != CODE_64BIT)
2463 reloc = bfd_reloc_type_lookup (stdoutput, other);
2465 as_bad (_("unknown relocation (%u)"), other);
2466 else if (size != bfd_get_reloc_size (reloc))
2467 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2468 bfd_get_reloc_size (reloc),
2470 else if (pcrel && !reloc->pc_relative)
2471 as_bad (_("non-pc-relative relocation for pc-relative field"));
2472 else if ((reloc->complain_on_overflow == complain_overflow_signed
2474 || (reloc->complain_on_overflow == complain_overflow_unsigned
2476 as_bad (_("relocated field and relocation type differ in signedness"));
2485 as_bad (_("there are no unsigned pc-relative relocations"));
2488 case 1: return BFD_RELOC_8_PCREL;
2489 case 2: return BFD_RELOC_16_PCREL;
2490 case 4: return BFD_RELOC_32_PCREL;
2491 case 8: return BFD_RELOC_64_PCREL;
2493 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2500 case 4: return BFD_RELOC_X86_64_32S;
2505 case 1: return BFD_RELOC_8;
2506 case 2: return BFD_RELOC_16;
2507 case 4: return BFD_RELOC_32;
2508 case 8: return BFD_RELOC_64;
2510 as_bad (_("cannot do %s %u byte relocation"),
2511 sign > 0 ? "signed" : "unsigned", size);
2517 /* Here we decide which fixups can be adjusted to make them relative to
2518 the beginning of the section instead of the symbol. Basically we need
2519 to make sure that the dynamic relocations are done correctly, so in
2520 some cases we force the original symbol to be used. */
2523 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2525 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2529 /* Don't adjust pc-relative references to merge sections in 64-bit
2531 if (use_rela_relocations
2532 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2536 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2537 and changed later by validate_fix. */
2538 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2539 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2542 /* adjust_reloc_syms doesn't know about the GOT. */
2543 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2544 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2545 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2546 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2547 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2548 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2549 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2550 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2551 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2552 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2553 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2554 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2555 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2556 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2557 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2558 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2559 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2560 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2561 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2562 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2563 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2564 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2565 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2566 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2567 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2568 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2569 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2570 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2577 intel_float_operand (const char *mnemonic)
2579 /* Note that the value returned is meaningful only for opcodes with (memory)
2580 operands, hence the code here is free to improperly handle opcodes that
2581 have no operands (for better performance and smaller code). */
2583 if (mnemonic[0] != 'f')
2584 return 0; /* non-math */
2586 switch (mnemonic[1])
2588 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2589 the fs segment override prefix not currently handled because no
2590 call path can make opcodes without operands get here */
2592 return 2 /* integer op */;
2594 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2595 return 3; /* fldcw/fldenv */
2598 if (mnemonic[2] != 'o' /* fnop */)
2599 return 3; /* non-waiting control op */
2602 if (mnemonic[2] == 's')
2603 return 3; /* frstor/frstpm */
2606 if (mnemonic[2] == 'a')
2607 return 3; /* fsave */
2608 if (mnemonic[2] == 't')
2610 switch (mnemonic[3])
2612 case 'c': /* fstcw */
2613 case 'd': /* fstdw */
2614 case 'e': /* fstenv */
2615 case 's': /* fsts[gw] */
2621 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2622 return 0; /* fxsave/fxrstor are not really math ops */
2629 /* Build the VEX prefix. */
2632 build_vex_prefix (const insn_template *t)
2634 unsigned int register_specifier;
2635 unsigned int implied_prefix;
2636 unsigned int vector_length;
2638 /* Check register specifier. */
2639 if (i.vex.register_specifier)
2641 register_specifier = i.vex.register_specifier->reg_num;
2642 if ((i.vex.register_specifier->reg_flags & RegRex))
2643 register_specifier += 8;
2644 register_specifier = ~register_specifier & 0xf;
2647 register_specifier = 0xf;
2649 /* Use 2-byte VEX prefix by swappping destination and source
2652 && i.operands == i.reg_operands
2653 && i.tm.opcode_modifier.vex0f
2654 && i.tm.opcode_modifier.s
2657 unsigned int xchg = i.operands - 1;
2658 union i386_op temp_op;
2659 i386_operand_type temp_type;
2661 temp_type = i.types[xchg];
2662 i.types[xchg] = i.types[0];
2663 i.types[0] = temp_type;
2664 temp_op = i.op[xchg];
2665 i.op[xchg] = i.op[0];
2668 gas_assert (i.rm.mode == 3);
2672 i.rm.regmem = i.rm.reg;
2675 /* Use the next insn. */
2679 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2681 switch ((i.tm.base_opcode >> 8) & 0xff)
2686 case DATA_PREFIX_OPCODE:
2689 case REPE_PREFIX_OPCODE:
2692 case REPNE_PREFIX_OPCODE:
2699 /* Use 2-byte VEX prefix if possible. */
2700 if (i.tm.opcode_modifier.vex0f
2701 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2703 /* 2-byte VEX prefix. */
2707 i.vex.bytes[0] = 0xc5;
2709 /* Check the REX.R bit. */
2710 r = (i.rex & REX_R) ? 0 : 1;
2711 i.vex.bytes[1] = (r << 7
2712 | register_specifier << 3
2713 | vector_length << 2
2718 /* 3-byte VEX prefix. */
2721 if (i.tm.opcode_modifier.vex0f)
2723 else if (i.tm.opcode_modifier.vex0f38)
2725 else if (i.tm.opcode_modifier.vex0f3a)
2731 i.vex.bytes[0] = 0xc4;
2733 /* The high 3 bits of the second VEX byte are 1's compliment
2734 of RXB bits from REX. */
2735 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2737 /* Check the REX.W bit. */
2738 w = (i.rex & REX_W) ? 1 : 0;
2739 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2744 if (i.tm.opcode_modifier.vexw1)
2748 i.vex.bytes[2] = (w << 7
2749 | register_specifier << 3
2750 | vector_length << 2
2756 process_immext (void)
2760 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2762 /* SSE3 Instructions have the fixed operands with an opcode
2763 suffix which is coded in the same place as an 8-bit immediate
2764 field would be. Here we check those operands and remove them
2768 for (x = 0; x < i.operands; x++)
2769 if (i.op[x].regs->reg_num != x)
2770 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2771 register_prefix, i.op[x].regs->reg_name, x + 1,
2777 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2778 which is coded in the same place as an 8-bit immediate field
2779 would be. Here we fake an 8-bit immediate operand from the
2780 opcode suffix stored in tm.extension_opcode.
2782 AVX instructions also use this encoding, for some of
2783 3 argument instructions. */
2785 gas_assert (i.imm_operands == 0
2787 || (i.tm.opcode_modifier.vex
2788 && i.operands <= 4)));
2790 exp = &im_expressions[i.imm_operands++];
2791 i.op[i.operands].imms = exp;
2792 i.types[i.operands] = imm8;
2794 exp->X_op = O_constant;
2795 exp->X_add_number = i.tm.extension_opcode;
2796 i.tm.extension_opcode = None;
2799 /* This is the guts of the machine-dependent assembler. LINE points to a
2800 machine dependent instruction. This function is supposed to emit
2801 the frags/bytes it assembles to. */
2804 md_assemble (char *line)
2807 char mnemonic[MAX_MNEM_SIZE];
2808 const insn_template *t;
2810 /* Initialize globals. */
2811 memset (&i, '\0', sizeof (i));
2812 for (j = 0; j < MAX_OPERANDS; j++)
2813 i.reloc[j] = NO_RELOC;
2814 memset (disp_expressions, '\0', sizeof (disp_expressions));
2815 memset (im_expressions, '\0', sizeof (im_expressions));
2816 save_stack_p = save_stack;
2818 /* First parse an instruction mnemonic & call i386_operand for the operands.
2819 We assume that the scrubber has arranged it so that line[0] is the valid
2820 start of a (possibly prefixed) mnemonic. */
2822 line = parse_insn (line, mnemonic);
2826 line = parse_operands (line, mnemonic);
2831 /* Now we've parsed the mnemonic into a set of templates, and have the
2832 operands at hand. */
2834 /* All intel opcodes have reversed operands except for "bound" and
2835 "enter". We also don't reverse intersegment "jmp" and "call"
2836 instructions with 2 immediate operands so that the immediate segment
2837 precedes the offset, as it does when in AT&T mode. */
2840 && (strcmp (mnemonic, "bound") != 0)
2841 && (strcmp (mnemonic, "invlpga") != 0)
2842 && !(operand_type_check (i.types[0], imm)
2843 && operand_type_check (i.types[1], imm)))
2846 /* The order of the immediates should be reversed
2847 for 2 immediates extrq and insertq instructions */
2848 if (i.imm_operands == 2
2849 && (strcmp (mnemonic, "extrq") == 0
2850 || strcmp (mnemonic, "insertq") == 0))
2851 swap_2_operands (0, 1);
2856 /* Don't optimize displacement for movabs since it only takes 64bit
2859 && (flag_code != CODE_64BIT
2860 || strcmp (mnemonic, "movabs") != 0))
2863 /* Next, we find a template that matches the given insn,
2864 making sure the overlap of the given operands types is consistent
2865 with the template operand types. */
2867 if (!(t = match_template ()))
2870 if (sse_check != sse_check_none
2871 && !i.tm.opcode_modifier.noavx
2872 && (i.tm.cpu_flags.bitfield.cpusse
2873 || i.tm.cpu_flags.bitfield.cpusse2
2874 || i.tm.cpu_flags.bitfield.cpusse3
2875 || i.tm.cpu_flags.bitfield.cpussse3
2876 || i.tm.cpu_flags.bitfield.cpusse4_1
2877 || i.tm.cpu_flags.bitfield.cpusse4_2))
2879 (sse_check == sse_check_warning
2881 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2884 /* Zap movzx and movsx suffix. The suffix has been set from
2885 "word ptr" or "byte ptr" on the source operand in Intel syntax
2886 or extracted from mnemonic in AT&T syntax. But we'll use
2887 the destination register to choose the suffix for encoding. */
2888 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2890 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2891 there is no suffix, the default will be byte extension. */
2892 if (i.reg_operands != 2
2895 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2900 if (i.tm.opcode_modifier.fwait)
2901 if (!add_prefix (FWAIT_OPCODE))
2904 /* Check string instruction segment overrides. */
2905 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2907 if (!check_string ())
2909 i.disp_operands = 0;
2912 if (!process_suffix ())
2915 /* Update operand types. */
2916 for (j = 0; j < i.operands; j++)
2917 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2919 /* Make still unresolved immediate matches conform to size of immediate
2920 given in i.suffix. */
2921 if (!finalize_imm ())
2924 if (i.types[0].bitfield.imm1)
2925 i.imm_operands = 0; /* kludge for shift insns. */
2927 /* We only need to check those implicit registers for instructions
2928 with 3 operands or less. */
2929 if (i.operands <= 3)
2930 for (j = 0; j < i.operands; j++)
2931 if (i.types[j].bitfield.inoutportreg
2932 || i.types[j].bitfield.shiftcount
2933 || i.types[j].bitfield.acc
2934 || i.types[j].bitfield.floatacc)
2937 /* ImmExt should be processed after SSE2AVX. */
2938 if (!i.tm.opcode_modifier.sse2avx
2939 && i.tm.opcode_modifier.immext)
2942 /* For insns with operands there are more diddles to do to the opcode. */
2945 if (!process_operands ())
2948 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2950 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2951 as_warn (_("translating to `%sp'"), i.tm.name);
2954 if (i.tm.opcode_modifier.vex)
2955 build_vex_prefix (t);
2957 /* Handle conversion of 'int $3' --> special int3 insn. */
2958 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2960 i.tm.base_opcode = INT3_OPCODE;
2964 if ((i.tm.opcode_modifier.jump
2965 || i.tm.opcode_modifier.jumpbyte
2966 || i.tm.opcode_modifier.jumpdword)
2967 && i.op[0].disps->X_op == O_constant)
2969 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2970 the absolute address given by the constant. Since ix86 jumps and
2971 calls are pc relative, we need to generate a reloc. */
2972 i.op[0].disps->X_add_symbol = &abs_symbol;
2973 i.op[0].disps->X_op = O_symbol;
2976 if (i.tm.opcode_modifier.rex64)
2979 /* For 8 bit registers we need an empty rex prefix. Also if the
2980 instruction already has a prefix, we need to convert old
2981 registers to new ones. */
2983 if ((i.types[0].bitfield.reg8
2984 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2985 || (i.types[1].bitfield.reg8
2986 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2987 || ((i.types[0].bitfield.reg8
2988 || i.types[1].bitfield.reg8)
2993 i.rex |= REX_OPCODE;
2994 for (x = 0; x < 2; x++)
2996 /* Look for 8 bit operand that uses old registers. */
2997 if (i.types[x].bitfield.reg8
2998 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3000 /* In case it is "hi" register, give up. */
3001 if (i.op[x].regs->reg_num > 3)
3002 as_bad (_("can't encode register '%s%s' in an "
3003 "instruction requiring REX prefix."),
3004 register_prefix, i.op[x].regs->reg_name);
3006 /* Otherwise it is equivalent to the extended register.
3007 Since the encoding doesn't change this is merely
3008 cosmetic cleanup for debug output. */
3010 i.op[x].regs = i.op[x].regs + 8;
3016 add_prefix (REX_OPCODE | i.rex);
3018 /* We are ready to output the insn. */
3023 parse_insn (char *line, char *mnemonic)
3026 char *token_start = l;
3029 const insn_template *t;
3032 /* Non-zero if we found a prefix only acceptable with string insns. */
3033 const char *expecting_string_instruction = NULL;
3038 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3043 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3045 as_bad (_("no such instruction: `%s'"), token_start);
3050 if (!is_space_char (*l)
3051 && *l != END_OF_INSN
3053 || (*l != PREFIX_SEPARATOR
3056 as_bad (_("invalid character %s in mnemonic"),
3057 output_invalid (*l));
3060 if (token_start == l)
3062 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3063 as_bad (_("expecting prefix; got nothing"));
3065 as_bad (_("expecting mnemonic; got nothing"));
3069 /* Look up instruction (or prefix) via hash table. */
3070 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3072 if (*l != END_OF_INSN
3073 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3074 && current_templates
3075 && current_templates->start->opcode_modifier.isprefix)
3077 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3079 as_bad ((flag_code != CODE_64BIT
3080 ? _("`%s' is only supported in 64-bit mode")
3081 : _("`%s' is not supported in 64-bit mode")),
3082 current_templates->start->name);
3085 /* If we are in 16-bit mode, do not allow addr16 or data16.
3086 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3087 if ((current_templates->start->opcode_modifier.size16
3088 || current_templates->start->opcode_modifier.size32)
3089 && flag_code != CODE_64BIT
3090 && (current_templates->start->opcode_modifier.size32
3091 ^ (flag_code == CODE_16BIT)))
3093 as_bad (_("redundant %s prefix"),
3094 current_templates->start->name);
3097 /* Add prefix, checking for repeated prefixes. */
3098 switch (add_prefix (current_templates->start->base_opcode))
3103 expecting_string_instruction = current_templates->start->name;
3106 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3113 if (!current_templates)
3115 /* Check if we should swap operand in encoding. */
3116 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3122 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3125 if (!current_templates)
3128 /* See if we can get a match by trimming off a suffix. */
3131 case WORD_MNEM_SUFFIX:
3132 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3133 i.suffix = SHORT_MNEM_SUFFIX;
3135 case BYTE_MNEM_SUFFIX:
3136 case QWORD_MNEM_SUFFIX:
3137 i.suffix = mnem_p[-1];
3139 current_templates = (const templates *) hash_find (op_hash,
3142 case SHORT_MNEM_SUFFIX:
3143 case LONG_MNEM_SUFFIX:
3146 i.suffix = mnem_p[-1];
3148 current_templates = (const templates *) hash_find (op_hash,
3157 if (intel_float_operand (mnemonic) == 1)
3158 i.suffix = SHORT_MNEM_SUFFIX;
3160 i.suffix = LONG_MNEM_SUFFIX;
3162 current_templates = (const templates *) hash_find (op_hash,
3167 if (!current_templates)
3169 as_bad (_("no such instruction: `%s'"), token_start);
3174 if (current_templates->start->opcode_modifier.jump
3175 || current_templates->start->opcode_modifier.jumpbyte)
3177 /* Check for a branch hint. We allow ",pt" and ",pn" for
3178 predict taken and predict not taken respectively.
3179 I'm not sure that branch hints actually do anything on loop
3180 and jcxz insns (JumpByte) for current Pentium4 chips. They
3181 may work in the future and it doesn't hurt to accept them
3183 if (l[0] == ',' && l[1] == 'p')
3187 if (!add_prefix (DS_PREFIX_OPCODE))
3191 else if (l[2] == 'n')
3193 if (!add_prefix (CS_PREFIX_OPCODE))
3199 /* Any other comma loses. */
3202 as_bad (_("invalid character %s in mnemonic"),
3203 output_invalid (*l));
3207 /* Check if instruction is supported on specified architecture. */
3209 for (t = current_templates->start; t < current_templates->end; ++t)
3211 supported |= cpu_flags_match (t);
3212 if (supported == CPU_FLAGS_PERFECT_MATCH)
3216 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3218 as_bad (flag_code == CODE_64BIT
3219 ? _("`%s' is not supported in 64-bit mode")
3220 : _("`%s' is only supported in 64-bit mode"),
3221 current_templates->start->name);
3224 if (supported != CPU_FLAGS_PERFECT_MATCH)
3226 as_bad (_("`%s' is not supported on `%s%s'"),
3227 current_templates->start->name,
3228 cpu_arch_name ? cpu_arch_name : default_arch,
3229 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3234 if (!cpu_arch_flags.bitfield.cpui386
3235 && (flag_code != CODE_16BIT))
3237 as_warn (_("use .code16 to ensure correct addressing mode"));
3240 /* Check for rep/repne without a string instruction. */
3241 if (expecting_string_instruction)
3243 static templates override;
3245 for (t = current_templates->start; t < current_templates->end; ++t)
3246 if (t->opcode_modifier.isstring)
3248 if (t >= current_templates->end)
3250 as_bad (_("expecting string instruction after `%s'"),
3251 expecting_string_instruction);
3254 for (override.start = t; t < current_templates->end; ++t)
3255 if (!t->opcode_modifier.isstring)
3258 current_templates = &override;
3265 parse_operands (char *l, const char *mnemonic)
3269 /* 1 if operand is pending after ','. */
3270 unsigned int expecting_operand = 0;
3272 /* Non-zero if operand parens not balanced. */
3273 unsigned int paren_not_balanced;
3275 while (*l != END_OF_INSN)
3277 /* Skip optional white space before operand. */
3278 if (is_space_char (*l))
3280 if (!is_operand_char (*l) && *l != END_OF_INSN)
3282 as_bad (_("invalid character %s before operand %d"),
3283 output_invalid (*l),
3287 token_start = l; /* after white space */
3288 paren_not_balanced = 0;
3289 while (paren_not_balanced || *l != ',')
3291 if (*l == END_OF_INSN)
3293 if (paren_not_balanced)
3296 as_bad (_("unbalanced parenthesis in operand %d."),
3299 as_bad (_("unbalanced brackets in operand %d."),
3304 break; /* we are done */
3306 else if (!is_operand_char (*l) && !is_space_char (*l))
3308 as_bad (_("invalid character %s in operand %d"),
3309 output_invalid (*l),
3316 ++paren_not_balanced;
3318 --paren_not_balanced;
3323 ++paren_not_balanced;
3325 --paren_not_balanced;
3329 if (l != token_start)
3330 { /* Yes, we've read in another operand. */
3331 unsigned int operand_ok;
3332 this_operand = i.operands++;
3333 i.types[this_operand].bitfield.unspecified = 1;
3334 if (i.operands > MAX_OPERANDS)
3336 as_bad (_("spurious operands; (%d operands/instruction max)"),
3340 /* Now parse operand adding info to 'i' as we go along. */
3341 END_STRING_AND_SAVE (l);
3345 i386_intel_operand (token_start,
3346 intel_float_operand (mnemonic));
3348 operand_ok = i386_att_operand (token_start);
3350 RESTORE_END_STRING (l);
3356 if (expecting_operand)
3358 expecting_operand_after_comma:
3359 as_bad (_("expecting operand after ','; got nothing"));
3364 as_bad (_("expecting operand before ','; got nothing"));
3369 /* Now *l must be either ',' or END_OF_INSN. */
3372 if (*++l == END_OF_INSN)
3374 /* Just skip it, if it's \n complain. */
3375 goto expecting_operand_after_comma;
3377 expecting_operand = 1;
3384 swap_2_operands (int xchg1, int xchg2)
3386 union i386_op temp_op;
3387 i386_operand_type temp_type;
3388 enum bfd_reloc_code_real temp_reloc;
3390 temp_type = i.types[xchg2];
3391 i.types[xchg2] = i.types[xchg1];
3392 i.types[xchg1] = temp_type;
3393 temp_op = i.op[xchg2];
3394 i.op[xchg2] = i.op[xchg1];
3395 i.op[xchg1] = temp_op;
3396 temp_reloc = i.reloc[xchg2];
3397 i.reloc[xchg2] = i.reloc[xchg1];
3398 i.reloc[xchg1] = temp_reloc;
3402 swap_operands (void)
3408 swap_2_operands (1, i.operands - 2);
3411 swap_2_operands (0, i.operands - 1);
3417 if (i.mem_operands == 2)
3419 const seg_entry *temp_seg;
3420 temp_seg = i.seg[0];
3421 i.seg[0] = i.seg[1];
3422 i.seg[1] = temp_seg;
3426 /* Try to ensure constant immediates are represented in the smallest
3431 char guess_suffix = 0;
3435 guess_suffix = i.suffix;
3436 else if (i.reg_operands)
3438 /* Figure out a suffix from the last register operand specified.
3439 We can't do this properly yet, ie. excluding InOutPortReg,
3440 but the following works for instructions with immediates.
3441 In any case, we can't set i.suffix yet. */
3442 for (op = i.operands; --op >= 0;)
3443 if (i.types[op].bitfield.reg8)
3445 guess_suffix = BYTE_MNEM_SUFFIX;
3448 else if (i.types[op].bitfield.reg16)
3450 guess_suffix = WORD_MNEM_SUFFIX;
3453 else if (i.types[op].bitfield.reg32)
3455 guess_suffix = LONG_MNEM_SUFFIX;
3458 else if (i.types[op].bitfield.reg64)
3460 guess_suffix = QWORD_MNEM_SUFFIX;
3464 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3465 guess_suffix = WORD_MNEM_SUFFIX;
3467 for (op = i.operands; --op >= 0;)
3468 if (operand_type_check (i.types[op], imm))
3470 switch (i.op[op].imms->X_op)
3473 /* If a suffix is given, this operand may be shortened. */
3474 switch (guess_suffix)
3476 case LONG_MNEM_SUFFIX:
3477 i.types[op].bitfield.imm32 = 1;
3478 i.types[op].bitfield.imm64 = 1;
3480 case WORD_MNEM_SUFFIX:
3481 i.types[op].bitfield.imm16 = 1;
3482 i.types[op].bitfield.imm32 = 1;
3483 i.types[op].bitfield.imm32s = 1;
3484 i.types[op].bitfield.imm64 = 1;
3486 case BYTE_MNEM_SUFFIX:
3487 i.types[op].bitfield.imm8 = 1;
3488 i.types[op].bitfield.imm8s = 1;
3489 i.types[op].bitfield.imm16 = 1;
3490 i.types[op].bitfield.imm32 = 1;
3491 i.types[op].bitfield.imm32s = 1;
3492 i.types[op].bitfield.imm64 = 1;
3496 /* If this operand is at most 16 bits, convert it
3497 to a signed 16 bit number before trying to see
3498 whether it will fit in an even smaller size.
3499 This allows a 16-bit operand such as $0xffe0 to
3500 be recognised as within Imm8S range. */
3501 if ((i.types[op].bitfield.imm16)
3502 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3504 i.op[op].imms->X_add_number =
3505 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3507 if ((i.types[op].bitfield.imm32)
3508 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3511 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3512 ^ ((offsetT) 1 << 31))
3513 - ((offsetT) 1 << 31));
3516 = operand_type_or (i.types[op],
3517 smallest_imm_type (i.op[op].imms->X_add_number));
3519 /* We must avoid matching of Imm32 templates when 64bit
3520 only immediate is available. */
3521 if (guess_suffix == QWORD_MNEM_SUFFIX)
3522 i.types[op].bitfield.imm32 = 0;
3529 /* Symbols and expressions. */
3531 /* Convert symbolic operand to proper sizes for matching, but don't
3532 prevent matching a set of insns that only supports sizes other
3533 than those matching the insn suffix. */
3535 i386_operand_type mask, allowed;
3536 const insn_template *t;
3538 operand_type_set (&mask, 0);
3539 operand_type_set (&allowed, 0);
3541 for (t = current_templates->start;
3542 t < current_templates->end;
3544 allowed = operand_type_or (allowed,
3545 t->operand_types[op]);
3546 switch (guess_suffix)
3548 case QWORD_MNEM_SUFFIX:
3549 mask.bitfield.imm64 = 1;
3550 mask.bitfield.imm32s = 1;
3552 case LONG_MNEM_SUFFIX:
3553 mask.bitfield.imm32 = 1;
3555 case WORD_MNEM_SUFFIX:
3556 mask.bitfield.imm16 = 1;
3558 case BYTE_MNEM_SUFFIX:
3559 mask.bitfield.imm8 = 1;
3564 allowed = operand_type_and (mask, allowed);
3565 if (!operand_type_all_zero (&allowed))
3566 i.types[op] = operand_type_and (i.types[op], mask);
3573 /* Try to use the smallest displacement type too. */
3575 optimize_disp (void)
3579 for (op = i.operands; --op >= 0;)
3580 if (operand_type_check (i.types[op], disp))
3582 if (i.op[op].disps->X_op == O_constant)
3584 offsetT disp = i.op[op].disps->X_add_number;
3586 if (i.types[op].bitfield.disp16
3587 && (disp & ~(offsetT) 0xffff) == 0)
3589 /* If this operand is at most 16 bits, convert
3590 to a signed 16 bit number and don't use 64bit
3592 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3593 i.types[op].bitfield.disp64 = 0;
3595 if (i.types[op].bitfield.disp32
3596 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3598 /* If this operand is at most 32 bits, convert
3599 to a signed 32 bit number and don't use 64bit
3601 disp &= (((offsetT) 2 << 31) - 1);
3602 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3603 i.types[op].bitfield.disp64 = 0;
3605 if (!disp && i.types[op].bitfield.baseindex)
3607 i.types[op].bitfield.disp8 = 0;
3608 i.types[op].bitfield.disp16 = 0;
3609 i.types[op].bitfield.disp32 = 0;
3610 i.types[op].bitfield.disp32s = 0;
3611 i.types[op].bitfield.disp64 = 0;
3615 else if (flag_code == CODE_64BIT)
3617 if (fits_in_signed_long (disp))
3619 i.types[op].bitfield.disp64 = 0;
3620 i.types[op].bitfield.disp32s = 1;
3622 if (fits_in_unsigned_long (disp))
3623 i.types[op].bitfield.disp32 = 1;
3625 if ((i.types[op].bitfield.disp32
3626 || i.types[op].bitfield.disp32s
3627 || i.types[op].bitfield.disp16)
3628 && fits_in_signed_byte (disp))
3629 i.types[op].bitfield.disp8 = 1;
3631 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3632 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3634 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3635 i.op[op].disps, 0, i.reloc[op]);
3636 i.types[op].bitfield.disp8 = 0;
3637 i.types[op].bitfield.disp16 = 0;
3638 i.types[op].bitfield.disp32 = 0;
3639 i.types[op].bitfield.disp32s = 0;
3640 i.types[op].bitfield.disp64 = 0;
3643 /* We only support 64bit displacement on constants. */
3644 i.types[op].bitfield.disp64 = 0;
3648 static const insn_template *
3649 match_template (void)
3651 /* Points to template once we've found it. */
3652 const insn_template *t;
3653 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3654 i386_operand_type overlap4;
3655 unsigned int found_reverse_match;
3656 i386_opcode_modifier suffix_check;
3657 i386_operand_type operand_types [MAX_OPERANDS];
3658 int addr_prefix_disp;
3660 unsigned int found_cpu_match;
3661 unsigned int check_register;
3663 #if MAX_OPERANDS != 5
3664 # error "MAX_OPERANDS must be 5."
3667 found_reverse_match = 0;
3668 addr_prefix_disp = -1;
3670 memset (&suffix_check, 0, sizeof (suffix_check));
3671 if (i.suffix == BYTE_MNEM_SUFFIX)
3672 suffix_check.no_bsuf = 1;
3673 else if (i.suffix == WORD_MNEM_SUFFIX)
3674 suffix_check.no_wsuf = 1;
3675 else if (i.suffix == SHORT_MNEM_SUFFIX)
3676 suffix_check.no_ssuf = 1;
3677 else if (i.suffix == LONG_MNEM_SUFFIX)
3678 suffix_check.no_lsuf = 1;
3679 else if (i.suffix == QWORD_MNEM_SUFFIX)
3680 suffix_check.no_qsuf = 1;
3681 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3682 suffix_check.no_ldsuf = 1;
3684 for (t = current_templates->start; t < current_templates->end; t++)
3686 addr_prefix_disp = -1;
3688 /* Must have right number of operands. */
3689 if (i.operands != t->operands)
3692 /* Check processor support. */
3693 found_cpu_match = (cpu_flags_match (t)
3694 == CPU_FLAGS_PERFECT_MATCH);
3695 if (!found_cpu_match)
3698 /* Check old gcc support. */
3699 if (!old_gcc && t->opcode_modifier.oldgcc)
3702 /* Check AT&T mnemonic. */
3703 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3706 /* Check AT&T syntax Intel syntax. */
3707 if ((intel_syntax && t->opcode_modifier.attsyntax)
3708 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3711 /* Check the suffix, except for some instructions in intel mode. */
3712 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3713 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3714 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3715 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3716 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3717 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3718 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3721 if (!operand_size_match (t))
3724 for (j = 0; j < MAX_OPERANDS; j++)
3725 operand_types[j] = t->operand_types[j];
3727 /* In general, don't allow 64-bit operands in 32-bit mode. */
3728 if (i.suffix == QWORD_MNEM_SUFFIX
3729 && flag_code != CODE_64BIT
3731 ? (!t->opcode_modifier.ignoresize
3732 && !intel_float_operand (t->name))
3733 : intel_float_operand (t->name) != 2)
3734 && ((!operand_types[0].bitfield.regmmx
3735 && !operand_types[0].bitfield.regxmm
3736 && !operand_types[0].bitfield.regymm)
3737 || (!operand_types[t->operands > 1].bitfield.regmmx
3738 && !!operand_types[t->operands > 1].bitfield.regxmm
3739 && !!operand_types[t->operands > 1].bitfield.regymm))
3740 && (t->base_opcode != 0x0fc7
3741 || t->extension_opcode != 1 /* cmpxchg8b */))
3744 /* In general, don't allow 32-bit operands on pre-386. */
3745 else if (i.suffix == LONG_MNEM_SUFFIX
3746 && !cpu_arch_flags.bitfield.cpui386
3748 ? (!t->opcode_modifier.ignoresize
3749 && !intel_float_operand (t->name))
3750 : intel_float_operand (t->name) != 2)
3751 && ((!operand_types[0].bitfield.regmmx
3752 && !operand_types[0].bitfield.regxmm)
3753 || (!operand_types[t->operands > 1].bitfield.regmmx
3754 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3757 /* Do not verify operands when there are none. */
3761 /* We've found a match; break out of loop. */
3765 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3766 into Disp32/Disp16/Disp32 operand. */
3767 if (i.prefix[ADDR_PREFIX] != 0)
3769 /* There should be only one Disp operand. */
3773 for (j = 0; j < MAX_OPERANDS; j++)
3775 if (operand_types[j].bitfield.disp16)
3777 addr_prefix_disp = j;
3778 operand_types[j].bitfield.disp32 = 1;
3779 operand_types[j].bitfield.disp16 = 0;
3785 for (j = 0; j < MAX_OPERANDS; j++)
3787 if (operand_types[j].bitfield.disp32)
3789 addr_prefix_disp = j;
3790 operand_types[j].bitfield.disp32 = 0;
3791 operand_types[j].bitfield.disp16 = 1;
3797 for (j = 0; j < MAX_OPERANDS; j++)
3799 if (operand_types[j].bitfield.disp64)
3801 addr_prefix_disp = j;
3802 operand_types[j].bitfield.disp64 = 0;
3803 operand_types[j].bitfield.disp32 = 1;
3811 /* We check register size only if size of operands can be
3812 encoded the canonical way. */
3813 check_register = t->opcode_modifier.w;
3814 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3815 switch (t->operands)
3818 if (!operand_type_match (overlap0, i.types[0]))
3822 /* xchg %eax, %eax is a special case. It is an aliase for nop
3823 only in 32bit mode and we can use opcode 0x90. In 64bit
3824 mode, we can't use 0x90 for xchg %eax, %eax since it should
3825 zero-extend %eax to %rax. */
3826 if (flag_code == CODE_64BIT
3827 && t->base_opcode == 0x90
3828 && operand_type_equal (&i.types [0], &acc32)
3829 && operand_type_equal (&i.types [1], &acc32))
3833 /* If we swap operand in encoding, we either match
3834 the next one or reverse direction of operands. */
3835 if (t->opcode_modifier.s)
3837 else if (t->opcode_modifier.d)
3842 /* If we swap operand in encoding, we match the next one. */
3843 if (i.swap_operand && t->opcode_modifier.s)
3847 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3848 if (!operand_type_match (overlap0, i.types[0])
3849 || !operand_type_match (overlap1, i.types[1])
3851 && !operand_type_register_match (overlap0, i.types[0],
3853 overlap1, i.types[1],
3856 /* Check if other direction is valid ... */
3857 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3861 /* Try reversing direction of operands. */
3862 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3863 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3864 if (!operand_type_match (overlap0, i.types[0])
3865 || !operand_type_match (overlap1, i.types[1])
3867 && !operand_type_register_match (overlap0,
3874 /* Does not match either direction. */
3877 /* found_reverse_match holds which of D or FloatDR
3879 if (t->opcode_modifier.d)
3880 found_reverse_match = Opcode_D;
3881 else if (t->opcode_modifier.floatd)
3882 found_reverse_match = Opcode_FloatD;
3884 found_reverse_match = 0;
3885 if (t->opcode_modifier.floatr)
3886 found_reverse_match |= Opcode_FloatR;
3890 /* Found a forward 2 operand match here. */
3891 switch (t->operands)
3894 overlap4 = operand_type_and (i.types[4],
3897 overlap3 = operand_type_and (i.types[3],
3900 overlap2 = operand_type_and (i.types[2],
3905 switch (t->operands)
3908 if (!operand_type_match (overlap4, i.types[4])
3909 || !operand_type_register_match (overlap3,
3917 if (!operand_type_match (overlap3, i.types[3])
3919 && !operand_type_register_match (overlap2,
3927 /* Here we make use of the fact that there are no
3928 reverse match 3 operand instructions, and all 3
3929 operand instructions only need to be checked for
3930 register consistency between operands 2 and 3. */
3931 if (!operand_type_match (overlap2, i.types[2])
3933 && !operand_type_register_match (overlap1,
3943 /* Found either forward/reverse 2, 3 or 4 operand match here:
3944 slip through to break. */
3946 if (!found_cpu_match)
3948 found_reverse_match = 0;
3952 /* We've found a match; break out of loop. */
3956 if (t == current_templates->end)
3958 /* We found no match. */
3960 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3961 current_templates->start->name);
3963 as_bad (_("suffix or operands invalid for `%s'"),
3964 current_templates->start->name);
3968 if (!quiet_warnings)
3971 && (i.types[0].bitfield.jumpabsolute
3972 != operand_types[0].bitfield.jumpabsolute))
3974 as_warn (_("indirect %s without `*'"), t->name);
3977 if (t->opcode_modifier.isprefix
3978 && t->opcode_modifier.ignoresize)
3980 /* Warn them that a data or address size prefix doesn't
3981 affect assembly of the next line of code. */
3982 as_warn (_("stand-alone `%s' prefix"), t->name);
3986 /* Copy the template we found. */
3989 if (addr_prefix_disp != -1)
3990 i.tm.operand_types[addr_prefix_disp]
3991 = operand_types[addr_prefix_disp];
3993 if (found_reverse_match)
3995 /* If we found a reverse match we must alter the opcode
3996 direction bit. found_reverse_match holds bits to change
3997 (different for int & float insns). */
3999 i.tm.base_opcode ^= found_reverse_match;
4001 i.tm.operand_types[0] = operand_types[1];
4002 i.tm.operand_types[1] = operand_types[0];
4011 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4012 if (i.tm.operand_types[mem_op].bitfield.esseg)
4014 if (i.seg[0] != NULL && i.seg[0] != &es)
4016 as_bad (_("`%s' operand %d must use `%ses' segment"),
4022 /* There's only ever one segment override allowed per instruction.
4023 This instruction possibly has a legal segment override on the
4024 second operand, so copy the segment to where non-string
4025 instructions store it, allowing common code. */
4026 i.seg[0] = i.seg[1];
4028 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
4030 if (i.seg[1] != NULL && i.seg[1] != &es)
4032 as_bad (_("`%s' operand %d must use `%ses' segment"),
4043 process_suffix (void)
4045 /* If matched instruction specifies an explicit instruction mnemonic
4047 if (i.tm.opcode_modifier.size16)
4048 i.suffix = WORD_MNEM_SUFFIX;
4049 else if (i.tm.opcode_modifier.size32)
4050 i.suffix = LONG_MNEM_SUFFIX;
4051 else if (i.tm.opcode_modifier.size64)
4052 i.suffix = QWORD_MNEM_SUFFIX;
4053 else if (i.reg_operands)
4055 /* If there's no instruction mnemonic suffix we try to invent one
4056 based on register operands. */
4059 /* We take i.suffix from the last register operand specified,
4060 Destination register type is more significant than source
4061 register type. crc32 in SSE4.2 prefers source register
4063 if (i.tm.base_opcode == 0xf20f38f1)
4065 if (i.types[0].bitfield.reg16)
4066 i.suffix = WORD_MNEM_SUFFIX;
4067 else if (i.types[0].bitfield.reg32)
4068 i.suffix = LONG_MNEM_SUFFIX;
4069 else if (i.types[0].bitfield.reg64)
4070 i.suffix = QWORD_MNEM_SUFFIX;
4072 else if (i.tm.base_opcode == 0xf20f38f0)
4074 if (i.types[0].bitfield.reg8)
4075 i.suffix = BYTE_MNEM_SUFFIX;
4082 if (i.tm.base_opcode == 0xf20f38f1
4083 || i.tm.base_opcode == 0xf20f38f0)
4085 /* We have to know the operand size for crc32. */
4086 as_bad (_("ambiguous memory operand size for `%s`"),
4091 for (op = i.operands; --op >= 0;)
4092 if (!i.tm.operand_types[op].bitfield.inoutportreg)
4094 if (i.types[op].bitfield.reg8)
4096 i.suffix = BYTE_MNEM_SUFFIX;
4099 else if (i.types[op].bitfield.reg16)
4101 i.suffix = WORD_MNEM_SUFFIX;
4104 else if (i.types[op].bitfield.reg32)
4106 i.suffix = LONG_MNEM_SUFFIX;
4109 else if (i.types[op].bitfield.reg64)
4111 i.suffix = QWORD_MNEM_SUFFIX;
4117 else if (i.suffix == BYTE_MNEM_SUFFIX)
4119 if (!check_byte_reg ())
4122 else if (i.suffix == LONG_MNEM_SUFFIX)
4124 if (!check_long_reg ())
4127 else if (i.suffix == QWORD_MNEM_SUFFIX)
4130 && i.tm.opcode_modifier.ignoresize
4131 && i.tm.opcode_modifier.no_qsuf)
4133 else if (!check_qword_reg ())
4136 else if (i.suffix == WORD_MNEM_SUFFIX)
4138 if (!check_word_reg ())
4141 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4142 || i.suffix == YMMWORD_MNEM_SUFFIX)
4144 /* Skip if the instruction has x/y suffix. match_template
4145 should check if it is a valid suffix. */
4147 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
4148 /* Do nothing if the instruction is going to ignore the prefix. */
4153 else if (i.tm.opcode_modifier.defaultsize
4155 /* exclude fldenv/frstor/fsave/fstenv */
4156 && i.tm.opcode_modifier.no_ssuf)
4158 i.suffix = stackop_size;
4160 else if (intel_syntax
4162 && (i.tm.operand_types[0].bitfield.jumpabsolute
4163 || i.tm.opcode_modifier.jumpbyte
4164 || i.tm.opcode_modifier.jumpintersegment
4165 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4166 && i.tm.extension_opcode <= 3)))
4171 if (!i.tm.opcode_modifier.no_qsuf)
4173 i.suffix = QWORD_MNEM_SUFFIX;
4177 if (!i.tm.opcode_modifier.no_lsuf)
4178 i.suffix = LONG_MNEM_SUFFIX;
4181 if (!i.tm.opcode_modifier.no_wsuf)
4182 i.suffix = WORD_MNEM_SUFFIX;
4191 if (i.tm.opcode_modifier.w)
4193 as_bad (_("no instruction mnemonic suffix given and "
4194 "no register operands; can't size instruction"));
4200 unsigned int suffixes;
4202 suffixes = !i.tm.opcode_modifier.no_bsuf;
4203 if (!i.tm.opcode_modifier.no_wsuf)
4205 if (!i.tm.opcode_modifier.no_lsuf)
4207 if (!i.tm.opcode_modifier.no_ldsuf)
4209 if (!i.tm.opcode_modifier.no_ssuf)
4211 if (!i.tm.opcode_modifier.no_qsuf)
4214 /* There are more than suffix matches. */
4215 if (i.tm.opcode_modifier.w
4216 || ((suffixes & (suffixes - 1))
4217 && !i.tm.opcode_modifier.defaultsize
4218 && !i.tm.opcode_modifier.ignoresize))
4220 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4226 /* Change the opcode based on the operand size given by i.suffix;
4227 We don't need to change things for byte insns. */
4230 && i.suffix != BYTE_MNEM_SUFFIX
4231 && i.suffix != XMMWORD_MNEM_SUFFIX
4232 && i.suffix != YMMWORD_MNEM_SUFFIX)
4234 /* It's not a byte, select word/dword operation. */
4235 if (i.tm.opcode_modifier.w)
4237 if (i.tm.opcode_modifier.shortform)
4238 i.tm.base_opcode |= 8;
4240 i.tm.base_opcode |= 1;
4243 /* Now select between word & dword operations via the operand
4244 size prefix, except for instructions that will ignore this
4246 if (i.tm.opcode_modifier.addrprefixop0)
4248 /* The address size override prefix changes the size of the
4250 if ((flag_code == CODE_32BIT
4251 && i.op->regs[0].reg_type.bitfield.reg16)
4252 || (flag_code != CODE_32BIT
4253 && i.op->regs[0].reg_type.bitfield.reg32))
4254 if (!add_prefix (ADDR_PREFIX_OPCODE))
4257 else if (i.suffix != QWORD_MNEM_SUFFIX
4258 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
4259 && !i.tm.opcode_modifier.ignoresize
4260 && !i.tm.opcode_modifier.floatmf
4261 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4262 || (flag_code == CODE_64BIT
4263 && i.tm.opcode_modifier.jumpbyte)))
4265 unsigned int prefix = DATA_PREFIX_OPCODE;
4267 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
4268 prefix = ADDR_PREFIX_OPCODE;
4270 if (!add_prefix (prefix))
4274 /* Set mode64 for an operand. */
4275 if (i.suffix == QWORD_MNEM_SUFFIX
4276 && flag_code == CODE_64BIT
4277 && !i.tm.opcode_modifier.norex64)
4279 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4280 need rex64. cmpxchg8b is also a special case. */
4281 if (! (i.operands == 2
4282 && i.tm.base_opcode == 0x90
4283 && i.tm.extension_opcode == None
4284 && operand_type_equal (&i.types [0], &acc64)
4285 && operand_type_equal (&i.types [1], &acc64))
4286 && ! (i.operands == 1
4287 && i.tm.base_opcode == 0xfc7
4288 && i.tm.extension_opcode == 1
4289 && !operand_type_check (i.types [0], reg)
4290 && operand_type_check (i.types [0], anymem)))
4294 /* Size floating point instruction. */
4295 if (i.suffix == LONG_MNEM_SUFFIX)
4296 if (i.tm.opcode_modifier.floatmf)
4297 i.tm.base_opcode ^= 4;
4304 check_byte_reg (void)
4308 for (op = i.operands; --op >= 0;)
4310 /* If this is an eight bit register, it's OK. If it's the 16 or
4311 32 bit version of an eight bit register, we will just use the
4312 low portion, and that's OK too. */
4313 if (i.types[op].bitfield.reg8)
4316 /* Don't generate this warning if not needed. */
4317 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
4320 /* crc32 doesn't generate this warning. */
4321 if (i.tm.base_opcode == 0xf20f38f0)
4324 if ((i.types[op].bitfield.reg16
4325 || i.types[op].bitfield.reg32
4326 || i.types[op].bitfield.reg64)
4327 && i.op[op].regs->reg_num < 4)
4329 /* Prohibit these changes in the 64bit mode, since the
4330 lowering is more complicated. */
4331 if (flag_code == CODE_64BIT
4332 && !i.tm.operand_types[op].bitfield.inoutportreg)
4334 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4335 register_prefix, i.op[op].regs->reg_name,
4339 #if REGISTER_WARNINGS
4341 && !i.tm.operand_types[op].bitfield.inoutportreg)
4342 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4344 (i.op[op].regs + (i.types[op].bitfield.reg16
4345 ? REGNAM_AL - REGNAM_AX
4346 : REGNAM_AL - REGNAM_EAX))->reg_name,
4348 i.op[op].regs->reg_name,
4353 /* Any other register is bad. */
4354 if (i.types[op].bitfield.reg16
4355 || i.types[op].bitfield.reg32
4356 || i.types[op].bitfield.reg64
4357 || i.types[op].bitfield.regmmx
4358 || i.types[op].bitfield.regxmm
4359 || i.types[op].bitfield.regymm
4360 || i.types[op].bitfield.sreg2
4361 || i.types[op].bitfield.sreg3
4362 || i.types[op].bitfield.control
4363 || i.types[op].bitfield.debug
4364 || i.types[op].bitfield.test
4365 || i.types[op].bitfield.floatreg
4366 || i.types[op].bitfield.floatacc)
4368 as_bad (_("`%s%s' not allowed with `%s%c'"),
4370 i.op[op].regs->reg_name,
4380 check_long_reg (void)
4384 for (op = i.operands; --op >= 0;)
4385 /* Reject eight bit registers, except where the template requires
4386 them. (eg. movzb) */
4387 if (i.types[op].bitfield.reg8
4388 && (i.tm.operand_types[op].bitfield.reg16
4389 || i.tm.operand_types[op].bitfield.reg32
4390 || i.tm.operand_types[op].bitfield.acc))
4392 as_bad (_("`%s%s' not allowed with `%s%c'"),
4394 i.op[op].regs->reg_name,
4399 /* Warn if the e prefix on a general reg is missing. */
4400 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4401 && i.types[op].bitfield.reg16
4402 && (i.tm.operand_types[op].bitfield.reg32
4403 || i.tm.operand_types[op].bitfield.acc))
4405 /* Prohibit these changes in the 64bit mode, since the
4406 lowering is more complicated. */
4407 if (flag_code == CODE_64BIT)
4409 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4410 register_prefix, i.op[op].regs->reg_name,
4414 #if REGISTER_WARNINGS
4416 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4418 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
4420 i.op[op].regs->reg_name,
4424 /* Warn if the r prefix on a general reg is missing. */
4425 else if (i.types[op].bitfield.reg64
4426 && (i.tm.operand_types[op].bitfield.reg32
4427 || i.tm.operand_types[op].bitfield.acc))
4430 && i.tm.opcode_modifier.toqword
4431 && !i.types[0].bitfield.regxmm)
4433 /* Convert to QWORD. We want REX byte. */
4434 i.suffix = QWORD_MNEM_SUFFIX;
4438 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4439 register_prefix, i.op[op].regs->reg_name,
4448 check_qword_reg (void)
4452 for (op = i.operands; --op >= 0; )
4453 /* Reject eight bit registers, except where the template requires
4454 them. (eg. movzb) */
4455 if (i.types[op].bitfield.reg8
4456 && (i.tm.operand_types[op].bitfield.reg16
4457 || i.tm.operand_types[op].bitfield.reg32
4458 || i.tm.operand_types[op].bitfield.acc))
4460 as_bad (_("`%s%s' not allowed with `%s%c'"),
4462 i.op[op].regs->reg_name,
4467 /* Warn if the e prefix on a general reg is missing. */
4468 else if ((i.types[op].bitfield.reg16
4469 || i.types[op].bitfield.reg32)
4470 && (i.tm.operand_types[op].bitfield.reg32
4471 || i.tm.operand_types[op].bitfield.acc))
4473 /* Prohibit these changes in the 64bit mode, since the
4474 lowering is more complicated. */
4476 && i.tm.opcode_modifier.todword
4477 && !i.types[0].bitfield.regxmm)
4479 /* Convert to DWORD. We don't want REX byte. */
4480 i.suffix = LONG_MNEM_SUFFIX;
4484 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4485 register_prefix, i.op[op].regs->reg_name,
4494 check_word_reg (void)
4497 for (op = i.operands; --op >= 0;)
4498 /* Reject eight bit registers, except where the template requires
4499 them. (eg. movzb) */
4500 if (i.types[op].bitfield.reg8
4501 && (i.tm.operand_types[op].bitfield.reg16
4502 || i.tm.operand_types[op].bitfield.reg32
4503 || i.tm.operand_types[op].bitfield.acc))
4505 as_bad (_("`%s%s' not allowed with `%s%c'"),
4507 i.op[op].regs->reg_name,
4512 /* Warn if the e prefix on a general reg is present. */
4513 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4514 && i.types[op].bitfield.reg32
4515 && (i.tm.operand_types[op].bitfield.reg16
4516 || i.tm.operand_types[op].bitfield.acc))
4518 /* Prohibit these changes in the 64bit mode, since the
4519 lowering is more complicated. */
4520 if (flag_code == CODE_64BIT)
4522 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4523 register_prefix, i.op[op].regs->reg_name,
4528 #if REGISTER_WARNINGS
4529 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4531 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4533 i.op[op].regs->reg_name,
4541 update_imm (unsigned int j)
4543 i386_operand_type overlap = i.types[j];
4544 if ((overlap.bitfield.imm8
4545 || overlap.bitfield.imm8s
4546 || overlap.bitfield.imm16
4547 || overlap.bitfield.imm32
4548 || overlap.bitfield.imm32s
4549 || overlap.bitfield.imm64)
4550 && !operand_type_equal (&overlap, &imm8)
4551 && !operand_type_equal (&overlap, &imm8s)
4552 && !operand_type_equal (&overlap, &imm16)
4553 && !operand_type_equal (&overlap, &imm32)
4554 && !operand_type_equal (&overlap, &imm32s)
4555 && !operand_type_equal (&overlap, &imm64))
4559 i386_operand_type temp;
4561 operand_type_set (&temp, 0);
4562 if (i.suffix == BYTE_MNEM_SUFFIX)
4564 temp.bitfield.imm8 = overlap.bitfield.imm8;
4565 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4567 else if (i.suffix == WORD_MNEM_SUFFIX)
4568 temp.bitfield.imm16 = overlap.bitfield.imm16;
4569 else if (i.suffix == QWORD_MNEM_SUFFIX)
4571 temp.bitfield.imm64 = overlap.bitfield.imm64;
4572 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4575 temp.bitfield.imm32 = overlap.bitfield.imm32;
4578 else if (operand_type_equal (&overlap, &imm16_32_32s)
4579 || operand_type_equal (&overlap, &imm16_32)
4580 || operand_type_equal (&overlap, &imm16_32s))
4582 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4587 if (!operand_type_equal (&overlap, &imm8)
4588 && !operand_type_equal (&overlap, &imm8s)
4589 && !operand_type_equal (&overlap, &imm16)
4590 && !operand_type_equal (&overlap, &imm32)
4591 && !operand_type_equal (&overlap, &imm32s)
4592 && !operand_type_equal (&overlap, &imm64))
4594 as_bad (_("no instruction mnemonic suffix given; "
4595 "can't determine immediate size"));
4599 i.types[j] = overlap;
4609 /* Update the first 2 immediate operands. */
4610 n = i.operands > 2 ? 2 : i.operands;
4613 for (j = 0; j < n; j++)
4614 if (update_imm (j) == 0)
4617 /* The 3rd operand can't be immediate operand. */
4618 gas_assert (operand_type_check (i.types[2], imm) == 0);
4625 bad_implicit_operand (int xmm)
4627 const char *reg = xmm ? "xmm0" : "ymm0";
4629 as_bad (_("the last operand of `%s' must be `%s%s'"),
4630 i.tm.name, register_prefix, reg);
4632 as_bad (_("the first operand of `%s' must be `%s%s'"),
4633 i.tm.name, register_prefix, reg);
4638 process_operands (void)
4640 /* Default segment register this instruction will use for memory
4641 accesses. 0 means unknown. This is only for optimizing out
4642 unnecessary segment overrides. */
4643 const seg_entry *default_seg = 0;
4645 if (i.tm.opcode_modifier.sse2avx
4646 && (i.tm.opcode_modifier.vexnds
4647 || i.tm.opcode_modifier.vexndd))
4649 unsigned int dup = i.operands;
4650 unsigned int dest = dup - 1;
4653 /* The destination must be an xmm register. */
4654 gas_assert (i.reg_operands
4655 && MAX_OPERANDS > dup
4656 && operand_type_equal (&i.types[dest], ®xmm));
4658 if (i.tm.opcode_modifier.firstxmm0)
4660 /* The first operand is implicit and must be xmm0. */
4661 gas_assert (operand_type_equal (&i.types[0], ®xmm));
4662 if (i.op[0].regs->reg_num != 0)
4663 return bad_implicit_operand (1);
4665 if (i.tm.opcode_modifier.vex3sources)
4667 /* Keep xmm0 for instructions with VEX prefix and 3
4673 /* We remove the first xmm0 and keep the number of
4674 operands unchanged, which in fact duplicates the
4676 for (j = 1; j < i.operands; j++)
4678 i.op[j - 1] = i.op[j];
4679 i.types[j - 1] = i.types[j];
4680 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4684 else if (i.tm.opcode_modifier.implicit1stxmm0)
4686 gas_assert ((MAX_OPERANDS - 1) > dup
4687 && i.tm.opcode_modifier.vex3sources);
4689 /* Add the implicit xmm0 for instructions with VEX prefix
4691 for (j = i.operands; j > 0; j--)
4693 i.op[j] = i.op[j - 1];
4694 i.types[j] = i.types[j - 1];
4695 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4698 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4699 i.types[0] = regxmm;
4700 i.tm.operand_types[0] = regxmm;
4703 i.reg_operands += 2;
4708 i.op[dup] = i.op[dest];
4709 i.types[dup] = i.types[dest];
4710 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4719 i.op[dup] = i.op[dest];
4720 i.types[dup] = i.types[dest];
4721 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4724 if (i.tm.opcode_modifier.immext)
4727 else if (i.tm.opcode_modifier.firstxmm0)
4731 /* The first operand is implicit and must be xmm0/ymm0. */
4732 gas_assert (i.reg_operands
4733 && (operand_type_equal (&i.types[0], ®xmm)
4734 || operand_type_equal (&i.types[0], ®ymm)));
4735 if (i.op[0].regs->reg_num != 0)
4736 return bad_implicit_operand (i.types[0].bitfield.regxmm);
4738 for (j = 1; j < i.operands; j++)
4740 i.op[j - 1] = i.op[j];
4741 i.types[j - 1] = i.types[j];
4743 /* We need to adjust fields in i.tm since they are used by
4744 build_modrm_byte. */
4745 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4752 else if (i.tm.opcode_modifier.regkludge)
4754 /* The imul $imm, %reg instruction is converted into
4755 imul $imm, %reg, %reg, and the clr %reg instruction
4756 is converted into xor %reg, %reg. */
4758 unsigned int first_reg_op;
4760 if (operand_type_check (i.types[0], reg))
4764 /* Pretend we saw the extra register operand. */
4765 gas_assert (i.reg_operands == 1
4766 && i.op[first_reg_op + 1].regs == 0);
4767 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4768 i.types[first_reg_op + 1] = i.types[first_reg_op];
4773 if (i.tm.opcode_modifier.shortform)
4775 if (i.types[0].bitfield.sreg2
4776 || i.types[0].bitfield.sreg3)
4778 if (i.tm.base_opcode == POP_SEG_SHORT
4779 && i.op[0].regs->reg_num == 1)
4781 as_bad (_("you can't `pop %scs'"), register_prefix);
4784 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4785 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4790 /* The register or float register operand is in operand
4794 if (i.types[0].bitfield.floatreg
4795 || operand_type_check (i.types[0], reg))
4799 /* Register goes in low 3 bits of opcode. */
4800 i.tm.base_opcode |= i.op[op].regs->reg_num;
4801 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4803 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4805 /* Warn about some common errors, but press on regardless.
4806 The first case can be generated by gcc (<= 2.8.1). */
4807 if (i.operands == 2)
4809 /* Reversed arguments on faddp, fsubp, etc. */
4810 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4811 register_prefix, i.op[!intel_syntax].regs->reg_name,
4812 register_prefix, i.op[intel_syntax].regs->reg_name);
4816 /* Extraneous `l' suffix on fp insn. */
4817 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4818 register_prefix, i.op[0].regs->reg_name);
4823 else if (i.tm.opcode_modifier.modrm)
4825 /* The opcode is completed (modulo i.tm.extension_opcode which
4826 must be put into the modrm byte). Now, we make the modrm and
4827 index base bytes based on all the info we've collected. */
4829 default_seg = build_modrm_byte ();
4831 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4835 else if (i.tm.opcode_modifier.isstring)
4837 /* For the string instructions that allow a segment override
4838 on one of their operands, the default segment is ds. */
4842 if (i.tm.base_opcode == 0x8d /* lea */
4845 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4847 /* If a segment was explicitly specified, and the specified segment
4848 is not the default, use an opcode prefix to select it. If we
4849 never figured out what the default segment is, then default_seg
4850 will be zero at this point, and the specified segment prefix will
4852 if ((i.seg[0]) && (i.seg[0] != default_seg))
4854 if (!add_prefix (i.seg[0]->seg_prefix))
4860 static const seg_entry *
4861 build_modrm_byte (void)
4863 const seg_entry *default_seg = 0;
4864 unsigned int source, dest;
4867 /* The first operand of instructions with VEX prefix and 3 sources
4868 must be VEX_Imm4. */
4869 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4872 unsigned int nds, reg;
4874 if (i.tm.opcode_modifier.veximmext
4875 && i.tm.opcode_modifier.immext)
4877 dest = i.operands - 2;
4878 gas_assert (dest == 3);
4881 dest = i.operands - 1;
4884 /* This instruction must have 4 register operands
4885 or 3 register operands plus 1 memory operand.
4886 It must have VexNDS and VexImmExt. */
4887 gas_assert ((i.reg_operands == 4
4888 || (i.reg_operands == 3 && i.mem_operands == 1))
4889 && i.tm.opcode_modifier.vexnds
4890 && i.tm.opcode_modifier.veximmext
4891 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
4892 || operand_type_equal (&i.tm.operand_types[dest], ®ymm)));
4894 /* Generate an 8bit immediate operand to encode the register
4896 expressionS *exp = &im_expressions[i.imm_operands++];
4897 i.op[i.operands].imms = exp;
4898 i.types[i.operands] = imm8;
4900 /* If VexW1 is set, the first operand is the source and
4901 the second operand is encoded in the immediate operand. */
4902 if (i.tm.opcode_modifier.vexw1)
4912 /* FMA4 swaps REG and NDS. */
4913 if (i.tm.cpu_flags.bitfield.cpufma4)
4920 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], ®xmm)
4921 || operand_type_equal (&i.tm.operand_types[reg],
4923 && (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
4924 || operand_type_equal (&i.tm.operand_types[nds],
4926 exp->X_op = O_constant;
4928 = ((i.op[reg].regs->reg_num
4929 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
4930 i.vex.register_specifier = i.op[nds].regs;
4935 /* i.reg_operands MUST be the number of real register operands;
4936 implicit registers do not count. If there are 3 register
4937 operands, it must be a instruction with VexNDS. For a
4938 instruction with VexNDD, the destination register is encoded
4939 in VEX prefix. If there are 4 register operands, it must be
4940 a instruction with VEX prefix and 3 sources. */
4941 if (i.mem_operands == 0
4942 && ((i.reg_operands == 2
4943 && !i.tm.opcode_modifier.vexndd)
4944 || (i.reg_operands == 3
4945 && i.tm.opcode_modifier.vexnds)
4946 || (i.reg_operands == 4 && vex_3_sources)))
4954 /* When there are 3 operands, one of them may be immediate,
4955 which may be the first or the last operand. Otherwise,
4956 the first operand must be shift count register (cl) or it
4957 is an instruction with VexNDS. */
4958 gas_assert (i.imm_operands == 1
4959 || (i.imm_operands == 0
4960 && (i.tm.opcode_modifier.vexnds
4961 || i.types[0].bitfield.shiftcount)));
4962 if (operand_type_check (i.types[0], imm)
4963 || i.types[0].bitfield.shiftcount)
4969 /* When there are 4 operands, the first two must be 8bit
4970 immediate operands. The source operand will be the 3rd
4973 For instructions with VexNDS, if the first operand
4974 an imm8, the source operand is the 2nd one. If the last
4975 operand is imm8, the source operand is the first one. */
4976 gas_assert ((i.imm_operands == 2
4977 && i.types[0].bitfield.imm8
4978 && i.types[1].bitfield.imm8)
4979 || (i.tm.opcode_modifier.vexnds
4980 && i.imm_operands == 1
4981 && (i.types[0].bitfield.imm8
4982 || i.types[i.operands - 1].bitfield.imm8)));
4983 if (i.tm.opcode_modifier.vexnds)
4985 if (i.types[0].bitfield.imm8)
5003 if (i.tm.opcode_modifier.vexnds)
5005 /* For instructions with VexNDS, the register-only
5006 source operand must be XMM or YMM register. It is
5007 encoded in VEX prefix. We need to clear RegMem bit
5008 before calling operand_type_equal. */
5009 i386_operand_type op = i.tm.operand_types[dest];
5010 op.bitfield.regmem = 0;
5011 if ((dest + 1) >= i.operands
5012 || (!operand_type_equal (&op, ®xmm)
5013 && !operand_type_equal (&op, ®ymm)))
5015 i.vex.register_specifier = i.op[dest].regs;
5021 /* One of the register operands will be encoded in the i.tm.reg
5022 field, the other in the combined i.tm.mode and i.tm.regmem
5023 fields. If no form of this instruction supports a memory
5024 destination operand, then we assume the source operand may
5025 sometimes be a memory operand and so we need to store the
5026 destination in the i.rm.reg field. */
5027 if (!i.tm.operand_types[dest].bitfield.regmem
5028 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
5030 i.rm.reg = i.op[dest].regs->reg_num;
5031 i.rm.regmem = i.op[source].regs->reg_num;
5032 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
5034 if ((i.op[source].regs->reg_flags & RegRex) != 0)
5039 i.rm.reg = i.op[source].regs->reg_num;
5040 i.rm.regmem = i.op[dest].regs->reg_num;
5041 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
5043 if ((i.op[source].regs->reg_flags & RegRex) != 0)
5046 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
5048 if (!i.types[0].bitfield.control
5049 && !i.types[1].bitfield.control)
5051 i.rex &= ~(REX_R | REX_B);
5052 add_prefix (LOCK_PREFIX_OPCODE);
5056 { /* If it's not 2 reg operands... */
5061 unsigned int fake_zero_displacement = 0;
5064 for (op = 0; op < i.operands; op++)
5065 if (operand_type_check (i.types[op], anymem))
5067 gas_assert (op < i.operands);
5071 if (i.base_reg == 0)
5074 if (!i.disp_operands)
5075 fake_zero_displacement = 1;
5076 if (i.index_reg == 0)
5078 /* Operand is just <disp> */
5079 if (flag_code == CODE_64BIT)
5081 /* 64bit mode overwrites the 32bit absolute
5082 addressing by RIP relative addressing and
5083 absolute addressing is encoded by one of the
5084 redundant SIB forms. */
5085 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5086 i.sib.base = NO_BASE_REGISTER;
5087 i.sib.index = NO_INDEX_REGISTER;
5088 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
5089 ? disp32s : disp32);
5091 else if ((flag_code == CODE_16BIT)
5092 ^ (i.prefix[ADDR_PREFIX] != 0))
5094 i.rm.regmem = NO_BASE_REGISTER_16;
5095 i.types[op] = disp16;
5099 i.rm.regmem = NO_BASE_REGISTER;
5100 i.types[op] = disp32;
5103 else /* !i.base_reg && i.index_reg */
5105 if (i.index_reg->reg_num == RegEiz
5106 || i.index_reg->reg_num == RegRiz)
5107 i.sib.index = NO_INDEX_REGISTER;
5109 i.sib.index = i.index_reg->reg_num;
5110 i.sib.base = NO_BASE_REGISTER;
5111 i.sib.scale = i.log2_scale_factor;
5112 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5113 i.types[op].bitfield.disp8 = 0;
5114 i.types[op].bitfield.disp16 = 0;
5115 i.types[op].bitfield.disp64 = 0;
5116 if (flag_code != CODE_64BIT)
5118 /* Must be 32 bit */
5119 i.types[op].bitfield.disp32 = 1;
5120 i.types[op].bitfield.disp32s = 0;
5124 i.types[op].bitfield.disp32 = 0;
5125 i.types[op].bitfield.disp32s = 1;
5127 if ((i.index_reg->reg_flags & RegRex) != 0)
5131 /* RIP addressing for 64bit mode. */
5132 else if (i.base_reg->reg_num == RegRip ||
5133 i.base_reg->reg_num == RegEip)
5135 i.rm.regmem = NO_BASE_REGISTER;
5136 i.types[op].bitfield.disp8 = 0;
5137 i.types[op].bitfield.disp16 = 0;
5138 i.types[op].bitfield.disp32 = 0;
5139 i.types[op].bitfield.disp32s = 1;
5140 i.types[op].bitfield.disp64 = 0;
5141 i.flags[op] |= Operand_PCrel;
5142 if (! i.disp_operands)
5143 fake_zero_displacement = 1;
5145 else if (i.base_reg->reg_type.bitfield.reg16)
5147 switch (i.base_reg->reg_num)
5150 if (i.index_reg == 0)
5152 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5153 i.rm.regmem = i.index_reg->reg_num - 6;
5157 if (i.index_reg == 0)
5160 if (operand_type_check (i.types[op], disp) == 0)
5162 /* fake (%bp) into 0(%bp) */
5163 i.types[op].bitfield.disp8 = 1;
5164 fake_zero_displacement = 1;
5167 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5168 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5170 default: /* (%si) -> 4 or (%di) -> 5 */
5171 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5173 i.rm.mode = mode_from_disp_size (i.types[op]);
5175 else /* i.base_reg and 32/64 bit mode */
5177 if (flag_code == CODE_64BIT
5178 && operand_type_check (i.types[op], disp))
5180 i386_operand_type temp;
5181 operand_type_set (&temp, 0);
5182 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5184 if (i.prefix[ADDR_PREFIX] == 0)
5185 i.types[op].bitfield.disp32s = 1;
5187 i.types[op].bitfield.disp32 = 1;
5190 i.rm.regmem = i.base_reg->reg_num;
5191 if ((i.base_reg->reg_flags & RegRex) != 0)
5193 i.sib.base = i.base_reg->reg_num;
5194 /* x86-64 ignores REX prefix bit here to avoid decoder
5196 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5199 if (i.disp_operands == 0)
5201 fake_zero_displacement = 1;
5202 i.types[op].bitfield.disp8 = 1;
5205 else if (i.base_reg->reg_num == ESP_REG_NUM)
5209 i.sib.scale = i.log2_scale_factor;
5210 if (i.index_reg == 0)
5212 /* <disp>(%esp) becomes two byte modrm with no index
5213 register. We've already stored the code for esp
5214 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5215 Any base register besides %esp will not use the
5216 extra modrm byte. */
5217 i.sib.index = NO_INDEX_REGISTER;
5221 if (i.index_reg->reg_num == RegEiz
5222 || i.index_reg->reg_num == RegRiz)
5223 i.sib.index = NO_INDEX_REGISTER;
5225 i.sib.index = i.index_reg->reg_num;
5226 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5227 if ((i.index_reg->reg_flags & RegRex) != 0)
5232 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5233 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5236 i.rm.mode = mode_from_disp_size (i.types[op]);
5239 if (fake_zero_displacement)
5241 /* Fakes a zero displacement assuming that i.types[op]
5242 holds the correct displacement size. */
5245 gas_assert (i.op[op].disps == 0);
5246 exp = &disp_expressions[i.disp_operands++];
5247 i.op[op].disps = exp;
5248 exp->X_op = O_constant;
5249 exp->X_add_number = 0;
5250 exp->X_add_symbol = (symbolS *) 0;
5251 exp->X_op_symbol = (symbolS *) 0;
5259 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5260 (if any) based on i.tm.extension_opcode. Again, we must be
5261 careful to make sure that segment/control/debug/test/MMX
5262 registers are coded into the i.rm.reg field. */
5266 unsigned int vex_reg = ~0;
5268 for (op = 0; op < i.operands; op++)
5269 if (i.types[op].bitfield.reg8
5270 || i.types[op].bitfield.reg16
5271 || i.types[op].bitfield.reg32
5272 || i.types[op].bitfield.reg64
5273 || i.types[op].bitfield.regmmx
5274 || i.types[op].bitfield.regxmm
5275 || i.types[op].bitfield.regymm
5276 || i.types[op].bitfield.sreg2
5277 || i.types[op].bitfield.sreg3
5278 || i.types[op].bitfield.control
5279 || i.types[op].bitfield.debug
5280 || i.types[op].bitfield.test)
5285 else if (i.tm.opcode_modifier.vexnds)
5287 /* For instructions with VexNDS, the register-only
5288 source operand is encoded in VEX prefix. */
5289 gas_assert (mem != (unsigned int) ~0);
5294 gas_assert (op < i.operands);
5299 gas_assert (vex_reg < i.operands);
5302 else if (i.tm.opcode_modifier.vexndd)
5304 /* For instructions with VexNDD, there should be
5305 no memory operand and the register destination
5306 is encoded in VEX prefix. */
5307 gas_assert (i.mem_operands == 0
5308 && (op + 2) == i.operands);
5312 gas_assert (op < i.operands);
5314 if (vex_reg != (unsigned int) ~0)
5316 gas_assert (i.reg_operands == 2);
5318 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5320 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5323 i.vex.register_specifier = i.op[vex_reg].regs;
5326 /* If there is an extension opcode to put here, the
5327 register number must be put into the regmem field. */
5328 if (i.tm.extension_opcode != None)
5330 i.rm.regmem = i.op[op].regs->reg_num;
5331 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5336 i.rm.reg = i.op[op].regs->reg_num;
5337 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5341 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5342 must set it to 3 to indicate this is a register operand
5343 in the regmem field. */
5344 if (!i.mem_operands)
5348 /* Fill in i.rm.reg field with extension opcode (if any). */
5349 if (i.tm.extension_opcode != None)
5350 i.rm.reg = i.tm.extension_opcode;
5356 output_branch (void)
5361 relax_substateT subtype;
5366 if (flag_code == CODE_16BIT)
5370 if (i.prefix[DATA_PREFIX] != 0)
5376 /* Pentium4 branch hints. */
5377 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5378 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5383 if (i.prefix[REX_PREFIX] != 0)
5389 if (i.prefixes != 0 && !intel_syntax)
5390 as_warn (_("skipping prefixes on this instruction"));
5392 /* It's always a symbol; End frag & setup for relax.
5393 Make sure there is enough room in this frag for the largest
5394 instruction we may generate in md_convert_frag. This is 2
5395 bytes for the opcode and room for the prefix and largest
5397 frag_grow (prefix + 2 + 4);
5398 /* Prefix and 1 opcode byte go in fr_fix. */
5399 p = frag_more (prefix + 1);
5400 if (i.prefix[DATA_PREFIX] != 0)
5401 *p++ = DATA_PREFIX_OPCODE;
5402 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5403 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5404 *p++ = i.prefix[SEG_PREFIX];
5405 if (i.prefix[REX_PREFIX] != 0)
5406 *p++ = i.prefix[REX_PREFIX];
5407 *p = i.tm.base_opcode;
5409 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5410 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5411 else if (cpu_arch_flags.bitfield.cpui386)
5412 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5414 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5417 sym = i.op[0].disps->X_add_symbol;
5418 off = i.op[0].disps->X_add_number;
5420 if (i.op[0].disps->X_op != O_constant
5421 && i.op[0].disps->X_op != O_symbol)
5423 /* Handle complex expressions. */
5424 sym = make_expr_symbol (i.op[0].disps);
5428 /* 1 possible extra opcode + 4 byte displacement go in var part.
5429 Pass reloc in fr_var. */
5430 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5440 if (i.tm.opcode_modifier.jumpbyte)
5442 /* This is a loop or jecxz type instruction. */
5444 if (i.prefix[ADDR_PREFIX] != 0)
5446 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5449 /* Pentium4 branch hints. */
5450 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5451 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5453 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5462 if (flag_code == CODE_16BIT)
5465 if (i.prefix[DATA_PREFIX] != 0)
5467 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5477 if (i.prefix[REX_PREFIX] != 0)
5479 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5483 if (i.prefixes != 0 && !intel_syntax)
5484 as_warn (_("skipping prefixes on this instruction"));
5486 p = frag_more (1 + size);
5487 *p++ = i.tm.base_opcode;
5489 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5490 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5492 /* All jumps handled here are signed, but don't use a signed limit
5493 check for 32 and 16 bit jumps as we want to allow wrap around at
5494 4G and 64k respectively. */
5496 fixP->fx_signed = 1;
5500 output_interseg_jump (void)
5508 if (flag_code == CODE_16BIT)
5512 if (i.prefix[DATA_PREFIX] != 0)
5518 if (i.prefix[REX_PREFIX] != 0)
5528 if (i.prefixes != 0 && !intel_syntax)
5529 as_warn (_("skipping prefixes on this instruction"));
5531 /* 1 opcode; 2 segment; offset */
5532 p = frag_more (prefix + 1 + 2 + size);
5534 if (i.prefix[DATA_PREFIX] != 0)
5535 *p++ = DATA_PREFIX_OPCODE;
5537 if (i.prefix[REX_PREFIX] != 0)
5538 *p++ = i.prefix[REX_PREFIX];
5540 *p++ = i.tm.base_opcode;
5541 if (i.op[1].imms->X_op == O_constant)
5543 offsetT n = i.op[1].imms->X_add_number;
5546 && !fits_in_unsigned_word (n)
5547 && !fits_in_signed_word (n))
5549 as_bad (_("16-bit jump out of range"));
5552 md_number_to_chars (p, n, size);
5555 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5556 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5557 if (i.op[0].imms->X_op != O_constant)
5558 as_bad (_("can't handle non absolute segment in `%s'"),
5560 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5566 fragS *insn_start_frag;
5567 offsetT insn_start_off;
5569 /* Tie dwarf2 debug info to the address at the start of the insn.
5570 We can't do this after the insn has been output as the current
5571 frag may have been closed off. eg. by frag_var. */
5572 dwarf2_emit_insn (0);
5574 insn_start_frag = frag_now;
5575 insn_start_off = frag_now_fix ();
5578 if (i.tm.opcode_modifier.jump)
5580 else if (i.tm.opcode_modifier.jumpbyte
5581 || i.tm.opcode_modifier.jumpdword)
5583 else if (i.tm.opcode_modifier.jumpintersegment)
5584 output_interseg_jump ();
5587 /* Output normal instructions here. */
5591 unsigned int prefix;
5593 /* Since the VEX prefix contains the implicit prefix, we don't
5594 need the explicit prefix. */
5595 if (!i.tm.opcode_modifier.vex)
5597 switch (i.tm.opcode_length)
5600 if (i.tm.base_opcode & 0xff000000)
5602 prefix = (i.tm.base_opcode >> 24) & 0xff;
5607 if ((i.tm.base_opcode & 0xff0000) != 0)
5609 prefix = (i.tm.base_opcode >> 16) & 0xff;
5610 if (i.tm.cpu_flags.bitfield.cpupadlock)
5613 if (prefix != REPE_PREFIX_OPCODE
5614 || (i.prefix[LOCKREP_PREFIX]
5615 != REPE_PREFIX_OPCODE))
5616 add_prefix (prefix);
5619 add_prefix (prefix);
5628 /* The prefix bytes. */
5629 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5631 FRAG_APPEND_1_CHAR (*q);
5634 if (i.tm.opcode_modifier.vex)
5636 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5641 /* REX byte is encoded in VEX prefix. */
5645 FRAG_APPEND_1_CHAR (*q);
5648 /* There should be no other prefixes for instructions
5653 /* Now the VEX prefix. */
5654 p = frag_more (i.vex.length);
5655 for (j = 0; j < i.vex.length; j++)
5656 p[j] = i.vex.bytes[j];
5659 /* Now the opcode; be careful about word order here! */
5660 if (i.tm.opcode_length == 1)
5662 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5666 switch (i.tm.opcode_length)
5670 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5680 /* Put out high byte first: can't use md_number_to_chars! */
5681 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5682 *p = i.tm.base_opcode & 0xff;
5685 /* Now the modrm byte and sib byte (if present). */
5686 if (i.tm.opcode_modifier.modrm)
5688 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5691 /* If i.rm.regmem == ESP (4)
5692 && i.rm.mode != (Register mode)
5694 ==> need second modrm byte. */
5695 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5697 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5698 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5700 | i.sib.scale << 6));
5703 if (i.disp_operands)
5704 output_disp (insn_start_frag, insn_start_off);
5707 output_imm (insn_start_frag, insn_start_off);
5713 pi ("" /*line*/, &i);
5715 #endif /* DEBUG386 */
5718 /* Return the size of the displacement operand N. */
5721 disp_size (unsigned int n)
5724 if (i.types[n].bitfield.disp64)
5726 else if (i.types[n].bitfield.disp8)
5728 else if (i.types[n].bitfield.disp16)
5733 /* Return the size of the immediate operand N. */
5736 imm_size (unsigned int n)
5739 if (i.types[n].bitfield.imm64)
5741 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5743 else if (i.types[n].bitfield.imm16)
5749 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5754 for (n = 0; n < i.operands; n++)
5756 if (operand_type_check (i.types[n], disp))
5758 if (i.op[n].disps->X_op == O_constant)
5760 int size = disp_size (n);
5763 val = offset_in_range (i.op[n].disps->X_add_number,
5765 p = frag_more (size);
5766 md_number_to_chars (p, val, size);
5770 enum bfd_reloc_code_real reloc_type;
5771 int size = disp_size (n);
5772 int sign = i.types[n].bitfield.disp32s;
5773 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5775 /* We can't have 8 bit displacement here. */
5776 gas_assert (!i.types[n].bitfield.disp8);
5778 /* The PC relative address is computed relative
5779 to the instruction boundary, so in case immediate
5780 fields follows, we need to adjust the value. */
5781 if (pcrel && i.imm_operands)
5786 for (n1 = 0; n1 < i.operands; n1++)
5787 if (operand_type_check (i.types[n1], imm))
5789 /* Only one immediate is allowed for PC
5790 relative address. */
5791 gas_assert (sz == 0);
5793 i.op[n].disps->X_add_number -= sz;
5795 /* We should find the immediate. */
5796 gas_assert (sz != 0);
5799 p = frag_more (size);
5800 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5802 && GOT_symbol == i.op[n].disps->X_add_symbol
5803 && (((reloc_type == BFD_RELOC_32
5804 || reloc_type == BFD_RELOC_X86_64_32S
5805 || (reloc_type == BFD_RELOC_64
5807 && (i.op[n].disps->X_op == O_symbol
5808 || (i.op[n].disps->X_op == O_add
5809 && ((symbol_get_value_expression
5810 (i.op[n].disps->X_op_symbol)->X_op)
5812 || reloc_type == BFD_RELOC_32_PCREL))
5816 if (insn_start_frag == frag_now)
5817 add = (p - frag_now->fr_literal) - insn_start_off;
5822 add = insn_start_frag->fr_fix - insn_start_off;
5823 for (fr = insn_start_frag->fr_next;
5824 fr && fr != frag_now; fr = fr->fr_next)
5826 add += p - frag_now->fr_literal;
5831 reloc_type = BFD_RELOC_386_GOTPC;
5832 i.op[n].imms->X_add_number += add;
5834 else if (reloc_type == BFD_RELOC_64)
5835 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5837 /* Don't do the adjustment for x86-64, as there
5838 the pcrel addressing is relative to the _next_
5839 insn, and that is taken care of in other code. */
5840 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5842 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5843 i.op[n].disps, pcrel, reloc_type);
5850 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5855 for (n = 0; n < i.operands; n++)
5857 if (operand_type_check (i.types[n], imm))
5859 if (i.op[n].imms->X_op == O_constant)
5861 int size = imm_size (n);
5864 val = offset_in_range (i.op[n].imms->X_add_number,
5866 p = frag_more (size);
5867 md_number_to_chars (p, val, size);
5871 /* Not absolute_section.
5872 Need a 32-bit fixup (don't support 8bit
5873 non-absolute imms). Try to support other
5875 enum bfd_reloc_code_real reloc_type;
5876 int size = imm_size (n);
5879 if (i.types[n].bitfield.imm32s
5880 && (i.suffix == QWORD_MNEM_SUFFIX
5881 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5886 p = frag_more (size);
5887 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5889 /* This is tough to explain. We end up with this one if we
5890 * have operands that look like
5891 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5892 * obtain the absolute address of the GOT, and it is strongly
5893 * preferable from a performance point of view to avoid using
5894 * a runtime relocation for this. The actual sequence of
5895 * instructions often look something like:
5900 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5902 * The call and pop essentially return the absolute address
5903 * of the label .L66 and store it in %ebx. The linker itself
5904 * will ultimately change the first operand of the addl so
5905 * that %ebx points to the GOT, but to keep things simple, the
5906 * .o file must have this operand set so that it generates not
5907 * the absolute address of .L66, but the absolute address of
5908 * itself. This allows the linker itself simply treat a GOTPC
5909 * relocation as asking for a pcrel offset to the GOT to be
5910 * added in, and the addend of the relocation is stored in the
5911 * operand field for the instruction itself.
5913 * Our job here is to fix the operand so that it would add
5914 * the correct offset so that %ebx would point to itself. The
5915 * thing that is tricky is that .-.L66 will point to the
5916 * beginning of the instruction, so we need to further modify
5917 * the operand so that it will point to itself. There are
5918 * other cases where you have something like:
5920 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5922 * and here no correction would be required. Internally in
5923 * the assembler we treat operands of this form as not being
5924 * pcrel since the '.' is explicitly mentioned, and I wonder
5925 * whether it would simplify matters to do it this way. Who
5926 * knows. In earlier versions of the PIC patches, the
5927 * pcrel_adjust field was used to store the correction, but
5928 * since the expression is not pcrel, I felt it would be
5929 * confusing to do it this way. */
5931 if ((reloc_type == BFD_RELOC_32
5932 || reloc_type == BFD_RELOC_X86_64_32S
5933 || reloc_type == BFD_RELOC_64)
5935 && GOT_symbol == i.op[n].imms->X_add_symbol
5936 && (i.op[n].imms->X_op == O_symbol
5937 || (i.op[n].imms->X_op == O_add
5938 && ((symbol_get_value_expression
5939 (i.op[n].imms->X_op_symbol)->X_op)
5944 if (insn_start_frag == frag_now)
5945 add = (p - frag_now->fr_literal) - insn_start_off;
5950 add = insn_start_frag->fr_fix - insn_start_off;
5951 for (fr = insn_start_frag->fr_next;
5952 fr && fr != frag_now; fr = fr->fr_next)
5954 add += p - frag_now->fr_literal;
5958 reloc_type = BFD_RELOC_386_GOTPC;
5960 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5962 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5963 i.op[n].imms->X_add_number += add;
5965 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5966 i.op[n].imms, 0, reloc_type);
5972 /* x86_cons_fix_new is called via the expression parsing code when a
5973 reloc is needed. We use this hook to get the correct .got reloc. */
5974 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5975 static int cons_sign = -1;
5978 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5981 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5983 got_reloc = NO_RELOC;
5986 if (exp->X_op == O_secrel)
5988 exp->X_op = O_symbol;
5989 r = BFD_RELOC_32_SECREL;
5993 fix_new_exp (frag, off, len, exp, 0, r);
5996 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5997 # define lex_got(reloc, adjust, types) NULL
5999 /* Parse operands of the form
6000 <symbol>@GOTOFF+<nnn>
6001 and similar .plt or .got references.
6003 If we find one, set up the correct relocation in RELOC and copy the
6004 input string, minus the `@GOTOFF' into a malloc'd buffer for
6005 parsing by the calling routine. Return this buffer, and if ADJUST
6006 is non-null set it to the length of the string we removed from the
6007 input line. Otherwise return NULL. */
6009 lex_got (enum bfd_reloc_code_real *reloc,
6011 i386_operand_type *types)
6013 /* Some of the relocations depend on the size of what field is to
6014 be relocated. But in our callers i386_immediate and i386_displacement
6015 we don't yet know the operand size (this will be set by insn
6016 matching). Hence we record the word32 relocation here,
6017 and adjust the reloc according to the real size in reloc(). */
6018 static const struct {
6020 const enum bfd_reloc_code_real rel[2];
6021 const i386_operand_type types64;
6023 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
6024 BFD_RELOC_X86_64_PLTOFF64 },
6025 OPERAND_TYPE_IMM64 },
6026 { "PLT", { BFD_RELOC_386_PLT32,
6027 BFD_RELOC_X86_64_PLT32 },
6028 OPERAND_TYPE_IMM32_32S_DISP32 },
6029 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
6030 BFD_RELOC_X86_64_GOTPLT64 },
6031 OPERAND_TYPE_IMM64_DISP64 },
6032 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6033 BFD_RELOC_X86_64_GOTOFF64 },
6034 OPERAND_TYPE_IMM64_DISP64 },
6035 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
6036 BFD_RELOC_X86_64_GOTPCREL },
6037 OPERAND_TYPE_IMM32_32S_DISP32 },
6038 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6039 BFD_RELOC_X86_64_TLSGD },
6040 OPERAND_TYPE_IMM32_32S_DISP32 },
6041 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6042 _dummy_first_bfd_reloc_code_real },
6043 OPERAND_TYPE_NONE },
6044 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
6045 BFD_RELOC_X86_64_TLSLD },
6046 OPERAND_TYPE_IMM32_32S_DISP32 },
6047 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6048 BFD_RELOC_X86_64_GOTTPOFF },
6049 OPERAND_TYPE_IMM32_32S_DISP32 },
6050 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6051 BFD_RELOC_X86_64_TPOFF32 },
6052 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6053 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6054 _dummy_first_bfd_reloc_code_real },
6055 OPERAND_TYPE_NONE },
6056 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6057 BFD_RELOC_X86_64_DTPOFF32 },
6059 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6060 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6061 _dummy_first_bfd_reloc_code_real },
6062 OPERAND_TYPE_NONE },
6063 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6064 _dummy_first_bfd_reloc_code_real },
6065 OPERAND_TYPE_NONE },
6066 { "GOT", { BFD_RELOC_386_GOT32,
6067 BFD_RELOC_X86_64_GOT32 },
6068 OPERAND_TYPE_IMM32_32S_64_DISP32 },
6069 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6070 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
6071 OPERAND_TYPE_IMM32_32S_DISP32 },
6072 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6073 BFD_RELOC_X86_64_TLSDESC_CALL },
6074 OPERAND_TYPE_IMM32_32S_DISP32 },
6082 for (cp = input_line_pointer; *cp != '@'; cp++)
6083 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6086 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6090 len = strlen (gotrel[j].str);
6091 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6093 if (gotrel[j].rel[object_64bit] != 0)
6096 char *tmpbuf, *past_reloc;
6098 *reloc = gotrel[j].rel[object_64bit];
6104 if (flag_code != CODE_64BIT)
6106 types->bitfield.imm32 = 1;
6107 types->bitfield.disp32 = 1;
6110 *types = gotrel[j].types64;
6113 if (GOT_symbol == NULL)
6114 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6116 /* The length of the first part of our input line. */
6117 first = cp - input_line_pointer;
6119 /* The second part goes from after the reloc token until
6120 (and including) an end_of_line char or comma. */
6121 past_reloc = cp + 1 + len;
6123 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6125 second = cp + 1 - past_reloc;
6127 /* Allocate and copy string. The trailing NUL shouldn't
6128 be necessary, but be safe. */
6129 tmpbuf = (char *) xmalloc (first + second + 2);
6130 memcpy (tmpbuf, input_line_pointer, first);
6131 if (second != 0 && *past_reloc != ' ')
6132 /* Replace the relocation token with ' ', so that
6133 errors like foo@GOTOFF1 will be detected. */
6134 tmpbuf[first++] = ' ';
6135 memcpy (tmpbuf + first, past_reloc, second);
6136 tmpbuf[first + second] = '\0';
6140 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6141 gotrel[j].str, 1 << (5 + object_64bit));
6146 /* Might be a symbol version string. Don't as_bad here. */
6151 x86_cons (expressionS *exp, int size)
6153 intel_syntax = -intel_syntax;
6155 if (size == 4 || (object_64bit && size == 8))
6157 /* Handle @GOTOFF and the like in an expression. */
6159 char *gotfree_input_line;
6162 save = input_line_pointer;
6163 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
6164 if (gotfree_input_line)
6165 input_line_pointer = gotfree_input_line;
6169 if (gotfree_input_line)
6171 /* expression () has merrily parsed up to the end of line,
6172 or a comma - in the wrong buffer. Transfer how far
6173 input_line_pointer has moved to the right buffer. */
6174 input_line_pointer = (save
6175 + (input_line_pointer - gotfree_input_line)
6177 free (gotfree_input_line);
6178 if (exp->X_op == O_constant
6179 || exp->X_op == O_absent
6180 || exp->X_op == O_illegal
6181 || exp->X_op == O_register
6182 || exp->X_op == O_big)
6184 char c = *input_line_pointer;
6185 *input_line_pointer = 0;
6186 as_bad (_("missing or invalid expression `%s'"), save);
6187 *input_line_pointer = c;
6194 intel_syntax = -intel_syntax;
6197 i386_intel_simplify (exp);
6201 static void signed_cons (int size)
6203 if (flag_code == CODE_64BIT)
6211 pe_directive_secrel (dummy)
6212 int dummy ATTRIBUTE_UNUSED;
6219 if (exp.X_op == O_symbol)
6220 exp.X_op = O_secrel;
6222 emit_expr (&exp, 4);
6224 while (*input_line_pointer++ == ',');
6226 input_line_pointer--;
6227 demand_empty_rest_of_line ();
6232 i386_immediate (char *imm_start)
6234 char *save_input_line_pointer;
6235 char *gotfree_input_line;
6238 i386_operand_type types;
6240 operand_type_set (&types, ~0);
6242 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6244 as_bad (_("at most %d immediate operands are allowed"),
6245 MAX_IMMEDIATE_OPERANDS);
6249 exp = &im_expressions[i.imm_operands++];
6250 i.op[this_operand].imms = exp;
6252 if (is_space_char (*imm_start))
6255 save_input_line_pointer = input_line_pointer;
6256 input_line_pointer = imm_start;
6258 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6259 if (gotfree_input_line)
6260 input_line_pointer = gotfree_input_line;
6262 exp_seg = expression (exp);
6265 if (*input_line_pointer)
6266 as_bad (_("junk `%s' after expression"), input_line_pointer);
6268 input_line_pointer = save_input_line_pointer;
6269 if (gotfree_input_line)
6271 free (gotfree_input_line);
6273 if (exp->X_op == O_constant || exp->X_op == O_register)
6274 exp->X_op = O_illegal;
6277 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6281 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6282 i386_operand_type types, const char *imm_start)
6284 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
6286 as_bad (_("missing or invalid immediate expression `%s'"),
6290 else if (exp->X_op == O_constant)
6292 /* Size it properly later. */
6293 i.types[this_operand].bitfield.imm64 = 1;
6294 /* If BFD64, sign extend val. */
6295 if (!use_rela_relocations
6296 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6298 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
6300 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6301 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
6302 && exp_seg != absolute_section
6303 && exp_seg != text_section
6304 && exp_seg != data_section
6305 && exp_seg != bss_section
6306 && exp_seg != undefined_section
6307 && !bfd_is_com_section (exp_seg))
6309 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6313 else if (!intel_syntax && exp->X_op == O_register)
6315 as_bad (_("illegal immediate register operand %s"), imm_start);
6320 /* This is an address. The size of the address will be
6321 determined later, depending on destination register,
6322 suffix, or the default for the section. */
6323 i.types[this_operand].bitfield.imm8 = 1;
6324 i.types[this_operand].bitfield.imm16 = 1;
6325 i.types[this_operand].bitfield.imm32 = 1;
6326 i.types[this_operand].bitfield.imm32s = 1;
6327 i.types[this_operand].bitfield.imm64 = 1;
6328 i.types[this_operand] = operand_type_and (i.types[this_operand],
6336 i386_scale (char *scale)
6339 char *save = input_line_pointer;
6341 input_line_pointer = scale;
6342 val = get_absolute_expression ();
6347 i.log2_scale_factor = 0;
6350 i.log2_scale_factor = 1;
6353 i.log2_scale_factor = 2;
6356 i.log2_scale_factor = 3;
6360 char sep = *input_line_pointer;
6362 *input_line_pointer = '\0';
6363 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6365 *input_line_pointer = sep;
6366 input_line_pointer = save;
6370 if (i.log2_scale_factor != 0 && i.index_reg == 0)
6372 as_warn (_("scale factor of %d without an index register"),
6373 1 << i.log2_scale_factor);
6374 i.log2_scale_factor = 0;
6376 scale = input_line_pointer;
6377 input_line_pointer = save;
6382 i386_displacement (char *disp_start, char *disp_end)
6386 char *save_input_line_pointer;
6387 char *gotfree_input_line;
6389 i386_operand_type bigdisp, types = anydisp;
6392 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6394 as_bad (_("at most %d displacement operands are allowed"),
6395 MAX_MEMORY_OPERANDS);
6399 operand_type_set (&bigdisp, 0);
6400 if ((i.types[this_operand].bitfield.jumpabsolute)
6401 || (!current_templates->start->opcode_modifier.jump
6402 && !current_templates->start->opcode_modifier.jumpdword))
6404 bigdisp.bitfield.disp32 = 1;
6405 override = (i.prefix[ADDR_PREFIX] != 0);
6406 if (flag_code == CODE_64BIT)
6410 bigdisp.bitfield.disp32s = 1;
6411 bigdisp.bitfield.disp64 = 1;
6414 else if ((flag_code == CODE_16BIT) ^ override)
6416 bigdisp.bitfield.disp32 = 0;
6417 bigdisp.bitfield.disp16 = 1;
6422 /* For PC-relative branches, the width of the displacement
6423 is dependent upon data size, not address size. */
6424 override = (i.prefix[DATA_PREFIX] != 0);
6425 if (flag_code == CODE_64BIT)
6427 if (override || i.suffix == WORD_MNEM_SUFFIX)
6428 bigdisp.bitfield.disp16 = 1;
6431 bigdisp.bitfield.disp32 = 1;
6432 bigdisp.bitfield.disp32s = 1;
6438 override = (i.suffix == (flag_code != CODE_16BIT
6440 : LONG_MNEM_SUFFIX));
6441 bigdisp.bitfield.disp32 = 1;
6442 if ((flag_code == CODE_16BIT) ^ override)
6444 bigdisp.bitfield.disp32 = 0;
6445 bigdisp.bitfield.disp16 = 1;
6449 i.types[this_operand] = operand_type_or (i.types[this_operand],
6452 exp = &disp_expressions[i.disp_operands];
6453 i.op[this_operand].disps = exp;
6455 save_input_line_pointer = input_line_pointer;
6456 input_line_pointer = disp_start;
6457 END_STRING_AND_SAVE (disp_end);
6459 #ifndef GCC_ASM_O_HACK
6460 #define GCC_ASM_O_HACK 0
6463 END_STRING_AND_SAVE (disp_end + 1);
6464 if (i.types[this_operand].bitfield.baseIndex
6465 && displacement_string_end[-1] == '+')
6467 /* This hack is to avoid a warning when using the "o"
6468 constraint within gcc asm statements.
6471 #define _set_tssldt_desc(n,addr,limit,type) \
6472 __asm__ __volatile__ ( \
6474 "movw %w1,2+%0\n\t" \
6476 "movb %b1,4+%0\n\t" \
6477 "movb %4,5+%0\n\t" \
6478 "movb $0,6+%0\n\t" \
6479 "movb %h1,7+%0\n\t" \
6481 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6483 This works great except that the output assembler ends
6484 up looking a bit weird if it turns out that there is
6485 no offset. You end up producing code that looks like:
6498 So here we provide the missing zero. */
6500 *displacement_string_end = '0';
6503 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6504 if (gotfree_input_line)
6505 input_line_pointer = gotfree_input_line;
6507 exp_seg = expression (exp);
6510 if (*input_line_pointer)
6511 as_bad (_("junk `%s' after expression"), input_line_pointer);
6513 RESTORE_END_STRING (disp_end + 1);
6515 input_line_pointer = save_input_line_pointer;
6516 if (gotfree_input_line)
6518 free (gotfree_input_line);
6520 if (exp->X_op == O_constant || exp->X_op == O_register)
6521 exp->X_op = O_illegal;
6524 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6526 RESTORE_END_STRING (disp_end);
6532 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6533 i386_operand_type types, const char *disp_start)
6535 i386_operand_type bigdisp;
6538 /* We do this to make sure that the section symbol is in
6539 the symbol table. We will ultimately change the relocation
6540 to be relative to the beginning of the section. */
6541 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6542 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6543 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6545 if (exp->X_op != O_symbol)
6548 if (S_IS_LOCAL (exp->X_add_symbol)
6549 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6550 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6551 exp->X_op = O_subtract;
6552 exp->X_op_symbol = GOT_symbol;
6553 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6554 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6555 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6556 i.reloc[this_operand] = BFD_RELOC_64;
6558 i.reloc[this_operand] = BFD_RELOC_32;
6561 else if (exp->X_op == O_absent
6562 || exp->X_op == O_illegal
6563 || exp->X_op == O_big)
6566 as_bad (_("missing or invalid displacement expression `%s'"),
6571 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6572 else if (exp->X_op != O_constant
6573 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6574 && exp_seg != absolute_section
6575 && exp_seg != text_section
6576 && exp_seg != data_section
6577 && exp_seg != bss_section
6578 && exp_seg != undefined_section
6579 && !bfd_is_com_section (exp_seg))
6581 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6586 /* Check if this is a displacement only operand. */
6587 bigdisp = i.types[this_operand];
6588 bigdisp.bitfield.disp8 = 0;
6589 bigdisp.bitfield.disp16 = 0;
6590 bigdisp.bitfield.disp32 = 0;
6591 bigdisp.bitfield.disp32s = 0;
6592 bigdisp.bitfield.disp64 = 0;
6593 if (operand_type_all_zero (&bigdisp))
6594 i.types[this_operand] = operand_type_and (i.types[this_operand],
6600 /* Make sure the memory operand we've been dealt is valid.
6601 Return 1 on success, 0 on a failure. */
6604 i386_index_check (const char *operand_string)
6607 const char *kind = "base/index";
6608 #if INFER_ADDR_PREFIX
6614 if (current_templates->start->opcode_modifier.isstring
6615 && !current_templates->start->opcode_modifier.immext
6616 && (current_templates->end[-1].opcode_modifier.isstring
6619 /* Memory operands of string insns are special in that they only allow
6620 a single register (rDI, rSI, or rBX) as their memory address. */
6621 unsigned int expected;
6623 kind = "string address";
6625 if (current_templates->start->opcode_modifier.w)
6627 i386_operand_type type = current_templates->end[-1].operand_types[0];
6629 if (!type.bitfield.baseindex
6630 || ((!i.mem_operands != !intel_syntax)
6631 && current_templates->end[-1].operand_types[1]
6632 .bitfield.baseindex))
6633 type = current_templates->end[-1].operand_types[1];
6634 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6637 expected = 3 /* rBX */;
6639 if (!i.base_reg || i.index_reg
6640 || operand_type_check (i.types[this_operand], disp))
6642 else if (!(flag_code == CODE_64BIT
6643 ? i.prefix[ADDR_PREFIX]
6644 ? i.base_reg->reg_type.bitfield.reg32
6645 : i.base_reg->reg_type.bitfield.reg64
6646 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6647 ? i.base_reg->reg_type.bitfield.reg32
6648 : i.base_reg->reg_type.bitfield.reg16))
6650 else if (i.base_reg->reg_num != expected)
6657 for (j = 0; j < i386_regtab_size; ++j)
6658 if ((flag_code == CODE_64BIT
6659 ? i.prefix[ADDR_PREFIX]
6660 ? i386_regtab[j].reg_type.bitfield.reg32
6661 : i386_regtab[j].reg_type.bitfield.reg64
6662 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6663 ? i386_regtab[j].reg_type.bitfield.reg32
6664 : i386_regtab[j].reg_type.bitfield.reg16)
6665 && i386_regtab[j].reg_num == expected)
6667 gas_assert (j < i386_regtab_size);
6668 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6670 intel_syntax ? '[' : '(',
6672 i386_regtab[j].reg_name,
6673 intel_syntax ? ']' : ')');
6677 else if (flag_code == CODE_64BIT)
6680 && ((i.prefix[ADDR_PREFIX] == 0
6681 && !i.base_reg->reg_type.bitfield.reg64)
6682 || (i.prefix[ADDR_PREFIX]
6683 && !i.base_reg->reg_type.bitfield.reg32))
6685 || i.base_reg->reg_num !=
6686 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6688 && (!i.index_reg->reg_type.bitfield.baseindex
6689 || (i.prefix[ADDR_PREFIX] == 0
6690 && i.index_reg->reg_num != RegRiz
6691 && !i.index_reg->reg_type.bitfield.reg64
6693 || (i.prefix[ADDR_PREFIX]
6694 && i.index_reg->reg_num != RegEiz
6695 && !i.index_reg->reg_type.bitfield.reg32))))
6700 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6704 && (!i.base_reg->reg_type.bitfield.reg16
6705 || !i.base_reg->reg_type.bitfield.baseindex))
6707 && (!i.index_reg->reg_type.bitfield.reg16
6708 || !i.index_reg->reg_type.bitfield.baseindex
6710 && i.base_reg->reg_num < 6
6711 && i.index_reg->reg_num >= 6
6712 && i.log2_scale_factor == 0))))
6719 && !i.base_reg->reg_type.bitfield.reg32)
6721 && ((!i.index_reg->reg_type.bitfield.reg32
6722 && i.index_reg->reg_num != RegEiz)
6723 || !i.index_reg->reg_type.bitfield.baseindex)))
6729 #if INFER_ADDR_PREFIX
6730 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
6732 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6734 /* Change the size of any displacement too. At most one of
6735 Disp16 or Disp32 is set.
6736 FIXME. There doesn't seem to be any real need for separate
6737 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6738 Removing them would probably clean up the code quite a lot. */
6739 if (flag_code != CODE_64BIT
6740 && (i.types[this_operand].bitfield.disp16
6741 || i.types[this_operand].bitfield.disp32))
6742 i.types[this_operand]
6743 = operand_type_xor (i.types[this_operand], disp16_32);
6748 as_bad (_("`%s' is not a valid %s expression"),
6753 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6755 flag_code_names[i.prefix[ADDR_PREFIX]
6756 ? flag_code == CODE_32BIT
6765 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6769 i386_att_operand (char *operand_string)
6773 char *op_string = operand_string;
6775 if (is_space_char (*op_string))
6778 /* We check for an absolute prefix (differentiating,
6779 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6780 if (*op_string == ABSOLUTE_PREFIX)
6783 if (is_space_char (*op_string))
6785 i.types[this_operand].bitfield.jumpabsolute = 1;
6788 /* Check if operand is a register. */
6789 if ((r = parse_register (op_string, &end_op)) != NULL)
6791 i386_operand_type temp;
6793 /* Check for a segment override by searching for ':' after a
6794 segment register. */
6796 if (is_space_char (*op_string))
6798 if (*op_string == ':'
6799 && (r->reg_type.bitfield.sreg2
6800 || r->reg_type.bitfield.sreg3))
6805 i.seg[i.mem_operands] = &es;
6808 i.seg[i.mem_operands] = &cs;
6811 i.seg[i.mem_operands] = &ss;
6814 i.seg[i.mem_operands] = &ds;
6817 i.seg[i.mem_operands] = &fs;
6820 i.seg[i.mem_operands] = &gs;
6824 /* Skip the ':' and whitespace. */
6826 if (is_space_char (*op_string))
6829 if (!is_digit_char (*op_string)
6830 && !is_identifier_char (*op_string)
6831 && *op_string != '('
6832 && *op_string != ABSOLUTE_PREFIX)
6834 as_bad (_("bad memory operand `%s'"), op_string);
6837 /* Handle case of %es:*foo. */
6838 if (*op_string == ABSOLUTE_PREFIX)
6841 if (is_space_char (*op_string))
6843 i.types[this_operand].bitfield.jumpabsolute = 1;
6845 goto do_memory_reference;
6849 as_bad (_("junk `%s' after register"), op_string);
6853 temp.bitfield.baseindex = 0;
6854 i.types[this_operand] = operand_type_or (i.types[this_operand],
6856 i.types[this_operand].bitfield.unspecified = 0;
6857 i.op[this_operand].regs = r;
6860 else if (*op_string == REGISTER_PREFIX)
6862 as_bad (_("bad register name `%s'"), op_string);
6865 else if (*op_string == IMMEDIATE_PREFIX)
6868 if (i.types[this_operand].bitfield.jumpabsolute)
6870 as_bad (_("immediate operand illegal with absolute jump"));
6873 if (!i386_immediate (op_string))
6876 else if (is_digit_char (*op_string)
6877 || is_identifier_char (*op_string)
6878 || *op_string == '(')
6880 /* This is a memory reference of some sort. */
6883 /* Start and end of displacement string expression (if found). */
6884 char *displacement_string_start;
6885 char *displacement_string_end;
6887 do_memory_reference:
6888 if ((i.mem_operands == 1
6889 && !current_templates->start->opcode_modifier.isstring)
6890 || i.mem_operands == 2)
6892 as_bad (_("too many memory references for `%s'"),
6893 current_templates->start->name);
6897 /* Check for base index form. We detect the base index form by
6898 looking for an ')' at the end of the operand, searching
6899 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6901 base_string = op_string + strlen (op_string);
6904 if (is_space_char (*base_string))
6907 /* If we only have a displacement, set-up for it to be parsed later. */
6908 displacement_string_start = op_string;
6909 displacement_string_end = base_string + 1;
6911 if (*base_string == ')')
6914 unsigned int parens_balanced = 1;
6915 /* We've already checked that the number of left & right ()'s are
6916 equal, so this loop will not be infinite. */
6920 if (*base_string == ')')
6922 if (*base_string == '(')
6925 while (parens_balanced);
6927 temp_string = base_string;
6929 /* Skip past '(' and whitespace. */
6931 if (is_space_char (*base_string))
6934 if (*base_string == ','
6935 || ((i.base_reg = parse_register (base_string, &end_op))
6938 displacement_string_end = temp_string;
6940 i.types[this_operand].bitfield.baseindex = 1;
6944 base_string = end_op;
6945 if (is_space_char (*base_string))
6949 /* There may be an index reg or scale factor here. */
6950 if (*base_string == ',')
6953 if (is_space_char (*base_string))
6956 if ((i.index_reg = parse_register (base_string, &end_op))
6959 base_string = end_op;
6960 if (is_space_char (*base_string))
6962 if (*base_string == ',')
6965 if (is_space_char (*base_string))
6968 else if (*base_string != ')')
6970 as_bad (_("expecting `,' or `)' "
6971 "after index register in `%s'"),
6976 else if (*base_string == REGISTER_PREFIX)
6978 as_bad (_("bad register name `%s'"), base_string);
6982 /* Check for scale factor. */
6983 if (*base_string != ')')
6985 char *end_scale = i386_scale (base_string);
6990 base_string = end_scale;
6991 if (is_space_char (*base_string))
6993 if (*base_string != ')')
6995 as_bad (_("expecting `)' "
6996 "after scale factor in `%s'"),
7001 else if (!i.index_reg)
7003 as_bad (_("expecting index register or scale factor "
7004 "after `,'; got '%c'"),
7009 else if (*base_string != ')')
7011 as_bad (_("expecting `,' or `)' "
7012 "after base register in `%s'"),
7017 else if (*base_string == REGISTER_PREFIX)
7019 as_bad (_("bad register name `%s'"), base_string);
7024 /* If there's an expression beginning the operand, parse it,
7025 assuming displacement_string_start and
7026 displacement_string_end are meaningful. */
7027 if (displacement_string_start != displacement_string_end)
7029 if (!i386_displacement (displacement_string_start,
7030 displacement_string_end))
7034 /* Special case for (%dx) while doing input/output op. */
7036 && operand_type_equal (&i.base_reg->reg_type,
7037 ®16_inoutportreg)
7039 && i.log2_scale_factor == 0
7040 && i.seg[i.mem_operands] == 0
7041 && !operand_type_check (i.types[this_operand], disp))
7043 i.types[this_operand] = inoutportreg;
7047 if (i386_index_check (operand_string) == 0)
7049 i.types[this_operand].bitfield.mem = 1;
7054 /* It's not a memory operand; argh! */
7055 as_bad (_("invalid char %s beginning operand %d `%s'"),
7056 output_invalid (*op_string),
7061 return 1; /* Normal return. */
7064 /* md_estimate_size_before_relax()
7066 Called just before relax() for rs_machine_dependent frags. The x86
7067 assembler uses these frags to handle variable size jump
7070 Any symbol that is now undefined will not become defined.
7071 Return the correct fr_subtype in the frag.
7072 Return the initial "guess for variable size of frag" to caller.
7073 The guess is actually the growth beyond the fixed part. Whatever
7074 we do to grow the fixed or variable part contributes to our
7078 md_estimate_size_before_relax (fragP, segment)
7082 /* We've already got fragP->fr_subtype right; all we have to do is
7083 check for un-relaxable symbols. On an ELF system, we can't relax
7084 an externally visible symbol, because it may be overridden by a
7086 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
7087 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7089 && (S_IS_EXTERNAL (fragP->fr_symbol)
7090 || S_IS_WEAK (fragP->fr_symbol)
7091 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7092 & BSF_GNU_INDIRECT_FUNCTION))))
7094 #if defined (OBJ_COFF) && defined (TE_PE)
7095 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
7096 && S_IS_WEAK (fragP->fr_symbol))
7100 /* Symbol is undefined in this segment, or we need to keep a
7101 reloc so that weak symbols can be overridden. */
7102 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
7103 enum bfd_reloc_code_real reloc_type;
7104 unsigned char *opcode;
7107 if (fragP->fr_var != NO_RELOC)
7108 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
7110 reloc_type = BFD_RELOC_16_PCREL;
7112 reloc_type = BFD_RELOC_32_PCREL;
7114 old_fr_fix = fragP->fr_fix;
7115 opcode = (unsigned char *) fragP->fr_opcode;
7117 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
7120 /* Make jmp (0xeb) a (d)word displacement jump. */
7122 fragP->fr_fix += size;
7123 fix_new (fragP, old_fr_fix, size,
7125 fragP->fr_offset, 1,
7131 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
7133 /* Negate the condition, and branch past an
7134 unconditional jump. */
7137 /* Insert an unconditional jump. */
7139 /* We added two extra opcode bytes, and have a two byte
7141 fragP->fr_fix += 2 + 2;
7142 fix_new (fragP, old_fr_fix + 2, 2,
7144 fragP->fr_offset, 1,
7151 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7156 fixP = fix_new (fragP, old_fr_fix, 1,
7158 fragP->fr_offset, 1,
7160 fixP->fx_signed = 1;
7164 /* This changes the byte-displacement jump 0x7N
7165 to the (d)word-displacement jump 0x0f,0x8N. */
7166 opcode[1] = opcode[0] + 0x10;
7167 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7168 /* We've added an opcode byte. */
7169 fragP->fr_fix += 1 + size;
7170 fix_new (fragP, old_fr_fix + 1, size,
7172 fragP->fr_offset, 1,
7177 BAD_CASE (fragP->fr_subtype);
7181 return fragP->fr_fix - old_fr_fix;
7184 /* Guess size depending on current relax state. Initially the relax
7185 state will correspond to a short jump and we return 1, because
7186 the variable part of the frag (the branch offset) is one byte
7187 long. However, we can relax a section more than once and in that
7188 case we must either set fr_subtype back to the unrelaxed state,
7189 or return the value for the appropriate branch. */
7190 return md_relax_table[fragP->fr_subtype].rlx_length;
7193 /* Called after relax() is finished.
7195 In: Address of frag.
7196 fr_type == rs_machine_dependent.
7197 fr_subtype is what the address relaxed to.
7199 Out: Any fixSs and constants are set up.
7200 Caller will turn frag into a ".space 0". */
7203 md_convert_frag (abfd, sec, fragP)
7204 bfd *abfd ATTRIBUTE_UNUSED;
7205 segT sec ATTRIBUTE_UNUSED;
7208 unsigned char *opcode;
7209 unsigned char *where_to_put_displacement = NULL;
7210 offsetT target_address;
7211 offsetT opcode_address;
7212 unsigned int extension = 0;
7213 offsetT displacement_from_opcode_start;
7215 opcode = (unsigned char *) fragP->fr_opcode;
7217 /* Address we want to reach in file space. */
7218 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
7220 /* Address opcode resides at in file space. */
7221 opcode_address = fragP->fr_address + fragP->fr_fix;
7223 /* Displacement from opcode start to fill into instruction. */
7224 displacement_from_opcode_start = target_address - opcode_address;
7226 if ((fragP->fr_subtype & BIG) == 0)
7228 /* Don't have to change opcode. */
7229 extension = 1; /* 1 opcode + 1 displacement */
7230 where_to_put_displacement = &opcode[1];
7234 if (no_cond_jump_promotion
7235 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
7236 as_warn_where (fragP->fr_file, fragP->fr_line,
7237 _("long jump required"));
7239 switch (fragP->fr_subtype)
7241 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7242 extension = 4; /* 1 opcode + 4 displacement */
7244 where_to_put_displacement = &opcode[1];
7247 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7248 extension = 2; /* 1 opcode + 2 displacement */
7250 where_to_put_displacement = &opcode[1];
7253 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7254 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7255 extension = 5; /* 2 opcode + 4 displacement */
7256 opcode[1] = opcode[0] + 0x10;
7257 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7258 where_to_put_displacement = &opcode[2];
7261 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7262 extension = 3; /* 2 opcode + 2 displacement */
7263 opcode[1] = opcode[0] + 0x10;
7264 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7265 where_to_put_displacement = &opcode[2];
7268 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7273 where_to_put_displacement = &opcode[3];
7277 BAD_CASE (fragP->fr_subtype);
7282 /* If size if less then four we are sure that the operand fits,
7283 but if it's 4, then it could be that the displacement is larger
7285 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7287 && ((addressT) (displacement_from_opcode_start - extension
7288 + ((addressT) 1 << 31))
7289 > (((addressT) 2 << 31) - 1)))
7291 as_bad_where (fragP->fr_file, fragP->fr_line,
7292 _("jump target out of range"));
7293 /* Make us emit 0. */
7294 displacement_from_opcode_start = extension;
7296 /* Now put displacement after opcode. */
7297 md_number_to_chars ((char *) where_to_put_displacement,
7298 (valueT) (displacement_from_opcode_start - extension),
7299 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
7300 fragP->fr_fix += extension;
7303 /* Apply a fixup (fixS) to segment data, once it has been determined
7304 by our caller that we have all the info we need to fix it up.
7306 On the 386, immediates, displacements, and data pointers are all in
7307 the same (little-endian) format, so we don't need to care about which
7311 md_apply_fix (fixP, valP, seg)
7312 /* The fix we're to put in. */
7314 /* Pointer to the value of the bits. */
7316 /* Segment fix is from. */
7317 segT seg ATTRIBUTE_UNUSED;
7319 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
7320 valueT value = *valP;
7322 #if !defined (TE_Mach)
7325 switch (fixP->fx_r_type)
7331 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7334 case BFD_RELOC_X86_64_32S:
7335 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7338 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7341 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7346 if (fixP->fx_addsy != NULL
7347 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
7348 || fixP->fx_r_type == BFD_RELOC_64_PCREL
7349 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7350 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7351 && !use_rela_relocations)
7353 /* This is a hack. There should be a better way to handle this.
7354 This covers for the fact that bfd_install_relocation will
7355 subtract the current location (for partial_inplace, PC relative
7356 relocations); see more below. */
7360 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7363 value += fixP->fx_where + fixP->fx_frag->fr_address;
7365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7368 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
7371 || (symbol_section_p (fixP->fx_addsy)
7372 && sym_seg != absolute_section))
7373 && !generic_force_reloc (fixP))
7375 /* Yes, we add the values in twice. This is because
7376 bfd_install_relocation subtracts them out again. I think
7377 bfd_install_relocation is broken, but I don't dare change
7379 value += fixP->fx_where + fixP->fx_frag->fr_address;
7383 #if defined (OBJ_COFF) && defined (TE_PE)
7384 /* For some reason, the PE format does not store a
7385 section address offset for a PC relative symbol. */
7386 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7387 || S_IS_WEAK (fixP->fx_addsy))
7388 value += md_pcrel_from (fixP);
7391 #if defined (OBJ_COFF) && defined (TE_PE)
7392 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7394 value -= S_GET_VALUE (fixP->fx_addsy);
7398 /* Fix a few things - the dynamic linker expects certain values here,
7399 and we must not disappoint it. */
7400 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7401 if (IS_ELF && fixP->fx_addsy)
7402 switch (fixP->fx_r_type)
7404 case BFD_RELOC_386_PLT32:
7405 case BFD_RELOC_X86_64_PLT32:
7406 /* Make the jump instruction point to the address of the operand. At
7407 runtime we merely add the offset to the actual PLT entry. */
7411 case BFD_RELOC_386_TLS_GD:
7412 case BFD_RELOC_386_TLS_LDM:
7413 case BFD_RELOC_386_TLS_IE_32:
7414 case BFD_RELOC_386_TLS_IE:
7415 case BFD_RELOC_386_TLS_GOTIE:
7416 case BFD_RELOC_386_TLS_GOTDESC:
7417 case BFD_RELOC_X86_64_TLSGD:
7418 case BFD_RELOC_X86_64_TLSLD:
7419 case BFD_RELOC_X86_64_GOTTPOFF:
7420 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7421 value = 0; /* Fully resolved at runtime. No addend. */
7423 case BFD_RELOC_386_TLS_LE:
7424 case BFD_RELOC_386_TLS_LDO_32:
7425 case BFD_RELOC_386_TLS_LE_32:
7426 case BFD_RELOC_X86_64_DTPOFF32:
7427 case BFD_RELOC_X86_64_DTPOFF64:
7428 case BFD_RELOC_X86_64_TPOFF32:
7429 case BFD_RELOC_X86_64_TPOFF64:
7430 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7433 case BFD_RELOC_386_TLS_DESC_CALL:
7434 case BFD_RELOC_X86_64_TLSDESC_CALL:
7435 value = 0; /* Fully resolved at runtime. No addend. */
7436 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7440 case BFD_RELOC_386_GOT32:
7441 case BFD_RELOC_X86_64_GOT32:
7442 value = 0; /* Fully resolved at runtime. No addend. */
7445 case BFD_RELOC_VTABLE_INHERIT:
7446 case BFD_RELOC_VTABLE_ENTRY:
7453 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7455 #endif /* !defined (TE_Mach) */
7457 /* Are we finished with this relocation now? */
7458 if (fixP->fx_addsy == NULL)
7460 #if defined (OBJ_COFF) && defined (TE_PE)
7461 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7464 /* Remember value for tc_gen_reloc. */
7465 fixP->fx_addnumber = value;
7466 /* Clear out the frag for now. */
7470 else if (use_rela_relocations)
7472 fixP->fx_no_overflow = 1;
7473 /* Remember value for tc_gen_reloc. */
7474 fixP->fx_addnumber = value;
7478 md_number_to_chars (p, value, fixP->fx_size);
7482 md_atof (int type, char *litP, int *sizeP)
7484 /* This outputs the LITTLENUMs in REVERSE order;
7485 in accord with the bigendian 386. */
7486 return ieee_md_atof (type, litP, sizeP, FALSE);
7489 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
7492 output_invalid (int c)
7495 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7498 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7499 "(0x%x)", (unsigned char) c);
7500 return output_invalid_buf;
7503 /* REG_STRING starts *before* REGISTER_PREFIX. */
7505 static const reg_entry *
7506 parse_real_register (char *reg_string, char **end_op)
7508 char *s = reg_string;
7510 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7513 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7514 if (*s == REGISTER_PREFIX)
7517 if (is_space_char (*s))
7521 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7523 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7524 return (const reg_entry *) NULL;
7528 /* For naked regs, make sure that we are not dealing with an identifier.
7529 This prevents confusing an identifier like `eax_var' with register
7531 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7532 return (const reg_entry *) NULL;
7536 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7538 /* Handle floating point regs, allowing spaces in the (i) part. */
7539 if (r == i386_regtab /* %st is first entry of table */)
7541 if (is_space_char (*s))
7546 if (is_space_char (*s))
7548 if (*s >= '0' && *s <= '7')
7552 if (is_space_char (*s))
7557 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
7562 /* We have "%st(" then garbage. */
7563 return (const reg_entry *) NULL;
7567 if (r == NULL || allow_pseudo_reg)
7570 if (operand_type_all_zero (&r->reg_type))
7571 return (const reg_entry *) NULL;
7573 if ((r->reg_type.bitfield.reg32
7574 || r->reg_type.bitfield.sreg3
7575 || r->reg_type.bitfield.control
7576 || r->reg_type.bitfield.debug
7577 || r->reg_type.bitfield.test)
7578 && !cpu_arch_flags.bitfield.cpui386)
7579 return (const reg_entry *) NULL;
7581 if (r->reg_type.bitfield.floatreg
7582 && !cpu_arch_flags.bitfield.cpu8087
7583 && !cpu_arch_flags.bitfield.cpu287
7584 && !cpu_arch_flags.bitfield.cpu387)
7585 return (const reg_entry *) NULL;
7587 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7588 return (const reg_entry *) NULL;
7590 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7591 return (const reg_entry *) NULL;
7593 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7594 return (const reg_entry *) NULL;
7596 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7597 if (!allow_index_reg
7598 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7599 return (const reg_entry *) NULL;
7601 if (((r->reg_flags & (RegRex64 | RegRex))
7602 || r->reg_type.bitfield.reg64)
7603 && (!cpu_arch_flags.bitfield.cpulm
7604 || !operand_type_equal (&r->reg_type, &control))
7605 && flag_code != CODE_64BIT)
7606 return (const reg_entry *) NULL;
7608 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7609 return (const reg_entry *) NULL;
7614 /* REG_STRING starts *before* REGISTER_PREFIX. */
7616 static const reg_entry *
7617 parse_register (char *reg_string, char **end_op)
7621 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7622 r = parse_real_register (reg_string, end_op);
7627 char *save = input_line_pointer;
7631 input_line_pointer = reg_string;
7632 c = get_symbol_end ();
7633 symbolP = symbol_find (reg_string);
7634 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7636 const expressionS *e = symbol_get_value_expression (symbolP);
7638 know (e->X_op == O_register);
7639 know (e->X_add_number >= 0
7640 && (valueT) e->X_add_number < i386_regtab_size);
7641 r = i386_regtab + e->X_add_number;
7642 *end_op = input_line_pointer;
7644 *input_line_pointer = c;
7645 input_line_pointer = save;
7651 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7654 char *end = input_line_pointer;
7657 r = parse_register (name, &input_line_pointer);
7658 if (r && end <= input_line_pointer)
7660 *nextcharP = *input_line_pointer;
7661 *input_line_pointer = 0;
7662 e->X_op = O_register;
7663 e->X_add_number = r - i386_regtab;
7666 input_line_pointer = end;
7668 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
7672 md_operand (expressionS *e)
7677 switch (*input_line_pointer)
7679 case REGISTER_PREFIX:
7680 r = parse_real_register (input_line_pointer, &end);
7683 e->X_op = O_register;
7684 e->X_add_number = r - i386_regtab;
7685 input_line_pointer = end;
7690 gas_assert (intel_syntax);
7691 end = input_line_pointer++;
7693 if (*input_line_pointer == ']')
7695 ++input_line_pointer;
7696 e->X_op_symbol = make_expr_symbol (e);
7697 e->X_add_symbol = NULL;
7698 e->X_add_number = 0;
7704 input_line_pointer = end;
7711 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7712 const char *md_shortopts = "kVQ:sqn";
7714 const char *md_shortopts = "qn";
7717 #define OPTION_32 (OPTION_MD_BASE + 0)
7718 #define OPTION_64 (OPTION_MD_BASE + 1)
7719 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7720 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7721 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7722 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7723 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7724 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7725 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7726 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7727 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7728 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7730 struct option md_longopts[] =
7732 {"32", no_argument, NULL, OPTION_32},
7733 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7734 || defined (TE_PE) || defined (TE_PEP))
7735 {"64", no_argument, NULL, OPTION_64},
7737 {"divide", no_argument, NULL, OPTION_DIVIDE},
7738 {"march", required_argument, NULL, OPTION_MARCH},
7739 {"mtune", required_argument, NULL, OPTION_MTUNE},
7740 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7741 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7742 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7743 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7744 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7745 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
7746 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7747 {NULL, no_argument, NULL, 0}
7749 size_t md_longopts_size = sizeof (md_longopts);
7752 md_parse_option (int c, char *arg)
7760 optimize_align_code = 0;
7767 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7768 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7769 should be emitted or not. FIXME: Not implemented. */
7773 /* -V: SVR4 argument to print version ID. */
7775 print_version_id ();
7778 /* -k: Ignore for FreeBSD compatibility. */
7783 /* -s: On i386 Solaris, this tells the native assembler to use
7784 .stab instead of .stab.excl. We always use .stab anyhow. */
7787 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7788 || defined (TE_PE) || defined (TE_PEP))
7791 const char **list, **l;
7793 list = bfd_target_list ();
7794 for (l = list; *l != NULL; l++)
7795 if (CONST_STRNEQ (*l, "elf64-x86-64")
7796 || strcmp (*l, "coff-x86-64") == 0
7797 || strcmp (*l, "pe-x86-64") == 0
7798 || strcmp (*l, "pei-x86-64") == 0)
7800 default_arch = "x86_64";
7804 as_fatal (_("No compiled in support for x86_64"));
7811 default_arch = "i386";
7815 #ifdef SVR4_COMMENT_CHARS
7820 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7822 for (s = i386_comment_chars; *s != '\0'; s++)
7826 i386_comment_chars = n;
7832 arch = xstrdup (arg);
7836 as_fatal (_("Invalid -march= option: `%s'"), arg);
7837 next = strchr (arch, '+');
7840 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7842 if (strcmp (arch, cpu_arch [i].name) == 0)
7845 cpu_arch_name = cpu_arch[i].name;
7846 cpu_sub_arch_name = NULL;
7847 cpu_arch_flags = cpu_arch[i].flags;
7848 cpu_arch_isa = cpu_arch[i].type;
7849 cpu_arch_isa_flags = cpu_arch[i].flags;
7850 if (!cpu_arch_tune_set)
7852 cpu_arch_tune = cpu_arch_isa;
7853 cpu_arch_tune_flags = cpu_arch_isa_flags;
7857 else if (*cpu_arch [i].name == '.'
7858 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7860 /* ISA entension. */
7861 i386_cpu_flags flags;
7863 if (strncmp (arch, "no", 2))
7864 flags = cpu_flags_or (cpu_arch_flags,
7867 flags = cpu_flags_and_not (cpu_arch_flags,
7869 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
7871 if (cpu_sub_arch_name)
7873 char *name = cpu_sub_arch_name;
7874 cpu_sub_arch_name = concat (name,
7876 (const char *) NULL);
7880 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7881 cpu_arch_flags = flags;
7887 if (i >= ARRAY_SIZE (cpu_arch))
7888 as_fatal (_("Invalid -march= option: `%s'"), arg);
7892 while (next != NULL );
7897 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7898 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7900 if (strcmp (arg, cpu_arch [i].name) == 0)
7902 cpu_arch_tune_set = 1;
7903 cpu_arch_tune = cpu_arch [i].type;
7904 cpu_arch_tune_flags = cpu_arch[i].flags;
7908 if (i >= ARRAY_SIZE (cpu_arch))
7909 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7912 case OPTION_MMNEMONIC:
7913 if (strcasecmp (arg, "att") == 0)
7915 else if (strcasecmp (arg, "intel") == 0)
7918 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7921 case OPTION_MSYNTAX:
7922 if (strcasecmp (arg, "att") == 0)
7924 else if (strcasecmp (arg, "intel") == 0)
7927 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7930 case OPTION_MINDEX_REG:
7931 allow_index_reg = 1;
7934 case OPTION_MNAKED_REG:
7935 allow_naked_reg = 1;
7938 case OPTION_MOLD_GCC:
7942 case OPTION_MSSE2AVX:
7946 case OPTION_MSSE_CHECK:
7947 if (strcasecmp (arg, "error") == 0)
7948 sse_check = sse_check_error;
7949 else if (strcasecmp (arg, "warning") == 0)
7950 sse_check = sse_check_warning;
7951 else if (strcasecmp (arg, "none") == 0)
7952 sse_check = sse_check_none;
7954 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7964 md_show_usage (stream)
7967 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7968 fprintf (stream, _("\
7970 -V print assembler version number\n\
7973 fprintf (stream, _("\
7974 -n Do not optimize code alignment\n\
7975 -q quieten some warnings\n"));
7976 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7977 fprintf (stream, _("\
7980 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7981 || defined (TE_PE) || defined (TE_PEP))
7982 fprintf (stream, _("\
7983 --32/--64 generate 32bit/64bit code\n"));
7985 #ifdef SVR4_COMMENT_CHARS
7986 fprintf (stream, _("\
7987 --divide do not treat `/' as a comment character\n"));
7989 fprintf (stream, _("\
7990 --divide ignored\n"));
7992 fprintf (stream, _("\
7993 -march=CPU[,+EXTENSION...]\n\
7994 generate code for CPU and EXTENSION, CPU is one of:\n\
7995 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7996 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7997 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
7998 amdfam10, generic32, generic64\n\
7999 EXTENSION is combination of:\n\
8000 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8001 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8002 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8003 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8004 svme, abm, padlock, fma4\n"));
8005 fprintf (stream, _("\
8006 -mtune=CPU optimize for CPU, CPU is one of:\n\
8007 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8008 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8009 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8010 amdfam10, generic32, generic64\n"));
8011 fprintf (stream, _("\
8012 -msse2avx encode SSE instructions with VEX prefix\n"));
8013 fprintf (stream, _("\
8014 -msse-check=[none|error|warning]\n\
8015 check SSE instructions\n"));
8016 fprintf (stream, _("\
8017 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8018 fprintf (stream, _("\
8019 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8020 fprintf (stream, _("\
8021 -mindex-reg support pseudo index registers\n"));
8022 fprintf (stream, _("\
8023 -mnaked-reg don't require `%%' prefix for registers\n"));
8024 fprintf (stream, _("\
8025 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8028 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8029 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8030 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8032 /* Pick the target format to use. */
8035 i386_target_format (void)
8037 if (!strcmp (default_arch, "x86_64"))
8039 set_code_flag (CODE_64BIT);
8040 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8042 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8043 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8044 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8045 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8046 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8047 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8048 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
8049 cpu_arch_isa_flags.bitfield.cpummx= 1;
8050 cpu_arch_isa_flags.bitfield.cpusse = 1;
8051 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8052 cpu_arch_isa_flags.bitfield.cpulm = 1;
8054 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8056 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8057 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8058 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8059 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8060 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8061 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8062 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
8063 cpu_arch_tune_flags.bitfield.cpummx= 1;
8064 cpu_arch_tune_flags.bitfield.cpusse = 1;
8065 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8068 else if (!strcmp (default_arch, "i386"))
8070 set_code_flag (CODE_32BIT);
8071 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8073 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8074 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8075 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8077 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8079 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8080 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8081 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8085 as_fatal (_("Unknown architecture"));
8086 switch (OUTPUT_FLAVOR)
8088 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8089 case bfd_target_aout_flavour:
8090 return AOUT_TARGET_FORMAT;
8092 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8093 # if defined (TE_PE) || defined (TE_PEP)
8094 case bfd_target_coff_flavour:
8095 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8096 # elif defined (TE_GO32)
8097 case bfd_target_coff_flavour:
8100 case bfd_target_coff_flavour:
8104 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8105 case bfd_target_elf_flavour:
8107 if (flag_code == CODE_64BIT)
8110 use_rela_relocations = 1;
8112 if (cpu_arch_isa == PROCESSOR_L1OM)
8114 if (flag_code != CODE_64BIT)
8115 as_fatal (_("Intel L1OM is 64bit only"));
8116 return ELF_TARGET_L1OM_FORMAT;
8119 return (flag_code == CODE_64BIT
8120 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
8123 #if defined (OBJ_MACH_O)
8124 case bfd_target_mach_o_flavour:
8125 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
8133 #endif /* OBJ_MAYBE_ more than one */
8135 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8137 i386_elf_emit_arch_note (void)
8139 if (IS_ELF && cpu_arch_name != NULL)
8142 asection *seg = now_seg;
8143 subsegT subseg = now_subseg;
8144 Elf_Internal_Note i_note;
8145 Elf_External_Note e_note;
8146 asection *note_secp;
8149 /* Create the .note section. */
8150 note_secp = subseg_new (".note", 0);
8151 bfd_set_section_flags (stdoutput,
8153 SEC_HAS_CONTENTS | SEC_READONLY);
8155 /* Process the arch string. */
8156 len = strlen (cpu_arch_name);
8158 i_note.namesz = len + 1;
8160 i_note.type = NT_ARCH;
8161 p = frag_more (sizeof (e_note.namesz));
8162 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8163 p = frag_more (sizeof (e_note.descsz));
8164 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8165 p = frag_more (sizeof (e_note.type));
8166 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8167 p = frag_more (len + 1);
8168 strcpy (p, cpu_arch_name);
8170 frag_align (2, 0, 0);
8172 subseg_set (seg, subseg);
8178 md_undefined_symbol (name)
8181 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8182 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8183 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8184 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
8188 if (symbol_find (name))
8189 as_bad (_("GOT already in symbol table"));
8190 GOT_symbol = symbol_new (name, undefined_section,
8191 (valueT) 0, &zero_address_frag);
8198 /* Round up a section size to the appropriate boundary. */
8201 md_section_align (segment, size)
8202 segT segment ATTRIBUTE_UNUSED;
8205 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8206 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8208 /* For a.out, force the section size to be aligned. If we don't do
8209 this, BFD will align it for us, but it will not write out the
8210 final bytes of the section. This may be a bug in BFD, but it is
8211 easier to fix it here since that is how the other a.out targets
8215 align = bfd_get_section_alignment (stdoutput, segment);
8216 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8223 /* On the i386, PC-relative offsets are relative to the start of the
8224 next instruction. That is, the address of the offset, plus its
8225 size, since the offset is always the last part of the insn. */
8228 md_pcrel_from (fixS *fixP)
8230 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8236 s_bss (int ignore ATTRIBUTE_UNUSED)
8240 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8242 obj_elf_section_change_hook ();
8244 temp = get_absolute_expression ();
8245 subseg_set (bss_section, (subsegT) temp);
8246 demand_empty_rest_of_line ();
8252 i386_validate_fix (fixS *fixp)
8254 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8256 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8260 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8265 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8267 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
8274 tc_gen_reloc (section, fixp)
8275 asection *section ATTRIBUTE_UNUSED;
8279 bfd_reloc_code_real_type code;
8281 switch (fixp->fx_r_type)
8283 case BFD_RELOC_X86_64_PLT32:
8284 case BFD_RELOC_X86_64_GOT32:
8285 case BFD_RELOC_X86_64_GOTPCREL:
8286 case BFD_RELOC_386_PLT32:
8287 case BFD_RELOC_386_GOT32:
8288 case BFD_RELOC_386_GOTOFF:
8289 case BFD_RELOC_386_GOTPC:
8290 case BFD_RELOC_386_TLS_GD:
8291 case BFD_RELOC_386_TLS_LDM:
8292 case BFD_RELOC_386_TLS_LDO_32:
8293 case BFD_RELOC_386_TLS_IE_32:
8294 case BFD_RELOC_386_TLS_IE:
8295 case BFD_RELOC_386_TLS_GOTIE:
8296 case BFD_RELOC_386_TLS_LE_32:
8297 case BFD_RELOC_386_TLS_LE:
8298 case BFD_RELOC_386_TLS_GOTDESC:
8299 case BFD_RELOC_386_TLS_DESC_CALL:
8300 case BFD_RELOC_X86_64_TLSGD:
8301 case BFD_RELOC_X86_64_TLSLD:
8302 case BFD_RELOC_X86_64_DTPOFF32:
8303 case BFD_RELOC_X86_64_DTPOFF64:
8304 case BFD_RELOC_X86_64_GOTTPOFF:
8305 case BFD_RELOC_X86_64_TPOFF32:
8306 case BFD_RELOC_X86_64_TPOFF64:
8307 case BFD_RELOC_X86_64_GOTOFF64:
8308 case BFD_RELOC_X86_64_GOTPC32:
8309 case BFD_RELOC_X86_64_GOT64:
8310 case BFD_RELOC_X86_64_GOTPCREL64:
8311 case BFD_RELOC_X86_64_GOTPC64:
8312 case BFD_RELOC_X86_64_GOTPLT64:
8313 case BFD_RELOC_X86_64_PLTOFF64:
8314 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8315 case BFD_RELOC_X86_64_TLSDESC_CALL:
8317 case BFD_RELOC_VTABLE_ENTRY:
8318 case BFD_RELOC_VTABLE_INHERIT:
8320 case BFD_RELOC_32_SECREL:
8322 code = fixp->fx_r_type;
8324 case BFD_RELOC_X86_64_32S:
8325 if (!fixp->fx_pcrel)
8327 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8328 code = fixp->fx_r_type;
8334 switch (fixp->fx_size)
8337 as_bad_where (fixp->fx_file, fixp->fx_line,
8338 _("can not do %d byte pc-relative relocation"),
8340 code = BFD_RELOC_32_PCREL;
8342 case 1: code = BFD_RELOC_8_PCREL; break;
8343 case 2: code = BFD_RELOC_16_PCREL; break;
8344 case 4: code = BFD_RELOC_32_PCREL; break;
8346 case 8: code = BFD_RELOC_64_PCREL; break;
8352 switch (fixp->fx_size)
8355 as_bad_where (fixp->fx_file, fixp->fx_line,
8356 _("can not do %d byte relocation"),
8358 code = BFD_RELOC_32;
8360 case 1: code = BFD_RELOC_8; break;
8361 case 2: code = BFD_RELOC_16; break;
8362 case 4: code = BFD_RELOC_32; break;
8364 case 8: code = BFD_RELOC_64; break;
8371 if ((code == BFD_RELOC_32
8372 || code == BFD_RELOC_32_PCREL
8373 || code == BFD_RELOC_X86_64_32S)
8375 && fixp->fx_addsy == GOT_symbol)
8378 code = BFD_RELOC_386_GOTPC;
8380 code = BFD_RELOC_X86_64_GOTPC32;
8382 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8384 && fixp->fx_addsy == GOT_symbol)
8386 code = BFD_RELOC_X86_64_GOTPC64;
8389 rel = (arelent *) xmalloc (sizeof (arelent));
8390 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8391 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8393 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
8395 if (!use_rela_relocations)
8397 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8398 vtable entry to be used in the relocation's section offset. */
8399 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8400 rel->address = fixp->fx_offset;
8401 #if defined (OBJ_COFF) && defined (TE_PE)
8402 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8403 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8408 /* Use the rela in 64bit mode. */
8411 if (!fixp->fx_pcrel)
8412 rel->addend = fixp->fx_offset;
8416 case BFD_RELOC_X86_64_PLT32:
8417 case BFD_RELOC_X86_64_GOT32:
8418 case BFD_RELOC_X86_64_GOTPCREL:
8419 case BFD_RELOC_X86_64_TLSGD:
8420 case BFD_RELOC_X86_64_TLSLD:
8421 case BFD_RELOC_X86_64_GOTTPOFF:
8422 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8423 case BFD_RELOC_X86_64_TLSDESC_CALL:
8424 rel->addend = fixp->fx_offset - fixp->fx_size;
8427 rel->addend = (section->vma
8429 + fixp->fx_addnumber
8430 + md_pcrel_from (fixp));
8435 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8436 if (rel->howto == NULL)
8438 as_bad_where (fixp->fx_file, fixp->fx_line,
8439 _("cannot represent relocation type %s"),
8440 bfd_get_reloc_code_name (code));
8441 /* Set howto to a garbage value so that we can keep going. */
8442 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8443 gas_assert (rel->howto != NULL);
8449 #include "tc-i386-intel.c"
8452 tc_x86_parse_to_dw2regnum (expressionS *exp)
8454 int saved_naked_reg;
8455 char saved_register_dot;
8457 saved_naked_reg = allow_naked_reg;
8458 allow_naked_reg = 1;
8459 saved_register_dot = register_chars['.'];
8460 register_chars['.'] = '.';
8461 allow_pseudo_reg = 1;
8462 expression_and_evaluate (exp);
8463 allow_pseudo_reg = 0;
8464 register_chars['.'] = saved_register_dot;
8465 allow_naked_reg = saved_naked_reg;
8467 if (exp->X_op == O_register && exp->X_add_number >= 0)
8469 if ((addressT) exp->X_add_number < i386_regtab_size)
8471 exp->X_op = O_constant;
8472 exp->X_add_number = i386_regtab[exp->X_add_number]
8473 .dw2_regnum[flag_code >> 1];
8476 exp->X_op = O_illegal;
8481 tc_x86_frame_initial_instructions (void)
8483 static unsigned int sp_regno[2];
8485 if (!sp_regno[flag_code >> 1])
8487 char *saved_input = input_line_pointer;
8488 char sp[][4] = {"esp", "rsp"};
8491 input_line_pointer = sp[flag_code >> 1];
8492 tc_x86_parse_to_dw2regnum (&exp);
8493 gas_assert (exp.X_op == O_constant);
8494 sp_regno[flag_code >> 1] = exp.X_add_number;
8495 input_line_pointer = saved_input;
8498 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
8499 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8503 i386_elf_section_type (const char *str, size_t len)
8505 if (flag_code == CODE_64BIT
8506 && len == sizeof ("unwind") - 1
8507 && strncmp (str, "unwind", 6) == 0)
8508 return SHT_X86_64_UNWIND;
8515 i386_solaris_fix_up_eh_frame (segT sec)
8517 if (flag_code == CODE_64BIT)
8518 elf_section_type (sec) = SHT_X86_64_UNWIND;
8524 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8528 expr.X_op = O_secrel;
8529 expr.X_add_symbol = symbol;
8530 expr.X_add_number = 0;
8531 emit_expr (&expr, size);
8535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8536 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8539 x86_64_section_letter (int letter, char **ptr_msg)
8541 if (flag_code == CODE_64BIT)
8544 return SHF_X86_64_LARGE;
8546 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8549 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8554 x86_64_section_word (char *str, size_t len)
8556 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8557 return SHF_X86_64_LARGE;
8563 handle_large_common (int small ATTRIBUTE_UNUSED)
8565 if (flag_code != CODE_64BIT)
8567 s_comm_internal (0, elf_common_parse);
8568 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8572 static segT lbss_section;
8573 asection *saved_com_section_ptr = elf_com_section_ptr;
8574 asection *saved_bss_section = bss_section;
8576 if (lbss_section == NULL)
8578 flagword applicable;
8580 subsegT subseg = now_subseg;
8582 /* The .lbss section is for local .largecomm symbols. */
8583 lbss_section = subseg_new (".lbss", 0);
8584 applicable = bfd_applicable_section_flags (stdoutput);
8585 bfd_set_section_flags (stdoutput, lbss_section,
8586 applicable & SEC_ALLOC);
8587 seg_info (lbss_section)->bss = 1;
8589 subseg_set (seg, subseg);
8592 elf_com_section_ptr = &_bfd_elf_large_com_section;
8593 bss_section = lbss_section;
8595 s_comm_internal (0, elf_common_parse);
8597 elf_com_section_ptr = saved_com_section_ptr;
8598 bss_section = saved_bss_section;
8601 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */