2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
39 * Functions to provide access to special i386 instructions.
40 * This in included in sys/systm.h, and that file should be
41 * used in preference to this.
44 #ifndef _CPU_CPUFUNC_H_
45 #define _CPU_CPUFUNC_H_
47 #include <sys/cdefs.h>
48 #include <machine/psl.h>
51 struct region_descriptor;
54 #define readb(va) (*(volatile u_int8_t *) (va))
55 #define readw(va) (*(volatile u_int16_t *) (va))
56 #define readl(va) (*(volatile u_int32_t *) (va))
57 #define readq(va) (*(volatile u_int64_t *) (va))
59 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
60 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
61 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
67 #include <machine/lock.h> /* XXX */
73 __asm __volatile("int $3");
79 __asm __volatile("pause");
87 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
91 static __inline u_long
96 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
100 static __inline u_int
105 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
109 static __inline u_long
114 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
119 do_cpuid(u_int ax, u_int *p)
121 __asm __volatile("cpuid"
122 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
127 cpuid_count(u_int ax, u_int cx, u_int *p)
129 __asm __volatile("cpuid"
130 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
131 : "0" (ax), "c" (cx));
134 #ifndef _CPU_DISABLE_INTR_DEFINED
137 cpu_disable_intr(void)
139 __asm __volatile("cli" : : : "memory");
144 #ifndef _CPU_ENABLE_INTR_DEFINED
147 cpu_enable_intr(void)
149 __asm __volatile("sti");
155 * Cpu and compiler memory ordering fence. mfence ensures strong read and
158 * A serializing or fence instruction is required here. A locked bus
159 * cycle on data for which we already own cache mastership is the most
166 __asm __volatile("mfence" : : : "memory");
168 __asm __volatile("" : : : "memory");
173 * cpu_lfence() ensures strong read ordering for reads issued prior
174 * to the instruction verses reads issued afterwords.
176 * A serializing or fence instruction is required here. A locked bus
177 * cycle on data for which we already own cache mastership is the most
184 __asm __volatile("lfence" : : : "memory");
186 __asm __volatile("" : : : "memory");
191 * cpu_sfence() ensures strong write ordering for writes issued prior
192 * to the instruction verses writes issued afterwords. Writes are
193 * ordered on intel cpus so we do not actually have to do anything.
199 __asm __volatile("sfence" : : : "memory");
201 __asm __volatile("" : : : "memory");
206 * cpu_ccfence() prevents the compiler from reordering instructions, in
207 * particular stores, relative to the current cpu. Use cpu_sfence() if
208 * you need to guarentee ordering by both the compiler and by the cpu.
210 * This also prevents the compiler from caching memory loads into local
211 * variables across the routine.
216 __asm __volatile("" : : : "memory");
221 #define HAVE_INLINE_FFS
228 * Note that gcc-2's builtin ffs would be used if we didn't declare
229 * this inline or turn off the builtin. The builtin is faster but
230 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
233 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
235 /* Actually, the above is way out of date. The builtins use cmov etc */
236 return (__builtin_ffs(mask));
240 #define HAVE_INLINE_FFSL
245 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
248 #define HAVE_INLINE_FLS
253 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
256 #define HAVE_INLINE_FLSL
261 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
269 __asm __volatile("hlt");
273 * The following complications are to get around gcc not having a
274 * constraint letter for the range 0..255. We still put "d" in the
275 * constraint because "i" isn't a valid constraint when the port
276 * isn't constant. This only matters for -O0 because otherwise
277 * the non-working version gets optimized away.
279 * Use an expression-statement instead of a conditional expression
280 * because gcc-2.6.0 would promote the operands of the conditional
281 * and produce poor code for "if ((inb(var) & const1) == const2)".
283 * The unnecessary test `(port) < 0x10000' is to generate a warning if
284 * the `port' has type u_short or smaller. Such types are pessimal.
285 * This actually only works for signed types. The range check is
286 * careful to avoid generating warnings.
288 #define inb(port) __extension__ ({ \
290 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
291 && (port) < 0x10000) \
292 _data = inbc(port); \
294 _data = inbv(port); \
297 #define outb(port, data) ( \
298 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
299 && (port) < 0x10000 \
300 ? outbc(port, data) : outbv(port, data))
302 static __inline u_char
307 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
312 outbc(u_int port, u_char data)
314 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
317 static __inline u_char
322 * We use %%dx and not %1 here because i/o is done at %dx and not at
323 * %edx, while gcc generates inferior code (movw instead of movl)
324 * if we tell it to load (u_short) port.
326 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
330 static __inline u_int
335 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
340 insb(u_int port, void *addr, size_t cnt)
342 __asm __volatile("cld; rep; insb"
343 : "+D" (addr), "+c" (cnt)
349 insw(u_int port, void *addr, size_t cnt)
351 __asm __volatile("cld; rep; insw"
352 : "+D" (addr), "+c" (cnt)
358 insl(u_int port, void *addr, size_t cnt)
360 __asm __volatile("cld; rep; insl"
361 : "+D" (addr), "+c" (cnt)
369 __asm __volatile("invd");
375 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
376 * will cause the invl*() functions to be equivalent to the cpu_invl*()
380 void smp_invltlb(void);
382 #define smp_invltlb()
385 #ifndef _CPU_INVLPG_DEFINED
388 * Invalidate a patricular VA on this cpu only
391 cpu_invlpg(void *addr)
393 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
401 __asm __volatile("rep; nop");
406 static __inline u_short
411 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
415 static __inline u_int
416 loadandclear(volatile u_int *addr)
420 __asm __volatile("xorl %0,%0; xchgl %1,%0"
421 : "=&r" (result) : "m" (*addr));
426 outbv(u_int port, u_char data)
430 * Use an unnecessary assignment to help gcc's register allocator.
431 * This make a large difference for gcc-1.40 and a tiny difference
432 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
433 * best results. gcc-2.6.0 can't handle this.
436 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
440 outl(u_int port, u_int data)
443 * outl() and outw() aren't used much so we haven't looked at
444 * possible micro-optimizations such as the unnecessary
445 * assignment for them.
447 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
451 outsb(u_int port, const void *addr, size_t cnt)
453 __asm __volatile("cld; rep; outsb"
454 : "+S" (addr), "+c" (cnt)
459 outsw(u_int port, const void *addr, size_t cnt)
461 __asm __volatile("cld; rep; outsw"
462 : "+S" (addr), "+c" (cnt)
467 outsl(u_int port, const void *addr, size_t cnt)
469 __asm __volatile("cld; rep; outsl"
470 : "+S" (addr), "+c" (cnt)
475 outw(u_int port, u_short data)
477 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
483 __asm __volatile("pause");
486 static __inline u_long
491 __asm __volatile("pushfq; popq %0" : "=r" (rf));
495 static __inline u_int64_t
500 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
501 return (low | ((u_int64_t)high << 32));
504 static __inline u_int64_t
509 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
510 return (low | ((u_int64_t)high << 32));
513 #define _RDTSC_SUPPORTED_
515 static __inline u_int64_t
520 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
521 return (low | ((u_int64_t)high << 32));
527 __asm __volatile("wbinvd");
531 write_rflags(u_long rf)
533 __asm __volatile("pushq %0; popfq" : : "r" (rf));
537 wrmsr(u_int msr, u_int64_t newval)
543 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
547 load_cr0(u_long data)
550 __asm __volatile("movq %0,%%cr0" : : "r" (data));
553 static __inline u_long
558 __asm __volatile("movq %%cr0,%0" : "=r" (data));
562 static __inline u_long
567 __asm __volatile("movq %%cr2,%0" : "=r" (data));
572 load_cr3(u_long data)
575 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
578 static __inline u_long
583 __asm __volatile("movq %%cr3,%0" : "=r" (data));
588 load_cr4(u_long data)
590 __asm __volatile("movq %0,%%cr4" : : "r" (data));
593 static __inline u_long
598 __asm __volatile("movq %%cr4,%0" : "=r" (data));
602 #ifndef _CPU_INVLTLB_DEFINED
605 * Invalidate the TLB on this cpu only
611 #if defined(SWTCH_OPTIM_STATS)
619 * TLB flush for an individual page (even if it has PG_G).
620 * Only works on 486+ CPUs (i386 does not have PG_G).
626 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
629 static __inline u_int
633 __asm __volatile("movl %%fs,%0" : "=rm" (sel));
637 static __inline u_int
641 __asm __volatile("movl %%gs,%0" : "=rm" (sel));
648 __asm __volatile("movl %0,%%ds" : : "rm" (sel));
654 __asm __volatile("movl %0,%%es" : : "rm" (sel));
658 /* This is defined in <machine/specialreg.h> but is too painful to get to */
660 #define MSR_FSBASE 0xc0000100
665 /* Preserve the fsbase value across the selector load */
666 __asm __volatile("rdmsr; movl %0,%%fs; wrmsr"
667 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
671 #define MSR_GSBASE 0xc0000101
677 * Preserve the gsbase value across the selector load.
678 * Note that we have to disable interrupts because the gsbase
679 * being trashed happens to be the kernel gsbase at the time.
681 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
682 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
685 /* Usable by userland */
689 __asm __volatile("movl %0,%%fs" : : "rm" (sel));
695 __asm __volatile("movl %0,%%gs" : : "rm" (sel));
699 /* void lidt(struct region_descriptor *addr); */
701 lidt(struct region_descriptor *addr)
703 __asm __volatile("lidt (%0)" : : "r" (addr));
706 /* void lldt(u_short sel); */
710 __asm __volatile("lldt %0" : : "r" (sel));
713 /* void ltr(u_short sel); */
717 __asm __volatile("ltr %0" : : "r" (sel));
720 static __inline u_int64_t
724 __asm __volatile("movq %%dr0,%0" : "=r" (data));
729 load_dr0(u_int64_t dr0)
731 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
734 static __inline u_int64_t
738 __asm __volatile("movq %%dr1,%0" : "=r" (data));
743 load_dr1(u_int64_t dr1)
745 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
748 static __inline u_int64_t
752 __asm __volatile("movq %%dr2,%0" : "=r" (data));
757 load_dr2(u_int64_t dr2)
759 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
762 static __inline u_int64_t
766 __asm __volatile("movq %%dr3,%0" : "=r" (data));
771 load_dr3(u_int64_t dr3)
773 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
776 static __inline u_int64_t
780 __asm __volatile("movq %%dr4,%0" : "=r" (data));
785 load_dr4(u_int64_t dr4)
787 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
790 static __inline u_int64_t
794 __asm __volatile("movq %%dr5,%0" : "=r" (data));
799 load_dr5(u_int64_t dr5)
801 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
804 static __inline u_int64_t
808 __asm __volatile("movq %%dr6,%0" : "=r" (data));
813 load_dr6(u_int64_t dr6)
815 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
818 static __inline u_int64_t
822 __asm __volatile("movq %%dr7,%0" : "=r" (data));
827 load_dr7(u_int64_t dr7)
829 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
832 static __inline register_t
837 rflags = read_rflags();
843 intr_restore(register_t rflags)
845 write_rflags(rflags);
848 #else /* !__GNUC__ */
850 int breakpoint(void);
851 void cpu_pause(void);
852 u_int bsfl(u_int mask);
853 u_int bsrl(u_int mask);
854 void cpu_disable_intr(void);
855 void cpu_enable_intr(void);
856 void cpu_invlpg(u_long addr);
857 void cpu_invlpg_range(u_long start, u_long end);
858 void do_cpuid(u_int ax, u_int *p);
860 u_char inb(u_int port);
861 u_int inl(u_int port);
862 void insb(u_int port, void *addr, size_t cnt);
863 void insl(u_int port, void *addr, size_t cnt);
864 void insw(u_int port, void *addr, size_t cnt);
866 void invlpg(u_int addr);
867 void invlpg_range(u_int start, u_int end);
868 void cpu_invltlb(void);
869 u_short inw(u_int port);
870 void load_cr0(u_int cr0);
871 void load_cr3(u_int cr3);
872 void load_cr4(u_int cr4);
873 void load_fs(u_int sel);
874 void load_gs(u_int sel);
875 struct region_descriptor;
876 void lidt(struct region_descriptor *addr);
877 void lldt(u_short sel);
878 void ltr(u_short sel);
879 void outb(u_int port, u_char data);
880 void outl(u_int port, u_int data);
881 void outsb(u_int port, void *addr, size_t cnt);
882 void outsl(u_int port, void *addr, size_t cnt);
883 void outsw(u_int port, void *addr, size_t cnt);
884 void outw(u_int port, u_short data);
885 void ia32_pause(void);
892 u_int64_t rdmsr(u_int msr);
893 u_int64_t rdpmc(u_int pmc);
894 u_int64_t rdtsc(void);
895 u_int read_rflags(void);
897 void write_rflags(u_int rf);
898 void wrmsr(u_int msr, u_int64_t newval);
899 u_int64_t rdr0(void);
900 void load_dr0(u_int64_t dr0);
901 u_int64_t rdr1(void);
902 void load_dr1(u_int64_t dr1);
903 u_int64_t rdr2(void);
904 void load_dr2(u_int64_t dr2);
905 u_int64_t rdr3(void);
906 void load_dr3(u_int64_t dr3);
907 u_int64_t rdr4(void);
908 void load_dr4(u_int64_t dr4);
909 u_int64_t rdr5(void);
910 void load_dr5(u_int64_t dr5);
911 u_int64_t rdr6(void);
912 void load_dr6(u_int64_t dr6);
913 u_int64_t rdr7(void);
914 void load_dr7(u_int64_t dr7);
915 register_t intr_disable(void);
916 void intr_restore(register_t rf);
918 #endif /* __GNUC__ */
920 void reset_dbregs(void);
924 #endif /* !_CPU_CPUFUNC_H_ */