2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
166 vm_size_t mp_cth_mapsz;
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int need_hyperthreading_fixup;
222 static u_int logical_cpus;
223 u_int logical_cpus_mask;
225 static int madt_probe_test;
226 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
228 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
229 int current_postcode;
231 /** XXX FIXME: what system files declare these??? */
232 extern struct region_descriptor r_gdt, r_idt;
234 int bsp_apic_ready = 0; /* flags useability of BSP apic */
235 int mp_naps; /* # of Applications processors */
236 int mp_nbusses; /* # of busses */
238 int mp_napics; /* # of IO APICs */
240 vm_offset_t cpu_apic_address;
242 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
243 u_int32_t *io_apic_versions;
247 u_int32_t cpu_apic_versions[MAXCPU];
249 extern int64_t tsc_offsets[];
251 extern u_long ebda_addr;
254 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
258 * APIC ID logical/physical mapping structures.
259 * We oversize these to simplify boot-time config.
261 int cpu_num_to_apic_id[NAPICID];
263 int io_num_to_apic_id[NAPICID];
265 int apic_id_to_logical[NAPICID];
267 /* AP uses this during bootstrap. Do not staticize. */
272 * SMP page table page. Setup by locore to point to a page table
273 * page from which we allocate per-cpu privatespace areas io_apics,
277 #define IO_MAPPING_START_INDEX \
278 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
280 extern pt_entry_t *SMPpt;
282 struct pcb stoppcbs[MAXCPU];
284 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
287 * Local data and functions.
290 static u_int boot_address;
291 static u_int base_memory;
292 static int mp_finish;
294 static void mp_enable(u_int boot_addr);
296 static int mptable_probe(void);
297 static long mptable_search_sig(u_int32_t target, int count);
298 static void mptable_hyperthread_fixup(u_int id_mask);
299 static void mptable_pass1(struct mptable_pos *);
300 static int mptable_pass2(struct mptable_pos *);
301 static void mptable_default(int type);
302 static void mptable_fix(void);
303 static void mptable_map(struct mptable_pos *, vm_paddr_t);
304 static void mptable_unmap(struct mptable_pos *);
307 static void setup_apic_irq_mapping(void);
308 static int apic_int_is_bus_type(int intr, int bus_type);
310 static int start_all_aps(u_int boot_addr);
312 static void install_ap_tramp(u_int boot_addr);
314 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
315 static int smitest(void);
317 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
318 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
319 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
320 static u_int bootMP_size;
323 * Calculate usable address in base memory for AP trampoline code.
326 mp_bootaddress(u_int basemem)
328 POSTCODE(MP_BOOTADDRESS_POST);
330 base_memory = basemem;
332 bootMP_size = mptramp_end - mptramp_start;
333 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
334 if (((basemem * 1024) - boot_address) < bootMP_size)
335 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
336 /* 3 levels of page table pages */
337 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
339 return mptramp_pagetables;
344 * Look for an Intel MP spec table (ie, SMP capable hardware).
353 * Make sure our SMPpt[] page table is big enough to hold all the
356 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
358 POSTCODE(MP_PROBE_POST);
360 /* see if EBDA exists */
361 if (ebda_addr != 0) {
362 /* search first 1K of EBDA */
363 target = (u_int32_t)ebda_addr;
364 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
367 /* last 1K of base memory, effective 'top of base' passed in */
368 target = (u_int32_t)(base_memory - 0x400);
369 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
373 /* search the BIOS */
374 target = (u_int32_t)BIOS_BASE;
375 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
384 * Startup the SMP processors.
389 POSTCODE(MP_START_POST);
390 mp_enable(boot_address);
395 * Print various information about the SMP system hardware and setup.
402 POSTCODE(MP_ANNOUNCE_POST);
404 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
405 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
406 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
407 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
408 for (x = 1; x <= mp_naps; ++x) {
409 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
410 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
411 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
415 for (x = 0; x < mp_napics; ++x) {
416 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
417 kprintf(", version: 0x%08x", io_apic_versions[x]);
418 kprintf(", at 0x%08lx\n", io_apic_address[x]);
421 kprintf(" Warning: APIC I/O disabled\n");
426 * AP cpu's call this to sync up protected mode.
428 * WARNING! %gs is not set up on entry. This routine sets up %gs.
434 int x, myid = bootAP;
436 struct mdglobaldata *md;
437 struct privatespace *ps;
439 ps = &CPU_prvspace[myid];
441 gdt_segs[GPROC0_SEL].ssd_base =
442 (long) &ps->mdglobaldata.gd_common_tss;
443 ps->mdglobaldata.mi.gd_prvspace = ps;
445 /* We fill the 32-bit segment descriptors */
446 for (x = 0; x < NGDT; x++) {
447 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
448 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
450 /* And now a 64-bit one */
451 ssdtosyssd(&gdt_segs[GPROC0_SEL],
452 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
454 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
455 r_gdt.rd_base = (long) &gdt[myid * NGDT];
456 lgdt(&r_gdt); /* does magic intra-segment return */
458 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
459 wrmsr(MSR_FSBASE, 0); /* User value */
460 wrmsr(MSR_GSBASE, (u_int64_t)ps);
461 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
467 mdcpu->gd_currentldt = _default_ldt;
470 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
471 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
473 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
475 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
477 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
479 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
480 md->gd_common_tssd = *md->gd_tss_gdt;
482 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
487 * Set to a known state:
488 * Set by mpboot.s: CR0_PG, CR0_PE
489 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
492 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
495 /* Set up the fast syscall stuff */
496 msr = rdmsr(MSR_EFER) | EFER_SCE;
497 wrmsr(MSR_EFER, msr);
498 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
499 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
500 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
501 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
502 wrmsr(MSR_STAR, msr);
503 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
505 pmap_set_opt(); /* PSE/4MB pages, etc */
507 /* Initialize the PAT MSR. */
511 /* set up CPU registers and state */
514 /* set up SSE/NX registers */
517 /* set up FPU state on the AP */
518 npxinit(__INITIAL_NPXCW__);
520 /* disable the APIC, just to be SURE */
521 lapic->svr &= ~APIC_SVR_ENABLE;
523 /* data returned to BSP */
524 cpu_apic_versions[0] = lapic->version;
527 /*******************************************************************
528 * local functions and data
532 * start the SMP system
535 mp_enable(u_int boot_addr)
542 vm_paddr_t mpfps_paddr;
544 POSTCODE(MP_ENABLE_POST);
549 mpfps_paddr = mptable_probe();
552 struct mptable_pos mpt;
554 mptable_map(&mpt, mpfps_paddr);
557 * We can safely map physical memory into SMPpt after
558 * mptable_pass1() completes.
562 if (cpu_apic_address == 0)
563 panic("mp_enable: no local apic!\n");
565 /* examine the MP table for needed info */
566 x = mptable_pass2(&mpt);
571 * can't process default configs till the
572 * CPU APIC is pmapped
577 /* post scan cleanup */
581 * lapic not mapped yet (pmap_init is called too late)
583 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
584 sizeof(struct LAPIC));
586 vm_paddr_t madt_paddr;
589 madt_paddr = madt_probe();
591 panic("mp_enable: madt_probe failed\n");
593 cpu_apic_address = madt_pass1(madt_paddr);
594 if (cpu_apic_address == 0)
595 panic("mp_enable: no local apic (madt)!\n");
598 * lapic not mapped yet (pmap_init is called too late)
600 * XXX: where is the best place to set lapic?
602 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
603 sizeof(struct LAPIC));
605 bsp_apic_id = (lapic->id & 0xff000000) >> 24;
606 if (madt_pass2(madt_paddr, bsp_apic_id))
607 panic("mp_enable: madt_pass2 failed\n");
612 setup_apic_irq_mapping();
614 /* fill the LOGICAL io_apic_versions table */
615 for (apic = 0; apic < mp_napics; ++apic) {
616 ux = io_apic_read(apic, IOAPIC_VER);
617 io_apic_versions[apic] = ux;
618 io_apic_set_id(apic, IO_TO_ID(apic));
621 /* program each IO APIC in the system */
622 for (apic = 0; apic < mp_napics; ++apic)
623 if (io_apic_setup(apic) < 0)
624 panic("IO APIC setup failure");
629 * These are required for SMP operation
632 /* install a 'Spurious INTerrupt' vector */
633 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
634 SDT_SYSIGT, SEL_KPL, 0);
636 /* install an inter-CPU IPI for TLB invalidation */
637 setidt(XINVLTLB_OFFSET, Xinvltlb,
638 SDT_SYSIGT, SEL_KPL, 0);
640 /* install an inter-CPU IPI for IPIQ messaging */
641 setidt(XIPIQ_OFFSET, Xipiq,
642 SDT_SYSIGT, SEL_KPL, 0);
644 /* install a timer vector */
645 setidt(XTIMER_OFFSET, Xtimer,
646 SDT_SYSIGT, SEL_KPL, 0);
648 /* install an inter-CPU IPI for CPU stop/restart */
649 setidt(XCPUSTOP_OFFSET, Xcpustop,
650 SDT_SYSIGT, SEL_KPL, 0);
652 /* start each Application Processor */
653 start_all_aps(boot_addr);
658 * look for the MP spec signature
661 /* string defined by the Intel MP Spec as identifying the MP table */
662 #define MP_SIG 0x5f504d5f /* _MP_ */
663 #define NEXT(X) ((X) += 4)
665 mptable_search_sig(u_int32_t target, int count)
671 KKASSERT(target != 0);
673 map_size = count * sizeof(u_int32_t);
674 addr = pmap_mapdev((vm_paddr_t)target, map_size);
677 for (x = 0; x < count; NEXT(x)) {
678 if (addr[x] == MP_SIG) {
679 /* make array index a byte index */
680 ret = target + (x * sizeof(u_int32_t));
685 pmap_unmapdev((vm_offset_t)addr, map_size);
690 static basetable_entry basetable_entry_types[] =
692 {0, 20, "Processor"},
699 typedef struct BUSDATA {
701 enum busTypes bus_type;
704 typedef struct INTDATA {
714 typedef struct BUSTYPENAME {
719 static bus_type_name bus_type_table[] =
725 {UNKNOWN_BUSTYPE, "---"},
728 {UNKNOWN_BUSTYPE, "---"},
729 {UNKNOWN_BUSTYPE, "---"},
730 {UNKNOWN_BUSTYPE, "---"},
731 {UNKNOWN_BUSTYPE, "---"},
732 {UNKNOWN_BUSTYPE, "---"},
734 {UNKNOWN_BUSTYPE, "---"},
735 {UNKNOWN_BUSTYPE, "---"},
736 {UNKNOWN_BUSTYPE, "---"},
737 {UNKNOWN_BUSTYPE, "---"},
739 {UNKNOWN_BUSTYPE, "---"}
741 /* from MP spec v1.4, table 5-1 */
742 static int default_data[7][5] =
744 /* nbus, id0, type0, id1, type1 */
745 {1, 0, ISA, 255, 255},
746 {1, 0, EISA, 255, 255},
747 {1, 0, EISA, 255, 255},
748 {1, 0, MCA, 255, 255},
750 {2, 0, EISA, 1, PCI},
756 static bus_datum *bus_data;
759 /* the IO INT data, one entry per possible APIC INTerrupt */
760 static io_int *io_apic_ints;
764 static int processor_entry (proc_entry_ptr entry, int cpu);
765 static int bus_entry (bus_entry_ptr entry, int bus);
767 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
768 static int int_entry (int_entry_ptr entry, int intr);
770 static int lookup_bus_type (char *name);
774 * 1st pass on motherboard's Intel MP specification table.
777 * cpu_apic_address (common to all CPUs)
783 * need_hyperthreading_fixup
787 mptable_pass1(struct mptable_pos *mpt)
800 POSTCODE(MPTABLE_PASS1_POST);
803 KKASSERT(fps != NULL);
806 /* clear various tables */
807 for (x = 0; x < NAPICID; ++x) {
808 io_apic_address[x] = ~0; /* IO APIC address table */
812 /* init everything to empty */
821 /* check for use of 'default' configuration */
822 if (fps->mpfb1 != 0) {
823 /* use default addresses */
824 cpu_apic_address = DEFAULT_APIC_BASE;
826 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
829 /* fill in with defaults */
830 mp_naps = 2; /* includes BSP */
831 mp_nbusses = default_data[fps->mpfb1 - 1][0];
840 panic("MP Configuration Table Header MISSING!");
842 cpu_apic_address = (vm_offset_t) cth->apic_address;
844 /* walk the table, recording info of interest */
845 totalSize = cth->base_table_length - sizeof(struct MPCTH);
846 position = (u_char *) cth + sizeof(struct MPCTH);
847 count = cth->entry_count;
850 switch (type = *(u_char *) position) {
851 case 0: /* processor_entry */
852 if (((proc_entry_ptr)position)->cpu_flags
853 & PROCENTRY_FLAG_EN) {
856 ((proc_entry_ptr)position)->apic_id;
859 case 1: /* bus_entry */
862 case 2: /* io_apic_entry */
864 if (((io_apic_entry_ptr)position)->apic_flags
865 & IOAPICENTRY_FLAG_EN)
866 io_apic_address[mp_napics++] =
867 (vm_offset_t)((io_apic_entry_ptr)
868 position)->apic_address;
871 case 3: /* int_entry */
876 case 4: /* int_entry */
879 panic("mpfps Base Table HOSED!");
883 totalSize -= basetable_entry_types[type].length;
884 position = (uint8_t *)position +
885 basetable_entry_types[type].length;
889 /* qualify the numbers */
890 if (mp_naps > MAXCPU) {
891 kprintf("Warning: only using %d of %d available CPUs!\n",
896 /* See if we need to fixup HT logical CPUs. */
897 mptable_hyperthread_fixup(id_mask);
899 --mp_naps; /* subtract the BSP */
904 * 2nd pass on motherboard's Intel MP specification table.
908 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
909 * CPU_TO_ID(N), logical CPU to APIC ID table
910 * IO_TO_ID(N), logical IO to APIC ID table
915 mptable_pass2(struct mptable_pos *mpt)
917 struct PROCENTRY proc;
925 int apic, bus, cpu, intr;
928 POSTCODE(MPTABLE_PASS2_POST);
931 KKASSERT(fps != NULL);
933 /* Initialize fake proc entry for use with HT fixup. */
934 bzero(&proc, sizeof(proc));
936 proc.cpu_flags = PROCENTRY_FLAG_EN;
939 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
941 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
942 M_DEVBUF, M_WAITOK | M_ZERO);
943 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
946 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
950 for (i = 0; i < mp_napics; i++) {
951 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
955 /* clear various tables */
956 for (x = 0; x < NAPICID; ++x) {
957 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
959 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
960 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
964 /* clear bus data table */
965 for (x = 0; x < mp_nbusses; ++x)
966 bus_data[x].bus_id = 0xff;
969 /* clear IO APIC INT table */
970 for (x = 0; x < (nintrs + 1); ++x) {
971 io_apic_ints[x].int_type = 0xff;
972 io_apic_ints[x].int_vector = 0xff;
976 /* record whether PIC or virtual-wire mode */
977 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
979 /* check for use of 'default' configuration */
981 return fps->mpfb1; /* return default configuration type */
985 panic("MP Configuration Table Header MISSING!");
987 /* walk the table, recording info of interest */
988 totalSize = cth->base_table_length - sizeof(struct MPCTH);
989 position = (u_char *) cth + sizeof(struct MPCTH);
990 count = cth->entry_count;
991 apic = bus = intr = 0;
992 cpu = 1; /* pre-count the BSP */
995 switch (type = *(u_char *) position) {
997 if (processor_entry(position, cpu))
1000 if (need_hyperthreading_fixup) {
1002 * Create fake mptable processor entries
1003 * and feed them to processor_entry() to
1004 * enumerate the logical CPUs.
1006 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
1007 for (i = 1; i < logical_cpus; i++) {
1009 processor_entry(&proc, cpu);
1010 logical_cpus_mask |= (1 << cpu);
1016 if (bus_entry(position, bus))
1021 if (io_apic_entry(position, apic))
1027 if (int_entry(position, intr))
1032 /* int_entry(position); */
1035 panic("mpfps Base Table HOSED!");
1039 totalSize -= basetable_entry_types[type].length;
1040 position = (uint8_t *)position + basetable_entry_types[type].length;
1043 if (CPU_TO_ID(0) < 0)
1044 panic("NO BSP found!");
1046 /* report fact that its NOT a default configuration */
1052 * Check if we should perform a hyperthreading "fix-up" to
1053 * enumerate any logical CPU's that aren't already listed
1056 * XXX: We assume that all of the physical CPUs in the
1057 * system have the same number of logical CPUs.
1059 * XXX: We assume that APIC ID's are allocated such that
1060 * the APIC ID's for a physical processor are aligned
1061 * with the number of logical CPU's in the processor.
1064 mptable_hyperthread_fixup(u_int id_mask)
1068 /* Nothing to do if there is no HTT support. */
1069 if ((cpu_feature & CPUID_HTT) == 0)
1071 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1072 if (logical_cpus <= 1)
1076 * For each APIC ID of a CPU that is set in the mask,
1077 * scan the other candidate APIC ID's for this
1078 * physical processor. If any of those ID's are
1079 * already in the table, then kill the fixup.
1081 for (id = 0; id <= MAXCPU; id++) {
1082 if ((id_mask & 1 << id) == 0)
1084 /* First, make sure we are on a logical_cpus boundary. */
1085 if (id % logical_cpus != 0)
1087 for (i = id + 1; i < id + logical_cpus; i++)
1088 if ((id_mask & 1 << i) != 0)
1093 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1094 * mp_naps right now.
1096 need_hyperthreading_fixup = 1;
1097 mp_naps *= logical_cpus;
1101 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1105 vm_size_t cth_mapsz = 0;
1107 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1108 if (fps->pap != 0) {
1110 * Map configuration table header to get
1111 * the base table size
1113 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1114 cth_mapsz = cth->base_table_length;
1115 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1118 * Map the base table
1120 cth = pmap_mapdev(fps->pap, cth_mapsz);
1125 mpt->mp_cth_mapsz = cth_mapsz;
1129 mptable_unmap(struct mptable_pos *mpt)
1131 if (mpt->mp_cth != NULL) {
1132 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1134 mpt->mp_cth_mapsz = 0;
1136 if (mpt->mp_fps != NULL) {
1137 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1145 assign_apic_irq(int apic, int intpin, int irq)
1149 if (int_to_apicintpin[irq].ioapic != -1)
1150 panic("assign_apic_irq: inconsistent table");
1152 int_to_apicintpin[irq].ioapic = apic;
1153 int_to_apicintpin[irq].int_pin = intpin;
1154 int_to_apicintpin[irq].apic_address = ioapic[apic];
1155 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1157 for (x = 0; x < nintrs; x++) {
1158 if ((io_apic_ints[x].int_type == 0 ||
1159 io_apic_ints[x].int_type == 3) &&
1160 io_apic_ints[x].int_vector == 0xff &&
1161 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1162 io_apic_ints[x].dst_apic_int == intpin)
1163 io_apic_ints[x].int_vector = irq;
1168 revoke_apic_irq(int irq)
1174 if (int_to_apicintpin[irq].ioapic == -1)
1175 panic("revoke_apic_irq: inconsistent table");
1177 oldapic = int_to_apicintpin[irq].ioapic;
1178 oldintpin = int_to_apicintpin[irq].int_pin;
1180 int_to_apicintpin[irq].ioapic = -1;
1181 int_to_apicintpin[irq].int_pin = 0;
1182 int_to_apicintpin[irq].apic_address = NULL;
1183 int_to_apicintpin[irq].redirindex = 0;
1185 for (x = 0; x < nintrs; x++) {
1186 if ((io_apic_ints[x].int_type == 0 ||
1187 io_apic_ints[x].int_type == 3) &&
1188 io_apic_ints[x].int_vector != 0xff &&
1189 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1190 io_apic_ints[x].dst_apic_int == oldintpin)
1191 io_apic_ints[x].int_vector = 0xff;
1199 allocate_apic_irq(int intr)
1205 if (io_apic_ints[intr].int_vector != 0xff)
1206 return; /* Interrupt handler already assigned */
1208 if (io_apic_ints[intr].int_type != 0 &&
1209 (io_apic_ints[intr].int_type != 3 ||
1210 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1211 io_apic_ints[intr].dst_apic_int == 0)))
1212 return; /* Not INT or ExtInt on != (0, 0) */
1215 while (irq < APIC_INTMAPSIZE &&
1216 int_to_apicintpin[irq].ioapic != -1)
1219 if (irq >= APIC_INTMAPSIZE)
1220 return; /* No free interrupt handlers */
1222 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1223 intpin = io_apic_ints[intr].dst_apic_int;
1225 assign_apic_irq(apic, intpin, irq);
1230 swap_apic_id(int apic, int oldid, int newid)
1237 return; /* Nothing to do */
1239 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1240 apic, oldid, newid);
1242 /* Swap physical APIC IDs in interrupt entries */
1243 for (x = 0; x < nintrs; x++) {
1244 if (io_apic_ints[x].dst_apic_id == oldid)
1245 io_apic_ints[x].dst_apic_id = newid;
1246 else if (io_apic_ints[x].dst_apic_id == newid)
1247 io_apic_ints[x].dst_apic_id = oldid;
1250 /* Swap physical APIC IDs in IO_TO_ID mappings */
1251 for (oapic = 0; oapic < mp_napics; oapic++)
1252 if (IO_TO_ID(oapic) == newid)
1255 if (oapic < mp_napics) {
1256 kprintf("Changing APIC ID for IO APIC #%d from "
1257 "%d to %d in MP table\n",
1258 oapic, newid, oldid);
1259 IO_TO_ID(oapic) = oldid;
1261 IO_TO_ID(apic) = newid;
1266 fix_id_to_io_mapping(void)
1270 for (x = 0; x < NAPICID; x++)
1273 for (x = 0; x <= mp_naps; x++)
1274 if (CPU_TO_ID(x) < NAPICID)
1275 ID_TO_IO(CPU_TO_ID(x)) = x;
1277 for (x = 0; x < mp_napics; x++)
1278 if (IO_TO_ID(x) < NAPICID)
1279 ID_TO_IO(IO_TO_ID(x)) = x;
1284 first_free_apic_id(void)
1288 for (freeid = 0; freeid < NAPICID; freeid++) {
1289 for (x = 0; x <= mp_naps; x++)
1290 if (CPU_TO_ID(x) == freeid)
1294 for (x = 0; x < mp_napics; x++)
1295 if (IO_TO_ID(x) == freeid)
1306 io_apic_id_acceptable(int apic, int id)
1308 int cpu; /* Logical CPU number */
1309 int oapic; /* Logical IO APIC number for other IO APIC */
1312 return 0; /* Out of range */
1314 for (cpu = 0; cpu <= mp_naps; cpu++)
1315 if (CPU_TO_ID(cpu) == id)
1316 return 0; /* Conflict with CPU */
1318 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1319 if (IO_TO_ID(oapic) == id)
1320 return 0; /* Conflict with other APIC */
1322 return 1; /* ID is acceptable for IO APIC */
1327 io_apic_find_int_entry(int apic, int pin)
1331 /* search each of the possible INTerrupt sources */
1332 for (x = 0; x < nintrs; ++x) {
1333 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1334 (pin == io_apic_ints[x].dst_apic_int))
1335 return (&io_apic_ints[x]);
1343 * parse an Intel MP specification table
1351 int apic; /* IO APIC unit number */
1352 int freeid; /* Free physical APIC ID */
1353 int physid; /* Current physical IO APIC ID */
1356 int bus_0 = 0; /* Stop GCC warning */
1357 int bus_pci = 0; /* Stop GCC warning */
1361 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1362 * did it wrong. The MP spec says that when more than 1 PCI bus
1363 * exists the BIOS must begin with bus entries for the PCI bus and use
1364 * actual PCI bus numbering. This implies that when only 1 PCI bus
1365 * exists the BIOS can choose to ignore this ordering, and indeed many
1366 * MP motherboards do ignore it. This causes a problem when the PCI
1367 * sub-system makes requests of the MP sub-system based on PCI bus
1368 * numbers. So here we look for the situation and renumber the
1369 * busses and associated INTs in an effort to "make it right".
1372 /* find bus 0, PCI bus, count the number of PCI busses */
1373 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1374 if (bus_data[x].bus_id == 0) {
1377 if (bus_data[x].bus_type == PCI) {
1383 * bus_0 == slot of bus with ID of 0
1384 * bus_pci == slot of last PCI bus encountered
1387 /* check the 1 PCI bus case for sanity */
1388 /* if it is number 0 all is well */
1389 if (num_pci_bus == 1 &&
1390 bus_data[bus_pci].bus_id != 0) {
1392 /* mis-numbered, swap with whichever bus uses slot 0 */
1394 /* swap the bus entry types */
1395 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1396 bus_data[bus_0].bus_type = PCI;
1399 /* swap each relavant INTerrupt entry */
1400 id = bus_data[bus_pci].bus_id;
1401 for (x = 0; x < nintrs; ++x) {
1402 if (io_apic_ints[x].src_bus_id == id) {
1403 io_apic_ints[x].src_bus_id = 0;
1405 else if (io_apic_ints[x].src_bus_id == 0) {
1406 io_apic_ints[x].src_bus_id = id;
1413 /* Assign IO APIC IDs.
1415 * First try the existing ID. If a conflict is detected, try
1416 * the ID in the MP table. If a conflict is still detected, find
1419 * We cannot use the ID_TO_IO table before all conflicts has been
1420 * resolved and the table has been corrected.
1422 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1424 /* First try to use the value set by the BIOS */
1425 physid = io_apic_get_id(apic);
1426 if (io_apic_id_acceptable(apic, physid)) {
1427 if (IO_TO_ID(apic) != physid)
1428 swap_apic_id(apic, IO_TO_ID(apic), physid);
1432 /* Then check if the value in the MP table is acceptable */
1433 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1436 /* Last resort, find a free APIC ID and use it */
1437 freeid = first_free_apic_id();
1438 if (freeid >= NAPICID)
1439 panic("No free physical APIC IDs found");
1441 if (io_apic_id_acceptable(apic, freeid)) {
1442 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1445 panic("Free physical APIC ID not usable");
1447 fix_id_to_io_mapping();
1451 /* detect and fix broken Compaq MP table */
1452 if (apic_int_type(0, 0) == -1) {
1453 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1454 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1455 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1456 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1457 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1458 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1460 } else if (apic_int_type(0, 0) == 0) {
1461 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1462 for (x = 0; x < nintrs; ++x)
1463 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1464 (0 == io_apic_ints[x].dst_apic_int)) {
1465 io_apic_ints[x].int_type = 3;
1466 io_apic_ints[x].int_vector = 0xff;
1472 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1473 * controllers universally come in pairs. If IRQ 14 is specified
1474 * as an ISA interrupt, then IRQ 15 had better be too.
1476 * [ Shuttle XPC / AMD Athlon X2 ]
1477 * The MPTable is missing an entry for IRQ 15. Note that the
1478 * ACPI table has an entry for both 14 and 15.
1480 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1481 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1482 io14 = io_apic_find_int_entry(0, 14);
1483 io_apic_ints[nintrs] = *io14;
1484 io_apic_ints[nintrs].src_bus_irq = 15;
1485 io_apic_ints[nintrs].dst_apic_int = 15;
1493 /* Assign low level interrupt handlers */
1495 setup_apic_irq_mapping(void)
1501 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1502 int_to_apicintpin[x].ioapic = -1;
1503 int_to_apicintpin[x].int_pin = 0;
1504 int_to_apicintpin[x].apic_address = NULL;
1505 int_to_apicintpin[x].redirindex = 0;
1508 /* First assign ISA/EISA interrupts */
1509 for (x = 0; x < nintrs; x++) {
1510 int_vector = io_apic_ints[x].src_bus_irq;
1511 if (int_vector < APIC_INTMAPSIZE &&
1512 io_apic_ints[x].int_vector == 0xff &&
1513 int_to_apicintpin[int_vector].ioapic == -1 &&
1514 (apic_int_is_bus_type(x, ISA) ||
1515 apic_int_is_bus_type(x, EISA)) &&
1516 io_apic_ints[x].int_type == 0) {
1517 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1518 io_apic_ints[x].dst_apic_int,
1523 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1524 for (x = 0; x < nintrs; x++) {
1525 if (io_apic_ints[x].dst_apic_int == 0 &&
1526 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1527 io_apic_ints[x].int_vector == 0xff &&
1528 int_to_apicintpin[0].ioapic == -1 &&
1529 io_apic_ints[x].int_type == 3) {
1530 assign_apic_irq(0, 0, 0);
1535 /* Assign PCI interrupts */
1536 for (x = 0; x < nintrs; ++x) {
1537 if (io_apic_ints[x].int_type == 0 &&
1538 io_apic_ints[x].int_vector == 0xff &&
1539 apic_int_is_bus_type(x, PCI))
1540 allocate_apic_irq(x);
1547 mp_set_cpuids(int cpu_id, int apic_id)
1549 CPU_TO_ID(cpu_id) = apic_id;
1550 ID_TO_CPU(apic_id) = cpu_id;
1554 processor_entry(proc_entry_ptr entry, int cpu)
1558 /* check for usability */
1559 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1562 if(entry->apic_id >= NAPICID)
1563 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1564 /* check for BSP flag */
1565 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1566 mp_set_cpuids(0, entry->apic_id);
1567 return 0; /* its already been counted */
1570 /* add another AP to list, if less than max number of CPUs */
1571 else if (cpu < MAXCPU) {
1572 mp_set_cpuids(cpu, entry->apic_id);
1581 bus_entry(bus_entry_ptr entry, int bus)
1586 /* encode the name into an index */
1587 for (x = 0; x < 6; ++x) {
1588 if ((c = entry->bus_type[x]) == ' ')
1594 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1595 panic("unknown bus type: '%s'", name);
1597 bus_data[bus].bus_id = entry->bus_id;
1598 bus_data[bus].bus_type = x;
1606 io_apic_entry(io_apic_entry_ptr entry, int apic)
1608 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1611 IO_TO_ID(apic) = entry->apic_id;
1612 if (entry->apic_id < NAPICID)
1613 ID_TO_IO(entry->apic_id) = apic;
1621 lookup_bus_type(char *name)
1625 for (x = 0; x < MAX_BUSTYPE; ++x)
1626 if (strcmp(bus_type_table[x].name, name) == 0)
1627 return bus_type_table[x].type;
1629 return UNKNOWN_BUSTYPE;
1635 int_entry(int_entry_ptr entry, int intr)
1639 io_apic_ints[intr].int_type = entry->int_type;
1640 io_apic_ints[intr].int_flags = entry->int_flags;
1641 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1642 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1643 if (entry->dst_apic_id == 255) {
1644 /* This signal goes to all IO APICS. Select an IO APIC
1645 with sufficient number of interrupt pins */
1646 for (apic = 0; apic < mp_napics; apic++)
1647 if (((io_apic_read(apic, IOAPIC_VER) &
1648 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1649 entry->dst_apic_int)
1651 if (apic < mp_napics)
1652 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1654 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1656 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1657 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1663 apic_int_is_bus_type(int intr, int bus_type)
1667 for (bus = 0; bus < mp_nbusses; ++bus)
1668 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1669 && ((int) bus_data[bus].bus_type == bus_type))
1676 * Given a traditional ISA INT mask, return an APIC mask.
1679 isa_apic_mask(u_int isa_mask)
1684 #if defined(SKIP_IRQ15_REDIRECT)
1685 if (isa_mask == (1 << 15)) {
1686 kprintf("skipping ISA IRQ15 redirect\n");
1689 #endif /* SKIP_IRQ15_REDIRECT */
1691 isa_irq = ffs(isa_mask); /* find its bit position */
1692 if (isa_irq == 0) /* doesn't exist */
1694 --isa_irq; /* make it zero based */
1696 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1700 return (1 << apic_pin); /* convert pin# to a mask */
1704 * Determine which APIC pin an ISA/EISA INT is attached to.
1706 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1707 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1708 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1709 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1711 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1713 isa_apic_irq(int isa_irq)
1717 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1718 if (INTTYPE(intr) == 0) { /* standard INT */
1719 if (SRCBUSIRQ(intr) == isa_irq) {
1720 if (apic_int_is_bus_type(intr, ISA) ||
1721 apic_int_is_bus_type(intr, EISA)) {
1722 if (INTIRQ(intr) == 0xff)
1723 return -1; /* unassigned */
1724 return INTIRQ(intr); /* found */
1729 return -1; /* NOT found */
1734 * Determine which APIC pin a PCI INT is attached to.
1736 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1737 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1738 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1740 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1744 --pciInt; /* zero based */
1746 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1747 if ((INTTYPE(intr) == 0) /* standard INT */
1748 && (SRCBUSID(intr) == pciBus)
1749 && (SRCBUSDEVICE(intr) == pciDevice)
1750 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1751 if (apic_int_is_bus_type(intr, PCI)) {
1752 if (INTIRQ(intr) == 0xff) {
1753 kprintf("IOAPIC: pci_apic_irq() "
1755 return -1; /* unassigned */
1757 return INTIRQ(intr); /* exact match */
1762 return -1; /* NOT found */
1766 next_apic_irq(int irq)
1773 for (intr = 0; intr < nintrs; intr++) {
1774 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1776 bus = SRCBUSID(intr);
1777 bustype = apic_bus_type(bus);
1778 if (bustype != ISA &&
1784 if (intr >= nintrs) {
1787 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1788 if (INTTYPE(ointr) != 0)
1790 if (bus != SRCBUSID(ointr))
1792 if (bustype == PCI) {
1793 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1795 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1798 if (bustype == ISA || bustype == EISA) {
1799 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1802 if (INTPIN(intr) == INTPIN(ointr))
1806 if (ointr >= nintrs) {
1809 return INTIRQ(ointr);
1824 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1827 * Exactly what this means is unclear at this point. It is a solution
1828 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1829 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1830 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1834 undirect_isa_irq(int rirq)
1838 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1839 /** FIXME: tickle the MB redirector chip */
1843 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1850 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1853 undirect_pci_irq(int rirq)
1857 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1859 /** FIXME: tickle the MB redirector chip */
1863 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1871 * given a bus ID, return:
1872 * the bus type if found
1876 apic_bus_type(int id)
1880 for (x = 0; x < mp_nbusses; ++x)
1881 if (bus_data[x].bus_id == id)
1882 return bus_data[x].bus_type;
1890 * given a LOGICAL APIC# and pin#, return:
1891 * the associated src bus ID if found
1895 apic_src_bus_id(int apic, int pin)
1899 /* search each of the possible INTerrupt sources */
1900 for (x = 0; x < nintrs; ++x)
1901 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1902 (pin == io_apic_ints[x].dst_apic_int))
1903 return (io_apic_ints[x].src_bus_id);
1905 return -1; /* NOT found */
1909 * given a LOGICAL APIC# and pin#, return:
1910 * the associated src bus IRQ if found
1914 apic_src_bus_irq(int apic, int pin)
1918 for (x = 0; x < nintrs; x++)
1919 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1920 (pin == io_apic_ints[x].dst_apic_int))
1921 return (io_apic_ints[x].src_bus_irq);
1923 return -1; /* NOT found */
1928 * given a LOGICAL APIC# and pin#, return:
1929 * the associated INTerrupt type if found
1933 apic_int_type(int apic, int pin)
1937 /* search each of the possible INTerrupt sources */
1938 for (x = 0; x < nintrs; ++x) {
1939 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1940 (pin == io_apic_ints[x].dst_apic_int))
1941 return (io_apic_ints[x].int_type);
1943 return -1; /* NOT found */
1947 * Return the IRQ associated with an APIC pin
1950 apic_irq(int apic, int pin)
1955 for (x = 0; x < nintrs; ++x) {
1956 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1957 (pin == io_apic_ints[x].dst_apic_int)) {
1958 res = io_apic_ints[x].int_vector;
1961 if (apic != int_to_apicintpin[res].ioapic)
1962 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1963 if (pin != int_to_apicintpin[res].int_pin)
1964 panic("apic_irq inconsistent table (2)");
1973 * given a LOGICAL APIC# and pin#, return:
1974 * the associated trigger mode if found
1978 apic_trigger(int apic, int pin)
1982 /* search each of the possible INTerrupt sources */
1983 for (x = 0; x < nintrs; ++x)
1984 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1985 (pin == io_apic_ints[x].dst_apic_int))
1986 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1988 return -1; /* NOT found */
1993 * given a LOGICAL APIC# and pin#, return:
1994 * the associated 'active' level if found
1998 apic_polarity(int apic, int pin)
2002 /* search each of the possible INTerrupt sources */
2003 for (x = 0; x < nintrs; ++x)
2004 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2005 (pin == io_apic_ints[x].dst_apic_int))
2006 return (io_apic_ints[x].int_flags & 0x03);
2008 return -1; /* NOT found */
2014 * set data according to MP defaults
2015 * FIXME: probably not complete yet...
2018 mptable_default(int type)
2020 int ap_cpu_id, boot_cpu_id;
2021 #if defined(APIC_IO)
2024 #endif /* APIC_IO */
2027 kprintf(" MP default config type: %d\n", type);
2030 kprintf(" bus: ISA, APIC: 82489DX\n");
2033 kprintf(" bus: EISA, APIC: 82489DX\n");
2036 kprintf(" bus: EISA, APIC: 82489DX\n");
2039 kprintf(" bus: MCA, APIC: 82489DX\n");
2042 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2045 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2048 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2051 kprintf(" future type\n");
2057 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
2058 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2061 CPU_TO_ID(0) = boot_cpu_id;
2062 ID_TO_CPU(boot_cpu_id) = 0;
2064 /* one and only AP */
2065 CPU_TO_ID(1) = ap_cpu_id;
2066 ID_TO_CPU(ap_cpu_id) = 1;
2068 #if defined(APIC_IO)
2069 /* one and only IO APIC */
2070 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2073 * sanity check, refer to MP spec section 3.6.6, last paragraph
2074 * necessary as some hardware isn't properly setting up the IO APIC
2076 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2077 if (io_apic_id != 2) {
2079 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2080 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2081 io_apic_set_id(0, 2);
2084 IO_TO_ID(0) = io_apic_id;
2085 ID_TO_IO(io_apic_id) = 0;
2086 #endif /* APIC_IO */
2088 /* fill out bus entries */
2097 bus_data[0].bus_id = default_data[type - 1][1];
2098 bus_data[0].bus_type = default_data[type - 1][2];
2099 bus_data[1].bus_id = default_data[type - 1][3];
2100 bus_data[1].bus_type = default_data[type - 1][4];
2103 /* case 4: case 7: MCA NOT supported */
2104 default: /* illegal/reserved */
2105 panic("BAD default MP config: %d", type);
2109 #if defined(APIC_IO)
2110 /* general cases from MP v1.4, table 5-2 */
2111 for (pin = 0; pin < 16; ++pin) {
2112 io_apic_ints[pin].int_type = 0;
2113 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2114 io_apic_ints[pin].src_bus_id = 0;
2115 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2116 io_apic_ints[pin].dst_apic_id = io_apic_id;
2117 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2120 /* special cases from MP v1.4, table 5-2 */
2122 io_apic_ints[2].int_type = 0xff; /* N/C */
2123 io_apic_ints[13].int_type = 0xff; /* N/C */
2124 #if !defined(APIC_MIXED_MODE)
2126 panic("sorry, can't support type 2 default yet");
2127 #endif /* APIC_MIXED_MODE */
2130 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2133 io_apic_ints[0].int_type = 0xff; /* N/C */
2135 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2136 #endif /* APIC_IO */
2140 * Map a physical memory address representing I/O into KVA. The I/O
2141 * block is assumed not to cross a page boundary.
2144 permanent_io_mapping(vm_paddr_t pa)
2146 KKASSERT(pa < 0x100000000LL);
2148 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2152 * start each AP in our list
2155 start_all_aps(u_int boot_addr)
2157 vm_offset_t va = boot_address + KERNBASE;
2158 u_int64_t *pt4, *pt3, *pt2;
2164 u_char mpbiosreason;
2165 u_long mpbioswarmvec;
2166 struct mdglobaldata *gd;
2167 struct privatespace *ps;
2169 POSTCODE(START_ALL_APS_POST);
2171 /* Initialize BSP's local APIC */
2172 apic_initialize(TRUE);
2175 /* install the AP 1st level boot code */
2176 pmap_kenter(va, boot_address);
2177 cpu_invlpg((void *)va); /* JG XXX */
2178 bcopy(mptramp_start, (void *)va, bootMP_size);
2180 /* Locate the page tables, they'll be below the trampoline */
2181 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2182 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2183 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2185 /* Create the initial 1GB replicated page tables */
2186 for (i = 0; i < 512; i++) {
2187 /* Each slot of the level 4 pages points to the same level 3 page */
2188 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2189 pt4[i] |= PG_V | PG_RW | PG_U;
2191 /* Each slot of the level 3 pages points to the same level 2 page */
2192 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2193 pt3[i] |= PG_V | PG_RW | PG_U;
2195 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2196 pt2[i] = i * (2 * 1024 * 1024);
2197 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2200 /* save the current value of the warm-start vector */
2201 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2202 outb(CMOS_REG, BIOS_RESET);
2203 mpbiosreason = inb(CMOS_DATA);
2205 /* setup a vector to our boot code */
2206 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2207 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2208 outb(CMOS_REG, BIOS_RESET);
2209 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2212 * If we have a TSC we can figure out the SMI interrupt rate.
2213 * The SMI does not necessarily use a constant rate. Spend
2214 * up to 250ms trying to figure it out.
2217 if (cpu_feature & CPUID_TSC) {
2218 set_apic_timer(275000);
2219 smilast = read_apic_timer();
2220 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2221 smicount = smitest();
2222 if (smibest == 0 || smilast - smicount < smibest)
2223 smibest = smilast - smicount;
2226 if (smibest > 250000)
2229 smibest = smibest * (int64_t)1000000 /
2230 get_apic_timer_frequency();
2234 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2235 1000000 / smibest, smibest);
2238 for (x = 1; x <= mp_naps; ++x) {
2240 /* This is a bit verbose, it will go away soon. */
2242 /* first page of AP's private space */
2243 pg = x * x86_64_btop(sizeof(struct privatespace));
2245 /* allocate new private data page(s) */
2246 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2247 MDGLOBALDATA_BASEALLOC_SIZE);
2249 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2250 bzero(gd, sizeof(*gd));
2251 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2253 /* prime data page for it to use */
2254 mi_gdinit(&gd->mi, x);
2256 gd->gd_CMAP1 = &SMPpt[pg + 0];
2257 gd->gd_CMAP2 = &SMPpt[pg + 1];
2258 gd->gd_CMAP3 = &SMPpt[pg + 2];
2259 gd->gd_PMAP1 = &SMPpt[pg + 3];
2260 gd->gd_CADDR1 = ps->CPAGE1;
2261 gd->gd_CADDR2 = ps->CPAGE2;
2262 gd->gd_CADDR3 = ps->CPAGE3;
2263 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2264 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2265 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2267 /* setup a vector to our boot code */
2268 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2269 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2270 outb(CMOS_REG, BIOS_RESET);
2271 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2274 * Setup the AP boot stack
2276 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2279 /* attempt to start the Application Processor */
2280 CHECK_INIT(99); /* setup checkpoints */
2281 if (!start_ap(gd, boot_addr, smibest)) {
2282 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2283 CHECK_PRINT("trace"); /* show checkpoints */
2284 /* better panic as the AP may be running loose */
2285 kprintf("panic y/n? [y] ");
2286 if (cngetc() != 'n')
2289 CHECK_PRINT("trace"); /* show checkpoints */
2291 /* record its version info */
2292 cpu_apic_versions[x] = cpu_apic_versions[0];
2295 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2298 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2299 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2302 ncpus2_shift = shift;
2303 ncpus2 = 1 << shift;
2304 ncpus2_mask = ncpus2 - 1;
2306 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2307 if ((1 << shift) < ncpus)
2309 ncpus_fit = 1 << shift;
2310 ncpus_fit_mask = ncpus_fit - 1;
2312 /* build our map of 'other' CPUs */
2313 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2314 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2315 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2317 /* fill in our (BSP) APIC version */
2318 cpu_apic_versions[0] = lapic->version;
2320 /* restore the warmstart vector */
2321 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2322 outb(CMOS_REG, BIOS_RESET);
2323 outb(CMOS_DATA, mpbiosreason);
2326 * NOTE! The idlestack for the BSP was setup by locore. Finish
2327 * up, clean out the P==V mapping we did earlier.
2331 /* number of APs actually started */
2337 * load the 1st level AP boot code into base memory.
2340 /* targets for relocation */
2341 extern void bigJump(void);
2342 extern void bootCodeSeg(void);
2343 extern void bootDataSeg(void);
2344 extern void MPentry(void);
2345 extern u_int MP_GDT;
2346 extern u_int mp_gdtbase;
2351 install_ap_tramp(u_int boot_addr)
2354 int size = *(int *) ((u_long) & bootMP_size);
2355 u_char *src = (u_char *) ((u_long) bootMP);
2356 u_char *dst = (u_char *) boot_addr + KERNBASE;
2357 u_int boot_base = (u_int) bootMP;
2362 POSTCODE(INSTALL_AP_TRAMP_POST);
2364 for (x = 0; x < size; ++x)
2368 * modify addresses in code we just moved to basemem. unfortunately we
2369 * need fairly detailed info about mpboot.s for this to work. changes
2370 * to mpboot.s might require changes here.
2373 /* boot code is located in KERNEL space */
2374 dst = (u_char *) boot_addr + KERNBASE;
2376 /* modify the lgdt arg */
2377 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2378 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2380 /* modify the ljmp target for MPentry() */
2381 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2382 *dst32 = ((u_int) MPentry - KERNBASE);
2384 /* modify the target for boot code segment */
2385 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2386 dst8 = (u_int8_t *) (dst16 + 1);
2387 *dst16 = (u_int) boot_addr & 0xffff;
2388 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2390 /* modify the target for boot data segment */
2391 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2392 dst8 = (u_int8_t *) (dst16 + 1);
2393 *dst16 = (u_int) boot_addr & 0xffff;
2394 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2400 * This function starts the AP (application processor) identified
2401 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2402 * to accomplish this. This is necessary because of the nuances
2403 * of the different hardware we might encounter. It ain't pretty,
2404 * but it seems to work.
2406 * NOTE: eventually an AP gets to ap_init(), which is called just
2407 * before the AP goes into the LWKT scheduler's idle loop.
2410 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2414 u_long icr_lo, icr_hi;
2416 POSTCODE(START_AP_POST);
2418 /* get the PHYSICAL APIC ID# */
2419 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2421 /* calculate the vector */
2422 vector = (boot_addr >> 12) & 0xff;
2424 /* We don't want anything interfering */
2427 /* Make sure the target cpu sees everything */
2431 * Try to detect when a SMI has occurred, wait up to 200ms.
2433 * If a SMI occurs during an AP reset but before we issue
2434 * the STARTUP command, the AP may brick. To work around
2435 * this problem we hold off doing the AP startup until
2436 * after we have detected the SMI. Hopefully another SMI
2437 * will not occur before we finish the AP startup.
2439 * Retries don't seem to help. SMIs have a window of opportunity
2440 * and if USB->legacy keyboard emulation is enabled in the BIOS
2441 * the interrupt rate can be quite high.
2443 * NOTE: Don't worry about the L1 cache load, it might bloat
2444 * ldelta a little but ndelta will be so huge when the SMI
2445 * occurs the detection logic will still work fine.
2448 set_apic_timer(200000);
2453 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2454 * and running the target CPU. OR this INIT IPI might be latched (P5
2455 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2458 * see apic/apicreg.h for icr bit definitions.
2460 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2464 * Setup the address for the target AP. We can setup
2465 * icr_hi once and then just trigger operations with
2468 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2469 icr_hi |= (physical_cpu << 24);
2470 icr_lo = lapic->icr_lo & 0xfff00000;
2471 lapic->icr_hi = icr_hi;
2474 * Do an INIT IPI: assert RESET
2476 * Use edge triggered mode to assert INIT
2478 lapic->icr_lo = icr_lo | 0x00004500;
2479 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2483 * The spec calls for a 10ms delay but we may have to use a
2484 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2485 * interrupt. We have other loops here too and dividing by 2
2486 * doesn't seem to be enough even after subtracting 350us,
2487 * so we divide by 4.
2489 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2490 * interrupt was detected we use the full 10ms.
2494 else if (smibest < 150 * 4 + 350)
2496 else if ((smibest - 350) / 4 < 10000)
2497 u_sleep((smibest - 350) / 4);
2502 * Do an INIT IPI: deassert RESET
2504 * Use level triggered mode to deassert. It is unclear
2505 * why we need to do this.
2507 lapic->icr_lo = icr_lo | 0x00008500;
2508 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2510 u_sleep(150); /* wait 150us */
2513 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2514 * latched, (P5 bug) this 1st STARTUP would then terminate
2515 * immediately, and the previously started INIT IPI would continue. OR
2516 * the previous INIT IPI has already run. and this STARTUP IPI will
2517 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2520 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2521 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2523 u_sleep(200); /* wait ~200uS */
2526 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2527 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2528 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2529 * recognized after hardware RESET or INIT IPI.
2531 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2532 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2535 /* Resume normal operation */
2538 /* wait for it to start, see ap_init() */
2539 set_apic_timer(5000000);/* == 5 seconds */
2540 while (read_apic_timer()) {
2541 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2542 return 1; /* return SUCCESS */
2545 return 0; /* return FAILURE */
2560 while (read_apic_timer()) {
2562 for (count = 0; count < 100; ++count)
2563 ntsc = rdtsc(); /* force loop to occur */
2565 ndelta = ntsc - ltsc;
2566 if (ldelta > ndelta)
2568 if (ndelta > ldelta * 2)
2571 ldelta = ntsc - ltsc;
2574 return(read_apic_timer());
2578 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2580 * If for some reason we were unable to start all cpus we cannot safely
2581 * use broadcast IPIs.
2587 if (smp_startup_mask == smp_active_mask) {
2588 all_but_self_ipi(XINVLTLB_OFFSET);
2590 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2591 APIC_DELMODE_FIXED);
2597 * When called the executing CPU will send an IPI to all other CPUs
2598 * requesting that they halt execution.
2600 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2602 * - Signals all CPUs in map to stop.
2603 * - Waits for each to stop.
2610 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2611 * from executing at same time.
2614 stop_cpus(u_int map)
2616 map &= smp_active_mask;
2618 /* send the Xcpustop IPI to all CPUs in map */
2619 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2621 while ((stopped_cpus & map) != map)
2629 * Called by a CPU to restart stopped CPUs.
2631 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2633 * - Signals all CPUs in map to restart.
2634 * - Waits for each to restart.
2642 restart_cpus(u_int map)
2644 /* signal other cpus to restart */
2645 started_cpus = map & smp_active_mask;
2647 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2654 * This is called once the mpboot code has gotten us properly relocated
2655 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2656 * and when it returns the scheduler will call the real cpu_idle() main
2657 * loop for the idlethread. Interrupts are disabled on entry and should
2658 * remain disabled at return.
2666 * Adjust smp_startup_mask to signal the BSP that we have started
2667 * up successfully. Note that we do not yet hold the BGL. The BSP
2668 * is waiting for our signal.
2670 * We can't set our bit in smp_active_mask yet because we are holding
2671 * interrupts physically disabled and remote cpus could deadlock
2672 * trying to send us an IPI.
2674 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2678 * Interlock for finalization. Wait until mp_finish is non-zero,
2679 * then get the MP lock.
2681 * Note: We are in a critical section.
2683 * Note: We have to synchronize td_mpcount to our desired MP state
2684 * before calling cpu_try_mplock().
2686 * Note: we are the idle thread, we can only spin.
2688 * Note: The load fence is memory volatile and prevents the compiler
2689 * from improperly caching mp_finish, and the cpu from improperly
2692 while (mp_finish == 0)
2694 ++curthread->td_mpcount;
2695 while (cpu_try_mplock() == 0)
2698 if (cpu_feature & CPUID_TSC) {
2700 * The BSP is constantly updating tsc0_offset, figure out the
2701 * relative difference to synchronize ktrdump.
2703 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2706 /* BSP may have changed PTD while we're waiting for the lock */
2709 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2713 /* Build our map of 'other' CPUs. */
2714 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2716 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2718 /* A quick check from sanity claus */
2719 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2720 if (mycpu->gd_cpuid != apic_id) {
2721 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2722 kprintf("SMP: apic_id = %d\n", apic_id);
2724 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2726 panic("cpuid mismatch! boom!!");
2729 /* Initialize AP's local APIC for irq's */
2730 apic_initialize(FALSE);
2732 /* Set memory range attributes for this CPU to match the BSP */
2733 mem_range_AP_init();
2736 * Once we go active we must process any IPIQ messages that may
2737 * have been queued, because no actual IPI will occur until we
2738 * set our bit in the smp_active_mask. If we don't the IPI
2739 * message interlock could be left set which would also prevent
2742 * The idle loop doesn't expect the BGL to be held and while
2743 * lwkt_switch() normally cleans things up this is a special case
2744 * because we returning almost directly into the idle loop.
2746 * The idle thread is never placed on the runq, make sure
2747 * nothing we've done put it there.
2749 KKASSERT(curthread->td_mpcount == 1);
2750 smp_active_mask |= 1 << mycpu->gd_cpuid;
2753 * Enable interrupts here. idle_restore will also do it, but
2754 * doing it here lets us clean up any strays that got posted to
2755 * the CPU during the AP boot while we are still in a critical
2758 __asm __volatile("sti; pause; pause"::);
2759 mdcpu->gd_fpending = 0;
2761 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2762 lwkt_process_ipiq();
2765 * Releasing the mp lock lets the BSP finish up the SMP init
2768 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2772 * Get SMP fully working before we start initializing devices.
2780 kprintf("Finish MP startup\n");
2781 if (cpu_feature & CPUID_TSC)
2782 tsc0_offset = rdtsc();
2785 while (smp_active_mask != smp_startup_mask) {
2787 if (cpu_feature & CPUID_TSC)
2788 tsc0_offset = rdtsc();
2790 while (try_mplock() == 0)
2793 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2796 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2799 cpu_send_ipiq(int dcpu)
2801 if ((1 << dcpu) & smp_active_mask)
2802 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2805 #if 0 /* single_apic_ipi_passive() not working yet */
2807 * Returns 0 on failure, 1 on success
2810 cpu_send_ipiq_passive(int dcpu)
2813 if ((1 << dcpu) & smp_active_mask) {
2814 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2815 APIC_DELMODE_FIXED);