1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
2 /* $FreeBSD: src/sys/dev/stge/if_stge.c,v 1.2 2006/08/12 01:21:36 yongari Exp $ */
5 * Copyright (c) 2001 The NetBSD Foundation, Inc.
8 * This code is derived from software contributed to The NetBSD Foundation
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
41 * Device driver for the Sundance Tech. TC9021 10/100/1000
42 * Ethernet controller.
45 #include "opt_ifpoll.h"
47 #include <sys/param.h>
49 #include <sys/endian.h>
50 #include <sys/kernel.h>
51 #include <sys/interrupt.h>
52 #include <sys/malloc.h>
54 #include <sys/module.h>
56 #include <sys/serialize.h>
57 #include <sys/socket.h>
58 #include <sys/sockio.h>
59 #include <sys/sysctl.h>
62 #include <net/ethernet.h>
64 #include <net/if_arp.h>
65 #include <net/if_dl.h>
66 #include <net/if_media.h>
67 #include <net/if_poll.h>
68 #include <net/if_types.h>
69 #include <net/ifq_var.h>
70 #include <net/vlan/if_vlan_var.h>
71 #include <net/vlan/if_vlan_ether.h>
73 #include <dev/netif/mii_layer/mii.h>
74 #include <dev/netif/mii_layer/miivar.h>
76 #include <bus/pci/pcireg.h>
77 #include <bus/pci/pcivar.h>
79 #include "if_stgereg.h"
80 #include "if_stgevar.h"
82 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
84 /* "device miibus" required. See GENERIC if you get errors here. */
85 #include "miibus_if.h"
88 * Devices supported by this driver.
90 static struct stge_product {
91 uint16_t stge_vendorid;
92 uint16_t stge_deviceid;
93 const char *stge_name;
95 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
96 "Sundance ST-1023 Gigabit Ethernet" },
98 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
99 "Sundance ST-2021 Gigabit Ethernet" },
101 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
102 "Tamarack TC9021 Gigabit Ethernet" },
104 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
105 "Tamarack TC9021 Gigabit Ethernet" },
108 * The Sundance sample boards use the Sundance vendor ID,
109 * but the Tamarack product ID.
111 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
112 "Sundance TC9021 Gigabit Ethernet" },
114 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
115 "Sundance TC9021 Gigabit Ethernet" },
117 { VENDOR_DLINK, DEVICEID_DLINK_DL2000,
118 "D-Link DL-2000 Gigabit Ethernet" },
120 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
121 "Antares Gigabit Ethernet" },
126 static int stge_probe(device_t);
127 static int stge_attach(device_t);
128 static int stge_detach(device_t);
129 static void stge_shutdown(device_t);
130 static int stge_suspend(device_t);
131 static int stge_resume(device_t);
133 static int stge_encap(struct stge_softc *, struct mbuf **);
134 static void stge_start(struct ifnet *);
135 static void stge_watchdog(struct ifnet *);
136 static int stge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
137 static void stge_init(void *);
138 static void stge_vlan_setup(struct stge_softc *);
139 static void stge_stop(struct stge_softc *);
140 static void stge_start_tx(struct stge_softc *);
141 static void stge_start_rx(struct stge_softc *);
142 static void stge_stop_tx(struct stge_softc *);
143 static void stge_stop_rx(struct stge_softc *);
145 static void stge_reset(struct stge_softc *, uint32_t);
146 static int stge_eeprom_wait(struct stge_softc *);
147 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
148 static void stge_tick(void *);
149 static void stge_stats_update(struct stge_softc *);
150 static void stge_set_filter(struct stge_softc *);
151 static void stge_set_multi(struct stge_softc *);
153 static void stge_link(struct stge_softc *);
154 static void stge_intr(void *);
155 static __inline int stge_tx_error(struct stge_softc *);
156 static void stge_txeof(struct stge_softc *);
157 static void stge_rxeof(struct stge_softc *, int);
158 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
159 static int stge_newbuf(struct stge_softc *, int, int);
161 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
164 static void stge_mii_sync(struct stge_softc *);
165 static void stge_mii_send(struct stge_softc *, uint32_t, int);
166 static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *);
167 static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *);
168 static int stge_miibus_readreg(device_t, int, int);
169 static int stge_miibus_writereg(device_t, int, int, int);
170 static void stge_miibus_statchg(device_t);
171 static int stge_mediachange(struct ifnet *);
172 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
174 static int stge_dma_alloc(struct stge_softc *);
175 static void stge_dma_free(struct stge_softc *);
176 static void stge_dma_wait(struct stge_softc *);
177 static void stge_init_tx_ring(struct stge_softc *);
178 static int stge_init_rx_ring(struct stge_softc *);
180 static void stge_npoll(struct ifnet *, struct ifpoll_info *);
181 static void stge_npoll_compat(struct ifnet *, void *, int);
184 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
185 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
187 static device_method_t stge_methods[] = {
188 /* Device interface */
189 DEVMETHOD(device_probe, stge_probe),
190 DEVMETHOD(device_attach, stge_attach),
191 DEVMETHOD(device_detach, stge_detach),
192 DEVMETHOD(device_shutdown, stge_shutdown),
193 DEVMETHOD(device_suspend, stge_suspend),
194 DEVMETHOD(device_resume, stge_resume),
197 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
198 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
199 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
205 static driver_t stge_driver = {
208 sizeof(struct stge_softc)
211 static devclass_t stge_devclass;
213 DECLARE_DUMMY_MODULE(if_stge);
214 MODULE_DEPEND(if_stge, miibus, 1, 1, 1);
215 DRIVER_MODULE(if_stge, pci, stge_driver, stge_devclass, NULL, NULL);
216 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, NULL, NULL);
219 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
221 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
224 * Sync the PHYs by setting data bit and strobing the clock 32 times.
227 stge_mii_sync(struct stge_softc *sc)
231 MII_SET(PC_MgmtDir | PC_MgmtData);
233 for (i = 0; i < 32; i++) {
242 * Clock a series of bits through the MII.
245 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt)
251 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
253 MII_SET(PC_MgmtData);
255 MII_CLR(PC_MgmtData);
264 * Read an PHY register through the MII.
267 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame)
272 * Set up frame for RX.
274 frame->mii_stdelim = STGE_MII_STARTDELIM;
275 frame->mii_opcode = STGE_MII_READOP;
276 frame->mii_turnaround = 0;
279 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl);
288 * Send command/address info.
290 stge_mii_send(sc, frame->mii_stdelim, 2);
291 stge_mii_send(sc, frame->mii_opcode, 2);
292 stge_mii_send(sc, frame->mii_phyaddr, 5);
293 stge_mii_send(sc, frame->mii_regaddr, 5);
299 MII_CLR((PC_MgmtClk | PC_MgmtData));
307 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData;
312 * Now try reading data bits. If the ack failed, we still
313 * need to clock through 16 cycles to keep the PHY(s) in sync.
316 for(i = 0; i < 16; i++) {
325 for (i = 0x8000; i; i >>= 1) {
329 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData)
330 frame->mii_data |= i;
349 * Write to a PHY register through the MII.
352 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame)
356 * Set up frame for TX.
358 frame->mii_stdelim = STGE_MII_STARTDELIM;
359 frame->mii_opcode = STGE_MII_WRITEOP;
360 frame->mii_turnaround = STGE_MII_TURNAROUND;
363 * Turn on data output.
369 stge_mii_send(sc, frame->mii_stdelim, 2);
370 stge_mii_send(sc, frame->mii_opcode, 2);
371 stge_mii_send(sc, frame->mii_phyaddr, 5);
372 stge_mii_send(sc, frame->mii_regaddr, 5);
373 stge_mii_send(sc, frame->mii_turnaround, 2);
374 stge_mii_send(sc, frame->mii_data, 16);
391 * sc_miibus_readreg: [mii interface function]
393 * Read a PHY register on the MII of the TC9021.
396 stge_miibus_readreg(device_t dev, int phy, int reg)
398 struct stge_softc *sc;
399 struct stge_mii_frame frame;
402 sc = device_get_softc(dev);
404 if (reg == STGE_PhyCtrl) {
405 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
406 error = CSR_READ_1(sc, STGE_PhyCtrl);
409 bzero(&frame, sizeof(frame));
410 frame.mii_phyaddr = phy;
411 frame.mii_regaddr = reg;
413 error = stge_mii_readreg(sc, &frame);
416 /* Don't show errors for PHY probe request */
418 device_printf(sc->sc_dev, "phy read fail\n");
421 return (frame.mii_data);
425 * stge_miibus_writereg: [mii interface function]
427 * Write a PHY register on the MII of the TC9021.
430 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
432 struct stge_softc *sc;
433 struct stge_mii_frame frame;
436 sc = device_get_softc(dev);
438 bzero(&frame, sizeof(frame));
439 frame.mii_phyaddr = phy;
440 frame.mii_regaddr = reg;
441 frame.mii_data = val;
443 error = stge_mii_writereg(sc, &frame);
446 device_printf(sc->sc_dev, "phy write fail\n");
451 * stge_miibus_statchg: [mii interface function]
453 * Callback from MII layer when media changes.
456 stge_miibus_statchg(device_t dev)
458 struct stge_softc *sc;
459 struct mii_data *mii;
461 sc = device_get_softc(dev);
462 mii = device_get_softc(sc->sc_miibus);
464 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)
468 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
469 sc->sc_MACCtrl |= MC_DuplexSelect;
470 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0)
471 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
472 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0)
473 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
479 * stge_mediastatus: [ifmedia interface function]
481 * Get the current interface media status.
484 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
486 struct stge_softc *sc;
487 struct mii_data *mii;
490 mii = device_get_softc(sc->sc_miibus);
493 ifmr->ifm_status = mii->mii_media_status;
494 ifmr->ifm_active = mii->mii_media_active;
498 * stge_mediachange: [ifmedia interface function]
500 * Set hardware to newly-selected media.
503 stge_mediachange(struct ifnet *ifp)
505 struct stge_softc *sc;
506 struct mii_data *mii;
509 mii = device_get_softc(sc->sc_miibus);
516 stge_eeprom_wait(struct stge_softc *sc)
520 for (i = 0; i < STGE_TIMEOUT; i++) {
522 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
531 * Read data from the serial EEPROM.
534 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
537 if (stge_eeprom_wait(sc))
538 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
540 CSR_WRITE_2(sc, STGE_EepromCtrl,
541 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
542 if (stge_eeprom_wait(sc))
543 device_printf(sc->sc_dev, "EEPROM read timed out\n");
544 *data = CSR_READ_2(sc, STGE_EepromData);
549 stge_probe(device_t dev)
551 struct stge_product *sp;
552 uint16_t vendor, devid;
554 vendor = pci_get_vendor(dev);
555 devid = pci_get_device(dev);
557 for (sp = stge_products; sp->stge_name != NULL; sp++) {
558 if (vendor == sp->stge_vendorid &&
559 devid == sp->stge_deviceid) {
560 device_set_desc(dev, sp->stge_name);
569 stge_attach(device_t dev)
571 struct stge_softc *sc;
573 uint8_t enaddr[ETHER_ADDR_LEN];
579 sc = device_get_softc(dev);
581 ifp = &sc->arpcom.ac_if;
583 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
585 callout_init(&sc->sc_tick_ch);
589 * Handle power management nonsense.
591 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
592 uint32_t iobase, membase, irq;
594 /* Save important PCI config data. */
595 iobase = pci_read_config(dev, STGE_PCIR_LOIO, 4);
596 membase = pci_read_config(dev, STGE_PCIR_LOMEM, 4);
597 irq = pci_read_config(dev, PCIR_INTLINE, 4);
599 /* Reset the power state. */
600 device_printf(dev, "chip is in D%d power mode "
601 "-- setting to D0\n", pci_get_powerstate(dev));
603 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
605 /* Restore PCI config data. */
606 pci_write_config(dev, STGE_PCIR_LOIO, iobase, 4);
607 pci_write_config(dev, STGE_PCIR_LOMEM, membase, 4);
608 pci_write_config(dev, PCIR_INTLINE, irq, 4);
615 pci_enable_busmaster(dev);
616 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
617 val = pci_read_config(dev, STGE_PCIR_LOMEM, 4);
619 if ((val & 0x01) != 0) {
620 sc->sc_res_rid = STGE_PCIR_LOMEM;
621 sc->sc_res_type = SYS_RES_MEMORY;
623 sc->sc_res_rid = STGE_PCIR_LOIO;
624 sc->sc_res_type = SYS_RES_IOPORT;
626 val = pci_read_config(dev, sc->sc_res_rid, 4);
627 if ((val & 0x01) == 0) {
628 device_printf(dev, "couldn't locate IO BAR\n");
633 sc->sc_res = bus_alloc_resource_any(dev, sc->sc_res_type,
634 &sc->sc_res_rid, RF_ACTIVE);
635 if (sc->sc_res == NULL) {
636 device_printf(dev, "couldn't allocate resource\n");
639 sc->sc_btag = rman_get_bustag(sc->sc_res);
640 sc->sc_bhandle = rman_get_bushandle(sc->sc_res);
642 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
644 RF_ACTIVE | RF_SHAREABLE);
645 if (sc->sc_irq == NULL) {
646 device_printf(dev, "couldn't allocate IRQ\n");
651 sc->sc_rev = pci_get_revid(dev);
653 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
654 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
656 sysctl_ctx_init(&sc->sc_sysctl_ctx);
657 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
658 SYSCTL_STATIC_CHILDREN(_hw),
660 device_get_nameunit(dev),
662 if (sc->sc_sysctl_tree == NULL) {
663 device_printf(dev, "can't add sysctl node\n");
668 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
669 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
670 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
671 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
673 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
674 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
675 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
676 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
678 error = stge_dma_alloc(sc);
683 * Determine if we're copper or fiber. It affects how we
686 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
691 /* Load LED configuration from EEPROM. */
692 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
695 * Reset the chip to a known state.
697 stge_reset(sc, STGE_RESET_FULL);
700 * Reading the station address from the EEPROM doesn't seem
701 * to work, at least on my sample boards. Instead, since
702 * the reset sequence does AutoInit, read it from the station
703 * address registers. For Sundance 1023 you can only read it
706 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
709 v = CSR_READ_2(sc, STGE_StationAddress0);
710 enaddr[0] = v & 0xff;
712 v = CSR_READ_2(sc, STGE_StationAddress1);
713 enaddr[2] = v & 0xff;
715 v = CSR_READ_2(sc, STGE_StationAddress2);
716 enaddr[4] = v & 0xff;
720 uint16_t myaddr[ETHER_ADDR_LEN / 2];
721 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
722 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
724 myaddr[i] = le16toh(myaddr[i]);
726 bcopy(myaddr, enaddr, sizeof(enaddr));
731 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
732 ifp->if_ioctl = stge_ioctl;
733 ifp->if_start = stge_start;
734 ifp->if_watchdog = stge_watchdog;
735 ifp->if_init = stge_init;
737 ifp->if_npoll = stge_npoll;
739 ifp->if_mtu = ETHERMTU;
740 ifq_set_maxlen(&ifp->if_snd, STGE_TX_RING_CNT - 1);
741 ifq_set_ready(&ifp->if_snd);
742 /* Revision B3 and earlier chips have checksum bug. */
743 if (sc->sc_rev >= 0x0c) {
744 ifp->if_hwassist = STGE_CSUM_FEATURES;
745 ifp->if_capabilities = IFCAP_HWCSUM;
747 ifp->if_hwassist = 0;
748 ifp->if_capabilities = 0;
750 ifp->if_capenable = ifp->if_capabilities;
753 * Read some important bits from the PhyCtrl register.
755 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
756 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
758 /* Set up MII bus. */
759 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange,
760 stge_mediastatus)) != 0) {
761 device_printf(sc->sc_dev, "no PHY found!\n");
765 ether_ifattach(ifp, enaddr, NULL);
768 ifpoll_compat_setup(&sc->sc_npoll,
769 &sc->sc_sysctl_ctx, sc->sc_sysctl_tree, device_get_unit(dev),
773 /* VLAN capability setup */
774 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
776 if (sc->sc_rev >= 0x0c)
777 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
779 ifp->if_capenable = ifp->if_capabilities;
782 * Tell the upper layer(s) we support long frames.
783 * Must appear after the call to ether_ifattach() because
784 * ether_ifattach() sets ifi_hdrlen to the default value.
786 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
789 * The manual recommends disabling early transmit, so we
790 * do. It's disabled anyway, if using IP checksumming,
791 * since the entire packet must be in the FIFO in order
792 * for the chip to perform the checksum.
794 sc->sc_txthresh = 0x0fff;
797 * Disable MWI if the PCI layer tells us to.
800 if ((cmd & PCIM_CMD_MWRICEN) == 0)
801 sc->sc_DMACtrl |= DMAC_MWIDisable;
806 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, stge_intr, sc,
807 &sc->sc_ih, ifp->if_serializer);
810 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
814 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq));
824 stge_detach(device_t dev)
826 struct stge_softc *sc = device_get_softc(dev);
827 struct ifnet *ifp = &sc->arpcom.ac_if;
829 if (device_is_attached(dev)) {
830 lwkt_serialize_enter(ifp->if_serializer);
834 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
835 lwkt_serialize_exit(ifp->if_serializer);
840 if (sc->sc_sysctl_tree != NULL)
841 sysctl_ctx_free(&sc->sc_sysctl_ctx);
843 if (sc->sc_miibus != NULL)
844 device_delete_child(dev, sc->sc_miibus);
845 bus_generic_detach(dev);
849 if (sc->sc_irq != NULL) {
850 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
853 if (sc->sc_res != NULL) {
854 bus_release_resource(dev, sc->sc_res_type, sc->sc_res_rid,
862 stge_dma_alloc(struct stge_softc *sc)
864 struct stge_txdesc *txd;
865 struct stge_rxdesc *rxd;
868 /* create parent tag. */
869 error = bus_dma_tag_create(NULL, /* parent */
870 1, 0, /* algnmnt, boundary */
871 STGE_DMA_MAXADDR, /* lowaddr */
872 BUS_SPACE_MAXADDR, /* highaddr */
873 NULL, NULL, /* filter, filterarg */
874 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
876 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
878 &sc->sc_cdata.stge_parent_tag);
880 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
884 /* allocate Tx ring. */
885 sc->sc_rdata.stge_tx_ring =
886 bus_dmamem_coherent_any(sc->sc_cdata.stge_parent_tag,
887 STGE_RING_ALIGN, STGE_TX_RING_SZ,
888 BUS_DMA_WAITOK | BUS_DMA_ZERO,
889 &sc->sc_cdata.stge_tx_ring_tag,
890 &sc->sc_cdata.stge_tx_ring_map,
891 &sc->sc_rdata.stge_tx_ring_paddr);
892 if (sc->sc_rdata.stge_tx_ring == NULL) {
893 device_printf(sc->sc_dev,
894 "failed to allocate Tx ring\n");
898 /* allocate Rx ring. */
899 sc->sc_rdata.stge_rx_ring =
900 bus_dmamem_coherent_any(sc->sc_cdata.stge_parent_tag,
901 STGE_RING_ALIGN, STGE_RX_RING_SZ,
902 BUS_DMA_WAITOK | BUS_DMA_ZERO,
903 &sc->sc_cdata.stge_rx_ring_tag,
904 &sc->sc_cdata.stge_rx_ring_map,
905 &sc->sc_rdata.stge_rx_ring_paddr);
906 if (sc->sc_rdata.stge_rx_ring == NULL) {
907 device_printf(sc->sc_dev,
908 "failed to allocate Rx ring\n");
912 /* create tag for Tx buffers. */
913 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
914 1, 0, /* algnmnt, boundary */
915 BUS_SPACE_MAXADDR, /* lowaddr */
916 BUS_SPACE_MAXADDR, /* highaddr */
917 NULL, NULL, /* filter, filterarg */
918 STGE_JUMBO_FRAMELEN, /* maxsize */
919 STGE_MAXTXSEGS, /* nsegments */
920 STGE_MAXSGSIZE, /* maxsegsize */
921 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
922 &sc->sc_cdata.stge_tx_tag);
924 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
928 /* create DMA maps for Tx buffers. */
929 for (i = 0; i < STGE_TX_RING_CNT; i++) {
930 txd = &sc->sc_cdata.stge_txdesc[i];
931 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag,
932 BUS_DMA_WAITOK, &txd->tx_dmamap);
936 for (j = 0; j < i; ++j) {
937 txd = &sc->sc_cdata.stge_txdesc[j];
938 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
941 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
942 sc->sc_cdata.stge_tx_tag = NULL;
944 device_printf(sc->sc_dev,
945 "failed to create Tx dmamap\n");
950 /* create tag for Rx buffers. */
951 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
952 1, 0, /* algnmnt, boundary */
953 BUS_SPACE_MAXADDR, /* lowaddr */
954 BUS_SPACE_MAXADDR, /* highaddr */
955 NULL, NULL, /* filter, filterarg */
956 MCLBYTES, /* maxsize */
958 MCLBYTES, /* maxsegsize */
959 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
960 &sc->sc_cdata.stge_rx_tag);
962 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
966 /* create DMA maps for Rx buffers. */
967 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, BUS_DMA_WAITOK,
968 &sc->sc_cdata.stge_rx_sparemap);
970 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
971 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
972 sc->sc_cdata.stge_rx_tag = NULL;
975 for (i = 0; i < STGE_RX_RING_CNT; i++) {
976 rxd = &sc->sc_cdata.stge_rxdesc[i];
977 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag,
978 BUS_DMA_WAITOK, &rxd->rx_dmamap);
982 for (j = 0; j < i; ++j) {
983 rxd = &sc->sc_cdata.stge_rxdesc[j];
984 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
987 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
988 sc->sc_cdata.stge_rx_sparemap);
989 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
990 sc->sc_cdata.stge_rx_tag = NULL;
992 device_printf(sc->sc_dev,
993 "failed to create Rx dmamap\n");
1001 stge_dma_free(struct stge_softc *sc)
1003 struct stge_txdesc *txd;
1004 struct stge_rxdesc *rxd;
1008 if (sc->sc_cdata.stge_tx_ring_tag) {
1009 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
1010 sc->sc_cdata.stge_tx_ring_map);
1011 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
1012 sc->sc_rdata.stge_tx_ring,
1013 sc->sc_cdata.stge_tx_ring_map);
1014 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
1018 if (sc->sc_cdata.stge_rx_ring_tag) {
1019 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
1020 sc->sc_cdata.stge_rx_ring_map);
1021 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
1022 sc->sc_rdata.stge_rx_ring,
1023 sc->sc_cdata.stge_rx_ring_map);
1024 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
1028 if (sc->sc_cdata.stge_tx_tag) {
1029 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1030 txd = &sc->sc_cdata.stge_txdesc[i];
1031 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
1034 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
1038 if (sc->sc_cdata.stge_rx_tag) {
1039 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1040 rxd = &sc->sc_cdata.stge_rxdesc[i];
1041 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1044 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1045 sc->sc_cdata.stge_rx_sparemap);
1046 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
1050 if (sc->sc_cdata.stge_parent_tag)
1051 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
1057 * Make sure the interface is stopped at reboot time.
1060 stge_shutdown(device_t dev)
1062 struct stge_softc *sc = device_get_softc(dev);
1063 struct ifnet *ifp = &sc->arpcom.ac_if;
1065 lwkt_serialize_enter(ifp->if_serializer);
1067 lwkt_serialize_exit(ifp->if_serializer);
1071 stge_suspend(device_t dev)
1073 struct stge_softc *sc = device_get_softc(dev);
1074 struct ifnet *ifp = &sc->arpcom.ac_if;
1076 lwkt_serialize_enter(ifp->if_serializer);
1078 sc->sc_suspended = 1;
1079 lwkt_serialize_exit(ifp->if_serializer);
1085 stge_resume(device_t dev)
1087 struct stge_softc *sc = device_get_softc(dev);
1088 struct ifnet *ifp = &sc->arpcom.ac_if;
1090 lwkt_serialize_enter(ifp->if_serializer);
1091 if (ifp->if_flags & IFF_UP)
1093 sc->sc_suspended = 0;
1094 lwkt_serialize_exit(ifp->if_serializer);
1100 stge_dma_wait(struct stge_softc *sc)
1104 for (i = 0; i < STGE_TIMEOUT; i++) {
1106 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1110 if (i == STGE_TIMEOUT)
1111 device_printf(sc->sc_dev, "DMA wait timed out\n");
1115 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1117 struct stge_txdesc *txd;
1118 struct stge_tfd *tfd;
1120 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1121 int error, i, si, nsegs;
1122 uint64_t csum_flags, tfc;
1124 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq);
1125 KKASSERT(txd != NULL);
1127 error = bus_dmamap_load_mbuf_defrag(sc->sc_cdata.stge_tx_tag,
1128 txd->tx_dmamap, m_head,
1129 txsegs, STGE_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT);
1135 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1136 BUS_DMASYNC_PREWRITE);
1141 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1142 if (m->m_pkthdr.csum_flags & CSUM_IP)
1143 csum_flags |= TFD_IPChecksumEnable;
1144 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1145 csum_flags |= TFD_TCPChecksumEnable;
1146 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1147 csum_flags |= TFD_UDPChecksumEnable;
1150 si = sc->sc_cdata.stge_tx_prod;
1151 tfd = &sc->sc_rdata.stge_tx_ring[si];
1152 for (i = 0; i < nsegs; i++) {
1153 tfd->tfd_frags[i].frag_word0 =
1154 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1155 FRAG_LEN(txsegs[i].ds_len));
1157 sc->sc_cdata.stge_tx_cnt++;
1159 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1160 TFD_FragCount(nsegs) | csum_flags;
1161 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1162 tfc |= TFD_TxDMAIndicate;
1164 /* Update producer index. */
1165 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1167 /* Check if we have a VLAN tag to insert. */
1168 if (m->m_flags & M_VLANTAG)
1169 tfc |= TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vlantag);
1170 tfd->tfd_control = htole64(tfc);
1172 /* Update Tx Queue. */
1173 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1174 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1181 * stge_start: [ifnet interface function]
1183 * Start packet transmission on the interface.
1186 stge_start(struct ifnet *ifp)
1188 struct stge_softc *sc;
1189 struct mbuf *m_head;
1194 ASSERT_SERIALIZED(ifp->if_serializer);
1196 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1200 while (!ifq_is_empty(&ifp->if_snd)) {
1201 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1202 ifq_set_oactive(&ifp->if_snd);
1206 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1211 * Pack the data into the transmit ring. If we
1212 * don't have room, set the OACTIVE flag and wait
1213 * for the NIC to drain the ring.
1215 if (stge_encap(sc, &m_head)) {
1216 if (sc->sc_cdata.stge_tx_cnt == 0) {
1219 ifq_set_oactive(&ifp->if_snd);
1226 * If there's a BPF listener, bounce a copy of this frame
1229 ETHER_BPF_MTAP(ifp, m_head);
1234 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1236 /* Set a timeout in case the chip goes out to lunch. */
1242 * stge_watchdog: [ifnet interface function]
1244 * Watchdog timer handler.
1247 stge_watchdog(struct ifnet *ifp)
1249 ASSERT_SERIALIZED(ifp->if_serializer);
1251 if_printf(ifp, "device timeout\n");
1253 stge_init(ifp->if_softc);
1257 * stge_ioctl: [ifnet interface function]
1259 * Handle control requests from the operator.
1262 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1264 struct stge_softc *sc;
1266 struct mii_data *mii;
1269 ASSERT_SERIALIZED(ifp->if_serializer);
1272 ifr = (struct ifreq *)data;
1276 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1278 else if (ifp->if_mtu != ifr->ifr_mtu) {
1279 ifp->if_mtu = ifr->ifr_mtu;
1284 if ((ifp->if_flags & IFF_UP) != 0) {
1285 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1286 if (((ifp->if_flags ^ sc->sc_if_flags)
1287 & IFF_PROMISC) != 0)
1288 stge_set_filter(sc);
1290 if (sc->sc_detach == 0)
1294 if ((ifp->if_flags & IFF_RUNNING) != 0)
1297 sc->sc_if_flags = ifp->if_flags;
1301 if ((ifp->if_flags & IFF_RUNNING) != 0)
1306 mii = device_get_softc(sc->sc_miibus);
1307 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1310 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1311 if ((mask & IFCAP_HWCSUM) != 0) {
1312 ifp->if_capenable ^= IFCAP_HWCSUM;
1313 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1314 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1315 ifp->if_hwassist = STGE_CSUM_FEATURES;
1317 ifp->if_hwassist = 0;
1319 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1320 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1321 if (ifp->if_flags & IFF_RUNNING)
1322 stge_vlan_setup(sc);
1325 VLAN_CAPABILITIES(ifp);
1329 error = ether_ioctl(ifp, cmd, data);
1337 stge_link(struct stge_softc *sc)
1343 * Update STGE_MACCtrl register depending on link status.
1344 * (duplex, flow control etc)
1346 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1347 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1348 v |= sc->sc_MACCtrl;
1349 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1350 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1351 /* Duplex setting changed, reset Tx/Rx functions. */
1352 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1353 ac |= AC_TxReset | AC_RxReset;
1354 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1355 for (i = 0; i < STGE_TIMEOUT; i++) {
1357 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1360 if (i == STGE_TIMEOUT)
1361 device_printf(sc->sc_dev, "reset failed to complete\n");
1366 stge_tx_error(struct stge_softc *sc)
1372 txstat = CSR_READ_4(sc, STGE_TxStatus);
1373 if ((txstat & TS_TxComplete) == 0)
1376 if ((txstat & TS_TxUnderrun) != 0) {
1379 * There should be a more better way to recover
1380 * from Tx underrun instead of a full reset.
1382 if (sc->sc_nerr++ < STGE_MAXERR)
1383 device_printf(sc->sc_dev, "Tx underrun, "
1385 if (sc->sc_nerr == STGE_MAXERR)
1386 device_printf(sc->sc_dev, "too many errors; "
1387 "not reporting any more\n");
1391 /* Maximum/Late collisions, Re-enable Tx MAC. */
1392 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1393 CSR_WRITE_4(sc, STGE_MACCtrl,
1394 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1404 * Interrupt service routine.
1407 stge_intr(void *arg)
1409 struct stge_softc *sc = arg;
1410 struct ifnet *ifp = &sc->arpcom.ac_if;
1414 ASSERT_SERIALIZED(ifp->if_serializer);
1416 status = CSR_READ_2(sc, STGE_IntStatus);
1417 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1420 /* Disable interrupts. */
1421 for (reinit = 0;;) {
1422 status = CSR_READ_2(sc, STGE_IntStatusAck);
1423 status &= sc->sc_IntEnable;
1426 /* Host interface errors. */
1427 if ((status & IS_HostError) != 0) {
1428 device_printf(sc->sc_dev,
1429 "Host interface error, resetting...\n");
1434 /* Receive interrupts. */
1435 if ((status & IS_RxDMAComplete) != 0) {
1437 if ((status & IS_RFDListEnd) != 0)
1438 CSR_WRITE_4(sc, STGE_DMACtrl,
1442 /* Transmit interrupts. */
1443 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1446 /* Transmission errors.*/
1447 if ((status & IS_TxComplete) != 0) {
1448 if ((reinit = stge_tx_error(sc)) != 0)
1457 /* Re-enable interrupts. */
1458 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1460 /* Try to get more packets going. */
1461 if (!ifq_is_empty(&ifp->if_snd))
1468 * Helper; handle transmit interrupts.
1471 stge_txeof(struct stge_softc *sc)
1473 struct ifnet *ifp = &sc->arpcom.ac_if;
1474 struct stge_txdesc *txd;
1478 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1483 * Go through our Tx list and free mbufs for those
1484 * frames which have been transmitted.
1486 for (cons = sc->sc_cdata.stge_tx_cons;;
1487 cons = (cons + 1) % STGE_TX_RING_CNT) {
1488 if (sc->sc_cdata.stge_tx_cnt <= 0)
1490 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1491 if ((control & TFD_TFDDone) == 0)
1493 sc->sc_cdata.stge_tx_cnt--;
1495 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1497 /* Output counter is updated with statistics register */
1500 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1501 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1502 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1504 sc->sc_cdata.stge_tx_cons = cons;
1506 if (sc->sc_cdata.stge_tx_cnt < STGE_TX_HIWAT)
1507 ifq_clr_oactive(&ifp->if_snd);
1508 if (sc->sc_cdata.stge_tx_cnt == 0)
1512 static __inline void
1513 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1515 struct stge_rfd *rfd;
1517 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1518 rfd->rfd_status = 0;
1523 * It seems that TC9021's DMA engine has alignment restrictions in
1524 * DMA scatter operations. The first DMA segment has no address
1525 * alignment restrictins but the rest should be aligned on 4(?) bytes
1526 * boundary. Otherwise it would corrupt random memory. Since we don't
1527 * know which one is used for the first segment in advance we simply
1528 * don't align at all.
1529 * To avoid copying over an entire frame to align, we allocate a new
1530 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1531 * prepended into the existing mbuf chain.
1533 static __inline struct mbuf *
1534 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1539 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1540 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1541 m->m_data += ETHER_HDR_LEN;
1544 MGETHDR(n, MB_DONTWAIT, MT_DATA);
1546 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1547 m->m_data += ETHER_HDR_LEN;
1548 m->m_len -= ETHER_HDR_LEN;
1549 n->m_len = ETHER_HDR_LEN;
1550 M_MOVE_PKTHDR(n, m);
1563 * Helper; handle receive interrupts.
1566 stge_rxeof(struct stge_softc *sc, int count)
1568 struct ifnet *ifp = &sc->arpcom.ac_if;
1569 struct stge_rxdesc *rxd;
1570 struct mbuf *mp, *m;
1576 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1577 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1578 #ifdef IFPOLL_ENABLE
1579 if (count >= 0 && count-- == 0)
1583 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1584 status = RFD_RxStatus(status64);
1585 if ((status & RFD_RFDDone) == 0)
1589 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1593 * If the packet had an error, drop it. Note we count
1594 * the error later in the periodic stats update.
1596 if ((status & RFD_FrameEnd) != 0 && (status &
1597 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1598 RFD_RxAlignmentError | RFD_RxFCSError |
1599 RFD_RxLengthError)) != 0) {
1600 stge_discard_rxbuf(sc, cons);
1601 if (sc->sc_cdata.stge_rxhead != NULL) {
1602 m_freem(sc->sc_cdata.stge_rxhead);
1603 STGE_RXCHAIN_RESET(sc);
1608 * Add a new receive buffer to the ring.
1610 if (stge_newbuf(sc, cons, 0) != 0) {
1612 stge_discard_rxbuf(sc, cons);
1613 if (sc->sc_cdata.stge_rxhead != NULL) {
1614 m_freem(sc->sc_cdata.stge_rxhead);
1615 STGE_RXCHAIN_RESET(sc);
1620 if ((status & RFD_FrameEnd) != 0)
1621 mp->m_len = RFD_RxDMAFrameLen(status) -
1622 sc->sc_cdata.stge_rxlen;
1623 sc->sc_cdata.stge_rxlen += mp->m_len;
1626 if (sc->sc_cdata.stge_rxhead == NULL) {
1627 sc->sc_cdata.stge_rxhead = mp;
1628 sc->sc_cdata.stge_rxtail = mp;
1630 mp->m_flags &= ~M_PKTHDR;
1631 sc->sc_cdata.stge_rxtail->m_next = mp;
1632 sc->sc_cdata.stge_rxtail = mp;
1635 if ((status & RFD_FrameEnd) != 0) {
1636 m = sc->sc_cdata.stge_rxhead;
1637 m->m_pkthdr.rcvif = ifp;
1638 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1640 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1642 STGE_RXCHAIN_RESET(sc);
1646 * Set the incoming checksum information for
1649 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1650 if ((status & RFD_IPDetected) != 0) {
1651 m->m_pkthdr.csum_flags |=
1653 if ((status & RFD_IPError) == 0)
1654 m->m_pkthdr.csum_flags |=
1657 if (((status & RFD_TCPDetected) != 0 &&
1658 (status & RFD_TCPError) == 0) ||
1659 ((status & RFD_UDPDetected) != 0 &&
1660 (status & RFD_UDPError) == 0)) {
1661 m->m_pkthdr.csum_flags |=
1664 CSUM_FRAG_NOT_CHECKED);
1665 m->m_pkthdr.csum_data = 0xffff;
1670 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1671 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1672 STGE_RXCHAIN_RESET(sc);
1678 /* Check for VLAN tagged packets. */
1679 if ((status & RFD_VLANDetected) != 0 &&
1680 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1681 m->m_flags |= M_VLANTAG;
1682 m->m_pkthdr.ether_vlantag = RFD_TCI(status64);
1685 ifp->if_input(ifp, m);
1687 STGE_RXCHAIN_RESET(sc);
1692 /* Update the consumer index. */
1693 sc->sc_cdata.stge_rx_cons = cons;
1697 #ifdef IFPOLL_ENABLE
1700 stge_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1702 struct stge_softc *sc = ifp->if_softc;
1704 ASSERT_SERIALIZED(ifp->if_serializer);
1706 if (sc->sc_npoll.ifpc_stcount-- == 0) {
1709 sc->sc_npoll.ifpc_stcount = sc->sc_npoll.ifpc_stfrac;
1711 status = CSR_READ_2(sc, STGE_IntStatus);
1712 status &= sc->sc_IntEnable;
1714 if (status & IS_HostError) {
1715 device_printf(sc->sc_dev,
1716 "Host interface error, "
1720 if ((status & IS_TxComplete) != 0 &&
1721 stge_tx_error(sc) != 0)
1726 stge_rxeof(sc, count);
1729 if (!ifq_is_empty(&ifp->if_snd))
1734 stge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1736 struct stge_softc *sc = ifp->if_softc;
1738 ASSERT_SERIALIZED(ifp->if_serializer);
1741 int cpuid = sc->sc_npoll.ifpc_cpuid;
1743 info->ifpi_rx[cpuid].poll_func = stge_npoll_compat;
1744 info->ifpi_rx[cpuid].arg = NULL;
1745 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1747 if (ifp->if_flags & IFF_RUNNING) {
1748 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1749 sc->sc_npoll.ifpc_stcount = 0;
1751 ifq_set_cpuid(&ifp->if_snd, cpuid);
1753 if (ifp->if_flags & IFF_RUNNING)
1754 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1755 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq));
1759 #endif /* IFPOLL_ENABLE */
1764 * One second timer, used to tick the MII.
1767 stge_tick(void *arg)
1769 struct stge_softc *sc = arg;
1770 struct ifnet *ifp = &sc->arpcom.ac_if;
1771 struct mii_data *mii;
1773 lwkt_serialize_enter(ifp->if_serializer);
1775 mii = device_get_softc(sc->sc_miibus);
1778 /* Update statistics counters. */
1779 stge_stats_update(sc);
1782 * Relcaim any pending Tx descriptors to release mbufs in a
1783 * timely manner as we don't generate Tx completion interrupts
1784 * for every frame. This limits the delay to a maximum of one
1787 if (sc->sc_cdata.stge_tx_cnt != 0)
1790 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1792 lwkt_serialize_exit(ifp->if_serializer);
1796 * stge_stats_update:
1798 * Read the TC9021 statistics counters.
1801 stge_stats_update(struct stge_softc *sc)
1803 struct ifnet *ifp = &sc->arpcom.ac_if;
1805 CSR_READ_4(sc,STGE_OctetRcvOk);
1807 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk);
1809 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
1811 CSR_READ_4(sc, STGE_OctetXmtdOk);
1813 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk);
1815 ifp->if_collisions +=
1816 CSR_READ_4(sc, STGE_LateCollisions) +
1817 CSR_READ_4(sc, STGE_MultiColFrames) +
1818 CSR_READ_4(sc, STGE_SingleColFrames);
1821 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1822 CSR_READ_2(sc, STGE_FramesWEXDeferal);
1828 * Perform a soft reset on the TC9021.
1831 stge_reset(struct stge_softc *sc, uint32_t how)
1838 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1841 ac |= AC_TxReset | AC_FIFO;
1845 ac |= AC_RxReset | AC_FIFO;
1848 case STGE_RESET_FULL:
1851 * Only assert RstOut if we're fiber. We need GMII clocks
1852 * to be present in order for the reset to complete on fiber
1855 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1856 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1857 (sc->sc_usefiber ? AC_RstOut : 0);
1861 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1863 /* Account for reset problem at 10Mbps. */
1866 for (i = 0; i < STGE_TIMEOUT; i++) {
1867 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1872 if (i == STGE_TIMEOUT)
1873 device_printf(sc->sc_dev, "reset failed to complete\n");
1875 /* Set LED, from Linux IPG driver. */
1876 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1877 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1878 if ((sc->sc_led & 0x01) != 0)
1880 if ((sc->sc_led & 0x03) != 0)
1881 ac |= AC_LEDModeBit1;
1882 if ((sc->sc_led & 0x08) != 0)
1884 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1886 /* Set PHY, from Linux IPG driver */
1887 v = CSR_READ_1(sc, STGE_PhySet);
1888 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1889 v |= ((sc->sc_led & 0x70) >> 4);
1890 CSR_WRITE_1(sc, STGE_PhySet, v);
1894 * stge_init: [ ifnet interface function ]
1896 * Initialize the interface.
1899 stge_init(void *xsc)
1901 struct stge_softc *sc = xsc;
1902 struct ifnet *ifp = &sc->arpcom.ac_if;
1903 struct mii_data *mii;
1908 ASSERT_SERIALIZED(ifp->if_serializer);
1910 mii = device_get_softc(sc->sc_miibus);
1913 * Cancel any pending I/O.
1917 /* Init descriptors. */
1918 error = stge_init_rx_ring(sc);
1920 device_printf(sc->sc_dev,
1921 "initialization failed: no memory for rx buffers\n");
1925 stge_init_tx_ring(sc);
1927 /* Set the station address. */
1928 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
1929 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
1930 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
1931 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
1934 * Set the statistics masks. Disable all the RMON stats,
1935 * and disable selected stats in the non-RMON stats registers.
1937 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
1938 CSR_WRITE_4(sc, STGE_StatisticsMask,
1939 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
1940 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
1941 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
1944 /* Set up the receive filter. */
1945 stge_set_filter(sc);
1946 /* Program multicast filter. */
1950 * Give the transmit and receive ring to the chip.
1952 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
1953 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
1954 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
1955 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
1957 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
1958 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
1959 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
1960 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
1963 * Initialize the Tx auto-poll period. It's OK to make this number
1964 * large (255 is the max, but we use 127) -- we explicitly kick the
1965 * transmit engine when there's actually a packet.
1967 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
1969 /* ..and the Rx auto-poll period. */
1970 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
1972 /* Initialize the Tx start threshold. */
1973 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
1975 /* Rx DMA thresholds, from Linux */
1976 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
1977 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
1979 /* Rx early threhold, from Linux */
1980 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
1982 /* Tx DMA thresholds, from Linux */
1983 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
1984 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
1987 * Initialize the Rx DMA interrupt control register. We
1988 * request an interrupt after every incoming packet, but
1989 * defer it for sc_rxint_dmawait us. When the number of
1990 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
1991 * deferring the interrupt, and signal it immediately.
1993 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
1994 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
1995 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
1998 * Initialize the interrupt mask.
2000 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2001 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2002 #ifdef IFPOLL_ENABLE
2003 /* Disable interrupts if we are polling. */
2004 if (ifp->if_flags & IFF_NPOLLING) {
2005 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2006 sc->sc_npoll.ifpc_stcount = 0;
2009 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2012 * Configure the DMA engine.
2013 * XXX Should auto-tune TxBurstLimit.
2015 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2018 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2019 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2022 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2023 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2026 * Set the maximum frame size.
2028 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2029 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2032 * Initialize MacCtrl -- do it before setting the media,
2033 * as setting the media will actually program the register.
2035 * Note: We have to poke the IFS value before poking
2038 /* Tx/Rx MAC should be disabled before programming IFS.*/
2039 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2041 stge_vlan_setup(sc);
2043 if (sc->sc_rev >= 6) { /* >= B.2 */
2044 /* Multi-frag frame bug work-around. */
2045 CSR_WRITE_2(sc, STGE_DebugCtrl,
2046 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2048 /* Tx Poll Now bug work-around. */
2049 CSR_WRITE_2(sc, STGE_DebugCtrl,
2050 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2051 /* Tx Poll Now bug work-around. */
2052 CSR_WRITE_2(sc, STGE_DebugCtrl,
2053 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2056 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2057 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2058 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2060 * It seems that transmitting frames without checking the state of
2061 * Rx/Tx MAC wedge the hardware.
2067 * Set the current media.
2072 * Start the one second MII clock.
2074 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2079 ifp->if_flags |= IFF_RUNNING;
2080 ifq_clr_oactive(&ifp->if_snd);
2084 device_printf(sc->sc_dev, "interface not running\n");
2088 stge_vlan_setup(struct stge_softc *sc)
2090 struct ifnet *ifp = &sc->arpcom.ac_if;
2094 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2095 * MC_AutoVLANuntagging bit.
2096 * MC_AutoVLANtagging bit selects which VLAN source to use
2097 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2098 * bit has priority over MC_AutoVLANtagging bit. So we always
2099 * use TFC instead of STGE_VLANTag register.
2101 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2102 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2103 v |= MC_AutoVLANuntagging;
2105 v &= ~MC_AutoVLANuntagging;
2106 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2110 * Stop transmission on the interface.
2113 stge_stop(struct stge_softc *sc)
2115 struct ifnet *ifp = &sc->arpcom.ac_if;
2116 struct stge_txdesc *txd;
2117 struct stge_rxdesc *rxd;
2121 ASSERT_SERIALIZED(ifp->if_serializer);
2124 * Stop the one second clock.
2126 callout_stop(&sc->sc_tick_ch);
2129 * Reset the chip to a known state.
2131 stge_reset(sc, STGE_RESET_FULL);
2134 * Disable interrupts.
2136 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2139 * Stop receiver, transmitter, and stats update.
2143 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2144 v |= MC_StatisticsDisable;
2145 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2148 * Stop the transmit and receive DMA.
2151 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2152 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2153 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2154 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2157 * Free RX and TX mbufs still in the queues.
2159 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2160 rxd = &sc->sc_cdata.stge_rxdesc[i];
2161 if (rxd->rx_m != NULL) {
2162 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2168 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2169 txd = &sc->sc_cdata.stge_txdesc[i];
2170 if (txd->tx_m != NULL) {
2171 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2179 * Mark the interface down and cancel the watchdog timer.
2181 ifp->if_flags &= ~IFF_RUNNING;
2182 ifq_clr_oactive(&ifp->if_snd);
2187 stge_start_tx(struct stge_softc *sc)
2192 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2193 if ((v & MC_TxEnabled) != 0)
2196 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2197 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2198 for (i = STGE_TIMEOUT; i > 0; i--) {
2200 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2201 if ((v & MC_TxEnabled) != 0)
2205 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2209 stge_start_rx(struct stge_softc *sc)
2214 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2215 if ((v & MC_RxEnabled) != 0)
2218 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2219 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2220 for (i = STGE_TIMEOUT; i > 0; i--) {
2222 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2223 if ((v & MC_RxEnabled) != 0)
2227 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2231 stge_stop_tx(struct stge_softc *sc)
2236 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2237 if ((v & MC_TxEnabled) == 0)
2240 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2241 for (i = STGE_TIMEOUT; i > 0; i--) {
2243 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2244 if ((v & MC_TxEnabled) == 0)
2248 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2252 stge_stop_rx(struct stge_softc *sc)
2257 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2258 if ((v & MC_RxEnabled) == 0)
2261 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2262 for (i = STGE_TIMEOUT; i > 0; i--) {
2264 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2265 if ((v & MC_RxEnabled) == 0)
2269 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2273 stge_init_tx_ring(struct stge_softc *sc)
2275 struct stge_ring_data *rd;
2276 struct stge_txdesc *txd;
2280 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2281 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2283 sc->sc_cdata.stge_tx_prod = 0;
2284 sc->sc_cdata.stge_tx_cons = 0;
2285 sc->sc_cdata.stge_tx_cnt = 0;
2288 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2289 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2290 if (i == (STGE_TX_RING_CNT - 1))
2291 addr = STGE_TX_RING_ADDR(sc, 0);
2293 addr = STGE_TX_RING_ADDR(sc, i + 1);
2294 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2295 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2296 txd = &sc->sc_cdata.stge_txdesc[i];
2297 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2302 stge_init_rx_ring(struct stge_softc *sc)
2304 struct stge_ring_data *rd;
2308 sc->sc_cdata.stge_rx_cons = 0;
2309 STGE_RXCHAIN_RESET(sc);
2312 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2313 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2314 if (stge_newbuf(sc, i, 1) != 0)
2316 if (i == (STGE_RX_RING_CNT - 1))
2317 addr = STGE_RX_RING_ADDR(sc, 0);
2319 addr = STGE_RX_RING_ADDR(sc, i + 1);
2320 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2321 rd->stge_rx_ring[i].rfd_status = 0;
2329 * Add a receive buffer to the indicated descriptor.
2332 stge_newbuf(struct stge_softc *sc, int idx, int waitok)
2334 struct stge_rxdesc *rxd;
2335 struct stge_rfd *rfd;
2337 bus_dma_segment_t seg;
2341 m = m_getcl(waitok ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2344 m->m_len = m->m_pkthdr.len = MCLBYTES;
2347 * The hardware requires 4bytes aligned DMA address when JUMBO
2350 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2351 m_adj(m, ETHER_ALIGN);
2353 error = bus_dmamap_load_mbuf_segment(sc->sc_cdata.stge_rx_tag,
2354 sc->sc_cdata.stge_rx_sparemap, m,
2355 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2361 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2362 if (rxd->rx_m != NULL) {
2363 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2364 BUS_DMASYNC_POSTREAD);
2365 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2368 map = rxd->rx_dmamap;
2369 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2370 sc->sc_cdata.stge_rx_sparemap = map;
2374 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2375 rfd->rfd_frag.frag_word0 =
2376 htole64(FRAG_ADDR(seg.ds_addr) | FRAG_LEN(seg.ds_len));
2377 rfd->rfd_status = 0;
2385 * Set up the receive filter.
2388 stge_set_filter(struct stge_softc *sc)
2390 struct ifnet *ifp = &sc->arpcom.ac_if;
2393 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2394 mode |= RM_ReceiveUnicast;
2395 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2396 mode |= RM_ReceiveBroadcast;
2398 mode &= ~RM_ReceiveBroadcast;
2399 if ((ifp->if_flags & IFF_PROMISC) != 0)
2400 mode |= RM_ReceiveAllFrames;
2402 mode &= ~RM_ReceiveAllFrames;
2404 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2408 stge_set_multi(struct stge_softc *sc)
2410 struct ifnet *ifp = &sc->arpcom.ac_if;
2411 struct ifmultiaddr *ifma;
2417 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2418 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2419 if ((ifp->if_flags & IFF_PROMISC) != 0)
2420 mode |= RM_ReceiveAllFrames;
2421 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2422 mode |= RM_ReceiveMulticast;
2423 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2427 /* clear existing filters. */
2428 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2429 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2432 * Set up the multicast address filter by passing all multicast
2433 * addresses through a CRC generator, and then using the low-order
2434 * 6 bits as an index into the 64 bit multicast hash table. The
2435 * high order bits select the register, while the rest of the bits
2436 * select the bit within the register.
2439 bzero(mchash, sizeof(mchash));
2442 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2443 if (ifma->ifma_addr->sa_family != AF_LINK)
2445 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2446 ifma->ifma_addr), ETHER_ADDR_LEN);
2448 /* Just want the 6 least significant bits. */
2451 /* Set the corresponding bit in the hash table. */
2452 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2456 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2458 mode |= RM_ReceiveMulticastHash;
2460 mode &= ~RM_ReceiveMulticastHash;
2462 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2463 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2464 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2468 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2470 return (sysctl_int_range(oidp, arg1, arg2, req,
2471 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2475 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2477 return (sysctl_int_range(oidp, arg1, arg2, req,
2478 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));